1 // Copyright 2015 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 // Lowering arithmetic
6 (Add(64|32|16|8) ...) => (ADD(Q|L|L|L) ...)
7 (AddPtr ...) => (ADDQ ...)
8 (Add(32|64)F ...) => (ADDS(S|D) ...)
9
10 (Sub(64|32|16|8) ...) => (SUB(Q|L|L|L) ...)
11 (SubPtr ...) => (SUBQ ...)
12 (Sub(32|64)F ...) => (SUBS(S|D) ...)
13
14 (Mul(64|32|16|8) ...) => (MUL(Q|L|L|L) ...)
15 (Mul(32|64)F ...) => (MULS(S|D) ...)
16
17 (Select0 (Mul64uover x y)) => (Select0 <typ.UInt64> (MULQU x y))
18 (Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y))
19 (Select1 (Mul(64|32)uover x y)) => (SETO (Select1 <types.TypeFlags> (MUL(Q|L)U x y)))
20
21 (Hmul(64|32) ...) => (HMUL(Q|L) ...)
22 (Hmul(64|32)u ...) => (HMUL(Q|L)U ...)
23
24 (Div(64|32|16) [a] x y) => (Select0 (DIV(Q|L|W) [a] x y))
25 (Div8 x y) => (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
26 (Div(64|32|16)u x y) => (Select0 (DIV(Q|L|W)U x y))
27 (Div8u x y) => (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
28 (Div(32|64)F ...) => (DIVS(S|D) ...)
29
30 (Select0 (Add64carry x y c)) =>
31 (Select0 <typ.UInt64> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
32 (Select1 (Add64carry x y c)) =>
33 (NEGQ <typ.UInt64> (SBBQcarrymask <typ.UInt64> (Select1 <types.TypeFlags> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
34 (Select0 (Sub64borrow x y c)) =>
35 (Select0 <typ.UInt64> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
36 (Select1 (Sub64borrow x y c)) =>
37 (NEGQ <typ.UInt64> (SBBQcarrymask <typ.UInt64> (Select1 <types.TypeFlags> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
38
39 // Optimize ADCQ and friends
40 (ADCQ x (MOVQconst [c]) carry) && is32Bit(c) => (ADCQconst x [int32(c)] carry)
41 (ADCQ x y (FlagEQ)) => (ADDQcarry x y)
42 (ADCQconst x [c] (FlagEQ)) => (ADDQconstcarry x [c])
43 (ADDQcarry x (MOVQconst [c])) && is32Bit(c) => (ADDQconstcarry x [int32(c)])
44 (SBBQ x (MOVQconst [c]) borrow) && is32Bit(c) => (SBBQconst x [int32(c)] borrow)
45 (SBBQ x y (FlagEQ)) => (SUBQborrow x y)
46 (SBBQconst x [c] (FlagEQ)) => (SUBQconstborrow x [c])
47 (SUBQborrow x (MOVQconst [c])) && is32Bit(c) => (SUBQconstborrow x [int32(c)])
48 (Select1 (NEGLflags (MOVQconst [0]))) => (FlagEQ)
49 (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) => x
50
51
52 (Mul64uhilo ...) => (MULQU2 ...)
53 (Div128u ...) => (DIVQU2 ...)
54
55 (Avg64u ...) => (AVGQU ...)
56
57 (Mod(64|32|16) [a] x y) => (Select1 (DIV(Q|L|W) [a] x y))
58 (Mod8 x y) => (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
59 (Mod(64|32|16)u x y) => (Select1 (DIV(Q|L|W)U x y))
60 (Mod8u x y) => (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
61
62 (And(64|32|16|8) ...) => (AND(Q|L|L|L) ...)
63 (Or(64|32|16|8) ...) => (OR(Q|L|L|L) ...)
64 (Xor(64|32|16|8) ...) => (XOR(Q|L|L|L) ...)
65 (Com(64|32|16|8) ...) => (NOT(Q|L|L|L) ...)
66
67 (Neg(64|32|16|8) ...) => (NEG(Q|L|L|L) ...)
68 (Neg32F x) => (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
69 (Neg64F x) => (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
70
71 // Lowering boolean ops
72 (AndB ...) => (ANDL ...)
73 (OrB ...) => (ORL ...)
74 (Not x) => (XORLconst [1] x)
75
76 // Lowering pointer arithmetic
77 (OffPtr [off] ptr) && is32Bit(off) => (ADDQconst [int32(off)] ptr)
78 (OffPtr [off] ptr) => (ADDQ (MOVQconst [off]) ptr)
79
80 // Lowering other arithmetic
81 (Ctz64 x) && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
82 (Ctz32 x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
83 (Ctz64 <t> x) && buildcfg.GOAMD64 < 3 => (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <types.TypeFlags> (BSFQ x)))
84 (Ctz32 x) && buildcfg.GOAMD64 < 3 => (Select0 (BSFQ (BTSQconst <typ.UInt64> [32] x)))
85 (Ctz16 x) => (BSFL (ORLconst <typ.UInt32> [1<<16] x))
86 (Ctz8 x) => (BSFL (ORLconst <typ.UInt32> [1<<8 ] x))
87
88 (Ctz64NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
89 (Ctz32NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
90 (Ctz16NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
91 (Ctz8NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
92 (Ctz64NonZero x) && buildcfg.GOAMD64 < 3 => (Select0 (BSFQ x))
93 (Ctz32NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
94 (Ctz16NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
95 (Ctz8NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
96
97 // BitLen64 of a 64 bit value x requires checking whether x == 0, since BSRQ is undefined when x == 0.
98 // However, for zero-extended values, we can cheat a bit, and calculate
99 // BSR(x<<1 + 1), which is guaranteed to be non-zero, and which conveniently
100 // places the index of the highest set bit where we want it.
101 // For GOAMD64>=3, BitLen can be calculated by OperandSize - LZCNT(x).
102 (BitLen64 <t> x) && buildcfg.GOAMD64 < 3 => (ADDQconst [1] (CMOVQEQ <t> (Select0 <t> (BSRQ x)) (MOVQconst <t> [-1]) (Select1 <types.TypeFlags> (BSRQ x))))
103 (BitLen32 x) && buildcfg.GOAMD64 < 3 => (Select0 (BSRQ (LEAQ1 <typ.UInt64> [1] (MOVLQZX <typ.UInt64> x) (MOVLQZX <typ.UInt64> x))))
104 (BitLen16 x) && buildcfg.GOAMD64 < 3 => (BSRL (LEAL1 <typ.UInt32> [1] (MOVWQZX <typ.UInt32> x) (MOVWQZX <typ.UInt32> x)))
105 (BitLen8 x) && buildcfg.GOAMD64 < 3 => (BSRL (LEAL1 <typ.UInt32> [1] (MOVBQZX <typ.UInt32> x) (MOVBQZX <typ.UInt32> x)))
106 (BitLen64 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-64] (LZCNTQ x)))
107 // Use 64-bit version to allow const-fold remove unnecessary arithmetic.
108 (BitLen32 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL x)))
109 (BitLen16 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVWQZX <x.Type> x))))
110 (BitLen8 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVBQZX <x.Type> x))))
111
112 (Bswap(64|32) ...) => (BSWAP(Q|L) ...)
113 (Bswap16 x) => (ROLWconst [8] x)
114
115 (PopCount(64|32) ...) => (POPCNT(Q|L) ...)
116 (PopCount16 x) => (POPCNTL (MOVWQZX <typ.UInt32> x))
117 (PopCount8 x) => (POPCNTL (MOVBQZX <typ.UInt32> x))
118
119 (Sqrt ...) => (SQRTSD ...)
120 (Sqrt32 ...) => (SQRTSS ...)
121
122 (RoundToEven x) => (ROUNDSD [0] x)
123 (Floor x) => (ROUNDSD [1] x)
124 (Ceil x) => (ROUNDSD [2] x)
125 (Trunc x) => (ROUNDSD [3] x)
126
127 (FMA x y z) => (VFMADD231SD z x y)
128
129 // Lowering extension
130 // Note: we always extend to 64 bits even though some ops don't need that many result bits.
131 (SignExt8to16 ...) => (MOVBQSX ...)
132 (SignExt8to32 ...) => (MOVBQSX ...)
133 (SignExt8to64 ...) => (MOVBQSX ...)
134 (SignExt16to32 ...) => (MOVWQSX ...)
135 (SignExt16to64 ...) => (MOVWQSX ...)
136 (SignExt32to64 ...) => (MOVLQSX ...)
137
138 (ZeroExt8to16 ...) => (MOVBQZX ...)
139 (ZeroExt8to32 ...) => (MOVBQZX ...)
140 (ZeroExt8to64 ...) => (MOVBQZX ...)
141 (ZeroExt16to32 ...) => (MOVWQZX ...)
142 (ZeroExt16to64 ...) => (MOVWQZX ...)
143 (ZeroExt32to64 ...) => (MOVLQZX ...)
144
145 (Slicemask <t> x) => (SARQconst (NEGQ <t> x) [63])
146
147 (SpectreIndex <t> x y) => (CMOVQCC x (MOVQconst [0]) (CMPQ x y))
148 (SpectreSliceIndex <t> x y) => (CMOVQHI x (MOVQconst [0]) (CMPQ x y))
149
150 // Lowering truncation
151 // Because we ignore high parts of registers, truncates are just copies.
152 (Trunc16to8 ...) => (Copy ...)
153 (Trunc32to8 ...) => (Copy ...)
154 (Trunc32to16 ...) => (Copy ...)
155 (Trunc64to8 ...) => (Copy ...)
156 (Trunc64to16 ...) => (Copy ...)
157 (Trunc64to32 ...) => (Copy ...)
158
159 // Lowering float <-> int
160 (Cvt32to32F ...) => (CVTSL2SS ...)
161 (Cvt32to64F ...) => (CVTSL2SD ...)
162 (Cvt64to32F ...) => (CVTSQ2SS ...)
163 (Cvt64to64F ...) => (CVTSQ2SD ...)
164
165 (Cvt32Fto32 ...) => (CVTTSS2SL ...)
166 (Cvt32Fto64 ...) => (CVTTSS2SQ ...)
167 (Cvt64Fto32 ...) => (CVTTSD2SL ...)
168 (Cvt64Fto64 ...) => (CVTTSD2SQ ...)
169
170 (Cvt32Fto64F ...) => (CVTSS2SD ...)
171 (Cvt64Fto32F ...) => (CVTSD2SS ...)
172
173 (Round(32|64)F ...) => (Copy ...)
174
175 // Floating-point min is tricky, as the hardware op isn't right for various special
176 // cases (-0 and NaN). We use two hardware ops organized just right to make the
177 // result come out how we want it. See https://github.com/golang/go/issues/59488#issuecomment-1553493207
178 // (although that comment isn't exactly right, as the value overwritten is not simulated correctly).
179 // t1 = MINSD x, y => incorrect if x==NaN or x==-0,y==+0
180 // t2 = MINSD t1, x => fixes x==NaN case
181 // res = POR t1, t2 => fixes x==-0,y==+0 case
182 // Note that this trick depends on the special property that (NaN OR x) produces a NaN (although
183 // it might not produce the same NaN as the input).
184 (Min(64|32)F <t> x y) => (POR (MINS(D|S) <t> (MINS(D|S) <t> x y) x) (MINS(D|S) <t> x y))
185 // Floating-point max is even trickier. Punt to using min instead.
186 // max(x,y) == -min(-x,-y)
187 (Max(64|32)F <t> x y) => (Neg(64|32)F <t> (Min(64|32)F <t> (Neg(64|32)F <t> x) (Neg(64|32)F <t> y)))
188
189 (CvtBoolToUint8 ...) => (Copy ...)
190
191 // Lowering shifts
192 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value.
193 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff)
194 (Lsh64x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
195 (Lsh32x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
196 (Lsh16x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
197 (Lsh8x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
198
199 (Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SHLQ x y)
200 (Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SHLL x y)
201 (Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SHLL x y)
202 (Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SHLL x y)
203
204 (Rsh64Ux(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
205 (Rsh32Ux(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
206 (Rsh16Ux(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [16])))
207 (Rsh8Ux(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [8])))
208
209 (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SHRQ x y)
210 (Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SHRL x y)
211 (Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SHRW x y)
212 (Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SHRB x y)
213
214 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value.
215 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width.
216 (Rsh64x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (SARQ <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [64])))))
217 (Rsh32x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (SARL <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [32])))))
218 (Rsh16x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (SARW <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [16])))))
219 (Rsh8x(64|32|16|8) <t> x y) && !shiftIsBounded(v) => (SARB <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [8])))))
220
221 (Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SARQ x y)
222 (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SARL x y)
223 (Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SARW x y)
224 (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SARB x y)
225
226 // Lowering integer comparisons
227 (Less(64|32|16|8) x y) => (SETL (CMP(Q|L|W|B) x y))
228 (Less(64|32|16|8)U x y) => (SETB (CMP(Q|L|W|B) x y))
229 (Leq(64|32|16|8) x y) => (SETLE (CMP(Q|L|W|B) x y))
230 (Leq(64|32|16|8)U x y) => (SETBE (CMP(Q|L|W|B) x y))
231 (Eq(Ptr|64|32|16|8|B) x y) => (SETEQ (CMP(Q|Q|L|W|B|B) x y))
232 (Neq(Ptr|64|32|16|8|B) x y) => (SETNE (CMP(Q|Q|L|W|B|B) x y))
233
234 // Lowering floating point comparisons
235 // Note Go assembler gets UCOMISx operand order wrong, but it is right here
236 // and the operands are reversed when generating assembly language.
237 (Eq(32|64)F x y) => (SETEQF (UCOMIS(S|D) x y))
238 (Neq(32|64)F x y) => (SETNEF (UCOMIS(S|D) x y))
239 // Use SETGF/SETGEF with reversed operands to dodge NaN case.
240 (Less(32|64)F x y) => (SETGF (UCOMIS(S|D) y x))
241 (Leq(32|64)F x y) => (SETGEF (UCOMIS(S|D) y x))
242
243 // Lowering loads
244 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVQload ptr mem)
245 (Load <t> ptr mem) && is32BitInt(t) => (MOVLload ptr mem)
246 (Load <t> ptr mem) && is16BitInt(t) => (MOVWload ptr mem)
247 (Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) => (MOVBload ptr mem)
248 (Load <t> ptr mem) && is32BitFloat(t) => (MOVSSload ptr mem)
249 (Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
250
251 // Lowering stores
252 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
253 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
254 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVQstore ptr val mem)
255 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
256 (Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
257 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
258
259 // Lowering moves
260 (Move [0] _ _ mem) => mem
261 (Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
262 (Move [2] dst src mem) => (MOVWstore dst (MOVWload src mem) mem)
263 (Move [4] dst src mem) => (MOVLstore dst (MOVLload src mem) mem)
264 (Move [8] dst src mem) => (MOVQstore dst (MOVQload src mem) mem)
265 (Move [16] dst src mem) && config.useSSE => (MOVOstore dst (MOVOload src mem) mem)
266 (Move [16] dst src mem) && !config.useSSE =>
267 (MOVQstore [8] dst (MOVQload [8] src mem)
268 (MOVQstore dst (MOVQload src mem) mem))
269
270 (Move [32] dst src mem) =>
271 (Move [16]
272 (OffPtr <dst.Type> dst [16])
273 (OffPtr <src.Type> src [16])
274 (Move [16] dst src mem))
275
276 (Move [48] dst src mem) && config.useSSE =>
277 (Move [32]
278 (OffPtr <dst.Type> dst [16])
279 (OffPtr <src.Type> src [16])
280 (Move [16] dst src mem))
281
282 (Move [64] dst src mem) && config.useSSE =>
283 (Move [32]
284 (OffPtr <dst.Type> dst [32])
285 (OffPtr <src.Type> src [32])
286 (Move [32] dst src mem))
287
288 (Move [3] dst src mem) =>
289 (MOVBstore [2] dst (MOVBload [2] src mem)
290 (MOVWstore dst (MOVWload src mem) mem))
291 (Move [5] dst src mem) =>
292 (MOVBstore [4] dst (MOVBload [4] src mem)
293 (MOVLstore dst (MOVLload src mem) mem))
294 (Move [6] dst src mem) =>
295 (MOVWstore [4] dst (MOVWload [4] src mem)
296 (MOVLstore dst (MOVLload src mem) mem))
297 (Move [7] dst src mem) =>
298 (MOVLstore [3] dst (MOVLload [3] src mem)
299 (MOVLstore dst (MOVLload src mem) mem))
300 (Move [9] dst src mem) =>
301 (MOVBstore [8] dst (MOVBload [8] src mem)
302 (MOVQstore dst (MOVQload src mem) mem))
303 (Move [10] dst src mem) =>
304 (MOVWstore [8] dst (MOVWload [8] src mem)
305 (MOVQstore dst (MOVQload src mem) mem))
306 (Move [11] dst src mem) =>
307 (MOVLstore [7] dst (MOVLload [7] src mem)
308 (MOVQstore dst (MOVQload src mem) mem))
309 (Move [12] dst src mem) =>
310 (MOVLstore [8] dst (MOVLload [8] src mem)
311 (MOVQstore dst (MOVQload src mem) mem))
312 (Move [s] dst src mem) && s >= 13 && s <= 15 =>
313 (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem)
314 (MOVQstore dst (MOVQload src mem) mem))
315
316 // Adjust moves to be a multiple of 16 bytes.
317 (Move [s] dst src mem)
318 && s > 16 && s%16 != 0 && s%16 <= 8 =>
319 (Move [s-s%16]
320 (OffPtr <dst.Type> dst [s%16])
321 (OffPtr <src.Type> src [s%16])
322 (MOVQstore dst (MOVQload src mem) mem))
323 (Move [s] dst src mem)
324 && s > 16 && s%16 != 0 && s%16 > 8 && config.useSSE =>
325 (Move [s-s%16]
326 (OffPtr <dst.Type> dst [s%16])
327 (OffPtr <src.Type> src [s%16])
328 (MOVOstore dst (MOVOload src mem) mem))
329 (Move [s] dst src mem)
330 && s > 16 && s%16 != 0 && s%16 > 8 && !config.useSSE =>
331 (Move [s-s%16]
332 (OffPtr <dst.Type> dst [s%16])
333 (OffPtr <src.Type> src [s%16])
334 (MOVQstore [8] dst (MOVQload [8] src mem)
335 (MOVQstore dst (MOVQload src mem) mem)))
336
337 // Medium copying uses a duff device.
338 (Move [s] dst src mem)
339 && s > 64 && s <= 16*64 && s%16 == 0
340 && !config.noDuffDevice && logLargeCopy(v, s) =>
341 (DUFFCOPY [s] dst src mem)
342
343 // Large copying uses REP MOVSQ.
344 (Move [s] dst src mem) && (s > 16*64 || config.noDuffDevice) && s%8 == 0 && logLargeCopy(v, s) =>
345 (REPMOVSQ dst src (MOVQconst [s/8]) mem)
346
347 // Lowering Zero instructions
348 (Zero [0] _ mem) => mem
349 (Zero [1] destptr mem) => (MOVBstoreconst [makeValAndOff(0,0)] destptr mem)
350 (Zero [2] destptr mem) => (MOVWstoreconst [makeValAndOff(0,0)] destptr mem)
351 (Zero [4] destptr mem) => (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)
352 (Zero [8] destptr mem) => (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)
353
354 (Zero [3] destptr mem) =>
355 (MOVBstoreconst [makeValAndOff(0,2)] destptr
356 (MOVWstoreconst [makeValAndOff(0,0)] destptr mem))
357 (Zero [5] destptr mem) =>
358 (MOVBstoreconst [makeValAndOff(0,4)] destptr
359 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
360 (Zero [6] destptr mem) =>
361 (MOVWstoreconst [makeValAndOff(0,4)] destptr
362 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
363 (Zero [7] destptr mem) =>
364 (MOVLstoreconst [makeValAndOff(0,3)] destptr
365 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
366
367 // Strip off any fractional word zeroing.
368 (Zero [s] destptr mem) && s%8 != 0 && s > 8 && !config.useSSE =>
369 (Zero [s-s%8] (OffPtr <destptr.Type> destptr [s%8])
370 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
371
372 // Zero small numbers of words directly.
373 (Zero [16] destptr mem) && !config.useSSE =>
374 (MOVQstoreconst [makeValAndOff(0,8)] destptr
375 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
376 (Zero [24] destptr mem) && !config.useSSE =>
377 (MOVQstoreconst [makeValAndOff(0,16)] destptr
378 (MOVQstoreconst [makeValAndOff(0,8)] destptr
379 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem)))
380 (Zero [32] destptr mem) && !config.useSSE =>
381 (MOVQstoreconst [makeValAndOff(0,24)] destptr
382 (MOVQstoreconst [makeValAndOff(0,16)] destptr
383 (MOVQstoreconst [makeValAndOff(0,8)] destptr
384 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))))
385
386 (Zero [9] destptr mem) && config.useSSE =>
387 (MOVBstoreconst [makeValAndOff(0,8)] destptr
388 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
389
390 (Zero [10] destptr mem) && config.useSSE =>
391 (MOVWstoreconst [makeValAndOff(0,8)] destptr
392 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
393
394 (Zero [11] destptr mem) && config.useSSE =>
395 (MOVLstoreconst [makeValAndOff(0,7)] destptr
396 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
397
398 (Zero [12] destptr mem) && config.useSSE =>
399 (MOVLstoreconst [makeValAndOff(0,8)] destptr
400 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
401
402 (Zero [s] destptr mem) && s > 12 && s < 16 && config.useSSE =>
403 (MOVQstoreconst [makeValAndOff(0,int32(s-8))] destptr
404 (MOVQstoreconst [makeValAndOff(0,0)] destptr mem))
405
406 // Adjust zeros to be a multiple of 16 bytes.
407 (Zero [s] destptr mem) && s%16 != 0 && s > 16 && s%16 > 8 && config.useSSE =>
408 (Zero [s-s%16] (OffPtr <destptr.Type> destptr [s%16])
409 (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))
410
411 (Zero [s] destptr mem) && s%16 != 0 && s > 16 && s%16 <= 8 && config.useSSE =>
412 (Zero [s-s%16] (OffPtr <destptr.Type> destptr [s%16])
413 (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))
414
415 (Zero [16] destptr mem) && config.useSSE =>
416 (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)
417 (Zero [32] destptr mem) && config.useSSE =>
418 (MOVOstoreconst [makeValAndOff(0,16)] destptr
419 (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))
420 (Zero [48] destptr mem) && config.useSSE =>
421 (MOVOstoreconst [makeValAndOff(0,32)] destptr
422 (MOVOstoreconst [makeValAndOff(0,16)] destptr
423 (MOVOstoreconst [makeValAndOff(0,0)] destptr mem)))
424 (Zero [64] destptr mem) && config.useSSE =>
425 (MOVOstoreconst [makeValAndOff(0,48)] destptr
426 (MOVOstoreconst [makeValAndOff(0,32)] destptr
427 (MOVOstoreconst [makeValAndOff(0,16)] destptr
428 (MOVOstoreconst [makeValAndOff(0,0)] destptr mem))))
429
430 // Medium zeroing uses a duff device.
431 (Zero [s] destptr mem)
432 && s > 64 && s <= 1024 && s%16 == 0 && !config.noDuffDevice =>
433 (DUFFZERO [s] destptr mem)
434
435 // Large zeroing uses REP STOSQ.
436 (Zero [s] destptr mem)
437 && (s > 1024 || (config.noDuffDevice && s > 64 || !config.useSSE && s > 32))
438 && s%8 == 0 =>
439 (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem)
440
441 // Lowering constants
442 (Const8 [c]) => (MOVLconst [int32(c)])
443 (Const16 [c]) => (MOVLconst [int32(c)])
444 (Const32 ...) => (MOVLconst ...)
445 (Const64 ...) => (MOVQconst ...)
446 (Const32F ...) => (MOVSSconst ...)
447 (Const64F ...) => (MOVSDconst ...)
448 (ConstNil ) => (MOVQconst [0])
449 (ConstBool [c]) => (MOVLconst [b2i32(c)])
450
451 // Lowering calls
452 (StaticCall ...) => (CALLstatic ...)
453 (ClosureCall ...) => (CALLclosure ...)
454 (InterCall ...) => (CALLinter ...)
455 (TailCall ...) => (CALLtail ...)
456
457 // Lowering conditional moves
458 // If the condition is a SETxx, we can just run a CMOV from the comparison that was
459 // setting the flags.
460 // Legend: HI=unsigned ABOVE, CS=unsigned BELOW, CC=unsigned ABOVE EQUAL, LS=unsigned BELOW EQUAL
461 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && (is64BitInt(t) || isPtr(t))
462 => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
463 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && is32BitInt(t)
464 => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
465 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && is16BitInt(t)
466 => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
467
468 // If the condition does not set the flags, we need to generate a comparison.
469 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1
470 => (CondSelect <t> x y (MOVBQZX <typ.UInt64> check))
471 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2
472 => (CondSelect <t> x y (MOVWQZX <typ.UInt64> check))
473 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4
474 => (CondSelect <t> x y (MOVLQZX <typ.UInt64> check))
475
476 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && (is64BitInt(t) || isPtr(t))
477 => (CMOVQNE y x (CMPQconst [0] check))
478 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && is32BitInt(t)
479 => (CMOVLNE y x (CMPQconst [0] check))
480 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && is16BitInt(t)
481 => (CMOVWNE y x (CMPQconst [0] check))
482
483 // Absorb InvertFlags
484 (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
485 => (CMOVQ(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
486 (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
487 => (CMOVL(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
488 (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
489 => (CMOVW(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
490
491 // Absorb constants generated during lower
492 (CMOV(QEQ|QLE|QGE|QCC|QLS|LEQ|LLE|LGE|LCC|LLS|WEQ|WLE|WGE|WCC|WLS) _ x (FlagEQ)) => x
493 (CMOV(QNE|QLT|QGT|QCS|QHI|LNE|LLT|LGT|LCS|LHI|WNE|WLT|WGT|WCS|WHI) y _ (FlagEQ)) => y
494 (CMOV(QNE|QGT|QGE|QHI|QCC|LNE|LGT|LGE|LHI|LCC|WNE|WGT|WGE|WHI|WCC) _ x (FlagGT_UGT)) => x
495 (CMOV(QEQ|QLE|QLT|QLS|QCS|LEQ|LLE|LLT|LLS|LCS|WEQ|WLE|WLT|WLS|WCS) y _ (FlagGT_UGT)) => y
496 (CMOV(QNE|QGT|QGE|QLS|QCS|LNE|LGT|LGE|LLS|LCS|WNE|WGT|WGE|WLS|WCS) _ x (FlagGT_ULT)) => x
497 (CMOV(QEQ|QLE|QLT|QHI|QCC|LEQ|LLE|LLT|LHI|LCC|WEQ|WLE|WLT|WHI|WCC) y _ (FlagGT_ULT)) => y
498 (CMOV(QNE|QLT|QLE|QCS|QLS|LNE|LLT|LLE|LCS|LLS|WNE|WLT|WLE|WCS|WLS) _ x (FlagLT_ULT)) => x
499 (CMOV(QEQ|QGT|QGE|QHI|QCC|LEQ|LGT|LGE|LHI|LCC|WEQ|WGT|WGE|WHI|WCC) y _ (FlagLT_ULT)) => y
500 (CMOV(QNE|QLT|QLE|QHI|QCC|LNE|LLT|LLE|LHI|LCC|WNE|WLT|WLE|WHI|WCC) _ x (FlagLT_UGT)) => x
501 (CMOV(QEQ|QGT|QGE|QCS|QLS|LEQ|LGT|LGE|LCS|LLS|WEQ|WGT|WGE|WCS|WLS) y _ (FlagLT_UGT)) => y
502
503 // Miscellaneous
504 (IsNonNil p) => (SETNE (TESTQ p p))
505 (IsInBounds idx len) => (SETB (CMPQ idx len))
506 (IsSliceInBounds idx len) => (SETBE (CMPQ idx len))
507 (NilCheck ...) => (LoweredNilCheck ...)
508 (GetG mem) && v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal => (LoweredGetG mem) // only lower in old ABI. in new ABI we have a G register.
509 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
510 (GetCallerPC ...) => (LoweredGetCallerPC ...)
511 (GetCallerSP ...) => (LoweredGetCallerSP ...)
512
513 (HasCPUFeature {s}) => (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s})))
514 (Addr {sym} base) => (LEAQ {sym} base)
515 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (LEAQ {sym} (SPanchored base mem))
516 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (LEAQ {sym} base)
517
518 (MOVBstore [off] {sym} ptr y:(SETL x) mem) && y.Uses == 1 => (SETLstore [off] {sym} ptr x mem)
519 (MOVBstore [off] {sym} ptr y:(SETLE x) mem) && y.Uses == 1 => (SETLEstore [off] {sym} ptr x mem)
520 (MOVBstore [off] {sym} ptr y:(SETG x) mem) && y.Uses == 1 => (SETGstore [off] {sym} ptr x mem)
521 (MOVBstore [off] {sym} ptr y:(SETGE x) mem) && y.Uses == 1 => (SETGEstore [off] {sym} ptr x mem)
522 (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) && y.Uses == 1 => (SETEQstore [off] {sym} ptr x mem)
523 (MOVBstore [off] {sym} ptr y:(SETNE x) mem) && y.Uses == 1 => (SETNEstore [off] {sym} ptr x mem)
524 (MOVBstore [off] {sym} ptr y:(SETB x) mem) && y.Uses == 1 => (SETBstore [off] {sym} ptr x mem)
525 (MOVBstore [off] {sym} ptr y:(SETBE x) mem) && y.Uses == 1 => (SETBEstore [off] {sym} ptr x mem)
526 (MOVBstore [off] {sym} ptr y:(SETA x) mem) && y.Uses == 1 => (SETAstore [off] {sym} ptr x mem)
527 (MOVBstore [off] {sym} ptr y:(SETAE x) mem) && y.Uses == 1 => (SETAEstore [off] {sym} ptr x mem)
528
529 // block rewrites
530 (If (SETL cmp) yes no) => (LT cmp yes no)
531 (If (SETLE cmp) yes no) => (LE cmp yes no)
532 (If (SETG cmp) yes no) => (GT cmp yes no)
533 (If (SETGE cmp) yes no) => (GE cmp yes no)
534 (If (SETEQ cmp) yes no) => (EQ cmp yes no)
535 (If (SETNE cmp) yes no) => (NE cmp yes no)
536 (If (SETB cmp) yes no) => (ULT cmp yes no)
537 (If (SETBE cmp) yes no) => (ULE cmp yes no)
538 (If (SETA cmp) yes no) => (UGT cmp yes no)
539 (If (SETAE cmp) yes no) => (UGE cmp yes no)
540 (If (SETO cmp) yes no) => (OS cmp yes no)
541
542 // Special case for floating point - LF/LEF not generated
543 (If (SETGF cmp) yes no) => (UGT cmp yes no)
544 (If (SETGEF cmp) yes no) => (UGE cmp yes no)
545 (If (SETEQF cmp) yes no) => (EQF cmp yes no)
546 (If (SETNEF cmp) yes no) => (NEF cmp yes no)
547
548 (If cond yes no) => (NE (TESTB cond cond) yes no)
549
550 (JumpTable idx) => (JUMPTABLE {makeJumpTableSym(b)} idx (LEAQ <typ.Uintptr> {makeJumpTableSym(b)} (SB)))
551
552 // Atomic loads. Other than preserving their ordering with respect to other loads, nothing special here.
553 (AtomicLoad8 ptr mem) => (MOVBatomicload ptr mem)
554 (AtomicLoad32 ptr mem) => (MOVLatomicload ptr mem)
555 (AtomicLoad64 ptr mem) => (MOVQatomicload ptr mem)
556 (AtomicLoadPtr ptr mem) => (MOVQatomicload ptr mem)
557
558 // Atomic stores. We use XCHG to prevent the hardware reordering a subsequent load.
559 // TODO: most runtime uses of atomic stores don't need that property. Use normal stores for those?
560 (AtomicStore8 ptr val mem) => (Select1 (XCHGB <types.NewTuple(typ.UInt8,types.TypeMem)> val ptr mem))
561 (AtomicStore32 ptr val mem) => (Select1 (XCHGL <types.NewTuple(typ.UInt32,types.TypeMem)> val ptr mem))
562 (AtomicStore64 ptr val mem) => (Select1 (XCHGQ <types.NewTuple(typ.UInt64,types.TypeMem)> val ptr mem))
563 (AtomicStorePtrNoWB ptr val mem) => (Select1 (XCHGQ <types.NewTuple(typ.BytePtr,types.TypeMem)> val ptr mem))
564
565 // Atomic exchanges.
566 (AtomicExchange32 ptr val mem) => (XCHGL val ptr mem)
567 (AtomicExchange64 ptr val mem) => (XCHGQ val ptr mem)
568
569 // Atomic adds.
570 (AtomicAdd32 ptr val mem) => (AddTupleFirst32 val (XADDLlock val ptr mem))
571 (AtomicAdd64 ptr val mem) => (AddTupleFirst64 val (XADDQlock val ptr mem))
572 (Select0 <t> (AddTupleFirst32 val tuple)) => (ADDL val (Select0 <t> tuple))
573 (Select1 (AddTupleFirst32 _ tuple)) => (Select1 tuple)
574 (Select0 <t> (AddTupleFirst64 val tuple)) => (ADDQ val (Select0 <t> tuple))
575 (Select1 (AddTupleFirst64 _ tuple)) => (Select1 tuple)
576
577 // Atomic compare and swap.
578 (AtomicCompareAndSwap32 ptr old new_ mem) => (CMPXCHGLlock ptr old new_ mem)
579 (AtomicCompareAndSwap64 ptr old new_ mem) => (CMPXCHGQlock ptr old new_ mem)
580
581 // Atomic memory updates.
582 (AtomicAnd8 ptr val mem) => (ANDBlock ptr val mem)
583 (AtomicAnd32 ptr val mem) => (ANDLlock ptr val mem)
584 (AtomicOr8 ptr val mem) => (ORBlock ptr val mem)
585 (AtomicOr32 ptr val mem) => (ORLlock ptr val mem)
586
587 // Write barrier.
588 (WB ...) => (LoweredWB ...)
589
590 (PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
591 (PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
592 (PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
593
594 // lowering rotates
595 (RotateLeft8 ...) => (ROLB ...)
596 (RotateLeft16 ...) => (ROLW ...)
597 (RotateLeft32 ...) => (ROLL ...)
598 (RotateLeft64 ...) => (ROLQ ...)
599
600 // ***************************
601 // Above: lowering rules
602 // Below: optimizations
603 // ***************************
604 // TODO: Should the optimizations be a separate pass?
605
606 // Fold boolean tests into blocks
607 (NE (TESTB (SETL cmp) (SETL cmp)) yes no) => (LT cmp yes no)
608 (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) => (LE cmp yes no)
609 (NE (TESTB (SETG cmp) (SETG cmp)) yes no) => (GT cmp yes no)
610 (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) => (GE cmp yes no)
611 (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) => (EQ cmp yes no)
612 (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) => (NE cmp yes no)
613 (NE (TESTB (SETB cmp) (SETB cmp)) yes no) => (ULT cmp yes no)
614 (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) => (ULE cmp yes no)
615 (NE (TESTB (SETA cmp) (SETA cmp)) yes no) => (UGT cmp yes no)
616 (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) => (UGE cmp yes no)
617 (NE (TESTB (SETO cmp) (SETO cmp)) yes no) => (OS cmp yes no)
618
619 // Unsigned comparisons to 0/1
620 (ULT (TEST(Q|L|W|B) x x) yes no) => (First no yes)
621 (UGE (TEST(Q|L|W|B) x x) yes no) => (First yes no)
622 (SETB (TEST(Q|L|W|B) x x)) => (ConstBool [false])
623 (SETAE (TEST(Q|L|W|B) x x)) => (ConstBool [true])
624
625 // x & 1 != 0 -> x & 1
626 (SETNE (TEST(B|W)const [1] x)) => (AND(L|L)const [1] x)
627 (SETB (BT(L|Q)const [0] x)) => (AND(L|Q)const [1] x)
628
629 // Recognize bit tests: a&(1<<b) != 0 for b suitably bounded
630 // Note that BTx instructions use the carry bit, so we need to convert tests for zero flag
631 // into tests for carry flags.
632 // ULT and SETB check the carry flag; they are identical to CS and SETCS. Same, mutatis
633 // mutandis, for UGE and SETAE, and CC and SETCC.
634 ((NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => ((ULT|UGE) (BTL x y))
635 ((NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => ((ULT|UGE) (BTQ x y))
636 ((NE|EQ) (TESTLconst [c] x)) && isUint32PowerOfTwo(int64(c))
637 => ((ULT|UGE) (BTLconst [int8(log32(c))] x))
638 ((NE|EQ) (TESTQconst [c] x)) && isUint64PowerOfTwo(int64(c))
639 => ((ULT|UGE) (BTQconst [int8(log32(c))] x))
640 ((NE|EQ) (TESTQ (MOVQconst [c]) x)) && isUint64PowerOfTwo(c)
641 => ((ULT|UGE) (BTQconst [int8(log64(c))] x))
642 (SET(NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => (SET(B|AE) (BTL x y))
643 (SET(NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => (SET(B|AE) (BTQ x y))
644 (SET(NE|EQ) (TESTLconst [c] x)) && isUint32PowerOfTwo(int64(c))
645 => (SET(B|AE) (BTLconst [int8(log32(c))] x))
646 (SET(NE|EQ) (TESTQconst [c] x)) && isUint64PowerOfTwo(int64(c))
647 => (SET(B|AE) (BTQconst [int8(log32(c))] x))
648 (SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && isUint64PowerOfTwo(c)
649 => (SET(B|AE) (BTQconst [int8(log64(c))] x))
650 // SET..store variant
651 (SET(NE|EQ)store [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem)
652 => (SET(B|AE)store [off] {sym} ptr (BTL x y) mem)
653 (SET(NE|EQ)store [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem)
654 => (SET(B|AE)store [off] {sym} ptr (BTQ x y) mem)
655 (SET(NE|EQ)store [off] {sym} ptr (TESTLconst [c] x) mem) && isUint32PowerOfTwo(int64(c))
656 => (SET(B|AE)store [off] {sym} ptr (BTLconst [int8(log32(c))] x) mem)
657 (SET(NE|EQ)store [off] {sym} ptr (TESTQconst [c] x) mem) && isUint64PowerOfTwo(int64(c))
658 => (SET(B|AE)store [off] {sym} ptr (BTQconst [int8(log32(c))] x) mem)
659 (SET(NE|EQ)store [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && isUint64PowerOfTwo(c)
660 => (SET(B|AE)store [off] {sym} ptr (BTQconst [int8(log64(c))] x) mem)
661
662 // Handle bit-testing in the form (a>>b)&1 != 0 by building the above rules
663 // and further combining shifts.
664 (BT(Q|L)const [c] (SHRQconst [d] x)) && (c+d)<64 => (BTQconst [c+d] x)
665 (BT(Q|L)const [c] (SHLQconst [d] x)) && c>d => (BT(Q|L)const [c-d] x)
666 (BT(Q|L)const [0] s:(SHRQ x y)) => (BTQ y x)
667 (BTLconst [c] (SHRLconst [d] x)) && (c+d)<32 => (BTLconst [c+d] x)
668 (BTLconst [c] (SHLLconst [d] x)) && c>d => (BTLconst [c-d] x)
669 (BTLconst [0] s:(SHR(L|XL) x y)) => (BTL y x)
670
671 // Rewrite a & 1 != 1 into a & 1 == 0.
672 // Among other things, this lets us turn (a>>b)&1 != 1 into a bit test.
673 (SET(NE|EQ) (CMPLconst [1] s:(ANDLconst [1] _))) => (SET(EQ|NE) (CMPLconst [0] s))
674 (SET(NE|EQ)store [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) => (SET(EQ|NE)store [off] {sym} ptr (CMPLconst [0] s) mem)
675 (SET(NE|EQ) (CMPQconst [1] s:(ANDQconst [1] _))) => (SET(EQ|NE) (CMPQconst [0] s))
676 (SET(NE|EQ)store [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) => (SET(EQ|NE)store [off] {sym} ptr (CMPQconst [0] s) mem)
677
678 // Recognize bit setting (a |= 1<<b) and toggling (a ^= 1<<b)
679 (OR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTS(Q|L) x y)
680 (XOR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTC(Q|L) x y)
681 // Note: only convert OR/XOR to BTS/BTC if the constant wouldn't fit in
682 // the constant field of the OR/XOR instruction. See issue 61694.
683 ((OR|XOR)Q (MOVQconst [c]) x) && isUint64PowerOfTwo(c) && uint64(c) >= 1<<31 => (BT(S|C)Qconst [int8(log64(c))] x)
684
685 // Recognize bit clearing: a &^= 1<<b
686 (AND(Q|L) (NOT(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y)) x) => (BTR(Q|L) x y)
687 (ANDN(Q|L) x (SHL(Q|L) (MOV(Q|L)const [1]) y)) => (BTR(Q|L) x y)
688 // Note: only convert AND to BTR if the constant wouldn't fit in
689 // the constant field of the AND instruction. See issue 61694.
690 (ANDQ (MOVQconst [c]) x) && isUint64PowerOfTwo(^c) && uint64(^c) >= 1<<31 => (BTRQconst [int8(log64(^c))] x)
691
692 // Special-case bit patterns on first/last bit.
693 // generic.rules changes ANDs of high-part/low-part masks into a couple of shifts,
694 // for instance:
695 // x & 0xFFFF0000 -> (x >> 16) << 16
696 // x & 0x80000000 -> (x >> 31) << 31
697 //
698 // In case the mask is just one bit (like second example above), it conflicts
699 // with the above rules to detect bit-testing / bit-clearing of first/last bit.
700 // We thus special-case them, by detecting the shift patterns.
701
702 // Special case resetting first/last bit
703 (SHL(L|Q)const [1] (SHR(L|Q)const [1] x))
704 => (AND(L|Q)const [-2] x)
705 (SHRLconst [1] (SHLLconst [1] x))
706 => (ANDLconst [0x7fffffff] x)
707 (SHRQconst [1] (SHLQconst [1] x))
708 => (BTRQconst [63] x)
709
710 // Special case testing first/last bit (with double-shift generated by generic.rules)
711 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) && z1==z2
712 => ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
713 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) && z1==z2
714 => ((SETB|SETAE|ULT|UGE) (BTQconst [31] x))
715 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) && z1==z2
716 => (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
717 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) && z1==z2
718 => (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)
719
720 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) && z1==z2
721 => ((SETB|SETAE|ULT|UGE) (BTQconst [0] x))
722 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) && z1==z2
723 => ((SETB|SETAE|ULT|UGE) (BTLconst [0] x))
724 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) && z1==z2
725 => (SET(B|AE)store [off] {sym} ptr (BTQconst [0] x) mem)
726 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) && z1==z2
727 => (SET(B|AE)store [off] {sym} ptr (BTLconst [0] x) mem)
728
729 // Special-case manually testing last bit with "a>>63 != 0" (without "&1")
730 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] x) z2)) && z1==z2
731 => ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
732 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] x) z2)) && z1==z2
733 => ((SETB|SETAE|ULT|UGE) (BTLconst [31] x))
734 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) && z1==z2
735 => (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
736 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) && z1==z2
737 => (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)
738
739 // Fold combinations of bit ops on same bit. An example is math.Copysign(c,-1)
740 (BTSQconst [c] (BTRQconst [c] x)) => (BTSQconst [c] x)
741 (BTSQconst [c] (BTCQconst [c] x)) => (BTSQconst [c] x)
742 (BTRQconst [c] (BTSQconst [c] x)) => (BTRQconst [c] x)
743 (BTRQconst [c] (BTCQconst [c] x)) => (BTRQconst [c] x)
744
745 // Fold boolean negation into SETcc.
746 (XORLconst [1] (SETNE x)) => (SETEQ x)
747 (XORLconst [1] (SETEQ x)) => (SETNE x)
748 (XORLconst [1] (SETL x)) => (SETGE x)
749 (XORLconst [1] (SETGE x)) => (SETL x)
750 (XORLconst [1] (SETLE x)) => (SETG x)
751 (XORLconst [1] (SETG x)) => (SETLE x)
752 (XORLconst [1] (SETB x)) => (SETAE x)
753 (XORLconst [1] (SETAE x)) => (SETB x)
754 (XORLconst [1] (SETBE x)) => (SETA x)
755 (XORLconst [1] (SETA x)) => (SETBE x)
756
757 // Special case for floating point - LF/LEF not generated
758 (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) => (UGT cmp yes no)
759 (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) => (UGE cmp yes no)
760 (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) => (EQF cmp yes no)
761 (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) => (NEF cmp yes no)
762
763 // Disabled because it interferes with the pattern match above and makes worse code.
764 // (SETNEF x) => (ORQ (SETNE <typ.Int8> x) (SETNAN <typ.Int8> x))
765 // (SETEQF x) => (ANDQ (SETEQ <typ.Int8> x) (SETORD <typ.Int8> x))
766
767 // fold constants into instructions
768 (ADDQ x (MOVQconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDQconst [int32(c)] x)
769 (ADDQ x (MOVLconst [c])) => (ADDQconst [c] x)
770 (ADDL x (MOVLconst [c])) => (ADDLconst [c] x)
771
772 (SUBQ x (MOVQconst [c])) && is32Bit(c) => (SUBQconst x [int32(c)])
773 (SUBQ (MOVQconst [c]) x) && is32Bit(c) => (NEGQ (SUBQconst <v.Type> x [int32(c)]))
774 (SUBL x (MOVLconst [c])) => (SUBLconst x [c])
775 (SUBL (MOVLconst [c]) x) => (NEGL (SUBLconst <v.Type> x [c]))
776
777 (MULQ x (MOVQconst [c])) && is32Bit(c) => (MULQconst [int32(c)] x)
778 (MULL x (MOVLconst [c])) => (MULLconst [c] x)
779
780 (ANDQ x (MOVQconst [c])) && is32Bit(c) => (ANDQconst [int32(c)] x)
781 (ANDL x (MOVLconst [c])) => (ANDLconst [c] x)
782
783 (AND(L|Q)const [c] (AND(L|Q)const [d] x)) => (AND(L|Q)const [c & d] x)
784 (XOR(L|Q)const [c] (XOR(L|Q)const [d] x)) => (XOR(L|Q)const [c ^ d] x)
785 (OR(L|Q)const [c] (OR(L|Q)const [d] x)) => (OR(L|Q)const [c | d] x)
786
787 (MULLconst [c] (MULLconst [d] x)) => (MULLconst [c * d] x)
788 (MULQconst [c] (MULQconst [d] x)) && is32Bit(int64(c)*int64(d)) => (MULQconst [c * d] x)
789
790 (ORQ x (MOVQconst [c])) && is32Bit(c) => (ORQconst [int32(c)] x)
791 (ORQ x (MOVLconst [c])) => (ORQconst [c] x)
792 (ORL x (MOVLconst [c])) => (ORLconst [c] x)
793
794 (XORQ x (MOVQconst [c])) && is32Bit(c) => (XORQconst [int32(c)] x)
795 (XORL x (MOVLconst [c])) => (XORLconst [c] x)
796
797 (SHLQ x (MOV(Q|L)const [c])) => (SHLQconst [int8(c&63)] x)
798 (SHLL x (MOV(Q|L)const [c])) => (SHLLconst [int8(c&31)] x)
799
800 (SHRQ x (MOV(Q|L)const [c])) => (SHRQconst [int8(c&63)] x)
801 (SHRL x (MOV(Q|L)const [c])) => (SHRLconst [int8(c&31)] x)
802 (SHRW x (MOV(Q|L)const [c])) && c&31 < 16 => (SHRWconst [int8(c&31)] x)
803 (SHRW _ (MOV(Q|L)const [c])) && c&31 >= 16 => (MOVLconst [0])
804 (SHRB x (MOV(Q|L)const [c])) && c&31 < 8 => (SHRBconst [int8(c&31)] x)
805 (SHRB _ (MOV(Q|L)const [c])) && c&31 >= 8 => (MOVLconst [0])
806
807 (SARQ x (MOV(Q|L)const [c])) => (SARQconst [int8(c&63)] x)
808 (SARL x (MOV(Q|L)const [c])) => (SARLconst [int8(c&31)] x)
809 (SARW x (MOV(Q|L)const [c])) => (SARWconst [int8(min(int64(c)&31,15))] x)
810 (SARB x (MOV(Q|L)const [c])) => (SARBconst [int8(min(int64(c)&31,7))] x)
811
812 // Operations which don't affect the low 6/5 bits of the shift amount are NOPs.
813 ((SHLQ|SHRQ|SARQ) x (ADDQconst [c] y)) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x y)
814 ((SHLQ|SHRQ|SARQ) x (NEGQ <t> (ADDQconst [c] y))) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x (NEGQ <t> y))
815 ((SHLQ|SHRQ|SARQ) x (ANDQconst [c] y)) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x y)
816 ((SHLQ|SHRQ|SARQ) x (NEGQ <t> (ANDQconst [c] y))) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x (NEGQ <t> y))
817
818 ((SHLL|SHRL|SARL) x (ADDQconst [c] y)) && c & 31 == 0 => ((SHLL|SHRL|SARL) x y)
819 ((SHLL|SHRL|SARL) x (NEGQ <t> (ADDQconst [c] y))) && c & 31 == 0 => ((SHLL|SHRL|SARL) x (NEGQ <t> y))
820 ((SHLL|SHRL|SARL) x (ANDQconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
821 ((SHLL|SHRL|SARL) x (NEGQ <t> (ANDQconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGQ <t> y))
822
823 ((SHLQ|SHRQ|SARQ) x (ADDLconst [c] y)) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x y)
824 ((SHLQ|SHRQ|SARQ) x (NEGL <t> (ADDLconst [c] y))) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x (NEGL <t> y))
825 ((SHLQ|SHRQ|SARQ) x (ANDLconst [c] y)) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x y)
826 ((SHLQ|SHRQ|SARQ) x (NEGL <t> (ANDLconst [c] y))) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x (NEGL <t> y))
827
828 ((SHLL|SHRL|SARL) x (ADDLconst [c] y)) && c & 31 == 0 => ((SHLL|SHRL|SARL) x y)
829 ((SHLL|SHRL|SARL) x (NEGL <t> (ADDLconst [c] y))) && c & 31 == 0 => ((SHLL|SHRL|SARL) x (NEGL <t> y))
830 ((SHLL|SHRL|SARL) x (ANDLconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
831 ((SHLL|SHRL|SARL) x (NEGL <t> (ANDLconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGL <t> y))
832
833 // rotate left negative = rotate right
834 (ROLQ x (NEG(Q|L) y)) => (RORQ x y)
835 (ROLL x (NEG(Q|L) y)) => (RORL x y)
836 (ROLW x (NEG(Q|L) y)) => (RORW x y)
837 (ROLB x (NEG(Q|L) y)) => (RORB x y)
838
839 // rotate right negative = rotate left
840 (RORQ x (NEG(Q|L) y)) => (ROLQ x y)
841 (RORL x (NEG(Q|L) y)) => (ROLL x y)
842 (RORW x (NEG(Q|L) y)) => (ROLW x y)
843 (RORB x (NEG(Q|L) y)) => (ROLB x y)
844
845 // rotate by constants
846 (ROLQ x (MOV(Q|L)const [c])) => (ROLQconst [int8(c&63)] x)
847 (ROLL x (MOV(Q|L)const [c])) => (ROLLconst [int8(c&31)] x)
848 (ROLW x (MOV(Q|L)const [c])) => (ROLWconst [int8(c&15)] x)
849 (ROLB x (MOV(Q|L)const [c])) => (ROLBconst [int8(c&7) ] x)
850
851 (RORQ x (MOV(Q|L)const [c])) => (ROLQconst [int8((-c)&63)] x)
852 (RORL x (MOV(Q|L)const [c])) => (ROLLconst [int8((-c)&31)] x)
853 (RORW x (MOV(Q|L)const [c])) => (ROLWconst [int8((-c)&15)] x)
854 (RORB x (MOV(Q|L)const [c])) => (ROLBconst [int8((-c)&7) ] x)
855
856 // Constant shift simplifications
857 ((SHLQ|SHRQ|SARQ)const x [0]) => x
858 ((SHLL|SHRL|SARL)const x [0]) => x
859 ((SHRW|SARW)const x [0]) => x
860 ((SHRB|SARB)const x [0]) => x
861 ((ROLQ|ROLL|ROLW|ROLB)const x [0]) => x
862
863 // Multi-register shifts
864 (ORQ (SH(R|L)Q lo bits) (SH(L|R)Q hi (NEGQ bits))) => (SH(R|L)DQ lo hi bits)
865 (ORQ (SH(R|L)XQ lo bits) (SH(L|R)XQ hi (NEGQ bits))) => (SH(R|L)DQ lo hi bits)
866
867 // Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits)
868 // because the x86 instructions are defined to use all 5 bits of the shift even
869 // for the small shifts. I don't think we'll ever generate a weird shift (e.g.
870 // (SHRW x (MOVLconst [24])), but just in case.
871
872 (CMPQ x (MOVQconst [c])) && is32Bit(c) => (CMPQconst x [int32(c)])
873 (CMPQ (MOVQconst [c]) x) && is32Bit(c) => (InvertFlags (CMPQconst x [int32(c)]))
874 (CMPL x (MOVLconst [c])) => (CMPLconst x [c])
875 (CMPL (MOVLconst [c]) x) => (InvertFlags (CMPLconst x [c]))
876 (CMPW x (MOVLconst [c])) => (CMPWconst x [int16(c)])
877 (CMPW (MOVLconst [c]) x) => (InvertFlags (CMPWconst x [int16(c)]))
878 (CMPB x (MOVLconst [c])) => (CMPBconst x [int8(c)])
879 (CMPB (MOVLconst [c]) x) => (InvertFlags (CMPBconst x [int8(c)]))
880
881 // Canonicalize the order of arguments to comparisons - helps with CSE.
882 (CMP(Q|L|W|B) x y) && canonLessThan(x,y) => (InvertFlags (CMP(Q|L|W|B) y x))
883
884 // Using MOVZX instead of AND is cheaper.
885 (AND(Q|L)const [ 0xFF] x) => (MOVBQZX x)
886 (AND(Q|L)const [0xFFFF] x) => (MOVWQZX x)
887 // This rule is currently invalid because 0xFFFFFFFF is not representable by a signed int32.
888 // Commenting out for now, because it also can't trigger because of the is32bit guard on the
889 // ANDQconst lowering-rule, above, prevents 0xFFFFFFFF from matching (for the same reason)
890 // Using an alternate form of this rule segfaults some binaries because of
891 // adverse interactions with other passes.
892 // (ANDQconst [0xFFFFFFFF] x) => (MOVLQZX x)
893
894 // strength reduction
895 // Assumes that the following costs from https://gmplib.org/~tege/x86-timing.pdf:
896 // 1 - addq, shlq, leaq, negq, subq
897 // 3 - imulq
898 // This limits the rewrites to two instructions.
899 // Note that negq always operates in-place,
900 // which can require a register-register move
901 // to preserve the original value,
902 // so it must be used with care.
903 (MUL(Q|L)const [-9] x) => (NEG(Q|L) (LEA(Q|L)8 <v.Type> x x))
904 (MUL(Q|L)const [-5] x) => (NEG(Q|L) (LEA(Q|L)4 <v.Type> x x))
905 (MUL(Q|L)const [-3] x) => (NEG(Q|L) (LEA(Q|L)2 <v.Type> x x))
906 (MUL(Q|L)const [-1] x) => (NEG(Q|L) x)
907 (MUL(Q|L)const [ 0] _) => (MOV(Q|L)const [0])
908 (MUL(Q|L)const [ 1] x) => x
909 (MUL(Q|L)const [ 3] x) => (LEA(Q|L)2 x x)
910 (MUL(Q|L)const [ 5] x) => (LEA(Q|L)4 x x)
911 (MUL(Q|L)const [ 7] x) => (LEA(Q|L)2 x (LEA(Q|L)2 <v.Type> x x))
912 (MUL(Q|L)const [ 9] x) => (LEA(Q|L)8 x x)
913 (MUL(Q|L)const [11] x) => (LEA(Q|L)2 x (LEA(Q|L)4 <v.Type> x x))
914 (MUL(Q|L)const [13] x) => (LEA(Q|L)4 x (LEA(Q|L)2 <v.Type> x x))
915 (MUL(Q|L)const [19] x) => (LEA(Q|L)2 x (LEA(Q|L)8 <v.Type> x x))
916 (MUL(Q|L)const [21] x) => (LEA(Q|L)4 x (LEA(Q|L)4 <v.Type> x x))
917 (MUL(Q|L)const [25] x) => (LEA(Q|L)8 x (LEA(Q|L)2 <v.Type> x x))
918 (MUL(Q|L)const [27] x) => (LEA(Q|L)8 (LEA(Q|L)2 <v.Type> x x) (LEA(Q|L)2 <v.Type> x x))
919 (MUL(Q|L)const [37] x) => (LEA(Q|L)4 x (LEA(Q|L)8 <v.Type> x x))
920 (MUL(Q|L)const [41] x) => (LEA(Q|L)8 x (LEA(Q|L)4 <v.Type> x x))
921 (MUL(Q|L)const [45] x) => (LEA(Q|L)8 (LEA(Q|L)4 <v.Type> x x) (LEA(Q|L)4 <v.Type> x x))
922 (MUL(Q|L)const [73] x) => (LEA(Q|L)8 x (LEA(Q|L)8 <v.Type> x x))
923 (MUL(Q|L)const [81] x) => (LEA(Q|L)8 (LEA(Q|L)8 <v.Type> x x) (LEA(Q|L)8 <v.Type> x x))
924
925 (MUL(Q|L)const [c] x) && isPowerOfTwo64(int64(c)+1) && c >= 15 => (SUB(Q|L) (SHL(Q|L)const <v.Type> [int8(log64(int64(c)+1))] x) x)
926 (MUL(Q|L)const [c] x) && isPowerOfTwo32(c-1) && c >= 17 => (LEA(Q|L)1 (SHL(Q|L)const <v.Type> [int8(log32(c-1))] x) x)
927 (MUL(Q|L)const [c] x) && isPowerOfTwo32(c-2) && c >= 34 => (LEA(Q|L)2 (SHL(Q|L)const <v.Type> [int8(log32(c-2))] x) x)
928 (MUL(Q|L)const [c] x) && isPowerOfTwo32(c-4) && c >= 68 => (LEA(Q|L)4 (SHL(Q|L)const <v.Type> [int8(log32(c-4))] x) x)
929 (MUL(Q|L)const [c] x) && isPowerOfTwo32(c-8) && c >= 136 => (LEA(Q|L)8 (SHL(Q|L)const <v.Type> [int8(log32(c-8))] x) x)
930 (MUL(Q|L)const [c] x) && c%3 == 0 && isPowerOfTwo32(c/3) => (SHL(Q|L)const [int8(log32(c/3))] (LEA(Q|L)2 <v.Type> x x))
931 (MUL(Q|L)const [c] x) && c%5 == 0 && isPowerOfTwo32(c/5) => (SHL(Q|L)const [int8(log32(c/5))] (LEA(Q|L)4 <v.Type> x x))
932 (MUL(Q|L)const [c] x) && c%9 == 0 && isPowerOfTwo32(c/9) => (SHL(Q|L)const [int8(log32(c/9))] (LEA(Q|L)8 <v.Type> x x))
933
934 // combine add/shift into LEAQ/LEAL
935 (ADD(L|Q) x (SHL(L|Q)const [3] y)) => (LEA(L|Q)8 x y)
936 (ADD(L|Q) x (SHL(L|Q)const [2] y)) => (LEA(L|Q)4 x y)
937 (ADD(L|Q) x (SHL(L|Q)const [1] y)) => (LEA(L|Q)2 x y)
938 (ADD(L|Q) x (ADD(L|Q) y y)) => (LEA(L|Q)2 x y)
939 (ADD(L|Q) x (ADD(L|Q) x y)) => (LEA(L|Q)2 y x)
940
941 // combine ADDQ/ADDQconst into LEAQ1/LEAL1
942 (ADD(Q|L)const [c] (ADD(Q|L) x y)) => (LEA(Q|L)1 [c] x y)
943 (ADD(Q|L) (ADD(Q|L)const [c] x) y) => (LEA(Q|L)1 [c] x y)
944 (ADD(Q|L)const [c] (SHL(Q|L)const [1] x)) => (LEA(Q|L)1 [c] x x)
945
946 // fold ADDQ/ADDL into LEAQ/LEAL
947 (ADD(Q|L)const [c] (LEA(Q|L) [d] {s} x)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L) [c+d] {s} x)
948 (LEA(Q|L) [c] {s} (ADD(Q|L)const [d] x)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L) [c+d] {s} x)
949 (LEA(Q|L) [c] {s} (ADD(Q|L) x y)) && x.Op != OpSB && y.Op != OpSB => (LEA(Q|L)1 [c] {s} x y)
950 (ADD(Q|L) x (LEA(Q|L) [c] {s} y)) && x.Op != OpSB && y.Op != OpSB => (LEA(Q|L)1 [c] {s} x y)
951
952 // fold ADDQconst/ADDLconst into LEAQx/LEALx
953 (ADD(Q|L)const [c] (LEA(Q|L)1 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)1 [c+d] {s} x y)
954 (ADD(Q|L)const [c] (LEA(Q|L)2 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)2 [c+d] {s} x y)
955 (ADD(Q|L)const [c] (LEA(Q|L)4 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)4 [c+d] {s} x y)
956 (ADD(Q|L)const [c] (LEA(Q|L)8 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEA(Q|L)8 [c+d] {s} x y)
957 (LEA(Q|L)1 [c] {s} (ADD(Q|L)const [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEA(Q|L)1 [c+d] {s} x y)
958 (LEA(Q|L)2 [c] {s} (ADD(Q|L)const [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEA(Q|L)2 [c+d] {s} x y)
959 (LEA(Q|L)2 [c] {s} x (ADD(Q|L)const [d] y)) && is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB => (LEA(Q|L)2 [c+2*d] {s} x y)
960 (LEA(Q|L)4 [c] {s} (ADD(Q|L)const [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEA(Q|L)4 [c+d] {s} x y)
961 (LEA(Q|L)4 [c] {s} x (ADD(Q|L)const [d] y)) && is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB => (LEA(Q|L)4 [c+4*d] {s} x y)
962 (LEA(Q|L)8 [c] {s} (ADD(Q|L)const [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEA(Q|L)8 [c+d] {s} x y)
963 (LEA(Q|L)8 [c] {s} x (ADD(Q|L)const [d] y)) && is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB => (LEA(Q|L)8 [c+8*d] {s} x y)
964
965 // fold shifts into LEAQx/LEALx
966 (LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [1] y)) => (LEA(Q|L)2 [c] {s} x y)
967 (LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [2] y)) => (LEA(Q|L)4 [c] {s} x y)
968 (LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [3] y)) => (LEA(Q|L)8 [c] {s} x y)
969 (LEA(Q|L)2 [c] {s} x (SHL(Q|L)const [1] y)) => (LEA(Q|L)4 [c] {s} x y)
970 (LEA(Q|L)2 [c] {s} x (SHL(Q|L)const [2] y)) => (LEA(Q|L)8 [c] {s} x y)
971 (LEA(Q|L)4 [c] {s} x (SHL(Q|L)const [1] y)) => (LEA(Q|L)8 [c] {s} x y)
972
973 // reverse ordering of compare instruction
974 (SETL (InvertFlags x)) => (SETG x)
975 (SETG (InvertFlags x)) => (SETL x)
976 (SETB (InvertFlags x)) => (SETA x)
977 (SETA (InvertFlags x)) => (SETB x)
978 (SETLE (InvertFlags x)) => (SETGE x)
979 (SETGE (InvertFlags x)) => (SETLE x)
980 (SETBE (InvertFlags x)) => (SETAE x)
981 (SETAE (InvertFlags x)) => (SETBE x)
982 (SETEQ (InvertFlags x)) => (SETEQ x)
983 (SETNE (InvertFlags x)) => (SETNE x)
984
985 (SETLstore [off] {sym} ptr (InvertFlags x) mem) => (SETGstore [off] {sym} ptr x mem)
986 (SETGstore [off] {sym} ptr (InvertFlags x) mem) => (SETLstore [off] {sym} ptr x mem)
987 (SETBstore [off] {sym} ptr (InvertFlags x) mem) => (SETAstore [off] {sym} ptr x mem)
988 (SETAstore [off] {sym} ptr (InvertFlags x) mem) => (SETBstore [off] {sym} ptr x mem)
989 (SETLEstore [off] {sym} ptr (InvertFlags x) mem) => (SETGEstore [off] {sym} ptr x mem)
990 (SETGEstore [off] {sym} ptr (InvertFlags x) mem) => (SETLEstore [off] {sym} ptr x mem)
991 (SETBEstore [off] {sym} ptr (InvertFlags x) mem) => (SETAEstore [off] {sym} ptr x mem)
992 (SETAEstore [off] {sym} ptr (InvertFlags x) mem) => (SETBEstore [off] {sym} ptr x mem)
993 (SETEQstore [off] {sym} ptr (InvertFlags x) mem) => (SETEQstore [off] {sym} ptr x mem)
994 (SETNEstore [off] {sym} ptr (InvertFlags x) mem) => (SETNEstore [off] {sym} ptr x mem)
995
996 // sign extended loads
997 // Note: The combined instruction must end up in the same block
998 // as the original load. If not, we end up making a value with
999 // memory type live in two different blocks, which can lead to
1000 // multiple memory values alive simultaneously.
1001 // Make sure we don't combine these ops if the load has another use.
1002 // This prevents a single load from being split into multiple loads
1003 // which then might return different values. See test/atomicload.go.
1004 (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
1005 (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
1006 (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
1007 (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
1008 (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
1009 (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
1010 (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
1011 (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
1012 (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
1013 (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
1014 (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
1015 (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
1016 (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
1017 (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
1018 (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
1019 (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
1020 (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
1021 (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
1022
1023 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
1024 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBQZX x)
1025 (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWQZX x)
1026 (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVLQZX x)
1027 (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
1028 (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBQSX x)
1029 (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWQSX x)
1030 (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVLQSX x)
1031
1032 // Fold extensions and ANDs together.
1033 (MOVBQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xff] x)
1034 (MOVWQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xffff] x)
1035 (MOVLQZX (ANDLconst [c] x)) => (ANDLconst [c] x)
1036 (MOVBQSX (ANDLconst [c] x)) && c & 0x80 == 0 => (ANDLconst [c & 0x7f] x)
1037 (MOVWQSX (ANDLconst [c] x)) && c & 0x8000 == 0 => (ANDLconst [c & 0x7fff] x)
1038 (MOVLQSX (ANDLconst [c] x)) && uint32(c) & 0x80000000 == 0 => (ANDLconst [c & 0x7fffffff] x)
1039
1040 // Don't extend before storing
1041 (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) => (MOVLstore [off] {sym} ptr x mem)
1042 (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) => (MOVWstore [off] {sym} ptr x mem)
1043 (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) => (MOVBstore [off] {sym} ptr x mem)
1044 (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) => (MOVLstore [off] {sym} ptr x mem)
1045 (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) => (MOVWstore [off] {sym} ptr x mem)
1046 (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) => (MOVBstore [off] {sym} ptr x mem)
1047
1048 // fold constants into memory operations
1049 // Note that this is not always a good idea because if not all the uses of
1050 // the ADDQconst get eliminated, we still have to compute the ADDQconst and we now
1051 // have potentially two live values (ptr and (ADDQconst [off] ptr)) instead of one.
1052 // Nevertheless, let's do it!
1053 (MOV(Q|L|W|B|SS|SD|O)load [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1054 (MOV(Q|L|W|B|SS|SD|O)load [off1+off2] {sym} ptr mem)
1055 (MOV(Q|L|W|B|SS|SD|O)store [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1056 (MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {sym} ptr val mem)
1057 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1058 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {sym} base val mem)
1059 ((ADD|SUB|AND|OR|XOR)Qload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
1060 ((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {sym} val base mem)
1061 ((ADD|SUB|AND|OR|XOR)Lload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
1062 ((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
1063 (CMP(Q|L|W|B)load [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1064 (CMP(Q|L|W|B)load [off1+off2] {sym} base val mem)
1065 (CMP(Q|L|W|B)constload [valoff1] {sym} (ADDQconst [off2] base) mem) && ValAndOff(valoff1).canAdd32(off2) =>
1066 (CMP(Q|L|W|B)constload [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem)
1067
1068 ((ADD|SUB|MUL|DIV)SSload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
1069 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {sym} val base mem)
1070 ((ADD|SUB|MUL|DIV)SDload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
1071 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {sym} val base mem)
1072 ((ADD|AND|OR|XOR)Qconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ValAndOff(valoff1).canAdd32(off2) =>
1073 ((ADD|AND|OR|XOR)Qconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem)
1074 ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ValAndOff(valoff1).canAdd32(off2) =>
1075 ((ADD|AND|OR|XOR)Lconstmodify [ValAndOff(valoff1).addOffset32(off2)] {sym} base mem)
1076 ((ADD|SUB|AND|OR|XOR)Qmodify [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1077 ((ADD|SUB|AND|OR|XOR)Qmodify [off1+off2] {sym} base val mem)
1078 ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
1079 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {sym} base val mem)
1080
1081 // Fold constants into stores.
1082 (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) && validVal(c) =>
1083 (MOVQstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem)
1084 (MOVLstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1085 (MOVLstoreconst [makeValAndOff(int32(c),off)] {sym} ptr mem)
1086 (MOVWstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1087 (MOVWstoreconst [makeValAndOff(int32(int16(c)),off)] {sym} ptr mem)
1088 (MOVBstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1089 (MOVBstoreconst [makeValAndOff(int32(int8(c)),off)] {sym} ptr mem)
1090
1091 // Fold address offsets into constant stores.
1092 (MOV(Q|L|W|B|O)storeconst [sc] {s} (ADDQconst [off] ptr) mem) && ValAndOff(sc).canAdd32(off) =>
1093 (MOV(Q|L|W|B|O)storeconst [ValAndOff(sc).addOffset32(off)] {s} ptr mem)
1094
1095 // We need to fold LEAQ into the MOVx ops so that the live variable analysis knows
1096 // what variables are being read/written by the ops.
1097 (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
1098 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1099 (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1+off2] {mergeSym(sym1,sym2)} base mem)
1100 (MOV(Q|L|W|B|SS|SD|O)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1101 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1102 (MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1103 (MOV(Q|L|W|B|O)storeconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd32(off) =>
1104 (MOV(Q|L|W|B|O)storeconst [ValAndOff(sc).addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem)
1105 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1106 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1107 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1108 ((ADD|SUB|AND|OR|XOR)Qload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1109 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1110 ((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
1111 ((ADD|SUB|AND|OR|XOR)Lload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1112 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1113 ((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
1114 (CMP(Q|L|W|B)load [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1115 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1116 (CMP(Q|L|W|B)load [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1117 (CMP(Q|L|W|B)constload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1118 && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) =>
1119 (CMP(Q|L|W|B)constload [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
1120
1121 ((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1122 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1123 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
1124 ((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1125 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1126 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
1127 ((ADD|AND|OR|XOR)Qconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1128 && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) =>
1129 ((ADD|AND|OR|XOR)Qconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
1130 ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1131 && ValAndOff(valoff1).canAdd32(off2) && canMergeSym(sym1, sym2) =>
1132 ((ADD|AND|OR|XOR)Lconstmodify [ValAndOff(valoff1).addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
1133 ((ADD|SUB|AND|OR|XOR)Qmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1134 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1135 ((ADD|SUB|AND|OR|XOR)Qmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1136 ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1137 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1138 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
1139
1140 // fold LEAQs together
1141 (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1142 (LEAQ [off1+off2] {mergeSym(sym1,sym2)} x)
1143
1144 // LEAQ into LEAQ1
1145 (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
1146 (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
1147
1148 // LEAQ1 into LEAQ
1149 (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1150 (LEAQ1 [off1+off2] {mergeSym(sym1,sym2)} x y)
1151
1152 // LEAQ into LEAQ[248]
1153 (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
1154 (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y)
1155 (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
1156 (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y)
1157 (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
1158 (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y)
1159
1160 // LEAQ[248] into LEAQ
1161 (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1162 (LEAQ2 [off1+off2] {mergeSym(sym1,sym2)} x y)
1163 (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1164 (LEAQ4 [off1+off2] {mergeSym(sym1,sym2)} x y)
1165 (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1166 (LEAQ8 [off1+off2] {mergeSym(sym1,sym2)} x y)
1167
1168 // LEAQ[1248] into LEAQ[1248]. Only some such merges are possible.
1169 (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1170 (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} x y)
1171 (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1172 (LEAQ2 [off1+off2] {mergeSym(sym1, sym2)} y x)
1173 (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil =>
1174 (LEAQ4 [off1+2*off2] {sym1} x y)
1175 (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil =>
1176 (LEAQ8 [off1+4*off2] {sym1} x y)
1177 // TODO: more?
1178
1179 // Lower LEAQ2/4/8 when the offset is a constant
1180 (LEAQ2 [off] {sym} x (MOV(Q|L)const [scale])) && is32Bit(int64(off)+int64(scale)*2) =>
1181 (LEAQ [off+int32(scale)*2] {sym} x)
1182 (LEAQ4 [off] {sym} x (MOV(Q|L)const [scale])) && is32Bit(int64(off)+int64(scale)*4) =>
1183 (LEAQ [off+int32(scale)*4] {sym} x)
1184 (LEAQ8 [off] {sym} x (MOV(Q|L)const [scale])) && is32Bit(int64(off)+int64(scale)*8) =>
1185 (LEAQ [off+int32(scale)*8] {sym} x)
1186
1187 // Absorb InvertFlags into branches.
1188 (LT (InvertFlags cmp) yes no) => (GT cmp yes no)
1189 (GT (InvertFlags cmp) yes no) => (LT cmp yes no)
1190 (LE (InvertFlags cmp) yes no) => (GE cmp yes no)
1191 (GE (InvertFlags cmp) yes no) => (LE cmp yes no)
1192 (ULT (InvertFlags cmp) yes no) => (UGT cmp yes no)
1193 (UGT (InvertFlags cmp) yes no) => (ULT cmp yes no)
1194 (ULE (InvertFlags cmp) yes no) => (UGE cmp yes no)
1195 (UGE (InvertFlags cmp) yes no) => (ULE cmp yes no)
1196 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
1197 (NE (InvertFlags cmp) yes no) => (NE cmp yes no)
1198
1199 // Constant comparisons.
1200 (CMPQconst (MOVQconst [x]) [y]) && x==int64(y) => (FlagEQ)
1201 (CMPQconst (MOVQconst [x]) [y]) && x<int64(y) && uint64(x)<uint64(int64(y)) => (FlagLT_ULT)
1202 (CMPQconst (MOVQconst [x]) [y]) && x<int64(y) && uint64(x)>uint64(int64(y)) => (FlagLT_UGT)
1203 (CMPQconst (MOVQconst [x]) [y]) && x>int64(y) && uint64(x)<uint64(int64(y)) => (FlagGT_ULT)
1204 (CMPQconst (MOVQconst [x]) [y]) && x>int64(y) && uint64(x)>uint64(int64(y)) => (FlagGT_UGT)
1205 (CMPLconst (MOVLconst [x]) [y]) && x==y => (FlagEQ)
1206 (CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)<uint32(y) => (FlagLT_ULT)
1207 (CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)>uint32(y) => (FlagLT_UGT)
1208 (CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)<uint32(y) => (FlagGT_ULT)
1209 (CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)>uint32(y) => (FlagGT_UGT)
1210 (CMPWconst (MOVLconst [x]) [y]) && int16(x)==y => (FlagEQ)
1211 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)<uint16(y) => (FlagLT_ULT)
1212 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)>uint16(y) => (FlagLT_UGT)
1213 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)<uint16(y) => (FlagGT_ULT)
1214 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)>uint16(y) => (FlagGT_UGT)
1215 (CMPBconst (MOVLconst [x]) [y]) && int8(x)==y => (FlagEQ)
1216 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)<uint8(y) => (FlagLT_ULT)
1217 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)>uint8(y) => (FlagLT_UGT)
1218 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)<uint8(y) => (FlagGT_ULT)
1219 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)>uint8(y) => (FlagGT_UGT)
1220
1221 // CMPQconst requires a 32 bit const, but we can still constant-fold 64 bit consts.
1222 // In theory this applies to any of the simplifications above,
1223 // but CMPQ is the only one I've actually seen occur.
1224 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x==y => (FlagEQ)
1225 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x<y && uint64(x)<uint64(y) => (FlagLT_ULT)
1226 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x<y && uint64(x)>uint64(y) => (FlagLT_UGT)
1227 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x>y && uint64(x)<uint64(y) => (FlagGT_ULT)
1228 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x>y && uint64(x)>uint64(y) => (FlagGT_UGT)
1229
1230 // Other known comparisons.
1231 (CMPQconst (MOVBQZX _) [c]) && 0xFF < c => (FlagLT_ULT)
1232 (CMPQconst (MOVWQZX _) [c]) && 0xFFFF < c => (FlagLT_ULT)
1233 (CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) => (FlagLT_ULT)
1234 (CMPQconst (SHRQconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) => (FlagLT_ULT)
1235 (CMPQconst (ANDQconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1236 (CMPQconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1237 (CMPLconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1238 (CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < n => (FlagLT_ULT)
1239 (CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < n => (FlagLT_ULT)
1240
1241 // TESTQ c c sets flags like CMPQ c 0.
1242 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c == 0 => (FlagEQ)
1243 (TESTLconst [c] (MOVLconst [c])) && c == 0 => (FlagEQ)
1244 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c < 0 => (FlagLT_UGT)
1245 (TESTLconst [c] (MOVLconst [c])) && c < 0 => (FlagLT_UGT)
1246 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c > 0 => (FlagGT_UGT)
1247 (TESTLconst [c] (MOVLconst [c])) && c > 0 => (FlagGT_UGT)
1248
1249 // TODO: DIVxU also.
1250
1251 // Absorb flag constants into SBB ops.
1252 (SBBQcarrymask (FlagEQ)) => (MOVQconst [0])
1253 (SBBQcarrymask (FlagLT_ULT)) => (MOVQconst [-1])
1254 (SBBQcarrymask (FlagLT_UGT)) => (MOVQconst [0])
1255 (SBBQcarrymask (FlagGT_ULT)) => (MOVQconst [-1])
1256 (SBBQcarrymask (FlagGT_UGT)) => (MOVQconst [0])
1257 (SBBLcarrymask (FlagEQ)) => (MOVLconst [0])
1258 (SBBLcarrymask (FlagLT_ULT)) => (MOVLconst [-1])
1259 (SBBLcarrymask (FlagLT_UGT)) => (MOVLconst [0])
1260 (SBBLcarrymask (FlagGT_ULT)) => (MOVLconst [-1])
1261 (SBBLcarrymask (FlagGT_UGT)) => (MOVLconst [0])
1262
1263 // Absorb flag constants into branches.
1264 ((EQ|LE|GE|ULE|UGE) (FlagEQ) yes no) => (First yes no)
1265 ((NE|LT|GT|ULT|UGT) (FlagEQ) yes no) => (First no yes)
1266 ((NE|LT|LE|ULT|ULE) (FlagLT_ULT) yes no) => (First yes no)
1267 ((EQ|GT|GE|UGT|UGE) (FlagLT_ULT) yes no) => (First no yes)
1268 ((NE|LT|LE|UGT|UGE) (FlagLT_UGT) yes no) => (First yes no)
1269 ((EQ|GT|GE|ULT|ULE) (FlagLT_UGT) yes no) => (First no yes)
1270 ((NE|GT|GE|ULT|ULE) (FlagGT_ULT) yes no) => (First yes no)
1271 ((EQ|LT|LE|UGT|UGE) (FlagGT_ULT) yes no) => (First no yes)
1272 ((NE|GT|GE|UGT|UGE) (FlagGT_UGT) yes no) => (First yes no)
1273 ((EQ|LT|LE|ULT|ULE) (FlagGT_UGT) yes no) => (First no yes)
1274
1275 // Absorb flag constants into SETxx ops.
1276 ((SETEQ|SETLE|SETGE|SETBE|SETAE) (FlagEQ)) => (MOVLconst [1])
1277 ((SETNE|SETL|SETG|SETB|SETA) (FlagEQ)) => (MOVLconst [0])
1278 ((SETNE|SETL|SETLE|SETB|SETBE) (FlagLT_ULT)) => (MOVLconst [1])
1279 ((SETEQ|SETG|SETGE|SETA|SETAE) (FlagLT_ULT)) => (MOVLconst [0])
1280 ((SETNE|SETL|SETLE|SETA|SETAE) (FlagLT_UGT)) => (MOVLconst [1])
1281 ((SETEQ|SETG|SETGE|SETB|SETBE) (FlagLT_UGT)) => (MOVLconst [0])
1282 ((SETNE|SETG|SETGE|SETB|SETBE) (FlagGT_ULT)) => (MOVLconst [1])
1283 ((SETEQ|SETL|SETLE|SETA|SETAE) (FlagGT_ULT)) => (MOVLconst [0])
1284 ((SETNE|SETG|SETGE|SETA|SETAE) (FlagGT_UGT)) => (MOVLconst [1])
1285 ((SETEQ|SETL|SETLE|SETB|SETBE) (FlagGT_UGT)) => (MOVLconst [0])
1286
1287 (SETEQstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1288 (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1289 (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1290 (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1291 (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1292
1293 (SETNEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1294 (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1295 (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1296 (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1297 (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1298
1299 (SETLstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1300 (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1301 (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1302 (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1303 (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1304
1305 (SETLEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1306 (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1307 (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1308 (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1309 (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1310
1311 (SETGstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1312 (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1313 (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1314 (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1315 (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1316
1317 (SETGEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1318 (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1319 (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1320 (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1321 (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1322
1323 (SETBstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1324 (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1325 (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1326 (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1327 (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1328
1329 (SETBEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1330 (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1331 (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1332 (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1333 (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1334
1335 (SETAstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1336 (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1337 (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1338 (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1339 (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1340
1341 (SETAEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1342 (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1343 (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1344 (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1345 (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1346
1347 // Remove redundant *const ops
1348 (ADDQconst [0] x) => x
1349 (ADDLconst [c] x) && c==0 => x
1350 (SUBQconst [0] x) => x
1351 (SUBLconst [c] x) && c==0 => x
1352 (ANDQconst [0] _) => (MOVQconst [0])
1353 (ANDLconst [c] _) && c==0 => (MOVLconst [0])
1354 (ANDQconst [-1] x) => x
1355 (ANDLconst [c] x) && c==-1 => x
1356 (ORQconst [0] x) => x
1357 (ORLconst [c] x) && c==0 => x
1358 (ORQconst [-1] _) => (MOVQconst [-1])
1359 (ORLconst [c] _) && c==-1 => (MOVLconst [-1])
1360 (XORQconst [0] x) => x
1361 (XORLconst [c] x) && c==0 => x
1362 // TODO: since we got rid of the W/B versions, we might miss
1363 // things like (ANDLconst [0x100] x) which were formerly
1364 // (ANDBconst [0] x). Probably doesn't happen very often.
1365 // If we cared, we might do:
1366 // (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 -> (MOVLconst [0])
1367
1368 // Remove redundant ops
1369 // Not in generic rules, because they may appear after lowering e. g. Slicemask
1370 (NEG(Q|L) (NEG(Q|L) x)) => x
1371 (NEG(Q|L) s:(SUB(Q|L) x y)) && s.Uses == 1 => (SUB(Q|L) y x)
1372
1373 // Convert constant subtracts to constant adds
1374 (SUBQconst [c] x) && c != -(1<<31) => (ADDQconst [-c] x)
1375 (SUBLconst [c] x) => (ADDLconst [-c] x)
1376
1377 // generic constant folding
1378 // TODO: more of this
1379 (ADDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)+d])
1380 (ADDLconst [c] (MOVLconst [d])) => (MOVLconst [c+d])
1381 (ADDQconst [c] (ADDQconst [d] x)) && is32Bit(int64(c)+int64(d)) => (ADDQconst [c+d] x)
1382 (ADDLconst [c] (ADDLconst [d] x)) => (ADDLconst [c+d] x)
1383 (SUBQconst (MOVQconst [d]) [c]) => (MOVQconst [d-int64(c)])
1384 (SUBQconst (SUBQconst x [d]) [c]) && is32Bit(int64(-c)-int64(d)) => (ADDQconst [-c-d] x)
1385 (SARQconst [c] (MOVQconst [d])) => (MOVQconst [d>>uint64(c)])
1386 (SARLconst [c] (MOVQconst [d])) => (MOVQconst [int64(int32(d))>>uint64(c)])
1387 (SARWconst [c] (MOVQconst [d])) => (MOVQconst [int64(int16(d))>>uint64(c)])
1388 (SARBconst [c] (MOVQconst [d])) => (MOVQconst [int64(int8(d))>>uint64(c)])
1389 (NEGQ (MOVQconst [c])) => (MOVQconst [-c])
1390 (NEGL (MOVLconst [c])) => (MOVLconst [-c])
1391 (MULQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)*d])
1392 (MULLconst [c] (MOVLconst [d])) => (MOVLconst [c*d])
1393 (ANDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)&d])
1394 (ANDLconst [c] (MOVLconst [d])) => (MOVLconst [c&d])
1395 (ORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)|d])
1396 (ORLconst [c] (MOVLconst [d])) => (MOVLconst [c|d])
1397 (XORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)^d])
1398 (XORLconst [c] (MOVLconst [d])) => (MOVLconst [c^d])
1399 (NOTQ (MOVQconst [c])) => (MOVQconst [^c])
1400 (NOTL (MOVLconst [c])) => (MOVLconst [^c])
1401 (BTSQconst [c] (MOVQconst [d])) => (MOVQconst [d|(1<<uint32(c))])
1402 (BTRQconst [c] (MOVQconst [d])) => (MOVQconst [d&^(1<<uint32(c))])
1403 (BTCQconst [c] (MOVQconst [d])) => (MOVQconst [d^(1<<uint32(c))])
1404
1405 // If c or d doesn't fit into 32 bits, then we can't construct ORQconst,
1406 // but we can still constant-fold.
1407 // In theory this applies to any of the simplifications above,
1408 // but ORQ is the only one I've actually seen occur.
1409 (ORQ (MOVQconst [c]) (MOVQconst [d])) => (MOVQconst [c|d])
1410
1411 // generic simplifications
1412 // TODO: more of this
1413 (ADDQ x (NEGQ y)) => (SUBQ x y)
1414 (ADDL x (NEGL y)) => (SUBL x y)
1415 (SUBQ x x) => (MOVQconst [0])
1416 (SUBL x x) => (MOVLconst [0])
1417 (ANDQ x x) => x
1418 (ANDL x x) => x
1419 (ORQ x x) => x
1420 (ORL x x) => x
1421 (XORQ x x) => (MOVQconst [0])
1422 (XORL x x) => (MOVLconst [0])
1423
1424 (SHLLconst [d] (MOVLconst [c])) => (MOVLconst [c << uint64(d)])
1425 (SHLQconst [d] (MOVQconst [c])) => (MOVQconst [c << uint64(d)])
1426 (SHLQconst [d] (MOVLconst [c])) => (MOVQconst [int64(c) << uint64(d)])
1427
1428 // Fold NEG into ADDconst/MULconst. Take care to keep c in 32 bit range.
1429 (NEGQ (ADDQconst [c] (NEGQ x))) && c != -(1<<31) => (ADDQconst [-c] x)
1430 (MULQconst [c] (NEGQ x)) && c != -(1<<31) => (MULQconst [-c] x)
1431
1432 // checking AND against 0.
1433 (CMPQconst a:(ANDQ x y) [0]) && a.Uses == 1 => (TESTQ x y)
1434 (CMPLconst a:(ANDL x y) [0]) && a.Uses == 1 => (TESTL x y)
1435 (CMPWconst a:(ANDL x y) [0]) && a.Uses == 1 => (TESTW x y)
1436 (CMPBconst a:(ANDL x y) [0]) && a.Uses == 1 => (TESTB x y)
1437 (CMPQconst a:(ANDQconst [c] x) [0]) && a.Uses == 1 => (TESTQconst [c] x)
1438 (CMPLconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTLconst [c] x)
1439 (CMPWconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTWconst [int16(c)] x)
1440 (CMPBconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTBconst [int8(c)] x)
1441
1442 // Convert TESTx to TESTxconst if possible.
1443 (TESTQ (MOVQconst [c]) x) && is32Bit(c) => (TESTQconst [int32(c)] x)
1444 (TESTL (MOVLconst [c]) x) => (TESTLconst [c] x)
1445 (TESTW (MOVLconst [c]) x) => (TESTWconst [int16(c)] x)
1446 (TESTB (MOVLconst [c]) x) => (TESTBconst [int8(c)] x)
1447
1448 // TEST %reg,%reg is shorter than CMP
1449 (CMPQconst x [0]) => (TESTQ x x)
1450 (CMPLconst x [0]) => (TESTL x x)
1451 (CMPWconst x [0]) => (TESTW x x)
1452 (CMPBconst x [0]) => (TESTB x x)
1453 (TESTQconst [-1] x) && x.Op != OpAMD64MOVQconst => (TESTQ x x)
1454 (TESTLconst [-1] x) && x.Op != OpAMD64MOVLconst => (TESTL x x)
1455 (TESTWconst [-1] x) && x.Op != OpAMD64MOVLconst => (TESTW x x)
1456 (TESTBconst [-1] x) && x.Op != OpAMD64MOVLconst => (TESTB x x)
1457
1458 // Convert LEAQ1 back to ADDQ if we can
1459 (LEAQ1 [0] x y) && v.Aux == nil => (ADDQ x y)
1460
1461 (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem))
1462 && config.useSSE
1463 && x.Uses == 1
1464 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off()))
1465 && a.Val() == 0
1466 && c.Val() == 0
1467 && setPos(v, x.Pos)
1468 && clobber(x)
1469 => (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem)
1470 (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem))
1471 && config.useSSE
1472 && x.Uses == 1
1473 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off()))
1474 && a.Val() == 0
1475 && c.Val() == 0
1476 && setPos(v, x.Pos)
1477 && clobber(x)
1478 => (MOVOstoreconst [makeValAndOff(0,a.Off())] {s} p0 mem)
1479
1480 // Merge load and op
1481 // TODO: add indexed variants?
1482 ((ADD|SUB|AND|OR|XOR)Q x l:(MOVQload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|AND|OR|XOR)Qload x [off] {sym} ptr mem)
1483 ((ADD|SUB|AND|OR|XOR)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|AND|OR|XOR)Lload x [off] {sym} ptr mem)
1484 ((ADD|SUB|MUL|DIV)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SDload x [off] {sym} ptr mem)
1485 ((ADD|SUB|MUL|DIV)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SSload x [off] {sym} ptr mem)
1486 (MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lload x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) => ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
1487 (MOVLstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)L l:(MOVLload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && clobber(y, l) =>
1488 ((ADD|SUB|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
1489 (MOVQstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Qload x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) => ((ADD|AND|OR|XOR)Qmodify [off] {sym} ptr x mem)
1490 (MOVQstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)Q l:(MOVQload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && clobber(y, l) =>
1491 ((ADD|SUB|AND|OR|XOR)Qmodify [off] {sym} ptr x mem)
1492 (MOVQstore {sym} [off] ptr x:(BT(S|R|C)Qconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) && x.Uses == 1 && l.Uses == 1 && clobber(x, l) =>
1493 (BT(S|R|C)Qconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem)
1494
1495 // Merge ADDQconst and LEAQ into atomic loads.
1496 (MOV(Q|L|B)atomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1497 (MOV(Q|L|B)atomicload [off1+off2] {sym} ptr mem)
1498 (MOV(Q|L|B)atomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
1499 (MOV(Q|L|B)atomicload [off1+off2] {mergeSym(sym1, sym2)} ptr mem)
1500
1501 // Merge ADDQconst and LEAQ into atomic stores.
1502 (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1503 (XCHGQ [off1+off2] {sym} val ptr mem)
1504 (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB =>
1505 (XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem)
1506 (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1507 (XCHGL [off1+off2] {sym} val ptr mem)
1508 (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB =>
1509 (XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem)
1510
1511 // Merge ADDQconst into atomic adds.
1512 // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions.
1513 (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1514 (XADDQlock [off1+off2] {sym} val ptr mem)
1515 (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
1516 (XADDLlock [off1+off2] {sym} val ptr mem)
1517
1518 // Merge ADDQconst into atomic compare and swaps.
1519 // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions.
1520 (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && is32Bit(int64(off1)+int64(off2)) =>
1521 (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem)
1522 (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && is32Bit(int64(off1)+int64(off2)) =>
1523 (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem)
1524
1525 // We don't need the conditional move if we know the arg of BSF is not zero.
1526 (CMOVQEQ x _ (Select1 (BS(F|R)Q (ORQconst [c] _)))) && c != 0 => x
1527 // Extension is unnecessary for trailing zeros.
1528 (BSFQ (ORQconst <t> [1<<8] (MOVBQZX x))) => (BSFQ (ORQconst <t> [1<<8] x))
1529 (BSFQ (ORQconst <t> [1<<16] (MOVWQZX x))) => (BSFQ (ORQconst <t> [1<<16] x))
1530
1531 // Redundant sign/zero extensions
1532 // Note: see issue 21963. We have to make sure we use the right type on
1533 // the resulting extension (the outer type, not the inner type).
1534 (MOVLQSX (MOVLQSX x)) => (MOVLQSX x)
1535 (MOVLQSX (MOVWQSX x)) => (MOVWQSX x)
1536 (MOVLQSX (MOVBQSX x)) => (MOVBQSX x)
1537 (MOVWQSX (MOVWQSX x)) => (MOVWQSX x)
1538 (MOVWQSX (MOVBQSX x)) => (MOVBQSX x)
1539 (MOVBQSX (MOVBQSX x)) => (MOVBQSX x)
1540 (MOVLQZX (MOVLQZX x)) => (MOVLQZX x)
1541 (MOVLQZX (MOVWQZX x)) => (MOVWQZX x)
1542 (MOVLQZX (MOVBQZX x)) => (MOVBQZX x)
1543 (MOVWQZX (MOVWQZX x)) => (MOVWQZX x)
1544 (MOVWQZX (MOVBQZX x)) => (MOVBQZX x)
1545 (MOVBQZX (MOVBQZX x)) => (MOVBQZX x)
1546
1547 (MOVQstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Qconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
1548 && isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) =>
1549 ((ADD|AND|OR|XOR)Qconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem)
1550 (MOVLstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Lconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
1551 && isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && clobber(l, a) =>
1552 ((ADD|AND|OR|XOR)Lconstmodify {sym} [makeValAndOff(int32(c),off)] ptr mem)
1553
1554 // float <-> int register moves, with no conversion.
1555 // These come up when compiling math.{Float{32,64}bits,Float{32,64}frombits}.
1556 (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) => (MOVQf2i val)
1557 (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) => (MOVLf2i val)
1558 (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) => (MOVQi2f val)
1559 (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) => (MOVLi2f val)
1560
1561 // Other load-like ops.
1562 (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (ADDQ x (MOVQf2i y))
1563 (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (ADDL x (MOVLf2i y))
1564 (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (SUBQ x (MOVQf2i y))
1565 (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (SUBL x (MOVLf2i y))
1566 (ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (ANDQ x (MOVQf2i y))
1567 (ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (ANDL x (MOVLf2i y))
1568 ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => ( ORQ x (MOVQf2i y))
1569 ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => ( ORL x (MOVLf2i y))
1570 (XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (XORQ x (MOVQf2i y))
1571 (XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (XORL x (MOVLf2i y))
1572
1573 (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (ADDSD x (MOVQi2f y))
1574 (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (ADDSS x (MOVLi2f y))
1575 (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (SUBSD x (MOVQi2f y))
1576 (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (SUBSS x (MOVLi2f y))
1577 (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (MULSD x (MOVQi2f y))
1578 (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (MULSS x (MOVLi2f y))
1579
1580 // Redirect stores to use the other register set.
1581 (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) => (MOVSDstore [off] {sym} ptr val mem)
1582 (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) => (MOVSSstore [off] {sym} ptr val mem)
1583 (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) => (MOVQstore [off] {sym} ptr val mem)
1584 (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) => (MOVLstore [off] {sym} ptr val mem)
1585
1586 // Load args directly into the register class where it will be used.
1587 // We do this by just modifying the type of the Arg.
1588 (MOVQf2i <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1589 (MOVLf2i <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1590 (MOVQi2f <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1591 (MOVLi2f <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1592
1593 // LEAQ is rematerializeable, so this helps to avoid register spill.
1594 // See issue 22947 for details
1595 (ADD(Q|L)const [off] x:(SP)) => (LEA(Q|L) [off] x)
1596
1597 // HMULx is commutative, but its first argument must go in AX.
1598 // If possible, put a rematerializeable value in the first argument slot,
1599 // to reduce the odds that another value will be have to spilled
1600 // specifically to free up AX.
1601 (HMUL(Q|L) x y) && !x.rematerializeable() && y.rematerializeable() => (HMUL(Q|L) y x)
1602 (HMUL(Q|L)U x y) && !x.rematerializeable() && y.rematerializeable() => (HMUL(Q|L)U y x)
1603
1604 // Fold loads into compares
1605 // Note: these may be undone by the flagalloc pass.
1606 (CMP(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) x) && canMergeLoad(v, l) && clobber(l) => (CMP(Q|L|W|B)load {sym} [off] ptr x mem)
1607 (CMP(Q|L|W|B) x l:(MOV(Q|L|W|B)load {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (InvertFlags (CMP(Q|L|W|B)load {sym} [off] ptr x mem))
1608
1609 (CMP(Q|L)const l:(MOV(Q|L)load {sym} [off] ptr mem) [c])
1610 && l.Uses == 1
1611 && clobber(l) =>
1612 @l.Block (CMP(Q|L)constload {sym} [makeValAndOff(c,off)] ptr mem)
1613 (CMP(W|B)const l:(MOV(W|B)load {sym} [off] ptr mem) [c])
1614 && l.Uses == 1
1615 && clobber(l) =>
1616 @l.Block (CMP(W|B)constload {sym} [makeValAndOff(int32(c),off)] ptr mem)
1617
1618 (CMPQload {sym} [off] ptr (MOVQconst [c]) mem) && validVal(c) => (CMPQconstload {sym} [makeValAndOff(int32(c),off)] ptr mem)
1619 (CMPLload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
1620 (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem)
1621 (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem)
1622
1623 (TEST(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) l2)
1624 && l == l2
1625 && l.Uses == 2
1626 && clobber(l) =>
1627 @l.Block (CMP(Q|L|W|B)constload {sym} [makeValAndOff(0, off)] ptr mem)
1628
1629 // Convert ANDload to MOVload when we can do the AND in a containing TEST op.
1630 // Only do when it's within the same block, so we don't have flags live across basic block boundaries.
1631 // See issue 44228.
1632 (TEST(Q|L) a:(AND(Q|L)load [off] {sym} x ptr mem) a) && a.Uses == 2 && a.Block == v.Block && clobber(a) => (TEST(Q|L) (MOV(Q|L)load <a.Type> [off] {sym} ptr mem) x)
1633
1634 (MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read8(sym, int64(off)))])
1635 (MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1636 (MOVLload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1637 (MOVQload [off] {sym} (SB) _) && symIsRO(sym) => (MOVQconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1638 (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) && symIsRO(srcSym) =>
1639 (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff)+8, config.ctxt.Arch.ByteOrder))])
1640 (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(read64(srcSym, int64(srcOff), config.ctxt.Arch.ByteOrder))]) mem))
1641
1642 // Arch-specific inlining for small or disjoint runtime.memmove
1643 // Match post-lowering calls, memory version.
1644 (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem)))))
1645 && sc.Val64() >= 0
1646 && isSameCall(sym, "runtime.memmove")
1647 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
1648 && isInlinableMemmove(dst, src, sc.Val64(), config)
1649 && clobber(s1, s2, s3, call)
1650 => (Move [sc.Val64()] dst src mem)
1651
1652 // Match post-lowering calls, register version.
1653 (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem))
1654 && sz >= 0
1655 && isSameCall(sym, "runtime.memmove")
1656 && call.Uses == 1
1657 && isInlinableMemmove(dst, src, sz, config)
1658 && clobber(call)
1659 => (Move [sz] dst src mem)
1660
1661 // Prefetch instructions
1662 (PrefetchCache ...) => (PrefetchT0 ...)
1663 (PrefetchCacheStreamed ...) => (PrefetchNTA ...)
1664
1665 // CPUID feature: BMI1.
1666 (AND(Q|L) x (NOT(Q|L) y)) && buildcfg.GOAMD64 >= 3 => (ANDN(Q|L) x y)
1667 (AND(Q|L) x (NEG(Q|L) x)) && buildcfg.GOAMD64 >= 3 => (BLSI(Q|L) x)
1668 (XOR(Q|L) x (ADD(Q|L)const [-1] x)) && buildcfg.GOAMD64 >= 3 => (BLSMSK(Q|L) x)
1669 (AND(Q|L) <t> x (ADD(Q|L)const [-1] x)) && buildcfg.GOAMD64 >= 3 => (Select0 <t> (BLSR(Q|L) x))
1670 // eliminate TEST instruction in classical "isPowerOfTwo" check
1671 (SETEQ (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (SETEQ (Select1 <types.TypeFlags> blsr))
1672 (CMOVQEQ x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVQEQ x y (Select1 <types.TypeFlags> blsr))
1673 (CMOVLEQ x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVLEQ x y (Select1 <types.TypeFlags> blsr))
1674 (EQ (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s) yes no) => (EQ (Select1 <types.TypeFlags> blsr) yes no)
1675 (SETNE (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (SETNE (Select1 <types.TypeFlags> blsr))
1676 (CMOVQNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVQNE x y (Select1 <types.TypeFlags> blsr))
1677 (CMOVLNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVLNE x y (Select1 <types.TypeFlags> blsr))
1678 (NE (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s) yes no) => (NE (Select1 <types.TypeFlags> blsr) yes no)
1679
1680 (BSWAP(Q|L) (BSWAP(Q|L) p)) => p
1681
1682 // CPUID feature: MOVBE.
1683 (MOV(Q|L)store [i] {s} p x:(BSWAP(Q|L) w) mem) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => (MOVBE(Q|L)store [i] {s} p w mem)
1684 (MOVBE(Q|L)store [i] {s} p x:(BSWAP(Q|L) w) mem) && x.Uses == 1 => (MOV(Q|L)store [i] {s} p w mem)
1685 (BSWAP(Q|L) x:(MOV(Q|L)load [i] {s} p mem)) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => @x.Block (MOVBE(Q|L)load [i] {s} p mem)
1686 (BSWAP(Q|L) x:(MOVBE(Q|L)load [i] {s} p mem)) && x.Uses == 1 => @x.Block (MOV(Q|L)load [i] {s} p mem)
1687 (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => (MOVBEWstore [i] {s} p w mem)
1688 (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) && x.Uses == 1 => (MOVWstore [i] {s} p w mem)
1689
1690 (SAR(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) => (SARX(Q|L)load [off] {sym} ptr x mem)
1691 (SHL(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) => (SHLX(Q|L)load [off] {sym} ptr x mem)
1692 (SHR(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && canMergeLoad(v, l) && clobber(l) => (SHRX(Q|L)load [off] {sym} ptr x mem)
1693
1694 ((SHL|SHR|SAR)XQload [off] {sym} ptr (MOVQconst [c]) mem) => ((SHL|SHR|SAR)Qconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
1695 ((SHL|SHR|SAR)XQload [off] {sym} ptr (MOVLconst [c]) mem) => ((SHL|SHR|SAR)Qconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
1696 ((SHL|SHR|SAR)XLload [off] {sym} ptr (MOVLconst [c]) mem) => ((SHL|SHR|SAR)Lconst [int8(c&31)] (MOVLload [off] {sym} ptr mem))
1697
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