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30 package s390x
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "fmt"
36 "log"
37 "math"
38 "slices"
39 )
40
41
42
43
44 type ctxtz struct {
45 ctxt *obj.Link
46 newprog obj.ProgAlloc
47 cursym *obj.LSym
48 autosize int32
49 instoffset int64
50 pc int64
51 }
52
53
54 const (
55 funcAlign = 16
56 )
57
58 type Optab struct {
59 as obj.As
60 i uint8
61 a1 uint8
62 a2 uint8
63 a3 uint8
64 a4 uint8
65 a5 uint8
66 a6 uint8
67 }
68
69 var optab = []Optab{
70
71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
75 {i: 0, as: obj.ANOP},
76 {i: 0, as: obj.ANOP, a1: C_SAUTO},
77
78
79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
86
87
88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
96
97
98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
118
119
120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
139
140
141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
160
161
162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
163
164
165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
166 {i: 2, as: AADD, a1: C_REG, a6: C_REG},
167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG},
169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG},
178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG},
182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG},
183 {i: 47, as: ANEG, a6: C_REG},
184
185
186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
187 {i: 6, as: AAND, a1: C_REG, a6: C_REG},
188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG},
189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG},
193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG},
197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
201
202
203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
204
205
206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
208 {i: 33, as: AFABS, a6: C_FREG},
209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
226
227
228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
232
233
234 {i: 5, as: ASYSCALL},
235 {i: 77, as: ASYSCALL, a1: C_SCON},
236
237
238 {i: 16, as: ABEQ, a6: C_SBRA},
239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA},
240 {i: 11, as: ABR, a6: C_LBRA},
241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
242 {i: 18, as: ABR, a6: C_REG},
243 {i: 18, as: ABR, a1: C_REG, a6: C_REG},
244 {i: 15, as: ABR, a6: C_ZOREG},
245 {i: 15, as: ABC, a6: C_ZOREG},
246
247
248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA},
254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
258
259
260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA},
261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA},
262
263
264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
265
266
267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG},
268
269
270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
271
272
273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
274
275
276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG},
277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
282
283
284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
285
286
287 {i: 92, as: AIPM, a1: C_REG},
288
289
290 {i: 76, as: ASPM, a1: C_REG},
291
292
293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
297
298
299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
301
302
303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
307
308
309 {i: 40, as: ABYTE, a1: C_SCON},
310 {i: 40, as: AWORD, a1: C_LCON},
311 {i: 31, as: ADWORD, a1: C_LCON},
312 {i: 31, as: ADWORD, a1: C_DCON},
313
314
315 {i: 80, as: ASYNC},
316
317
318 {i: 88, as: ASTCK, a6: C_SAUTO},
319 {i: 88, as: ASTCK, a6: C_SOREG},
320
321
322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
325
326
327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
332
333
334 {i: 78, as: obj.AUNDEF},
335
336
337 {i: 73, as: ABRRK},
338
339
340 {i: 66, as: ANOPH},
341
342
343
344
345 {i: 124, as: AKM, a1: C_REG, a6: C_REG},
346
347
348 {i: 125, as: AKDSA, a1: C_REG, a6: C_REG},
349
350
351 {i: 126, as: AKMA, a1: C_REG, a2: C_REG, a6: C_REG},
352
353
354
355
356 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
357 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
358 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
359 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
360
361
362 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
363 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
364 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
365 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
366
367
368 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
369 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
370
371
372 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
373 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
374
375
376 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
377 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
378 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
379 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
380 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
381 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
382 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
383 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
384
385
386 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
387 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
388
389
390 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
391 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
392
393
394 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
395 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
396
397
398 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
399 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
400
401
402 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
403 {i: 109, as: AVZERO, a6: C_VREG},
404 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
405 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
406 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
407 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
408
409
410 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
411
412
413 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
414
415
416
417 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
418 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
419
420
421 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
422
423
424 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
425
426
427 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
428
429
430 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
431 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
432 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
433
434
435 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
436 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
437 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
438 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
439
440
441 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
442 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
443
444
445 {i: 128, as: AVFMAXDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
446 {i: 128, as: AWFMAXDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
447 {i: 128, as: AWFMAXDB, a1: C_SCON, a2: C_FREG, a3: C_FREG, a6: C_FREG},
448
449
450 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
451
452
453 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
454
455
456 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
457
458
459 {i: 127, as: AMVCLE, a1: C_LOREG, a2: C_REG, a6: C_REG},
460 {i: 127, as: AMVCLE, a1: C_SCON, a2: C_REG, a6: C_REG},
461
462
463 {i: 129, as: AVSTRL, a1: C_VREG, a3: C_SCON, a6: C_SOREG},
464 {i: 129, as: AVSTRL, a1: C_VREG, a3: C_SCON, a6: C_SAUTO},
465 }
466
467 var oprange [ALAST & obj.AMask][]Optab
468
469 var xcmp [C_NCLASS][C_NCLASS]bool
470
471 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
472 if ctxt.Retpoline {
473 ctxt.Diag("-spectre=ret not supported on s390x")
474 ctxt.Retpoline = false
475 }
476
477 p := cursym.Func().Text
478 if p == nil || p.Link == nil {
479 return
480 }
481
482 if oprange[AORW&obj.AMask] == nil {
483 ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
484 }
485
486 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
487
488 buffer := make([]byte, 0)
489 changed := true
490 loop := 0
491 nrelocs0 := len(c.cursym.R)
492 for changed {
493 if loop > 100 {
494 c.ctxt.Diag("stuck in spanz loop")
495 break
496 }
497 changed = false
498 buffer = buffer[:0]
499 for i := range c.cursym.R[nrelocs0:] {
500 c.cursym.R[nrelocs0+i] = obj.Reloc{}
501 }
502 c.cursym.R = c.cursym.R[:nrelocs0]
503 for p := c.cursym.Func().Text; p != nil; p = p.Link {
504 pc := int64(len(buffer))
505 if pc != p.Pc {
506 changed = true
507 }
508 p.Pc = pc
509 c.pc = p.Pc
510 c.asmout(p, &buffer)
511 if pc == int64(len(buffer)) {
512 switch p.As {
513 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
514
515 default:
516 c.ctxt.Diag("zero-width instruction\n%v", p)
517 }
518 }
519 }
520 loop++
521 }
522
523 c.cursym.Size = int64(len(buffer))
524 if c.cursym.Size%funcAlign != 0 {
525 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
526 }
527 c.cursym.Grow(c.cursym.Size)
528 copy(c.cursym.P, buffer)
529
530
531
532
533
534 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil)
535 }
536
537
538 func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool {
539 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP {
540 return true
541 }
542 for _, a := range p.RestArgs {
543 if a.Reg == REGTMP {
544 return true
545 }
546 }
547 return p.Mark&USETMP != 0
548 }
549
550 func isint32(v int64) bool {
551 return int64(int32(v)) == v
552 }
553
554 func isuint32(v uint64) bool {
555 return uint64(uint32(v)) == v
556 }
557
558 func (c *ctxtz) aclass(a *obj.Addr) int {
559 switch a.Type {
560 case obj.TYPE_NONE:
561 return C_NONE
562
563 case obj.TYPE_REG:
564 if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
565 return C_REG
566 }
567 if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
568 return C_FREG
569 }
570 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
571 return C_AREG
572 }
573 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
574 return C_VREG
575 }
576 return C_GOK
577
578 case obj.TYPE_MEM:
579 switch a.Name {
580 case obj.NAME_EXTERN,
581 obj.NAME_STATIC:
582 if a.Sym == nil {
583
584 break
585 }
586 c.instoffset = a.Offset
587 if a.Sym.Type == objabi.STLSBSS {
588 if c.ctxt.Flag_shared {
589 return C_TLS_IE
590 }
591 return C_TLS_LE
592 }
593 return C_ADDR
594
595 case obj.NAME_GOTREF:
596 return C_GOTADDR
597
598 case obj.NAME_AUTO:
599 if a.Reg == REGSP {
600
601
602 a.Reg = obj.REG_NONE
603 }
604 c.instoffset = int64(c.autosize) + a.Offset
605 if c.instoffset >= -BIG && c.instoffset < BIG {
606 return C_SAUTO
607 }
608 return C_LAUTO
609
610 case obj.NAME_PARAM:
611 if a.Reg == REGSP {
612
613
614 a.Reg = obj.REG_NONE
615 }
616 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
617 if c.instoffset >= -BIG && c.instoffset < BIG {
618 return C_SAUTO
619 }
620 return C_LAUTO
621
622 case obj.NAME_NONE:
623 c.instoffset = a.Offset
624 if c.instoffset == 0 {
625 return C_ZOREG
626 }
627 if c.instoffset >= -BIG && c.instoffset < BIG {
628 return C_SOREG
629 }
630 return C_LOREG
631 }
632
633 return C_GOK
634
635 case obj.TYPE_TEXTSIZE:
636 return C_TEXTSIZE
637
638 case obj.TYPE_FCONST:
639 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
640 return C_ZCON
641 }
642 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
643
644 case obj.TYPE_CONST,
645 obj.TYPE_ADDR:
646 switch a.Name {
647 case obj.NAME_NONE:
648 c.instoffset = a.Offset
649 if a.Reg != 0 {
650 if -BIG <= c.instoffset && c.instoffset <= BIG {
651 return C_SACON
652 }
653 if isint32(c.instoffset) {
654 return C_LACON
655 }
656 return C_DACON
657 }
658
659 case obj.NAME_EXTERN,
660 obj.NAME_STATIC:
661 s := a.Sym
662 if s == nil {
663 return C_GOK
664 }
665 c.instoffset = a.Offset
666
667 return C_SYMADDR
668
669 case obj.NAME_AUTO:
670 if a.Reg == REGSP {
671
672
673 a.Reg = obj.REG_NONE
674 }
675 c.instoffset = int64(c.autosize) + a.Offset
676 if c.instoffset >= -BIG && c.instoffset < BIG {
677 return C_SACON
678 }
679 return C_LACON
680
681 case obj.NAME_PARAM:
682 if a.Reg == REGSP {
683
684
685 a.Reg = obj.REG_NONE
686 }
687 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
688 if c.instoffset >= -BIG && c.instoffset < BIG {
689 return C_SACON
690 }
691 return C_LACON
692
693 default:
694 return C_GOK
695 }
696
697 if c.instoffset == 0 {
698 return C_ZCON
699 }
700 if c.instoffset >= 0 {
701 if c.instoffset <= 0x7fff {
702 return C_SCON
703 }
704 if c.instoffset <= 0xffff {
705 return C_ANDCON
706 }
707 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) {
708 return C_UCON
709 }
710 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
711 return C_LCON
712 }
713 return C_DCON
714 }
715
716 if c.instoffset >= -0x8000 {
717 return C_ADDCON
718 }
719 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
720 return C_UCON
721 }
722 if isint32(c.instoffset) {
723 return C_LCON
724 }
725 return C_DCON
726
727 case obj.TYPE_BRANCH:
728 return C_SBRA
729 }
730
731 return C_GOK
732 }
733
734 func (c *ctxtz) oplook(p *obj.Prog) *Optab {
735
736 if p.Optab != 0 {
737 return &optab[p.Optab-1]
738 }
739 if len(p.RestArgs) > 3 {
740 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs))
741 return nil
742 }
743
744
745 p.From.Class = int8(c.aclass(&p.From) + 1)
746 p.To.Class = int8(c.aclass(&p.To) + 1)
747 for i := range p.RestArgs {
748 p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1)
749 }
750
751
752 args := [...]int8{
753 p.From.Class - 1,
754 C_NONE,
755 C_NONE,
756 C_NONE,
757 C_NONE,
758 p.To.Class - 1,
759 }
760
761 switch {
762 case REG_R0 <= p.Reg && p.Reg <= REG_R15:
763 args[1] = C_REG
764 case REG_V0 <= p.Reg && p.Reg <= REG_V31:
765 args[1] = C_VREG
766 case REG_F0 <= p.Reg && p.Reg <= REG_F15:
767 args[1] = C_FREG
768 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15:
769 args[1] = C_AREG
770 }
771
772 for i, a := range p.RestArgs {
773 args[2+i] = a.Class - 1
774 }
775
776
777 ops := oprange[p.As&obj.AMask]
778 cmp := [len(args)]*[C_NCLASS]bool{}
779 for i := range cmp {
780 cmp[i] = &xcmp[args[i]]
781 }
782 for i := range ops {
783 op := &ops[i]
784 if cmp[0][op.a1] && cmp[1][op.a2] &&
785 cmp[2][op.a3] && cmp[3][op.a4] &&
786 cmp[4][op.a5] && cmp[5][op.a6] {
787 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
788 return op
789 }
790 }
791
792
793 s := ""
794 for _, a := range args {
795 s += fmt.Sprintf(" %v", DRconv(int(a)))
796 }
797 c.ctxt.Diag("illegal combination %v%v\n", p.As, s)
798 c.ctxt.Diag("prog: %v\n", p)
799 return nil
800 }
801
802 func cmp(a int, b int) bool {
803 if a == b {
804 return true
805 }
806 switch a {
807 case C_DCON:
808 if b == C_LCON {
809 return true
810 }
811 fallthrough
812 case C_LCON:
813 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
814 return true
815 }
816
817 case C_ADDCON:
818 if b == C_ZCON || b == C_SCON {
819 return true
820 }
821
822 case C_ANDCON:
823 if b == C_ZCON || b == C_SCON {
824 return true
825 }
826
827 case C_UCON:
828 if b == C_ZCON || b == C_SCON {
829 return true
830 }
831
832 case C_SCON:
833 if b == C_ZCON {
834 return true
835 }
836
837 case C_LACON:
838 if b == C_SACON {
839 return true
840 }
841
842 case C_LBRA:
843 if b == C_SBRA {
844 return true
845 }
846
847 case C_LAUTO:
848 if b == C_SAUTO {
849 return true
850 }
851
852 case C_LOREG:
853 if b == C_ZOREG || b == C_SOREG {
854 return true
855 }
856
857 case C_SOREG:
858 if b == C_ZOREG {
859 return true
860 }
861
862 case C_ANY:
863 return true
864 }
865
866 return false
867 }
868
869 func ocmp(p1, p2 Optab) int {
870 if p1.as != p2.as {
871 return int(p1.as) - int(p2.as)
872 }
873 if p1.a1 != p2.a1 {
874 return int(p1.a1) - int(p2.a1)
875 }
876 if p1.a2 != p2.a2 {
877 return int(p1.a2) - int(p2.a2)
878 }
879 if p1.a3 != p2.a3 {
880 return int(p1.a3) - int(p2.a3)
881 }
882 if p1.a4 != p2.a4 {
883 return int(p1.a4) - int(p2.a4)
884 }
885 return 0
886 }
887 func opset(a, b obj.As) {
888 oprange[a&obj.AMask] = oprange[b&obj.AMask]
889 }
890
891 func buildop(ctxt *obj.Link) {
892 if oprange[AORW&obj.AMask] != nil {
893
894
895
896 return
897 }
898
899 for i := 0; i < C_NCLASS; i++ {
900 for n := 0; n < C_NCLASS; n++ {
901 if cmp(n, i) {
902 xcmp[i][n] = true
903 }
904 }
905 }
906 slices.SortFunc(optab, ocmp)
907 for i := 0; i < len(optab); i++ {
908 r := optab[i].as
909 start := i
910 for ; i+1 < len(optab); i++ {
911 if optab[i+1].as != r {
912 break
913 }
914 }
915 oprange[r&obj.AMask] = optab[start : i+1]
916
917
918
919 switch r {
920 case AADD:
921 opset(AADDC, r)
922 opset(AADDW, r)
923 opset(AADDE, r)
924 opset(AMULLD, r)
925 opset(AMULLW, r)
926 case ADIVW:
927 opset(ADIVD, r)
928 opset(ADIVDU, r)
929 opset(ADIVWU, r)
930 opset(AMODD, r)
931 opset(AMODDU, r)
932 opset(AMODW, r)
933 opset(AMODWU, r)
934 case AMULHD:
935 opset(AMULHDU, r)
936 case AMOVBZ:
937 opset(AMOVH, r)
938 opset(AMOVHZ, r)
939 case ALA:
940 opset(ALAY, r)
941 case AMVC:
942 opset(AMVCIN, r)
943 opset(ACLC, r)
944 opset(AXC, r)
945 opset(AOC, r)
946 opset(ANC, r)
947 case ASTCK:
948 opset(ASTCKC, r)
949 opset(ASTCKE, r)
950 opset(ASTCKF, r)
951 case ALAAG:
952 opset(ALAA, r)
953 opset(ALAAL, r)
954 opset(ALAALG, r)
955 opset(ALAN, r)
956 opset(ALANG, r)
957 opset(ALAX, r)
958 opset(ALAXG, r)
959 opset(ALAO, r)
960 opset(ALAOG, r)
961 case ASTMG:
962 opset(ASTMY, r)
963 case ALMG:
964 opset(ALMY, r)
965 case ABEQ:
966 opset(ABGE, r)
967 opset(ABGT, r)
968 opset(ABLE, r)
969 opset(ABLT, r)
970 opset(ABNE, r)
971 opset(ABVC, r)
972 opset(ABVS, r)
973 opset(ABLEU, r)
974 opset(ABLTU, r)
975 case ABR:
976 opset(ABL, r)
977 case ABC:
978 opset(ABCL, r)
979 case AFABS:
980 opset(AFNABS, r)
981 opset(ALPDFR, r)
982 opset(ALNDFR, r)
983 opset(AFNEG, r)
984 opset(AFNEGS, r)
985 opset(ALCDBR, r)
986 opset(ALEDBR, r)
987 opset(ALDEBR, r)
988 opset(AFSQRT, r)
989 opset(AFSQRTS, r)
990 case AFADD:
991 opset(AFADDS, r)
992 opset(AFDIV, r)
993 opset(AFDIVS, r)
994 opset(AFSUB, r)
995 opset(AFSUBS, r)
996 case AFMADD:
997 opset(AFMADDS, r)
998 opset(AFMSUB, r)
999 opset(AFMSUBS, r)
1000 case AFMUL:
1001 opset(AFMULS, r)
1002 case AFCMPO:
1003 opset(AFCMPU, r)
1004 opset(ACEBR, r)
1005 case AAND:
1006 opset(AOR, r)
1007 opset(AXOR, r)
1008 case AANDW:
1009 opset(AORW, r)
1010 opset(AXORW, r)
1011 case ASLD:
1012 opset(ASRD, r)
1013 opset(ASLW, r)
1014 opset(ASRW, r)
1015 opset(ASRAD, r)
1016 opset(ASRAW, r)
1017 opset(ARLL, r)
1018 opset(ARLLG, r)
1019 case ARNSBG:
1020 opset(ARXSBG, r)
1021 opset(AROSBG, r)
1022 opset(ARNSBGT, r)
1023 opset(ARXSBGT, r)
1024 opset(AROSBGT, r)
1025 opset(ARISBG, r)
1026 opset(ARISBGN, r)
1027 opset(ARISBGZ, r)
1028 opset(ARISBGNZ, r)
1029 opset(ARISBHG, r)
1030 opset(ARISBLG, r)
1031 opset(ARISBHGZ, r)
1032 opset(ARISBLGZ, r)
1033 case ACSG:
1034 opset(ACS, r)
1035 case ASUB:
1036 opset(ASUBC, r)
1037 opset(ASUBE, r)
1038 opset(ASUBW, r)
1039 case ANEG:
1040 opset(ANEGW, r)
1041 case AFMOVD:
1042 opset(AFMOVS, r)
1043 case AMOVDBR:
1044 opset(AMOVWBR, r)
1045 case ACMP:
1046 opset(ACMPW, r)
1047 case ACMPU:
1048 opset(ACMPWU, r)
1049 case ATMHH:
1050 opset(ATMHL, r)
1051 opset(ATMLH, r)
1052 opset(ATMLL, r)
1053 case ACEFBRA:
1054 opset(ACDFBRA, r)
1055 opset(ACEGBRA, r)
1056 opset(ACDGBRA, r)
1057 opset(ACELFBR, r)
1058 opset(ACDLFBR, r)
1059 opset(ACELGBR, r)
1060 opset(ACDLGBR, r)
1061 case ACFEBRA:
1062 opset(ACFDBRA, r)
1063 opset(ACGEBRA, r)
1064 opset(ACGDBRA, r)
1065 opset(ACLFEBR, r)
1066 opset(ACLFDBR, r)
1067 opset(ACLGEBR, r)
1068 opset(ACLGDBR, r)
1069 case AFIEBR:
1070 opset(AFIDBR, r)
1071 case ACMPBEQ:
1072 opset(ACMPBGE, r)
1073 opset(ACMPBGT, r)
1074 opset(ACMPBLE, r)
1075 opset(ACMPBLT, r)
1076 opset(ACMPBNE, r)
1077 case ACMPUBEQ:
1078 opset(ACMPUBGE, r)
1079 opset(ACMPUBGT, r)
1080 opset(ACMPUBLE, r)
1081 opset(ACMPUBLT, r)
1082 opset(ACMPUBNE, r)
1083 case ACGRJ:
1084 opset(ACRJ, r)
1085 case ACLGRJ:
1086 opset(ACLRJ, r)
1087 case ACGIJ:
1088 opset(ACIJ, r)
1089 case ACLGIJ:
1090 opset(ACLIJ, r)
1091 case AMOVDEQ:
1092 opset(AMOVDGE, r)
1093 opset(AMOVDGT, r)
1094 opset(AMOVDLE, r)
1095 opset(AMOVDLT, r)
1096 opset(AMOVDNE, r)
1097 case ALOCGR:
1098 opset(ALOCR, r)
1099 case ALTDBR:
1100 opset(ALTEBR, r)
1101 case ATCDB:
1102 opset(ATCEB, r)
1103 case AVL:
1104 opset(AVLLEZB, r)
1105 opset(AVLLEZH, r)
1106 opset(AVLLEZF, r)
1107 opset(AVLLEZG, r)
1108 opset(AVLREPB, r)
1109 opset(AVLREPH, r)
1110 opset(AVLREPF, r)
1111 opset(AVLREPG, r)
1112 case AVLEG:
1113 opset(AVLBB, r)
1114 opset(AVLEB, r)
1115 opset(AVLEH, r)
1116 opset(AVLEF, r)
1117 opset(AVLEG, r)
1118 opset(AVLREP, r)
1119 case AVSTEG:
1120 opset(AVSTEB, r)
1121 opset(AVSTEH, r)
1122 opset(AVSTEF, r)
1123 case AVSCEG:
1124 opset(AVSCEF, r)
1125 case AVGEG:
1126 opset(AVGEF, r)
1127 case AVESLG:
1128 opset(AVESLB, r)
1129 opset(AVESLH, r)
1130 opset(AVESLF, r)
1131 opset(AVERLLB, r)
1132 opset(AVERLLH, r)
1133 opset(AVERLLF, r)
1134 opset(AVERLLG, r)
1135 opset(AVESRAB, r)
1136 opset(AVESRAH, r)
1137 opset(AVESRAF, r)
1138 opset(AVESRAG, r)
1139 opset(AVESRLB, r)
1140 opset(AVESRLH, r)
1141 opset(AVESRLF, r)
1142 opset(AVESRLG, r)
1143 case AVLGVG:
1144 opset(AVLGVB, r)
1145 opset(AVLGVH, r)
1146 opset(AVLGVF, r)
1147 case AVLVGG:
1148 opset(AVLVGB, r)
1149 opset(AVLVGH, r)
1150 opset(AVLVGF, r)
1151 case AVZERO:
1152 opset(AVONE, r)
1153 case AVREPIG:
1154 opset(AVREPIB, r)
1155 opset(AVREPIH, r)
1156 opset(AVREPIF, r)
1157 case AVLEIG:
1158 opset(AVLEIB, r)
1159 opset(AVLEIH, r)
1160 opset(AVLEIF, r)
1161 case AVGMG:
1162 opset(AVGMB, r)
1163 opset(AVGMH, r)
1164 opset(AVGMF, r)
1165 case AVREPG:
1166 opset(AVREPB, r)
1167 opset(AVREPH, r)
1168 opset(AVREPF, r)
1169 case AVERIMG:
1170 opset(AVERIMB, r)
1171 opset(AVERIMH, r)
1172 opset(AVERIMF, r)
1173 case AVFTCIDB:
1174 opset(AWFTCIDB, r)
1175 case AVLR:
1176 opset(AVUPHB, r)
1177 opset(AVUPHH, r)
1178 opset(AVUPHF, r)
1179 opset(AVUPLHB, r)
1180 opset(AVUPLHH, r)
1181 opset(AVUPLHF, r)
1182 opset(AVUPLB, r)
1183 opset(AVUPLHW, r)
1184 opset(AVUPLF, r)
1185 opset(AVUPLLB, r)
1186 opset(AVUPLLH, r)
1187 opset(AVUPLLF, r)
1188 opset(AVCLZB, r)
1189 opset(AVCLZH, r)
1190 opset(AVCLZF, r)
1191 opset(AVCLZG, r)
1192 opset(AVCTZB, r)
1193 opset(AVCTZH, r)
1194 opset(AVCTZF, r)
1195 opset(AVCTZG, r)
1196 opset(AVLDEB, r)
1197 opset(AWLDEB, r)
1198 opset(AVFLCDB, r)
1199 opset(AWFLCDB, r)
1200 opset(AVFLNDB, r)
1201 opset(AWFLNDB, r)
1202 opset(AVFLPDB, r)
1203 opset(AWFLPDB, r)
1204 opset(AVFSQDB, r)
1205 opset(AWFSQDB, r)
1206 opset(AVISTRB, r)
1207 opset(AVISTRH, r)
1208 opset(AVISTRF, r)
1209 opset(AVISTRBS, r)
1210 opset(AVISTRHS, r)
1211 opset(AVISTRFS, r)
1212 opset(AVLCB, r)
1213 opset(AVLCH, r)
1214 opset(AVLCF, r)
1215 opset(AVLCG, r)
1216 opset(AVLPB, r)
1217 opset(AVLPH, r)
1218 opset(AVLPF, r)
1219 opset(AVLPG, r)
1220 opset(AVPOPCT, r)
1221 opset(AVSEGB, r)
1222 opset(AVSEGH, r)
1223 opset(AVSEGF, r)
1224 case AVECG:
1225 opset(AVECB, r)
1226 opset(AVECH, r)
1227 opset(AVECF, r)
1228 opset(AVECLB, r)
1229 opset(AVECLH, r)
1230 opset(AVECLF, r)
1231 opset(AVECLG, r)
1232 opset(AWFCDB, r)
1233 opset(AWFKDB, r)
1234 case AVCEQG:
1235 opset(AVCEQB, r)
1236 opset(AVCEQH, r)
1237 opset(AVCEQF, r)
1238 opset(AVCEQBS, r)
1239 opset(AVCEQHS, r)
1240 opset(AVCEQFS, r)
1241 opset(AVCEQGS, r)
1242 opset(AVCHB, r)
1243 opset(AVCHH, r)
1244 opset(AVCHF, r)
1245 opset(AVCHG, r)
1246 opset(AVCHBS, r)
1247 opset(AVCHHS, r)
1248 opset(AVCHFS, r)
1249 opset(AVCHGS, r)
1250 opset(AVCHLB, r)
1251 opset(AVCHLH, r)
1252 opset(AVCHLF, r)
1253 opset(AVCHLG, r)
1254 opset(AVCHLBS, r)
1255 opset(AVCHLHS, r)
1256 opset(AVCHLFS, r)
1257 opset(AVCHLGS, r)
1258 case AVFAEF:
1259 opset(AVFAEB, r)
1260 opset(AVFAEH, r)
1261 opset(AVFAEBS, r)
1262 opset(AVFAEHS, r)
1263 opset(AVFAEFS, r)
1264 opset(AVFAEZB, r)
1265 opset(AVFAEZH, r)
1266 opset(AVFAEZF, r)
1267 opset(AVFAEZBS, r)
1268 opset(AVFAEZHS, r)
1269 opset(AVFAEZFS, r)
1270 opset(AVFEEB, r)
1271 opset(AVFEEH, r)
1272 opset(AVFEEF, r)
1273 opset(AVFEEBS, r)
1274 opset(AVFEEHS, r)
1275 opset(AVFEEFS, r)
1276 opset(AVFEEZB, r)
1277 opset(AVFEEZH, r)
1278 opset(AVFEEZF, r)
1279 opset(AVFEEZBS, r)
1280 opset(AVFEEZHS, r)
1281 opset(AVFEEZFS, r)
1282 opset(AVFENEB, r)
1283 opset(AVFENEH, r)
1284 opset(AVFENEF, r)
1285 opset(AVFENEBS, r)
1286 opset(AVFENEHS, r)
1287 opset(AVFENEFS, r)
1288 opset(AVFENEZB, r)
1289 opset(AVFENEZH, r)
1290 opset(AVFENEZF, r)
1291 opset(AVFENEZBS, r)
1292 opset(AVFENEZHS, r)
1293 opset(AVFENEZFS, r)
1294 case AVPKSG:
1295 opset(AVPKSH, r)
1296 opset(AVPKSF, r)
1297 opset(AVPKSHS, r)
1298 opset(AVPKSFS, r)
1299 opset(AVPKSGS, r)
1300 opset(AVPKLSH, r)
1301 opset(AVPKLSF, r)
1302 opset(AVPKLSG, r)
1303 opset(AVPKLSHS, r)
1304 opset(AVPKLSFS, r)
1305 opset(AVPKLSGS, r)
1306 case AVAQ:
1307 opset(AVAB, r)
1308 opset(AVAH, r)
1309 opset(AVAF, r)
1310 opset(AVAG, r)
1311 opset(AVACCB, r)
1312 opset(AVACCH, r)
1313 opset(AVACCF, r)
1314 opset(AVACCG, r)
1315 opset(AVACCQ, r)
1316 opset(AVN, r)
1317 opset(AVNC, r)
1318 opset(AVAVGB, r)
1319 opset(AVAVGH, r)
1320 opset(AVAVGF, r)
1321 opset(AVAVGG, r)
1322 opset(AVAVGLB, r)
1323 opset(AVAVGLH, r)
1324 opset(AVAVGLF, r)
1325 opset(AVAVGLG, r)
1326 opset(AVCKSM, r)
1327 opset(AVX, r)
1328 opset(AVFADB, r)
1329 opset(AWFADB, r)
1330 opset(AVFCEDB, r)
1331 opset(AVFCEDBS, r)
1332 opset(AWFCEDB, r)
1333 opset(AWFCEDBS, r)
1334 opset(AVFCHDB, r)
1335 opset(AVFCHDBS, r)
1336 opset(AWFCHDB, r)
1337 opset(AWFCHDBS, r)
1338 opset(AVFCHEDB, r)
1339 opset(AVFCHEDBS, r)
1340 opset(AWFCHEDB, r)
1341 opset(AWFCHEDBS, r)
1342 opset(AVFMDB, r)
1343 opset(AWFMDB, r)
1344 opset(AVGFMB, r)
1345 opset(AVGFMH, r)
1346 opset(AVGFMF, r)
1347 opset(AVGFMG, r)
1348 opset(AVMXB, r)
1349 opset(AVMXH, r)
1350 opset(AVMXF, r)
1351 opset(AVMXG, r)
1352 opset(AVMXLB, r)
1353 opset(AVMXLH, r)
1354 opset(AVMXLF, r)
1355 opset(AVMXLG, r)
1356 opset(AVMNB, r)
1357 opset(AVMNH, r)
1358 opset(AVMNF, r)
1359 opset(AVMNG, r)
1360 opset(AVMNLB, r)
1361 opset(AVMNLH, r)
1362 opset(AVMNLF, r)
1363 opset(AVMNLG, r)
1364 opset(AVMRHB, r)
1365 opset(AVMRHH, r)
1366 opset(AVMRHF, r)
1367 opset(AVMRHG, r)
1368 opset(AVMRLB, r)
1369 opset(AVMRLH, r)
1370 opset(AVMRLF, r)
1371 opset(AVMRLG, r)
1372 opset(AVMEB, r)
1373 opset(AVMEH, r)
1374 opset(AVMEF, r)
1375 opset(AVMLEB, r)
1376 opset(AVMLEH, r)
1377 opset(AVMLEF, r)
1378 opset(AVMOB, r)
1379 opset(AVMOH, r)
1380 opset(AVMOF, r)
1381 opset(AVMLOB, r)
1382 opset(AVMLOH, r)
1383 opset(AVMLOF, r)
1384 opset(AVMHB, r)
1385 opset(AVMHH, r)
1386 opset(AVMHF, r)
1387 opset(AVMLHB, r)
1388 opset(AVMLHH, r)
1389 opset(AVMLHF, r)
1390 opset(AVMLH, r)
1391 opset(AVMLHW, r)
1392 opset(AVMLF, r)
1393 opset(AVNO, r)
1394 opset(AVO, r)
1395 opset(AVPKH, r)
1396 opset(AVPKF, r)
1397 opset(AVPKG, r)
1398 opset(AVSUMGH, r)
1399 opset(AVSUMGF, r)
1400 opset(AVSUMQF, r)
1401 opset(AVSUMQG, r)
1402 opset(AVSUMB, r)
1403 opset(AVSUMH, r)
1404 case AVERLLVG:
1405 opset(AVERLLVB, r)
1406 opset(AVERLLVH, r)
1407 opset(AVERLLVF, r)
1408 opset(AVESLVB, r)
1409 opset(AVESLVH, r)
1410 opset(AVESLVF, r)
1411 opset(AVESLVG, r)
1412 opset(AVESRAVB, r)
1413 opset(AVESRAVH, r)
1414 opset(AVESRAVF, r)
1415 opset(AVESRAVG, r)
1416 opset(AVESRLVB, r)
1417 opset(AVESRLVH, r)
1418 opset(AVESRLVF, r)
1419 opset(AVESRLVG, r)
1420 opset(AVFDDB, r)
1421 opset(AWFDDB, r)
1422 opset(AVFSDB, r)
1423 opset(AWFSDB, r)
1424 opset(AVSL, r)
1425 opset(AVSLB, r)
1426 opset(AVSRA, r)
1427 opset(AVSRAB, r)
1428 opset(AVSRL, r)
1429 opset(AVSRLB, r)
1430 opset(AVSB, r)
1431 opset(AVSH, r)
1432 opset(AVSF, r)
1433 opset(AVSG, r)
1434 opset(AVSQ, r)
1435 opset(AVSCBIB, r)
1436 opset(AVSCBIH, r)
1437 opset(AVSCBIF, r)
1438 opset(AVSCBIG, r)
1439 opset(AVSCBIQ, r)
1440 case AVACQ:
1441 opset(AVACCCQ, r)
1442 opset(AVGFMAB, r)
1443 opset(AVGFMAH, r)
1444 opset(AVGFMAF, r)
1445 opset(AVGFMAG, r)
1446 opset(AVMALB, r)
1447 opset(AVMALHW, r)
1448 opset(AVMALF, r)
1449 opset(AVMAHB, r)
1450 opset(AVMAHH, r)
1451 opset(AVMAHF, r)
1452 opset(AVMALHB, r)
1453 opset(AVMALHH, r)
1454 opset(AVMALHF, r)
1455 opset(AVMAEB, r)
1456 opset(AVMAEH, r)
1457 opset(AVMAEF, r)
1458 opset(AVMALEB, r)
1459 opset(AVMALEH, r)
1460 opset(AVMALEF, r)
1461 opset(AVMAOB, r)
1462 opset(AVMAOH, r)
1463 opset(AVMAOF, r)
1464 opset(AVMALOB, r)
1465 opset(AVMALOH, r)
1466 opset(AVMALOF, r)
1467 opset(AVSTRC, r)
1468 opset(AVSTRCB, r)
1469 opset(AVSTRCH, r)
1470 opset(AVSTRCF, r)
1471 opset(AVSTRCBS, r)
1472 opset(AVSTRCHS, r)
1473 opset(AVSTRCFS, r)
1474 opset(AVSTRCZB, r)
1475 opset(AVSTRCZH, r)
1476 opset(AVSTRCZF, r)
1477 opset(AVSTRCZBS, r)
1478 opset(AVSTRCZHS, r)
1479 opset(AVSTRCZFS, r)
1480 opset(AVSBCBIQ, r)
1481 opset(AVSBIQ, r)
1482 opset(AVMSLG, r)
1483 opset(AVMSLEG, r)
1484 opset(AVMSLOG, r)
1485 opset(AVMSLEOG, r)
1486 case AVSEL:
1487 opset(AVFMADB, r)
1488 opset(AWFMADB, r)
1489 opset(AVFMSDB, r)
1490 opset(AWFMSDB, r)
1491 opset(AVPERM, r)
1492 case AVFMAXDB:
1493 opset(AVFMAXSB, r)
1494 opset(AVFMINDB, r)
1495 opset(AVFMINSB, r)
1496 case AWFMAXDB:
1497 opset(AWFMAXSB, r)
1498 opset(AWFMINDB, r)
1499 opset(AWFMINSB, r)
1500 case AKM:
1501 opset(AKMC, r)
1502 opset(AKLMD, r)
1503 opset(AKIMD, r)
1504 case AKMA:
1505 opset(AKMCTR, r)
1506 }
1507 }
1508 }
1509
1510 const (
1511 op_A uint32 = 0x5A00
1512 op_AD uint32 = 0x6A00
1513 op_ADB uint32 = 0xED1A
1514 op_ADBR uint32 = 0xB31A
1515 op_ADR uint32 = 0x2A00
1516 op_ADTR uint32 = 0xB3D2
1517 op_ADTRA uint32 = 0xB3D2
1518 op_AE uint32 = 0x7A00
1519 op_AEB uint32 = 0xED0A
1520 op_AEBR uint32 = 0xB30A
1521 op_AER uint32 = 0x3A00
1522 op_AFI uint32 = 0xC209
1523 op_AG uint32 = 0xE308
1524 op_AGF uint32 = 0xE318
1525 op_AGFI uint32 = 0xC208
1526 op_AGFR uint32 = 0xB918
1527 op_AGHI uint32 = 0xA70B
1528 op_AGHIK uint32 = 0xECD9
1529 op_AGR uint32 = 0xB908
1530 op_AGRK uint32 = 0xB9E8
1531 op_AGSI uint32 = 0xEB7A
1532 op_AH uint32 = 0x4A00
1533 op_AHHHR uint32 = 0xB9C8
1534 op_AHHLR uint32 = 0xB9D8
1535 op_AHI uint32 = 0xA70A
1536 op_AHIK uint32 = 0xECD8
1537 op_AHY uint32 = 0xE37A
1538 op_AIH uint32 = 0xCC08
1539 op_AL uint32 = 0x5E00
1540 op_ALC uint32 = 0xE398
1541 op_ALCG uint32 = 0xE388
1542 op_ALCGR uint32 = 0xB988
1543 op_ALCR uint32 = 0xB998
1544 op_ALFI uint32 = 0xC20B
1545 op_ALG uint32 = 0xE30A
1546 op_ALGF uint32 = 0xE31A
1547 op_ALGFI uint32 = 0xC20A
1548 op_ALGFR uint32 = 0xB91A
1549 op_ALGHSIK uint32 = 0xECDB
1550 op_ALGR uint32 = 0xB90A
1551 op_ALGRK uint32 = 0xB9EA
1552 op_ALGSI uint32 = 0xEB7E
1553 op_ALHHHR uint32 = 0xB9CA
1554 op_ALHHLR uint32 = 0xB9DA
1555 op_ALHSIK uint32 = 0xECDA
1556 op_ALR uint32 = 0x1E00
1557 op_ALRK uint32 = 0xB9FA
1558 op_ALSI uint32 = 0xEB6E
1559 op_ALSIH uint32 = 0xCC0A
1560 op_ALSIHN uint32 = 0xCC0B
1561 op_ALY uint32 = 0xE35E
1562 op_AP uint32 = 0xFA00
1563 op_AR uint32 = 0x1A00
1564 op_ARK uint32 = 0xB9F8
1565 op_ASI uint32 = 0xEB6A
1566 op_AU uint32 = 0x7E00
1567 op_AUR uint32 = 0x3E00
1568 op_AW uint32 = 0x6E00
1569 op_AWR uint32 = 0x2E00
1570 op_AXBR uint32 = 0xB34A
1571 op_AXR uint32 = 0x3600
1572 op_AXTR uint32 = 0xB3DA
1573 op_AXTRA uint32 = 0xB3DA
1574 op_AY uint32 = 0xE35A
1575 op_BAKR uint32 = 0xB240
1576 op_BAL uint32 = 0x4500
1577 op_BALR uint32 = 0x0500
1578 op_BAS uint32 = 0x4D00
1579 op_BASR uint32 = 0x0D00
1580 op_BASSM uint32 = 0x0C00
1581 op_BC uint32 = 0x4700
1582 op_BCR uint32 = 0x0700
1583 op_BCT uint32 = 0x4600
1584 op_BCTG uint32 = 0xE346
1585 op_BCTGR uint32 = 0xB946
1586 op_BCTR uint32 = 0x0600
1587 op_BPP uint32 = 0xC700
1588 op_BPRP uint32 = 0xC500
1589 op_BRAS uint32 = 0xA705
1590 op_BRASL uint32 = 0xC005
1591 op_BRC uint32 = 0xA704
1592 op_BRCL uint32 = 0xC004
1593 op_BRCT uint32 = 0xA706
1594 op_BRCTG uint32 = 0xA707
1595 op_BRCTH uint32 = 0xCC06
1596 op_BRXH uint32 = 0x8400
1597 op_BRXHG uint32 = 0xEC44
1598 op_BRXLE uint32 = 0x8500
1599 op_BRXLG uint32 = 0xEC45
1600 op_BSA uint32 = 0xB25A
1601 op_BSG uint32 = 0xB258
1602 op_BSM uint32 = 0x0B00
1603 op_BXH uint32 = 0x8600
1604 op_BXHG uint32 = 0xEB44
1605 op_BXLE uint32 = 0x8700
1606 op_BXLEG uint32 = 0xEB45
1607 op_C uint32 = 0x5900
1608 op_CD uint32 = 0x6900
1609 op_CDB uint32 = 0xED19
1610 op_CDBR uint32 = 0xB319
1611 op_CDFBR uint32 = 0xB395
1612 op_CDFBRA uint32 = 0xB395
1613 op_CDFR uint32 = 0xB3B5
1614 op_CDFTR uint32 = 0xB951
1615 op_CDGBR uint32 = 0xB3A5
1616 op_CDGBRA uint32 = 0xB3A5
1617 op_CDGR uint32 = 0xB3C5
1618 op_CDGTR uint32 = 0xB3F1
1619 op_CDGTRA uint32 = 0xB3F1
1620 op_CDLFBR uint32 = 0xB391
1621 op_CDLFTR uint32 = 0xB953
1622 op_CDLGBR uint32 = 0xB3A1
1623 op_CDLGTR uint32 = 0xB952
1624 op_CDR uint32 = 0x2900
1625 op_CDS uint32 = 0xBB00
1626 op_CDSG uint32 = 0xEB3E
1627 op_CDSTR uint32 = 0xB3F3
1628 op_CDSY uint32 = 0xEB31
1629 op_CDTR uint32 = 0xB3E4
1630 op_CDUTR uint32 = 0xB3F2
1631 op_CDZT uint32 = 0xEDAA
1632 op_CE uint32 = 0x7900
1633 op_CEB uint32 = 0xED09
1634 op_CEBR uint32 = 0xB309
1635 op_CEDTR uint32 = 0xB3F4
1636 op_CEFBR uint32 = 0xB394
1637 op_CEFBRA uint32 = 0xB394
1638 op_CEFR uint32 = 0xB3B4
1639 op_CEGBR uint32 = 0xB3A4
1640 op_CEGBRA uint32 = 0xB3A4
1641 op_CEGR uint32 = 0xB3C4
1642 op_CELFBR uint32 = 0xB390
1643 op_CELGBR uint32 = 0xB3A0
1644 op_CER uint32 = 0x3900
1645 op_CEXTR uint32 = 0xB3FC
1646 op_CFC uint32 = 0xB21A
1647 op_CFDBR uint32 = 0xB399
1648 op_CFDBRA uint32 = 0xB399
1649 op_CFDR uint32 = 0xB3B9
1650 op_CFDTR uint32 = 0xB941
1651 op_CFEBR uint32 = 0xB398
1652 op_CFEBRA uint32 = 0xB398
1653 op_CFER uint32 = 0xB3B8
1654 op_CFI uint32 = 0xC20D
1655 op_CFXBR uint32 = 0xB39A
1656 op_CFXBRA uint32 = 0xB39A
1657 op_CFXR uint32 = 0xB3BA
1658 op_CFXTR uint32 = 0xB949
1659 op_CG uint32 = 0xE320
1660 op_CGDBR uint32 = 0xB3A9
1661 op_CGDBRA uint32 = 0xB3A9
1662 op_CGDR uint32 = 0xB3C9
1663 op_CGDTR uint32 = 0xB3E1
1664 op_CGDTRA uint32 = 0xB3E1
1665 op_CGEBR uint32 = 0xB3A8
1666 op_CGEBRA uint32 = 0xB3A8
1667 op_CGER uint32 = 0xB3C8
1668 op_CGF uint32 = 0xE330
1669 op_CGFI uint32 = 0xC20C
1670 op_CGFR uint32 = 0xB930
1671 op_CGFRL uint32 = 0xC60C
1672 op_CGH uint32 = 0xE334
1673 op_CGHI uint32 = 0xA70F
1674 op_CGHRL uint32 = 0xC604
1675 op_CGHSI uint32 = 0xE558
1676 op_CGIB uint32 = 0xECFC
1677 op_CGIJ uint32 = 0xEC7C
1678 op_CGIT uint32 = 0xEC70
1679 op_CGR uint32 = 0xB920
1680 op_CGRB uint32 = 0xECE4
1681 op_CGRJ uint32 = 0xEC64
1682 op_CGRL uint32 = 0xC608
1683 op_CGRT uint32 = 0xB960
1684 op_CGXBR uint32 = 0xB3AA
1685 op_CGXBRA uint32 = 0xB3AA
1686 op_CGXR uint32 = 0xB3CA
1687 op_CGXTR uint32 = 0xB3E9
1688 op_CGXTRA uint32 = 0xB3E9
1689 op_CH uint32 = 0x4900
1690 op_CHF uint32 = 0xE3CD
1691 op_CHHR uint32 = 0xB9CD
1692 op_CHHSI uint32 = 0xE554
1693 op_CHI uint32 = 0xA70E
1694 op_CHLR uint32 = 0xB9DD
1695 op_CHRL uint32 = 0xC605
1696 op_CHSI uint32 = 0xE55C
1697 op_CHY uint32 = 0xE379
1698 op_CIB uint32 = 0xECFE
1699 op_CIH uint32 = 0xCC0D
1700 op_CIJ uint32 = 0xEC7E
1701 op_CIT uint32 = 0xEC72
1702 op_CKSM uint32 = 0xB241
1703 op_CL uint32 = 0x5500
1704 op_CLC uint32 = 0xD500
1705 op_CLCL uint32 = 0x0F00
1706 op_CLCLE uint32 = 0xA900
1707 op_CLCLU uint32 = 0xEB8F
1708 op_CLFDBR uint32 = 0xB39D
1709 op_CLFDTR uint32 = 0xB943
1710 op_CLFEBR uint32 = 0xB39C
1711 op_CLFHSI uint32 = 0xE55D
1712 op_CLFI uint32 = 0xC20F
1713 op_CLFIT uint32 = 0xEC73
1714 op_CLFXBR uint32 = 0xB39E
1715 op_CLFXTR uint32 = 0xB94B
1716 op_CLG uint32 = 0xE321
1717 op_CLGDBR uint32 = 0xB3AD
1718 op_CLGDTR uint32 = 0xB942
1719 op_CLGEBR uint32 = 0xB3AC
1720 op_CLGF uint32 = 0xE331
1721 op_CLGFI uint32 = 0xC20E
1722 op_CLGFR uint32 = 0xB931
1723 op_CLGFRL uint32 = 0xC60E
1724 op_CLGHRL uint32 = 0xC606
1725 op_CLGHSI uint32 = 0xE559
1726 op_CLGIB uint32 = 0xECFD
1727 op_CLGIJ uint32 = 0xEC7D
1728 op_CLGIT uint32 = 0xEC71
1729 op_CLGR uint32 = 0xB921
1730 op_CLGRB uint32 = 0xECE5
1731 op_CLGRJ uint32 = 0xEC65
1732 op_CLGRL uint32 = 0xC60A
1733 op_CLGRT uint32 = 0xB961
1734 op_CLGT uint32 = 0xEB2B
1735 op_CLGXBR uint32 = 0xB3AE
1736 op_CLGXTR uint32 = 0xB94A
1737 op_CLHF uint32 = 0xE3CF
1738 op_CLHHR uint32 = 0xB9CF
1739 op_CLHHSI uint32 = 0xE555
1740 op_CLHLR uint32 = 0xB9DF
1741 op_CLHRL uint32 = 0xC607
1742 op_CLI uint32 = 0x9500
1743 op_CLIB uint32 = 0xECFF
1744 op_CLIH uint32 = 0xCC0F
1745 op_CLIJ uint32 = 0xEC7F
1746 op_CLIY uint32 = 0xEB55
1747 op_CLM uint32 = 0xBD00
1748 op_CLMH uint32 = 0xEB20
1749 op_CLMY uint32 = 0xEB21
1750 op_CLR uint32 = 0x1500
1751 op_CLRB uint32 = 0xECF7
1752 op_CLRJ uint32 = 0xEC77
1753 op_CLRL uint32 = 0xC60F
1754 op_CLRT uint32 = 0xB973
1755 op_CLST uint32 = 0xB25D
1756 op_CLT uint32 = 0xEB23
1757 op_CLY uint32 = 0xE355
1758 op_CMPSC uint32 = 0xB263
1759 op_CP uint32 = 0xF900
1760 op_CPSDR uint32 = 0xB372
1761 op_CPYA uint32 = 0xB24D
1762 op_CR uint32 = 0x1900
1763 op_CRB uint32 = 0xECF6
1764 op_CRDTE uint32 = 0xB98F
1765 op_CRJ uint32 = 0xEC76
1766 op_CRL uint32 = 0xC60D
1767 op_CRT uint32 = 0xB972
1768 op_CS uint32 = 0xBA00
1769 op_CSCH uint32 = 0xB230
1770 op_CSDTR uint32 = 0xB3E3
1771 op_CSG uint32 = 0xEB30
1772 op_CSP uint32 = 0xB250
1773 op_CSPG uint32 = 0xB98A
1774 op_CSST uint32 = 0xC802
1775 op_CSXTR uint32 = 0xB3EB
1776 op_CSY uint32 = 0xEB14
1777 op_CU12 uint32 = 0xB2A7
1778 op_CU14 uint32 = 0xB9B0
1779 op_CU21 uint32 = 0xB2A6
1780 op_CU24 uint32 = 0xB9B1
1781 op_CU41 uint32 = 0xB9B2
1782 op_CU42 uint32 = 0xB9B3
1783 op_CUDTR uint32 = 0xB3E2
1784 op_CUSE uint32 = 0xB257
1785 op_CUTFU uint32 = 0xB2A7
1786 op_CUUTF uint32 = 0xB2A6
1787 op_CUXTR uint32 = 0xB3EA
1788 op_CVB uint32 = 0x4F00
1789 op_CVBG uint32 = 0xE30E
1790 op_CVBY uint32 = 0xE306
1791 op_CVD uint32 = 0x4E00
1792 op_CVDG uint32 = 0xE32E
1793 op_CVDY uint32 = 0xE326
1794 op_CXBR uint32 = 0xB349
1795 op_CXFBR uint32 = 0xB396
1796 op_CXFBRA uint32 = 0xB396
1797 op_CXFR uint32 = 0xB3B6
1798 op_CXFTR uint32 = 0xB959
1799 op_CXGBR uint32 = 0xB3A6
1800 op_CXGBRA uint32 = 0xB3A6
1801 op_CXGR uint32 = 0xB3C6
1802 op_CXGTR uint32 = 0xB3F9
1803 op_CXGTRA uint32 = 0xB3F9
1804 op_CXLFBR uint32 = 0xB392
1805 op_CXLFTR uint32 = 0xB95B
1806 op_CXLGBR uint32 = 0xB3A2
1807 op_CXLGTR uint32 = 0xB95A
1808 op_CXR uint32 = 0xB369
1809 op_CXSTR uint32 = 0xB3FB
1810 op_CXTR uint32 = 0xB3EC
1811 op_CXUTR uint32 = 0xB3FA
1812 op_CXZT uint32 = 0xEDAB
1813 op_CY uint32 = 0xE359
1814 op_CZDT uint32 = 0xEDA8
1815 op_CZXT uint32 = 0xEDA9
1816 op_D uint32 = 0x5D00
1817 op_DD uint32 = 0x6D00
1818 op_DDB uint32 = 0xED1D
1819 op_DDBR uint32 = 0xB31D
1820 op_DDR uint32 = 0x2D00
1821 op_DDTR uint32 = 0xB3D1
1822 op_DDTRA uint32 = 0xB3D1
1823 op_DE uint32 = 0x7D00
1824 op_DEB uint32 = 0xED0D
1825 op_DEBR uint32 = 0xB30D
1826 op_DER uint32 = 0x3D00
1827 op_DIDBR uint32 = 0xB35B
1828 op_DIEBR uint32 = 0xB353
1829 op_DL uint32 = 0xE397
1830 op_DLG uint32 = 0xE387
1831 op_DLGR uint32 = 0xB987
1832 op_DLR uint32 = 0xB997
1833 op_DP uint32 = 0xFD00
1834 op_DR uint32 = 0x1D00
1835 op_DSG uint32 = 0xE30D
1836 op_DSGF uint32 = 0xE31D
1837 op_DSGFR uint32 = 0xB91D
1838 op_DSGR uint32 = 0xB90D
1839 op_DXBR uint32 = 0xB34D
1840 op_DXR uint32 = 0xB22D
1841 op_DXTR uint32 = 0xB3D9
1842 op_DXTRA uint32 = 0xB3D9
1843 op_EAR uint32 = 0xB24F
1844 op_ECAG uint32 = 0xEB4C
1845 op_ECTG uint32 = 0xC801
1846 op_ED uint32 = 0xDE00
1847 op_EDMK uint32 = 0xDF00
1848 op_EEDTR uint32 = 0xB3E5
1849 op_EEXTR uint32 = 0xB3ED
1850 op_EFPC uint32 = 0xB38C
1851 op_EPAIR uint32 = 0xB99A
1852 op_EPAR uint32 = 0xB226
1853 op_EPSW uint32 = 0xB98D
1854 op_EREG uint32 = 0xB249
1855 op_EREGG uint32 = 0xB90E
1856 op_ESAIR uint32 = 0xB99B
1857 op_ESAR uint32 = 0xB227
1858 op_ESDTR uint32 = 0xB3E7
1859 op_ESEA uint32 = 0xB99D
1860 op_ESTA uint32 = 0xB24A
1861 op_ESXTR uint32 = 0xB3EF
1862 op_ETND uint32 = 0xB2EC
1863 op_EX uint32 = 0x4400
1864 op_EXRL uint32 = 0xC600
1865 op_FIDBR uint32 = 0xB35F
1866 op_FIDBRA uint32 = 0xB35F
1867 op_FIDR uint32 = 0xB37F
1868 op_FIDTR uint32 = 0xB3D7
1869 op_FIEBR uint32 = 0xB357
1870 op_FIEBRA uint32 = 0xB357
1871 op_FIER uint32 = 0xB377
1872 op_FIXBR uint32 = 0xB347
1873 op_FIXBRA uint32 = 0xB347
1874 op_FIXR uint32 = 0xB367
1875 op_FIXTR uint32 = 0xB3DF
1876 op_FLOGR uint32 = 0xB983
1877 op_HDR uint32 = 0x2400
1878 op_HER uint32 = 0x3400
1879 op_HSCH uint32 = 0xB231
1880 op_IAC uint32 = 0xB224
1881 op_IC uint32 = 0x4300
1882 op_ICM uint32 = 0xBF00
1883 op_ICMH uint32 = 0xEB80
1884 op_ICMY uint32 = 0xEB81
1885 op_ICY uint32 = 0xE373
1886 op_IDTE uint32 = 0xB98E
1887 op_IEDTR uint32 = 0xB3F6
1888 op_IEXTR uint32 = 0xB3FE
1889 op_IIHF uint32 = 0xC008
1890 op_IIHH uint32 = 0xA500
1891 op_IIHL uint32 = 0xA501
1892 op_IILF uint32 = 0xC009
1893 op_IILH uint32 = 0xA502
1894 op_IILL uint32 = 0xA503
1895 op_IPK uint32 = 0xB20B
1896 op_IPM uint32 = 0xB222
1897 op_IPTE uint32 = 0xB221
1898 op_ISKE uint32 = 0xB229
1899 op_IVSK uint32 = 0xB223
1900 op_KDB uint32 = 0xED18
1901 op_KDBR uint32 = 0xB318
1902 op_KDTR uint32 = 0xB3E0
1903 op_KEB uint32 = 0xED08
1904 op_KEBR uint32 = 0xB308
1905 op_KIMD uint32 = 0xB93E
1906 op_KLMD uint32 = 0xB93F
1907 op_KM uint32 = 0xB92E
1908 op_KMAC uint32 = 0xB91E
1909 op_KMC uint32 = 0xB92F
1910 op_KMA uint32 = 0xB929
1911 op_KMCTR uint32 = 0xB92D
1912 op_KMF uint32 = 0xB92A
1913 op_KMO uint32 = 0xB92B
1914 op_KXBR uint32 = 0xB348
1915 op_KXTR uint32 = 0xB3E8
1916 op_L uint32 = 0x5800
1917 op_LA uint32 = 0x4100
1918 op_LAA uint32 = 0xEBF8
1919 op_LAAG uint32 = 0xEBE8
1920 op_LAAL uint32 = 0xEBFA
1921 op_LAALG uint32 = 0xEBEA
1922 op_LAE uint32 = 0x5100
1923 op_LAEY uint32 = 0xE375
1924 op_LAM uint32 = 0x9A00
1925 op_LAMY uint32 = 0xEB9A
1926 op_LAN uint32 = 0xEBF4
1927 op_LANG uint32 = 0xEBE4
1928 op_LAO uint32 = 0xEBF6
1929 op_LAOG uint32 = 0xEBE6
1930 op_LARL uint32 = 0xC000
1931 op_LASP uint32 = 0xE500
1932 op_LAT uint32 = 0xE39F
1933 op_LAX uint32 = 0xEBF7
1934 op_LAXG uint32 = 0xEBE7
1935 op_LAY uint32 = 0xE371
1936 op_LB uint32 = 0xE376
1937 op_LBH uint32 = 0xE3C0
1938 op_LBR uint32 = 0xB926
1939 op_LCDBR uint32 = 0xB313
1940 op_LCDFR uint32 = 0xB373
1941 op_LCDR uint32 = 0x2300
1942 op_LCEBR uint32 = 0xB303
1943 op_LCER uint32 = 0x3300
1944 op_LCGFR uint32 = 0xB913
1945 op_LCGR uint32 = 0xB903
1946 op_LCR uint32 = 0x1300
1947 op_LCTL uint32 = 0xB700
1948 op_LCTLG uint32 = 0xEB2F
1949 op_LCXBR uint32 = 0xB343
1950 op_LCXR uint32 = 0xB363
1951 op_LD uint32 = 0x6800
1952 op_LDE uint32 = 0xED24
1953 op_LDEB uint32 = 0xED04
1954 op_LDEBR uint32 = 0xB304
1955 op_LDER uint32 = 0xB324
1956 op_LDETR uint32 = 0xB3D4
1957 op_LDGR uint32 = 0xB3C1
1958 op_LDR uint32 = 0x2800
1959 op_LDXBR uint32 = 0xB345
1960 op_LDXBRA uint32 = 0xB345
1961 op_LDXR uint32 = 0x2500
1962 op_LDXTR uint32 = 0xB3DD
1963 op_LDY uint32 = 0xED65
1964 op_LE uint32 = 0x7800
1965 op_LEDBR uint32 = 0xB344
1966 op_LEDBRA uint32 = 0xB344
1967 op_LEDR uint32 = 0x3500
1968 op_LEDTR uint32 = 0xB3D5
1969 op_LER uint32 = 0x3800
1970 op_LEXBR uint32 = 0xB346
1971 op_LEXBRA uint32 = 0xB346
1972 op_LEXR uint32 = 0xB366
1973 op_LEY uint32 = 0xED64
1974 op_LFAS uint32 = 0xB2BD
1975 op_LFH uint32 = 0xE3CA
1976 op_LFHAT uint32 = 0xE3C8
1977 op_LFPC uint32 = 0xB29D
1978 op_LG uint32 = 0xE304
1979 op_LGAT uint32 = 0xE385
1980 op_LGB uint32 = 0xE377
1981 op_LGBR uint32 = 0xB906
1982 op_LGDR uint32 = 0xB3CD
1983 op_LGF uint32 = 0xE314
1984 op_LGFI uint32 = 0xC001
1985 op_LGFR uint32 = 0xB914
1986 op_LGFRL uint32 = 0xC40C
1987 op_LGH uint32 = 0xE315
1988 op_LGHI uint32 = 0xA709
1989 op_LGHR uint32 = 0xB907
1990 op_LGHRL uint32 = 0xC404
1991 op_LGR uint32 = 0xB904
1992 op_LGRL uint32 = 0xC408
1993 op_LH uint32 = 0x4800
1994 op_LHH uint32 = 0xE3C4
1995 op_LHI uint32 = 0xA708
1996 op_LHR uint32 = 0xB927
1997 op_LHRL uint32 = 0xC405
1998 op_LHY uint32 = 0xE378
1999 op_LLC uint32 = 0xE394
2000 op_LLCH uint32 = 0xE3C2
2001 op_LLCR uint32 = 0xB994
2002 op_LLGC uint32 = 0xE390
2003 op_LLGCR uint32 = 0xB984
2004 op_LLGF uint32 = 0xE316
2005 op_LLGFAT uint32 = 0xE39D
2006 op_LLGFR uint32 = 0xB916
2007 op_LLGFRL uint32 = 0xC40E
2008 op_LLGH uint32 = 0xE391
2009 op_LLGHR uint32 = 0xB985
2010 op_LLGHRL uint32 = 0xC406
2011 op_LLGT uint32 = 0xE317
2012 op_LLGTAT uint32 = 0xE39C
2013 op_LLGTR uint32 = 0xB917
2014 op_LLH uint32 = 0xE395
2015 op_LLHH uint32 = 0xE3C6
2016 op_LLHR uint32 = 0xB995
2017 op_LLHRL uint32 = 0xC402
2018 op_LLIHF uint32 = 0xC00E
2019 op_LLIHH uint32 = 0xA50C
2020 op_LLIHL uint32 = 0xA50D
2021 op_LLILF uint32 = 0xC00F
2022 op_LLILH uint32 = 0xA50E
2023 op_LLILL uint32 = 0xA50F
2024 op_LM uint32 = 0x9800
2025 op_LMD uint32 = 0xEF00
2026 op_LMG uint32 = 0xEB04
2027 op_LMH uint32 = 0xEB96
2028 op_LMY uint32 = 0xEB98
2029 op_LNDBR uint32 = 0xB311
2030 op_LNDFR uint32 = 0xB371
2031 op_LNDR uint32 = 0x2100
2032 op_LNEBR uint32 = 0xB301
2033 op_LNER uint32 = 0x3100
2034 op_LNGFR uint32 = 0xB911
2035 op_LNGR uint32 = 0xB901
2036 op_LNR uint32 = 0x1100
2037 op_LNXBR uint32 = 0xB341
2038 op_LNXR uint32 = 0xB361
2039 op_LOC uint32 = 0xEBF2
2040 op_LOCG uint32 = 0xEBE2
2041 op_LOCGR uint32 = 0xB9E2
2042 op_LOCR uint32 = 0xB9F2
2043 op_LPD uint32 = 0xC804
2044 op_LPDBR uint32 = 0xB310
2045 op_LPDFR uint32 = 0xB370
2046 op_LPDG uint32 = 0xC805
2047 op_LPDR uint32 = 0x2000
2048 op_LPEBR uint32 = 0xB300
2049 op_LPER uint32 = 0x3000
2050 op_LPGFR uint32 = 0xB910
2051 op_LPGR uint32 = 0xB900
2052 op_LPQ uint32 = 0xE38F
2053 op_LPR uint32 = 0x1000
2054 op_LPSW uint32 = 0x8200
2055 op_LPSWE uint32 = 0xB2B2
2056 op_LPTEA uint32 = 0xB9AA
2057 op_LPXBR uint32 = 0xB340
2058 op_LPXR uint32 = 0xB360
2059 op_LR uint32 = 0x1800
2060 op_LRA uint32 = 0xB100
2061 op_LRAG uint32 = 0xE303
2062 op_LRAY uint32 = 0xE313
2063 op_LRDR uint32 = 0x2500
2064 op_LRER uint32 = 0x3500
2065 op_LRL uint32 = 0xC40D
2066 op_LRV uint32 = 0xE31E
2067 op_LRVG uint32 = 0xE30F
2068 op_LRVGR uint32 = 0xB90F
2069 op_LRVH uint32 = 0xE31F
2070 op_LRVR uint32 = 0xB91F
2071 op_LT uint32 = 0xE312
2072 op_LTDBR uint32 = 0xB312
2073 op_LTDR uint32 = 0x2200
2074 op_LTDTR uint32 = 0xB3D6
2075 op_LTEBR uint32 = 0xB302
2076 op_LTER uint32 = 0x3200
2077 op_LTG uint32 = 0xE302
2078 op_LTGF uint32 = 0xE332
2079 op_LTGFR uint32 = 0xB912
2080 op_LTGR uint32 = 0xB902
2081 op_LTR uint32 = 0x1200
2082 op_LTXBR uint32 = 0xB342
2083 op_LTXR uint32 = 0xB362
2084 op_LTXTR uint32 = 0xB3DE
2085 op_LURA uint32 = 0xB24B
2086 op_LURAG uint32 = 0xB905
2087 op_LXD uint32 = 0xED25
2088 op_LXDB uint32 = 0xED05
2089 op_LXDBR uint32 = 0xB305
2090 op_LXDR uint32 = 0xB325
2091 op_LXDTR uint32 = 0xB3DC
2092 op_LXE uint32 = 0xED26
2093 op_LXEB uint32 = 0xED06
2094 op_LXEBR uint32 = 0xB306
2095 op_LXER uint32 = 0xB326
2096 op_LXR uint32 = 0xB365
2097 op_LY uint32 = 0xE358
2098 op_LZDR uint32 = 0xB375
2099 op_LZER uint32 = 0xB374
2100 op_LZXR uint32 = 0xB376
2101 op_M uint32 = 0x5C00
2102 op_MAD uint32 = 0xED3E
2103 op_MADB uint32 = 0xED1E
2104 op_MADBR uint32 = 0xB31E
2105 op_MADR uint32 = 0xB33E
2106 op_MAE uint32 = 0xED2E
2107 op_MAEB uint32 = 0xED0E
2108 op_MAEBR uint32 = 0xB30E
2109 op_MAER uint32 = 0xB32E
2110 op_MAY uint32 = 0xED3A
2111 op_MAYH uint32 = 0xED3C
2112 op_MAYHR uint32 = 0xB33C
2113 op_MAYL uint32 = 0xED38
2114 op_MAYLR uint32 = 0xB338
2115 op_MAYR uint32 = 0xB33A
2116 op_MC uint32 = 0xAF00
2117 op_MD uint32 = 0x6C00
2118 op_MDB uint32 = 0xED1C
2119 op_MDBR uint32 = 0xB31C
2120 op_MDE uint32 = 0x7C00
2121 op_MDEB uint32 = 0xED0C
2122 op_MDEBR uint32 = 0xB30C
2123 op_MDER uint32 = 0x3C00
2124 op_MDR uint32 = 0x2C00
2125 op_MDTR uint32 = 0xB3D0
2126 op_MDTRA uint32 = 0xB3D0
2127 op_ME uint32 = 0x7C00
2128 op_MEE uint32 = 0xED37
2129 op_MEEB uint32 = 0xED17
2130 op_MEEBR uint32 = 0xB317
2131 op_MEER uint32 = 0xB337
2132 op_MER uint32 = 0x3C00
2133 op_MFY uint32 = 0xE35C
2134 op_MGHI uint32 = 0xA70D
2135 op_MH uint32 = 0x4C00
2136 op_MHI uint32 = 0xA70C
2137 op_MHY uint32 = 0xE37C
2138 op_ML uint32 = 0xE396
2139 op_MLG uint32 = 0xE386
2140 op_MLGR uint32 = 0xB986
2141 op_MLR uint32 = 0xB996
2142 op_MP uint32 = 0xFC00
2143 op_MR uint32 = 0x1C00
2144 op_MS uint32 = 0x7100
2145 op_MSCH uint32 = 0xB232
2146 op_MSD uint32 = 0xED3F
2147 op_MSDB uint32 = 0xED1F
2148 op_MSDBR uint32 = 0xB31F
2149 op_MSDR uint32 = 0xB33F
2150 op_MSE uint32 = 0xED2F
2151 op_MSEB uint32 = 0xED0F
2152 op_MSEBR uint32 = 0xB30F
2153 op_MSER uint32 = 0xB32F
2154 op_MSFI uint32 = 0xC201
2155 op_MSG uint32 = 0xE30C
2156 op_MSGF uint32 = 0xE31C
2157 op_MSGFI uint32 = 0xC200
2158 op_MSGFR uint32 = 0xB91C
2159 op_MSGR uint32 = 0xB90C
2160 op_MSR uint32 = 0xB252
2161 op_MSTA uint32 = 0xB247
2162 op_MSY uint32 = 0xE351
2163 op_MVC uint32 = 0xD200
2164 op_MVCDK uint32 = 0xE50F
2165 op_MVCIN uint32 = 0xE800
2166 op_MVCK uint32 = 0xD900
2167 op_MVCL uint32 = 0x0E00
2168 op_MVCLE uint32 = 0xA800
2169 op_MVCLU uint32 = 0xEB8E
2170 op_MVCOS uint32 = 0xC800
2171 op_MVCP uint32 = 0xDA00
2172 op_MVCS uint32 = 0xDB00
2173 op_MVCSK uint32 = 0xE50E
2174 op_MVGHI uint32 = 0xE548
2175 op_MVHHI uint32 = 0xE544
2176 op_MVHI uint32 = 0xE54C
2177 op_MVI uint32 = 0x9200
2178 op_MVIY uint32 = 0xEB52
2179 op_MVN uint32 = 0xD100
2180 op_MVO uint32 = 0xF100
2181 op_MVPG uint32 = 0xB254
2182 op_MVST uint32 = 0xB255
2183 op_MVZ uint32 = 0xD300
2184 op_MXBR uint32 = 0xB34C
2185 op_MXD uint32 = 0x6700
2186 op_MXDB uint32 = 0xED07
2187 op_MXDBR uint32 = 0xB307
2188 op_MXDR uint32 = 0x2700
2189 op_MXR uint32 = 0x2600
2190 op_MXTR uint32 = 0xB3D8
2191 op_MXTRA uint32 = 0xB3D8
2192 op_MY uint32 = 0xED3B
2193 op_MYH uint32 = 0xED3D
2194 op_MYHR uint32 = 0xB33D
2195 op_MYL uint32 = 0xED39
2196 op_MYLR uint32 = 0xB339
2197 op_MYR uint32 = 0xB33B
2198 op_N uint32 = 0x5400
2199 op_NC uint32 = 0xD400
2200 op_NG uint32 = 0xE380
2201 op_NGR uint32 = 0xB980
2202 op_NGRK uint32 = 0xB9E4
2203 op_NI uint32 = 0x9400
2204 op_NIAI uint32 = 0xB2FA
2205 op_NIHF uint32 = 0xC00A
2206 op_NIHH uint32 = 0xA504
2207 op_NIHL uint32 = 0xA505
2208 op_NILF uint32 = 0xC00B
2209 op_NILH uint32 = 0xA506
2210 op_NILL uint32 = 0xA507
2211 op_NIY uint32 = 0xEB54
2212 op_NR uint32 = 0x1400
2213 op_NRK uint32 = 0xB9F4
2214 op_NTSTG uint32 = 0xE325
2215 op_NY uint32 = 0xE354
2216 op_O uint32 = 0x5600
2217 op_OC uint32 = 0xD600
2218 op_OG uint32 = 0xE381
2219 op_OGR uint32 = 0xB981
2220 op_OGRK uint32 = 0xB9E6
2221 op_OI uint32 = 0x9600
2222 op_OIHF uint32 = 0xC00C
2223 op_OIHH uint32 = 0xA508
2224 op_OIHL uint32 = 0xA509
2225 op_OILF uint32 = 0xC00D
2226 op_OILH uint32 = 0xA50A
2227 op_OILL uint32 = 0xA50B
2228 op_OIY uint32 = 0xEB56
2229 op_OR uint32 = 0x1600
2230 op_ORK uint32 = 0xB9F6
2231 op_OY uint32 = 0xE356
2232 op_PACK uint32 = 0xF200
2233 op_PALB uint32 = 0xB248
2234 op_PC uint32 = 0xB218
2235 op_PCC uint32 = 0xB92C
2236 op_PCKMO uint32 = 0xB928
2237 op_PFD uint32 = 0xE336
2238 op_PFDRL uint32 = 0xC602
2239 op_PFMF uint32 = 0xB9AF
2240 op_PFPO uint32 = 0x010A
2241 op_PGIN uint32 = 0xB22E
2242 op_PGOUT uint32 = 0xB22F
2243 op_PKA uint32 = 0xE900
2244 op_PKU uint32 = 0xE100
2245 op_PLO uint32 = 0xEE00
2246 op_POPCNT uint32 = 0xB9E1
2247 op_PPA uint32 = 0xB2E8
2248 op_PR uint32 = 0x0101
2249 op_PT uint32 = 0xB228
2250 op_PTF uint32 = 0xB9A2
2251 op_PTFF uint32 = 0x0104
2252 op_PTI uint32 = 0xB99E
2253 op_PTLB uint32 = 0xB20D
2254 op_QADTR uint32 = 0xB3F5
2255 op_QAXTR uint32 = 0xB3FD
2256 op_RCHP uint32 = 0xB23B
2257 op_RISBG uint32 = 0xEC55
2258 op_RISBGN uint32 = 0xEC59
2259 op_RISBHG uint32 = 0xEC5D
2260 op_RISBLG uint32 = 0xEC51
2261 op_RLL uint32 = 0xEB1D
2262 op_RLLG uint32 = 0xEB1C
2263 op_RNSBG uint32 = 0xEC54
2264 op_ROSBG uint32 = 0xEC56
2265 op_RP uint32 = 0xB277
2266 op_RRBE uint32 = 0xB22A
2267 op_RRBM uint32 = 0xB9AE
2268 op_RRDTR uint32 = 0xB3F7
2269 op_RRXTR uint32 = 0xB3FF
2270 op_RSCH uint32 = 0xB238
2271 op_RXSBG uint32 = 0xEC57
2272 op_S uint32 = 0x5B00
2273 op_SAC uint32 = 0xB219
2274 op_SACF uint32 = 0xB279
2275 op_SAL uint32 = 0xB237
2276 op_SAM24 uint32 = 0x010C
2277 op_SAM31 uint32 = 0x010D
2278 op_SAM64 uint32 = 0x010E
2279 op_SAR uint32 = 0xB24E
2280 op_SCHM uint32 = 0xB23C
2281 op_SCK uint32 = 0xB204
2282 op_SCKC uint32 = 0xB206
2283 op_SCKPF uint32 = 0x0107
2284 op_SD uint32 = 0x6B00
2285 op_SDB uint32 = 0xED1B
2286 op_SDBR uint32 = 0xB31B
2287 op_SDR uint32 = 0x2B00
2288 op_SDTR uint32 = 0xB3D3
2289 op_SDTRA uint32 = 0xB3D3
2290 op_SE uint32 = 0x7B00
2291 op_SEB uint32 = 0xED0B
2292 op_SEBR uint32 = 0xB30B
2293 op_SER uint32 = 0x3B00
2294 op_SFASR uint32 = 0xB385
2295 op_SFPC uint32 = 0xB384
2296 op_SG uint32 = 0xE309
2297 op_SGF uint32 = 0xE319
2298 op_SGFR uint32 = 0xB919
2299 op_SGR uint32 = 0xB909
2300 op_SGRK uint32 = 0xB9E9
2301 op_SH uint32 = 0x4B00
2302 op_SHHHR uint32 = 0xB9C9
2303 op_SHHLR uint32 = 0xB9D9
2304 op_SHY uint32 = 0xE37B
2305 op_SIGP uint32 = 0xAE00
2306 op_SL uint32 = 0x5F00
2307 op_SLA uint32 = 0x8B00
2308 op_SLAG uint32 = 0xEB0B
2309 op_SLAK uint32 = 0xEBDD
2310 op_SLB uint32 = 0xE399
2311 op_SLBG uint32 = 0xE389
2312 op_SLBGR uint32 = 0xB989
2313 op_SLBR uint32 = 0xB999
2314 op_SLDA uint32 = 0x8F00
2315 op_SLDL uint32 = 0x8D00
2316 op_SLDT uint32 = 0xED40
2317 op_SLFI uint32 = 0xC205
2318 op_SLG uint32 = 0xE30B
2319 op_SLGF uint32 = 0xE31B
2320 op_SLGFI uint32 = 0xC204
2321 op_SLGFR uint32 = 0xB91B
2322 op_SLGR uint32 = 0xB90B
2323 op_SLGRK uint32 = 0xB9EB
2324 op_SLHHHR uint32 = 0xB9CB
2325 op_SLHHLR uint32 = 0xB9DB
2326 op_SLL uint32 = 0x8900
2327 op_SLLG uint32 = 0xEB0D
2328 op_SLLK uint32 = 0xEBDF
2329 op_SLR uint32 = 0x1F00
2330 op_SLRK uint32 = 0xB9FB
2331 op_SLXT uint32 = 0xED48
2332 op_SLY uint32 = 0xE35F
2333 op_SP uint32 = 0xFB00
2334 op_SPKA uint32 = 0xB20A
2335 op_SPM uint32 = 0x0400
2336 op_SPT uint32 = 0xB208
2337 op_SPX uint32 = 0xB210
2338 op_SQD uint32 = 0xED35
2339 op_SQDB uint32 = 0xED15
2340 op_SQDBR uint32 = 0xB315
2341 op_SQDR uint32 = 0xB244
2342 op_SQE uint32 = 0xED34
2343 op_SQEB uint32 = 0xED14
2344 op_SQEBR uint32 = 0xB314
2345 op_SQER uint32 = 0xB245
2346 op_SQXBR uint32 = 0xB316
2347 op_SQXR uint32 = 0xB336
2348 op_SR uint32 = 0x1B00
2349 op_SRA uint32 = 0x8A00
2350 op_SRAG uint32 = 0xEB0A
2351 op_SRAK uint32 = 0xEBDC
2352 op_SRDA uint32 = 0x8E00
2353 op_SRDL uint32 = 0x8C00
2354 op_SRDT uint32 = 0xED41
2355 op_SRK uint32 = 0xB9F9
2356 op_SRL uint32 = 0x8800
2357 op_SRLG uint32 = 0xEB0C
2358 op_SRLK uint32 = 0xEBDE
2359 op_SRNM uint32 = 0xB299
2360 op_SRNMB uint32 = 0xB2B8
2361 op_SRNMT uint32 = 0xB2B9
2362 op_SRP uint32 = 0xF000
2363 op_SRST uint32 = 0xB25E
2364 op_SRSTU uint32 = 0xB9BE
2365 op_SRXT uint32 = 0xED49
2366 op_SSAIR uint32 = 0xB99F
2367 op_SSAR uint32 = 0xB225
2368 op_SSCH uint32 = 0xB233
2369 op_SSKE uint32 = 0xB22B
2370 op_SSM uint32 = 0x8000
2371 op_ST uint32 = 0x5000
2372 op_STAM uint32 = 0x9B00
2373 op_STAMY uint32 = 0xEB9B
2374 op_STAP uint32 = 0xB212
2375 op_STC uint32 = 0x4200
2376 op_STCH uint32 = 0xE3C3
2377 op_STCK uint32 = 0xB205
2378 op_STCKC uint32 = 0xB207
2379 op_STCKE uint32 = 0xB278
2380 op_STCKF uint32 = 0xB27C
2381 op_STCM uint32 = 0xBE00
2382 op_STCMH uint32 = 0xEB2C
2383 op_STCMY uint32 = 0xEB2D
2384 op_STCPS uint32 = 0xB23A
2385 op_STCRW uint32 = 0xB239
2386 op_STCTG uint32 = 0xEB25
2387 op_STCTL uint32 = 0xB600
2388 op_STCY uint32 = 0xE372
2389 op_STD uint32 = 0x6000
2390 op_STDY uint32 = 0xED67
2391 op_STE uint32 = 0x7000
2392 op_STEY uint32 = 0xED66
2393 op_STFH uint32 = 0xE3CB
2394 op_STFL uint32 = 0xB2B1
2395 op_STFLE uint32 = 0xB2B0
2396 op_STFPC uint32 = 0xB29C
2397 op_STG uint32 = 0xE324
2398 op_STGRL uint32 = 0xC40B
2399 op_STH uint32 = 0x4000
2400 op_STHH uint32 = 0xE3C7
2401 op_STHRL uint32 = 0xC407
2402 op_STHY uint32 = 0xE370
2403 op_STIDP uint32 = 0xB202
2404 op_STM uint32 = 0x9000
2405 op_STMG uint32 = 0xEB24
2406 op_STMH uint32 = 0xEB26
2407 op_STMY uint32 = 0xEB90
2408 op_STNSM uint32 = 0xAC00
2409 op_STOC uint32 = 0xEBF3
2410 op_STOCG uint32 = 0xEBE3
2411 op_STOSM uint32 = 0xAD00
2412 op_STPQ uint32 = 0xE38E
2413 op_STPT uint32 = 0xB209
2414 op_STPX uint32 = 0xB211
2415 op_STRAG uint32 = 0xE502
2416 op_STRL uint32 = 0xC40F
2417 op_STRV uint32 = 0xE33E
2418 op_STRVG uint32 = 0xE32F
2419 op_STRVH uint32 = 0xE33F
2420 op_STSCH uint32 = 0xB234
2421 op_STSI uint32 = 0xB27D
2422 op_STURA uint32 = 0xB246
2423 op_STURG uint32 = 0xB925
2424 op_STY uint32 = 0xE350
2425 op_SU uint32 = 0x7F00
2426 op_SUR uint32 = 0x3F00
2427 op_SVC uint32 = 0x0A00
2428 op_SW uint32 = 0x6F00
2429 op_SWR uint32 = 0x2F00
2430 op_SXBR uint32 = 0xB34B
2431 op_SXR uint32 = 0x3700
2432 op_SXTR uint32 = 0xB3DB
2433 op_SXTRA uint32 = 0xB3DB
2434 op_SY uint32 = 0xE35B
2435 op_TABORT uint32 = 0xB2FC
2436 op_TAM uint32 = 0x010B
2437 op_TAR uint32 = 0xB24C
2438 op_TB uint32 = 0xB22C
2439 op_TBDR uint32 = 0xB351
2440 op_TBEDR uint32 = 0xB350
2441 op_TBEGIN uint32 = 0xE560
2442 op_TBEGINC uint32 = 0xE561
2443 op_TCDB uint32 = 0xED11
2444 op_TCEB uint32 = 0xED10
2445 op_TCXB uint32 = 0xED12
2446 op_TDCDT uint32 = 0xED54
2447 op_TDCET uint32 = 0xED50
2448 op_TDCXT uint32 = 0xED58
2449 op_TDGDT uint32 = 0xED55
2450 op_TDGET uint32 = 0xED51
2451 op_TDGXT uint32 = 0xED59
2452 op_TEND uint32 = 0xB2F8
2453 op_THDER uint32 = 0xB358
2454 op_THDR uint32 = 0xB359
2455 op_TM uint32 = 0x9100
2456 op_TMH uint32 = 0xA700
2457 op_TMHH uint32 = 0xA702
2458 op_TMHL uint32 = 0xA703
2459 op_TML uint32 = 0xA701
2460 op_TMLH uint32 = 0xA700
2461 op_TMLL uint32 = 0xA701
2462 op_TMY uint32 = 0xEB51
2463 op_TP uint32 = 0xEBC0
2464 op_TPI uint32 = 0xB236
2465 op_TPROT uint32 = 0xE501
2466 op_TR uint32 = 0xDC00
2467 op_TRACE uint32 = 0x9900
2468 op_TRACG uint32 = 0xEB0F
2469 op_TRAP2 uint32 = 0x01FF
2470 op_TRAP4 uint32 = 0xB2FF
2471 op_TRE uint32 = 0xB2A5
2472 op_TROO uint32 = 0xB993
2473 op_TROT uint32 = 0xB992
2474 op_TRT uint32 = 0xDD00
2475 op_TRTE uint32 = 0xB9BF
2476 op_TRTO uint32 = 0xB991
2477 op_TRTR uint32 = 0xD000
2478 op_TRTRE uint32 = 0xB9BD
2479 op_TRTT uint32 = 0xB990
2480 op_TS uint32 = 0x9300
2481 op_TSCH uint32 = 0xB235
2482 op_UNPK uint32 = 0xF300
2483 op_UNPKA uint32 = 0xEA00
2484 op_UNPKU uint32 = 0xE200
2485 op_UPT uint32 = 0x0102
2486 op_X uint32 = 0x5700
2487 op_XC uint32 = 0xD700
2488 op_XG uint32 = 0xE382
2489 op_XGR uint32 = 0xB982
2490 op_XGRK uint32 = 0xB9E7
2491 op_XI uint32 = 0x9700
2492 op_XIHF uint32 = 0xC006
2493 op_XILF uint32 = 0xC007
2494 op_XIY uint32 = 0xEB57
2495 op_XR uint32 = 0x1700
2496 op_XRK uint32 = 0xB9F7
2497 op_XSCH uint32 = 0xB276
2498 op_XY uint32 = 0xE357
2499 op_ZAP uint32 = 0xF800
2500 op_BRRK uint32 = 0x0001
2501
2502
2503 op_CXPT uint32 = 0xEDAF
2504 op_CDPT uint32 = 0xEDAE
2505 op_CPXT uint32 = 0xEDAD
2506 op_CPDT uint32 = 0xEDAC
2507 op_LZRF uint32 = 0xE33B
2508 op_LZRG uint32 = 0xE32A
2509 op_LCCB uint32 = 0xE727
2510 op_LOCHHI uint32 = 0xEC4E
2511 op_LOCHI uint32 = 0xEC42
2512 op_LOCGHI uint32 = 0xEC46
2513 op_LOCFH uint32 = 0xEBE0
2514 op_LOCFHR uint32 = 0xB9E0
2515 op_LLZRGF uint32 = 0xE33A
2516 op_STOCFH uint32 = 0xEBE1
2517 op_VA uint32 = 0xE7F3
2518 op_VACC uint32 = 0xE7F1
2519 op_VAC uint32 = 0xE7BB
2520 op_VACCC uint32 = 0xE7B9
2521 op_VN uint32 = 0xE768
2522 op_VNC uint32 = 0xE769
2523 op_VAVG uint32 = 0xE7F2
2524 op_VAVGL uint32 = 0xE7F0
2525 op_VCKSM uint32 = 0xE766
2526 op_VCEQ uint32 = 0xE7F8
2527 op_VCH uint32 = 0xE7FB
2528 op_VCHL uint32 = 0xE7F9
2529 op_VCLZ uint32 = 0xE753
2530 op_VCTZ uint32 = 0xE752
2531 op_VEC uint32 = 0xE7DB
2532 op_VECL uint32 = 0xE7D9
2533 op_VERIM uint32 = 0xE772
2534 op_VERLL uint32 = 0xE733
2535 op_VERLLV uint32 = 0xE773
2536 op_VESLV uint32 = 0xE770
2537 op_VESL uint32 = 0xE730
2538 op_VESRA uint32 = 0xE73A
2539 op_VESRAV uint32 = 0xE77A
2540 op_VESRL uint32 = 0xE738
2541 op_VESRLV uint32 = 0xE778
2542 op_VX uint32 = 0xE76D
2543 op_VFAE uint32 = 0xE782
2544 op_VFEE uint32 = 0xE780
2545 op_VFENE uint32 = 0xE781
2546 op_VFA uint32 = 0xE7E3
2547 op_WFK uint32 = 0xE7CA
2548 op_VFCE uint32 = 0xE7E8
2549 op_VFCH uint32 = 0xE7EB
2550 op_VFCHE uint32 = 0xE7EA
2551 op_WFC uint32 = 0xE7CB
2552 op_VCDG uint32 = 0xE7C3
2553 op_VCDLG uint32 = 0xE7C1
2554 op_VCGD uint32 = 0xE7C2
2555 op_VCLGD uint32 = 0xE7C0
2556 op_VFD uint32 = 0xE7E5
2557 op_VLDE uint32 = 0xE7C4
2558 op_VLED uint32 = 0xE7C5
2559 op_VFM uint32 = 0xE7E7
2560 op_VFMA uint32 = 0xE78F
2561 op_VFMS uint32 = 0xE78E
2562 op_VFPSO uint32 = 0xE7CC
2563 op_VFSQ uint32 = 0xE7CE
2564 op_VFS uint32 = 0xE7E2
2565 op_VFTCI uint32 = 0xE74A
2566 op_VGFM uint32 = 0xE7B4
2567 op_VGFMA uint32 = 0xE7BC
2568 op_VGEF uint32 = 0xE713
2569 op_VGEG uint32 = 0xE712
2570 op_VGBM uint32 = 0xE744
2571 op_VGM uint32 = 0xE746
2572 op_VISTR uint32 = 0xE75C
2573 op_VL uint32 = 0xE706
2574 op_VLR uint32 = 0xE756
2575 op_VLREP uint32 = 0xE705
2576 op_VLC uint32 = 0xE7DE
2577 op_VLEH uint32 = 0xE701
2578 op_VLEF uint32 = 0xE703
2579 op_VLEG uint32 = 0xE702
2580 op_VLEB uint32 = 0xE700
2581 op_VLEIH uint32 = 0xE741
2582 op_VLEIF uint32 = 0xE743
2583 op_VLEIG uint32 = 0xE742
2584 op_VLEIB uint32 = 0xE740
2585 op_VFI uint32 = 0xE7C7
2586 op_VLGV uint32 = 0xE721
2587 op_VLLEZ uint32 = 0xE704
2588 op_VLM uint32 = 0xE736
2589 op_VLP uint32 = 0xE7DF
2590 op_VLBB uint32 = 0xE707
2591 op_VLVG uint32 = 0xE722
2592 op_VLVGP uint32 = 0xE762
2593 op_VLL uint32 = 0xE737
2594 op_VMX uint32 = 0xE7FF
2595 op_VMXL uint32 = 0xE7FD
2596 op_VMRH uint32 = 0xE761
2597 op_VMRL uint32 = 0xE760
2598 op_VMN uint32 = 0xE7FE
2599 op_VMNL uint32 = 0xE7FC
2600 op_VMAE uint32 = 0xE7AE
2601 op_VMAH uint32 = 0xE7AB
2602 op_VMALE uint32 = 0xE7AC
2603 op_VMALH uint32 = 0xE7A9
2604 op_VMALO uint32 = 0xE7AD
2605 op_VMAL uint32 = 0xE7AA
2606 op_VMAO uint32 = 0xE7AF
2607 op_VME uint32 = 0xE7A6
2608 op_VMH uint32 = 0xE7A3
2609 op_VMLE uint32 = 0xE7A4
2610 op_VMLH uint32 = 0xE7A1
2611 op_VMLO uint32 = 0xE7A5
2612 op_VML uint32 = 0xE7A2
2613 op_VMO uint32 = 0xE7A7
2614 op_VNO uint32 = 0xE76B
2615 op_VO uint32 = 0xE76A
2616 op_VPK uint32 = 0xE794
2617 op_VPKLS uint32 = 0xE795
2618 op_VPKS uint32 = 0xE797
2619 op_VPERM uint32 = 0xE78C
2620 op_VPDI uint32 = 0xE784
2621 op_VPOPCT uint32 = 0xE750
2622 op_VREP uint32 = 0xE74D
2623 op_VREPI uint32 = 0xE745
2624 op_VSCEF uint32 = 0xE71B
2625 op_VSCEG uint32 = 0xE71A
2626 op_VSEL uint32 = 0xE78D
2627 op_VSL uint32 = 0xE774
2628 op_VSLB uint32 = 0xE775
2629 op_VSLDB uint32 = 0xE777
2630 op_VSRA uint32 = 0xE77E
2631 op_VSRAB uint32 = 0xE77F
2632 op_VSRL uint32 = 0xE77C
2633 op_VSRLB uint32 = 0xE77D
2634 op_VSEG uint32 = 0xE75F
2635 op_VST uint32 = 0xE70E
2636 op_VSTEH uint32 = 0xE709
2637 op_VSTEF uint32 = 0xE70B
2638 op_VSTEG uint32 = 0xE70A
2639 op_VSTEB uint32 = 0xE708
2640 op_VSTM uint32 = 0xE73E
2641 op_VSTRL uint32 = 0xE63D
2642 op_VSTL uint32 = 0xE73F
2643 op_VSTRC uint32 = 0xE78A
2644 op_VS uint32 = 0xE7F7
2645 op_VSCBI uint32 = 0xE7F5
2646 op_VSBCBI uint32 = 0xE7BD
2647 op_VSBI uint32 = 0xE7BF
2648 op_VSUMG uint32 = 0xE765
2649 op_VSUMQ uint32 = 0xE767
2650 op_VSUM uint32 = 0xE764
2651 op_VTM uint32 = 0xE7D8
2652 op_VUPH uint32 = 0xE7D7
2653 op_VUPLH uint32 = 0xE7D5
2654 op_VUPLL uint32 = 0xE7D4
2655 op_VUPL uint32 = 0xE7D6
2656 op_VMSL uint32 = 0xE7B8
2657 op_VFMAX uint32 = 0xE7EF
2658 op_VFMIN uint32 = 0xE7EE
2659
2660
2661 op_KDSA uint32 = 0xB93A
2662
2663 )
2664
2665 func oclass(a *obj.Addr) int {
2666 return int(a.Class) - 1
2667 }
2668
2669
2670
2671 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) {
2672 if sym == nil {
2673 c.ctxt.Diag("require symbol to apply relocation")
2674 }
2675 offset := int64(2)
2676 c.cursym.AddRel(c.ctxt, obj.Reloc{
2677 Type: objabi.R_PCRELDBL,
2678 Off: int32(c.pc + offset),
2679 Siz: 4,
2680 Sym: sym,
2681 Add: add + offset + 4,
2682 })
2683 }
2684
2685
2686
2687 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) {
2688 if sym == nil {
2689 c.ctxt.Diag("require symbol to apply relocation")
2690 }
2691 offset := int64(2)
2692 c.cursym.AddRel(c.ctxt, obj.Reloc{
2693 Type: objabi.R_CALL,
2694 Off: int32(c.pc + offset),
2695 Siz: 4,
2696 Sym: sym,
2697 Add: add + offset + int64(4),
2698 })
2699 }
2700
2701 func (c *ctxtz) branchMask(p *obj.Prog) CCMask {
2702 switch p.As {
2703 case ABRC, ALOCR, ALOCGR,
2704 ACRJ, ACGRJ, ACIJ, ACGIJ,
2705 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ:
2706 return CCMask(p.From.Offset)
2707 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ:
2708 return Equal
2709 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE:
2710 return GreaterOrEqual
2711 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT:
2712 return Greater
2713 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE:
2714 return LessOrEqual
2715 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT:
2716 return Less
2717 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE:
2718 return NotEqual
2719 case ABLEU:
2720 return NotGreater
2721 case ABLTU:
2722 return LessOrUnordered
2723 case ABVC:
2724 return Never
2725 case ABVS:
2726 return Unordered
2727 }
2728 c.ctxt.Diag("unknown conditional branch %v", p.As)
2729 return Always
2730 }
2731
2732 func regtmp(p *obj.Prog) uint32 {
2733 p.Mark |= USETMP
2734 return REGTMP
2735 }
2736
2737 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
2738 o := c.oplook(p)
2739
2740 if o == nil {
2741 return
2742 }
2743
2744
2745
2746
2747 switch o.i {
2748 default:
2749 c.ctxt.Diag("unknown index %d", o.i)
2750
2751 case 0:
2752 break
2753
2754 case 1:
2755 switch p.As {
2756 default:
2757 c.ctxt.Diag("unhandled operation: %v", p.As)
2758 case AMOVD:
2759 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2760
2761 case AMOVW:
2762 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2763 case AMOVH:
2764 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2765 case AMOVB:
2766 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2767
2768 case AMOVWZ:
2769 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2770 case AMOVHZ:
2771 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2772 case AMOVBZ:
2773 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2774
2775 case AMOVDBR:
2776 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2777 case AMOVWBR:
2778 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2779
2780 case AFMOVD, AFMOVS:
2781 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2782 }
2783
2784 case 2:
2785 r := p.Reg
2786 if r == 0 {
2787 r = p.To.Reg
2788 }
2789
2790 var opcode uint32
2791
2792 switch p.As {
2793 default:
2794 c.ctxt.Diag("invalid opcode")
2795 case AADD:
2796 opcode = op_AGRK
2797 case AADDC:
2798 opcode = op_ALGRK
2799 case AADDE:
2800 opcode = op_ALCGR
2801 case AADDW:
2802 opcode = op_ARK
2803 case AMULLW:
2804 opcode = op_MSGFR
2805 case AMULLD:
2806 opcode = op_MSGR
2807 case ADIVW, AMODW:
2808 opcode = op_DSGFR
2809 case ADIVWU, AMODWU:
2810 opcode = op_DLR
2811 case ADIVD, AMODD:
2812 opcode = op_DSGR
2813 case ADIVDU, AMODDU:
2814 opcode = op_DLGR
2815 }
2816
2817 switch p.As {
2818 default:
2819
2820 case AADD, AADDC, AADDW:
2821 if p.As == AADDW && r == p.To.Reg {
2822 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2823 } else {
2824 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2825 }
2826
2827 case AADDE, AMULLW, AMULLD:
2828 if r == p.To.Reg {
2829 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2830 } else if p.From.Reg == p.To.Reg {
2831 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2832 } else {
2833 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2834 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2835 }
2836
2837 case ADIVW, ADIVWU, ADIVD, ADIVDU:
2838 if p.As == ADIVWU || p.As == ADIVDU {
2839 zRI(op_LGHI, regtmp(p), 0, asm)
2840 }
2841 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2842 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2843 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
2844
2845 case AMODW, AMODWU, AMODD, AMODDU:
2846 if p.As == AMODWU || p.As == AMODDU {
2847 zRI(op_LGHI, regtmp(p), 0, asm)
2848 }
2849 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2850 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2851 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2852
2853 }
2854
2855 case 3:
2856 v := c.vregoff(&p.From)
2857 switch p.As {
2858 case AMOVBZ:
2859 v = int64(uint8(v))
2860 case AMOVHZ:
2861 v = int64(uint16(v))
2862 case AMOVWZ:
2863 v = int64(uint32(v))
2864 case AMOVB:
2865 v = int64(int8(v))
2866 case AMOVH:
2867 v = int64(int16(v))
2868 case AMOVW:
2869 v = int64(int32(v))
2870 }
2871 if int64(int16(v)) == v {
2872 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
2873 } else if v&0xffff0000 == v {
2874 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
2875 } else if v&0xffff00000000 == v {
2876 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
2877 } else if uint64(v)&0xffff000000000000 == uint64(v) {
2878 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
2879 } else if int64(int32(v)) == v {
2880 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
2881 } else if int64(uint32(v)) == v {
2882 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2883 } else if uint64(v)&0xffffffff00000000 == uint64(v) {
2884 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2885 } else {
2886 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2887 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2888 }
2889
2890 case 4:
2891 r := p.Reg
2892 if r == 0 {
2893 r = p.To.Reg
2894 }
2895 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2896 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm)
2897 switch p.As {
2898 case AMULHDU:
2899
2900 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2901 case AMULHD:
2902
2903
2904 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm)
2905 zRRE(op_NGR, REGTMP2, uint32(r), asm)
2906 zRRE(op_SGR, regtmp(p), REGTMP2, asm)
2907 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm)
2908 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm)
2909 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm)
2910 }
2911
2912 case 5:
2913 zI(op_SVC, 0, asm)
2914
2915 case 6:
2916 var oprr, oprre, oprrf uint32
2917 switch p.As {
2918 case AAND:
2919 oprre = op_NGR
2920 oprrf = op_NGRK
2921 case AANDW:
2922 oprr = op_NR
2923 oprrf = op_NRK
2924 case AOR:
2925 oprre = op_OGR
2926 oprrf = op_OGRK
2927 case AORW:
2928 oprr = op_OR
2929 oprrf = op_ORK
2930 case AXOR:
2931 oprre = op_XGR
2932 oprrf = op_XGRK
2933 case AXORW:
2934 oprr = op_XR
2935 oprrf = op_XRK
2936 }
2937 if p.Reg == 0 {
2938 if oprr != 0 {
2939 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2940 } else {
2941 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2942 }
2943 } else {
2944 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2945 }
2946
2947 case 7:
2948 d2 := c.vregoff(&p.From)
2949 b2 := p.From.Reg
2950 r3 := p.Reg
2951 if r3 == 0 {
2952 r3 = p.To.Reg
2953 }
2954 r1 := p.To.Reg
2955 var opcode uint32
2956 switch p.As {
2957 default:
2958 case ASLD:
2959 opcode = op_SLLG
2960 case ASRD:
2961 opcode = op_SRLG
2962 case ASLW:
2963 opcode = op_SLLK
2964 case ASRW:
2965 opcode = op_SRLK
2966 case ARLL:
2967 opcode = op_RLL
2968 case ARLLG:
2969 opcode = op_RLLG
2970 case ASRAW:
2971 opcode = op_SRAK
2972 case ASRAD:
2973 opcode = op_SRAG
2974 }
2975 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm)
2976
2977 case 8:
2978 if p.To.Reg&1 != 0 {
2979 c.ctxt.Diag("target must be an even-numbered register")
2980 }
2981
2982 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2983
2984 case 9:
2985 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2986
2987 case 10:
2988 r := int(p.Reg)
2989
2990 switch p.As {
2991 default:
2992 case ASUB:
2993 if r == 0 {
2994 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2995 } else {
2996 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2997 }
2998 case ASUBC:
2999 if r == 0 {
3000 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3001 } else {
3002 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
3003 }
3004 case ASUBE:
3005 if r == 0 {
3006 r = int(p.To.Reg)
3007 }
3008 if r == int(p.To.Reg) {
3009 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3010 } else if p.From.Reg == p.To.Reg {
3011 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm)
3012 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3013 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm)
3014 } else {
3015 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3016 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3017 }
3018 case ASUBW:
3019 if r == 0 {
3020 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3021 } else {
3022 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
3023 }
3024 }
3025
3026 case 11:
3027 v := int32(0)
3028
3029 if p.To.Target() != nil {
3030 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3031 }
3032
3033 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v {
3034 zRI(op_BRC, 0xF, uint32(v), asm)
3035 } else {
3036 if p.As == ABL {
3037 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm)
3038 } else {
3039 zRIL(_c, op_BRCL, 0xF, uint32(v), asm)
3040 }
3041 if p.To.Sym != nil {
3042 c.addcallreloc(p.To.Sym, p.To.Offset)
3043 }
3044 }
3045
3046 case 12:
3047 r1 := p.To.Reg
3048 d2 := c.vregoff(&p.From)
3049 b2 := p.From.Reg
3050 if b2 == 0 {
3051 b2 = REGSP
3052 }
3053 x2 := p.From.Index
3054 if -DISP20/2 > d2 || d2 >= DISP20/2 {
3055 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3056 if x2 != 0 {
3057 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3058 }
3059 x2 = int16(regtmp(p))
3060 d2 = 0
3061 }
3062 var opx, opxy uint32
3063 switch p.As {
3064 case AADD:
3065 opxy = op_AG
3066 case AADDC:
3067 opxy = op_ALG
3068 case AADDE:
3069 opxy = op_ALCG
3070 case AADDW:
3071 opx = op_A
3072 opxy = op_AY
3073 case AMULLW:
3074 opx = op_MS
3075 opxy = op_MSY
3076 case AMULLD:
3077 opxy = op_MSG
3078 case ASUB:
3079 opxy = op_SG
3080 case ASUBC:
3081 opxy = op_SLG
3082 case ASUBE:
3083 opxy = op_SLBG
3084 case ASUBW:
3085 opx = op_S
3086 opxy = op_SY
3087 case AAND:
3088 opxy = op_NG
3089 case AANDW:
3090 opx = op_N
3091 opxy = op_NY
3092 case AOR:
3093 opxy = op_OG
3094 case AORW:
3095 opx = op_O
3096 opxy = op_OY
3097 case AXOR:
3098 opxy = op_XG
3099 case AXORW:
3100 opx = op_X
3101 opxy = op_XY
3102 }
3103 if opx != 0 && 0 <= d2 && d2 < DISP12 {
3104 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3105 } else {
3106 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3107 }
3108
3109 case 13:
3110 r1 := p.To.Reg
3111 r2 := p.RestArgs[2].Reg
3112 i3 := uint8(p.From.Offset)
3113 i4 := uint8(p.RestArgs[0].Offset)
3114 i5 := uint8(p.RestArgs[1].Offset)
3115 switch p.As {
3116 case ARNSBGT, ARXSBGT, AROSBGT:
3117 i3 |= 0x80
3118 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ:
3119 i4 |= 0x80
3120 }
3121 var opcode uint32
3122 switch p.As {
3123 case ARNSBG, ARNSBGT:
3124 opcode = op_RNSBG
3125 case ARXSBG, ARXSBGT:
3126 opcode = op_RXSBG
3127 case AROSBG, AROSBGT:
3128 opcode = op_ROSBG
3129 case ARISBG, ARISBGZ:
3130 opcode = op_RISBG
3131 case ARISBGN, ARISBGNZ:
3132 opcode = op_RISBGN
3133 case ARISBHG, ARISBHGZ:
3134 opcode = op_RISBHG
3135 case ARISBLG, ARISBLGZ:
3136 opcode = op_RISBLG
3137 }
3138 zRIE(_f, opcode, uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm)
3139
3140 case 15:
3141 r := p.To.Reg
3142 if p.As == ABCL || p.As == ABL {
3143 zRR(op_BASR, uint32(REG_LR), uint32(r), asm)
3144 } else {
3145 zRR(op_BCR, uint32(Always), uint32(r), asm)
3146 }
3147
3148 case 16:
3149 v := int32(0)
3150 if p.To.Target() != nil {
3151 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3152 }
3153 mask := uint32(c.branchMask(p))
3154 if p.To.Sym == nil && int32(int16(v)) == v {
3155 zRI(op_BRC, mask, uint32(v), asm)
3156 } else {
3157 zRIL(_c, op_BRCL, mask, uint32(v), asm)
3158 }
3159 if p.To.Sym != nil {
3160 c.addrilreloc(p.To.Sym, p.To.Offset)
3161 }
3162
3163 case 17:
3164 m3 := uint32(c.branchMask(p))
3165 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3166
3167 case 18:
3168 if p.As == ABL {
3169 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
3170 } else {
3171 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm)
3172 }
3173
3174 case 19:
3175 d := c.vregoff(&p.From)
3176 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm)
3177 if d&1 != 0 {
3178 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm)
3179 d -= 1
3180 }
3181 c.addrilreloc(p.From.Sym, d)
3182
3183 case 21:
3184 v := c.vregoff(&p.From)
3185 r := p.Reg
3186 if r == 0 {
3187 r = p.To.Reg
3188 }
3189 switch p.As {
3190 case ASUB:
3191 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3192 zRRF(op_SLGRK, regtmp(p), 0, uint32(p.To.Reg), uint32(r), asm)
3193 case ASUBC:
3194 if r != p.To.Reg {
3195 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3196 }
3197 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm)
3198 case ASUBW:
3199 if r != p.To.Reg {
3200 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3201 }
3202 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm)
3203 }
3204
3205 case 22:
3206 v := c.vregoff(&p.From)
3207 r := p.Reg
3208 if r == 0 {
3209 r = p.To.Reg
3210 }
3211 var opri, opril, oprie uint32
3212 switch p.As {
3213 case AADD:
3214 opri = op_AGHI
3215 opril = op_AGFI
3216 oprie = op_AGHIK
3217 case AADDC:
3218 opril = op_ALGFI
3219 oprie = op_ALGHSIK
3220 case AADDW:
3221 opri = op_AHI
3222 opril = op_AFI
3223 oprie = op_AHIK
3224 case AMULLW:
3225 opri = op_MHI
3226 opril = op_MSFI
3227 case AMULLD:
3228 opri = op_MGHI
3229 opril = op_MSGFI
3230 }
3231 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) {
3232 switch p.As {
3233 case AADD, AADDC, AMULLD:
3234 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3235 case AADDW, AMULLW:
3236 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3237 }
3238 r = p.To.Reg
3239 }
3240 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v {
3241 zRI(opri, uint32(p.To.Reg), uint32(v), asm)
3242 } else if oprie != 0 && int64(int16(v)) == v {
3243 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
3244 } else {
3245 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm)
3246 }
3247
3248 case 23:
3249
3250 v := c.vregoff(&p.From)
3251 switch p.As {
3252 default:
3253 c.ctxt.Diag("%v is not supported", p)
3254 case AAND:
3255 if v >= 0 {
3256 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3257 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm)
3258 } else if int64(int16(v)) == v {
3259 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3260 } else {
3261 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3262 }
3263 case AOR:
3264 if int64(uint32(v)) != v {
3265 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3266 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm)
3267 } else if int64(uint16(v)) == v {
3268 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3269 } else {
3270 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3271 }
3272 case AXOR:
3273 if int64(uint32(v)) != v {
3274 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3275 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm)
3276 } else {
3277 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3278 }
3279 }
3280
3281 case 24:
3282 v := c.vregoff(&p.From)
3283 switch p.As {
3284 case AANDW:
3285 if uint32(v&0xffff0000) == 0xffff0000 {
3286 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3287 } else if uint32(v&0x0000ffff) == 0x0000ffff {
3288 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3289 } else {
3290 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3291 }
3292 case AORW:
3293 if uint32(v&0xffff0000) == 0 {
3294 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3295 } else if uint32(v&0x0000ffff) == 0 {
3296 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3297 } else {
3298 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3299 }
3300 case AXORW:
3301 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3302 }
3303
3304 case 25:
3305 m3 := uint32(c.branchMask(p))
3306 var opcode uint32
3307 switch p.As {
3308 case ALOCR:
3309 opcode = op_LOCR
3310 case ALOCGR:
3311 opcode = op_LOCGR
3312 }
3313 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3314
3315 case 26:
3316 v := c.regoff(&p.From)
3317 r := p.From.Reg
3318 if r == 0 {
3319 r = REGSP
3320 }
3321 i := p.From.Index
3322 if v >= 0 && v < DISP12 {
3323 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3324 } else if v >= -DISP20/2 && v < DISP20/2 {
3325 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3326 } else {
3327 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3328 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm)
3329 }
3330
3331 case 31:
3332 wd := uint64(c.vregoff(&p.From))
3333 *asm = append(*asm,
3334 uint8(wd>>56),
3335 uint8(wd>>48),
3336 uint8(wd>>40),
3337 uint8(wd>>32),
3338 uint8(wd>>24),
3339 uint8(wd>>16),
3340 uint8(wd>>8),
3341 uint8(wd))
3342
3343 case 32:
3344 var opcode uint32
3345 switch p.As {
3346 default:
3347 c.ctxt.Diag("invalid opcode")
3348 case AFADD:
3349 opcode = op_ADBR
3350 case AFADDS:
3351 opcode = op_AEBR
3352 case AFDIV:
3353 opcode = op_DDBR
3354 case AFDIVS:
3355 opcode = op_DEBR
3356 case AFMUL:
3357 opcode = op_MDBR
3358 case AFMULS:
3359 opcode = op_MEEBR
3360 case AFSUB:
3361 opcode = op_SDBR
3362 case AFSUBS:
3363 opcode = op_SEBR
3364 }
3365 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3366
3367 case 33:
3368 r := p.From.Reg
3369 if oclass(&p.From) == C_NONE {
3370 r = p.To.Reg
3371 }
3372 var opcode uint32
3373 switch p.As {
3374 default:
3375 case AFABS:
3376 opcode = op_LPDBR
3377 case AFNABS:
3378 opcode = op_LNDBR
3379 case ALPDFR:
3380 opcode = op_LPDFR
3381 case ALNDFR:
3382 opcode = op_LNDFR
3383 case AFNEG:
3384 opcode = op_LCDFR
3385 case AFNEGS:
3386 opcode = op_LCEBR
3387 case ALCDBR:
3388 opcode = op_LCDBR
3389 case ALEDBR:
3390 opcode = op_LEDBR
3391 case ALDEBR:
3392 opcode = op_LDEBR
3393 case AFSQRT:
3394 opcode = op_SQDBR
3395 case AFSQRTS:
3396 opcode = op_SQEBR
3397 }
3398 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3399
3400 case 34:
3401 var opcode uint32
3402 switch p.As {
3403 default:
3404 c.ctxt.Diag("invalid opcode")
3405 case AFMADD:
3406 opcode = op_MADBR
3407 case AFMADDS:
3408 opcode = op_MAEBR
3409 case AFMSUB:
3410 opcode = op_MSDBR
3411 case AFMSUBS:
3412 opcode = op_MSEBR
3413 }
3414 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
3415
3416 case 35:
3417 d2 := c.regoff(&p.To)
3418 b2 := p.To.Reg
3419 if b2 == 0 {
3420 b2 = REGSP
3421 }
3422 x2 := p.To.Index
3423 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3424 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3425 if x2 != 0 {
3426 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3427 }
3428 x2 = int16(regtmp(p))
3429 d2 = 0
3430 }
3431
3432 if op, ok := c.zopstore12(p.As); ok && isU12(d2) {
3433 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3434 } else {
3435 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3436 }
3437
3438 case 36:
3439 d2 := c.regoff(&p.From)
3440 b2 := p.From.Reg
3441 if b2 == 0 {
3442 b2 = REGSP
3443 }
3444 x2 := p.From.Index
3445 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3446 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3447 if x2 != 0 {
3448 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3449 }
3450 x2 = int16(regtmp(p))
3451 d2 = 0
3452 }
3453
3454 if op, ok := c.zopload12(p.As); ok && isU12(d2) {
3455 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3456 } else {
3457 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3458 }
3459
3460 case 40:
3461 wd := uint32(c.regoff(&p.From))
3462 if p.As == AWORD {
3463 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd))
3464 } else {
3465 *asm = append(*asm, uint8(wd))
3466 }
3467
3468 case 41:
3469 r1 := p.From.Reg
3470 ri2 := (p.To.Target().Pc - p.Pc) >> 1
3471 if int64(int16(ri2)) != ri2 {
3472 c.ctxt.Diag("branch target too far away")
3473 }
3474 var opcode uint32
3475 switch p.As {
3476 case ABRCT:
3477 opcode = op_BRCT
3478 case ABRCTG:
3479 opcode = op_BRCTG
3480 }
3481 zRI(opcode, uint32(r1), uint32(ri2), asm)
3482
3483 case 47:
3484 r := p.From.Reg
3485 if r == 0 {
3486 r = p.To.Reg
3487 }
3488 switch p.As {
3489 case ANEG:
3490 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
3491 case ANEGW:
3492 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
3493 }
3494
3495 case 48:
3496 m3 := c.vregoff(&p.From)
3497 if 0 > m3 || m3 > 7 {
3498 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3)
3499 }
3500 var opcode uint32
3501 switch p.As {
3502 case AFIEBR:
3503 opcode = op_FIEBR
3504 case AFIDBR:
3505 opcode = op_FIDBR
3506 }
3507 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3508
3509 case 49:
3510 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3511
3512 case 50:
3513 var opcode uint32
3514 switch p.As {
3515 case ALTEBR:
3516 opcode = op_LTEBR
3517 case ALTDBR:
3518 opcode = op_LTDBR
3519 }
3520 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3521
3522 case 51:
3523 var opcode uint32
3524 switch p.As {
3525 case ATCEB:
3526 opcode = op_TCEB
3527 case ATCDB:
3528 opcode = op_TCDB
3529 }
3530 d2 := c.regoff(&p.To)
3531 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm)
3532
3533 case 62:
3534 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3535
3536 case 66:
3537 zRR(op_BCR, uint32(Never), 0, asm)
3538
3539 case 67:
3540 var opcode uint32
3541 switch p.As {
3542 case AFMOVS:
3543 opcode = op_LZER
3544 case AFMOVD:
3545 opcode = op_LZDR
3546 }
3547 zRRE(opcode, uint32(p.To.Reg), 0, asm)
3548
3549 case 68:
3550 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm)
3551
3552 case 69:
3553 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm)
3554
3555 case 70:
3556 if p.As == ACMPW || p.As == ACMPWU {
3557 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3558 } else {
3559 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3560 }
3561
3562 case 71:
3563 v := c.vregoff(&p.To)
3564 switch p.As {
3565 case ACMP, ACMPW:
3566 if int64(int32(v)) != v {
3567 c.ctxt.Diag("%v overflows an int32", v)
3568 }
3569 case ACMPU, ACMPWU:
3570 if int64(uint32(v)) != v {
3571 c.ctxt.Diag("%v overflows a uint32", v)
3572 }
3573 }
3574 if p.As == ACMP && int64(int16(v)) == v {
3575 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm)
3576 } else if p.As == ACMPW && int64(int16(v)) == v {
3577 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm)
3578 } else {
3579 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm)
3580 }
3581
3582 case 72:
3583 v := c.regoff(&p.From)
3584 d := c.regoff(&p.To)
3585 r := p.To.Reg
3586 if p.To.Index != 0 {
3587 c.ctxt.Diag("cannot use index register")
3588 }
3589 if r == 0 {
3590 r = REGSP
3591 }
3592 var opcode uint32
3593 switch p.As {
3594 case AMOVD:
3595 opcode = op_MVGHI
3596 case AMOVW, AMOVWZ:
3597 opcode = op_MVHI
3598 case AMOVH, AMOVHZ:
3599 opcode = op_MVHHI
3600 case AMOVB, AMOVBZ:
3601 opcode = op_MVI
3602 }
3603 if d < 0 || d >= DISP12 {
3604 if r == int16(regtmp(p)) {
3605 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r)
3606 }
3607 if d >= -DISP20/2 && d < DISP20/2 {
3608 if opcode == op_MVI {
3609 opcode = op_MVIY
3610 } else {
3611 zRXY(op_LAY, regtmp(p), 0, uint32(r), uint32(d), asm)
3612 r = int16(regtmp(p))
3613 d = 0
3614 }
3615 } else {
3616 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm)
3617 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm)
3618 r = int16(regtmp(p))
3619 d = 0
3620 }
3621 }
3622 switch opcode {
3623 case op_MVI:
3624 zSI(opcode, uint32(v), uint32(r), uint32(d), asm)
3625 case op_MVIY:
3626 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm)
3627 default:
3628 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm)
3629 }
3630
3631 case 73:
3632 zE(op_BRRK, asm)
3633
3634 case 74:
3635 i2 := c.regoff(&p.To)
3636 switch p.As {
3637 case AMOVD:
3638 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm)
3639 case AMOVW, AMOVWZ:
3640 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm)
3641 case AMOVH, AMOVHZ:
3642 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm)
3643 case AMOVB, AMOVBZ:
3644 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3645 adj := uint32(0)
3646 if i2&1 != 0 {
3647 i2 -= 1
3648 adj = 1
3649 }
3650 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm)
3651 case AFMOVD:
3652 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3653 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3654 case AFMOVS:
3655 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3656 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3657 }
3658 c.addrilreloc(p.To.Sym, int64(i2))
3659
3660 case 75:
3661 i2 := c.regoff(&p.From)
3662 switch p.As {
3663 case AMOVD:
3664 if i2&1 != 0 {
3665 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3666 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm)
3667 i2 -= 1
3668 } else {
3669 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3670 }
3671 case AMOVW:
3672 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm)
3673 case AMOVWZ:
3674 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm)
3675 case AMOVH:
3676 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm)
3677 case AMOVHZ:
3678 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm)
3679 case AMOVB, AMOVBZ:
3680 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3681 adj := uint32(0)
3682 if i2&1 != 0 {
3683 i2 -= 1
3684 adj = 1
3685 }
3686 switch p.As {
3687 case AMOVB:
3688 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3689 case AMOVBZ:
3690 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3691 }
3692 case AFMOVD:
3693 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3694 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3695 case AFMOVS:
3696 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3697 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3698 }
3699 c.addrilreloc(p.From.Sym, int64(i2))
3700
3701 case 76:
3702 zRR(op_SPM, uint32(p.From.Reg), 0, asm)
3703
3704 case 77:
3705 if p.From.Offset > 255 || p.From.Offset < 1 {
3706 c.ctxt.Diag("illegal system call; system call number out of range: %v", p)
3707 zE(op_TRAP2, asm)
3708 } else {
3709 zI(op_SVC, uint32(p.From.Offset), asm)
3710 }
3711
3712 case 78:
3713
3714
3715 *asm = append(*asm, 0, 0, 0, 0)
3716
3717 case 79:
3718 v := c.regoff(&p.To)
3719 if v < 0 {
3720 v = 0
3721 }
3722 if p.As == ACS {
3723 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3724 } else if p.As == ACSG {
3725 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3726 }
3727
3728 case 80:
3729 zRR(op_BCR, 14, 0, asm)
3730
3731 case 81:
3732 switch p.As {
3733 case ALDGR:
3734 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3735 case ALGDR:
3736 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3737 }
3738
3739 case 82:
3740 var opcode uint32
3741 switch p.As {
3742 default:
3743 log.Fatalf("unexpected opcode %v", p.As)
3744 case ACEFBRA:
3745 opcode = op_CEFBRA
3746 case ACDFBRA:
3747 opcode = op_CDFBRA
3748 case ACEGBRA:
3749 opcode = op_CEGBRA
3750 case ACDGBRA:
3751 opcode = op_CDGBRA
3752 case ACELFBR:
3753 opcode = op_CELFBR
3754 case ACDLFBR:
3755 opcode = op_CDLFBR
3756 case ACELGBR:
3757 opcode = op_CELGBR
3758 case ACDLGBR:
3759 opcode = op_CDLGBR
3760 }
3761
3762
3763
3764
3765 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3766
3767 case 83:
3768 var opcode uint32
3769 switch p.As {
3770 default:
3771 log.Fatalf("unexpected opcode %v", p.As)
3772 case ACFEBRA:
3773 opcode = op_CFEBRA
3774 case ACFDBRA:
3775 opcode = op_CFDBRA
3776 case ACGEBRA:
3777 opcode = op_CGEBRA
3778 case ACGDBRA:
3779 opcode = op_CGDBRA
3780 case ACLFEBR:
3781 opcode = op_CLFEBR
3782 case ACLFDBR:
3783 opcode = op_CLFDBR
3784 case ACLGEBR:
3785 opcode = op_CLGEBR
3786 case ACLGDBR:
3787 opcode = op_CLGDBR
3788 }
3789
3790
3791 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3792
3793 case 84:
3794 l := c.regoff(&p.From)
3795 if l < 1 || l > 256 {
3796 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l)
3797 }
3798 if p.GetFrom3().Index != 0 || p.To.Index != 0 {
3799 c.ctxt.Diag("cannot use index reg")
3800 }
3801 b1 := p.To.Reg
3802 b2 := p.GetFrom3().Reg
3803 if b1 == 0 {
3804 b1 = REGSP
3805 }
3806 if b2 == 0 {
3807 b2 = REGSP
3808 }
3809 d1 := c.regoff(&p.To)
3810 d2 := c.regoff(p.GetFrom3())
3811 if d1 < 0 || d1 >= DISP12 {
3812 if b2 == int16(regtmp(p)) {
3813 c.ctxt.Diag("regtmp(p) conflict")
3814 }
3815 if b1 != int16(regtmp(p)) {
3816 zRRE(op_LGR, regtmp(p), uint32(b1), asm)
3817 }
3818 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm)
3819 if d1 == d2 && b1 == b2 {
3820 d2 = 0
3821 b2 = int16(regtmp(p))
3822 }
3823 d1 = 0
3824 b1 = int16(regtmp(p))
3825 }
3826 if d2 < 0 || d2 >= DISP12 {
3827 if b1 == REGTMP2 {
3828 c.ctxt.Diag("REGTMP2 conflict")
3829 }
3830 if b2 != REGTMP2 {
3831 zRRE(op_LGR, REGTMP2, uint32(b2), asm)
3832 }
3833 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm)
3834 d2 = 0
3835 b2 = REGTMP2
3836 }
3837 var opcode uint32
3838 switch p.As {
3839 default:
3840 c.ctxt.Diag("unexpected opcode %v", p.As)
3841 case AMVC:
3842 opcode = op_MVC
3843 case AMVCIN:
3844 opcode = op_MVCIN
3845 case ACLC:
3846 opcode = op_CLC
3847
3848 b1, b2 = b2, b1
3849 d1, d2 = d2, d1
3850 case AXC:
3851 opcode = op_XC
3852 case AOC:
3853 opcode = op_OC
3854 case ANC:
3855 opcode = op_NC
3856 }
3857 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm)
3858
3859 case 85:
3860 v := c.regoff(&p.From)
3861 if p.From.Sym == nil {
3862 if (v & 1) != 0 {
3863 c.ctxt.Diag("cannot use LARL with odd offset: %v", v)
3864 }
3865 } else {
3866 c.addrilreloc(p.From.Sym, int64(v))
3867 v = 0
3868 }
3869 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm)
3870
3871 case 86:
3872 d := c.vregoff(&p.From)
3873 x := p.From.Index
3874 b := p.From.Reg
3875 if b == 0 {
3876 b = REGSP
3877 }
3878 switch p.As {
3879 case ALA:
3880 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3881 case ALAY:
3882 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3883 }
3884
3885 case 87:
3886 v := c.vregoff(&p.From)
3887 if p.From.Sym == nil {
3888 if v&1 != 0 {
3889 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v)
3890 }
3891 } else {
3892 c.addrilreloc(p.From.Sym, v)
3893 v = 0
3894 }
3895 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm)
3896
3897 case 88:
3898 var opcode uint32
3899 switch p.As {
3900 case ASTCK:
3901 opcode = op_STCK
3902 case ASTCKC:
3903 opcode = op_STCKC
3904 case ASTCKE:
3905 opcode = op_STCKE
3906 case ASTCKF:
3907 opcode = op_STCKF
3908 }
3909 v := c.vregoff(&p.To)
3910 r := p.To.Reg
3911 if r == 0 {
3912 r = REGSP
3913 }
3914 zS(opcode, uint32(r), uint32(v), asm)
3915
3916 case 89:
3917 var v int32
3918 if p.To.Target() != nil {
3919 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3920 }
3921
3922
3923 r1, r2 := p.From.Reg, p.Reg
3924 if p.From.Type == obj.TYPE_CONST {
3925 r1, r2 = p.Reg, p.RestArgs[0].Reg
3926 }
3927 m3 := uint32(c.branchMask(p))
3928
3929 var opcode uint32
3930 switch p.As {
3931 case ACRJ:
3932
3933 opcode = op_CRJ
3934 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3935
3936 opcode = op_CGRJ
3937 case ACLRJ:
3938
3939 opcode = op_CLRJ
3940 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3941
3942 opcode = op_CLGRJ
3943 }
3944
3945 if int32(int16(v)) != v {
3946
3947
3948
3949
3950
3951
3952
3953
3954 m3 ^= 0xe
3955 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm)
3956 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3957 } else {
3958 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm)
3959 }
3960
3961 case 90:
3962 var v int32
3963 if p.To.Target() != nil {
3964 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3965 }
3966
3967
3968 r1, i2 := p.From.Reg, p.RestArgs[0].Offset
3969 if p.From.Type == obj.TYPE_CONST {
3970 r1 = p.Reg
3971 }
3972 m3 := uint32(c.branchMask(p))
3973
3974 var opcode uint32
3975 switch p.As {
3976 case ACIJ:
3977 opcode = op_CIJ
3978 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3979 opcode = op_CGIJ
3980 case ACLIJ:
3981 opcode = op_CLIJ
3982 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3983 opcode = op_CLGIJ
3984 }
3985 if int32(int16(v)) != v {
3986
3987
3988
3989
3990
3991
3992
3993
3994 m3 ^= 0xe
3995 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm)
3996 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3997 } else {
3998 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm)
3999 }
4000
4001 case 91:
4002 var opcode uint32
4003 switch p.As {
4004 case ATMHH:
4005 opcode = op_TMHH
4006 case ATMHL:
4007 opcode = op_TMHL
4008 case ATMLH:
4009 opcode = op_TMLH
4010 case ATMLL:
4011 opcode = op_TMLL
4012 }
4013 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
4014
4015 case 92:
4016 zRRE(op_IPM, uint32(p.From.Reg), 0, asm)
4017
4018 case 93:
4019 v := c.vregoff(&p.To)
4020 if v != 0 {
4021 c.ctxt.Diag("invalid offset against GOT slot %v", p)
4022 }
4023 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
4024 c.cursym.AddRel(c.ctxt, obj.Reloc{
4025 Type: objabi.R_GOTPCREL,
4026 Off: int32(c.pc + 2),
4027 Siz: 4,
4028 Sym: p.From.Sym,
4029 Add: 2 + 4,
4030 })
4031
4032 case 94:
4033 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm)
4034 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4035 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm)
4036 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0)
4037 c.cursym.AddRel(c.ctxt, obj.Reloc{
4038 Type: objabi.R_TLS_LE,
4039 Off: int32(c.pc + sizeRIL + sizeRXY + sizeRI),
4040 Siz: 8,
4041 Sym: p.From.Sym,
4042 })
4043
4044 case 95:
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056 zRIL(_b, op_LARL, regtmp(p), 0, asm)
4057 c.cursym.AddRel(c.ctxt, obj.Reloc{
4058 Type: objabi.R_TLS_IE,
4059 Off: int32(c.pc + 2),
4060 Siz: 4,
4061 Sym: p.From.Sym,
4062 Add: 2 + 4,
4063 })
4064
4065
4066 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4067
4068
4069
4070 case 96:
4071 length := c.vregoff(&p.From)
4072 offset := c.vregoff(&p.To)
4073 reg := p.To.Reg
4074 if reg == 0 {
4075 reg = REGSP
4076 }
4077 if length <= 0 {
4078 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length)
4079 }
4080 for length > 0 {
4081 if offset < 0 || offset >= DISP12 {
4082 if offset >= -DISP20/2 && offset < DISP20/2 {
4083 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm)
4084 } else {
4085 if reg != int16(regtmp(p)) {
4086 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4087 }
4088 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4089 }
4090 reg = int16(regtmp(p))
4091 offset = 0
4092 }
4093 size := length
4094 if size > 256 {
4095 size = 256
4096 }
4097
4098 switch size {
4099 case 1:
4100 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm)
4101 case 2:
4102 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm)
4103 case 4:
4104 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm)
4105 case 8:
4106 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm)
4107 default:
4108 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm)
4109 }
4110
4111 length -= size
4112 offset += size
4113 }
4114
4115 case 97:
4116 rstart := p.From.Reg
4117 rend := p.Reg
4118 offset := c.regoff(&p.To)
4119 reg := p.To.Reg
4120 if reg == 0 {
4121 reg = REGSP
4122 }
4123 if offset < -DISP20/2 || offset >= DISP20/2 {
4124 if reg != int16(regtmp(p)) {
4125 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4126 }
4127 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4128 reg = int16(regtmp(p))
4129 offset = 0
4130 }
4131 switch p.As {
4132 case ASTMY:
4133 if offset >= 0 && offset < DISP12 {
4134 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4135 } else {
4136 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4137 }
4138 case ASTMG:
4139 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4140 }
4141
4142 case 98:
4143 rstart := p.Reg
4144 rend := p.To.Reg
4145 offset := c.regoff(&p.From)
4146 reg := p.From.Reg
4147 if reg == 0 {
4148 reg = REGSP
4149 }
4150 if offset < -DISP20/2 || offset >= DISP20/2 {
4151 if reg != int16(regtmp(p)) {
4152 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4153 }
4154 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4155 reg = int16(regtmp(p))
4156 offset = 0
4157 }
4158 switch p.As {
4159 case ALMY:
4160 if offset >= 0 && offset < DISP12 {
4161 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4162 } else {
4163 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4164 }
4165 case ALMG:
4166 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4167 }
4168
4169 case 99:
4170 if p.To.Index != 0 {
4171 c.ctxt.Diag("cannot use indexed address")
4172 }
4173 offset := c.regoff(&p.To)
4174 if offset < -DISP20/2 || offset >= DISP20/2 {
4175 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset)
4176 }
4177 var opcode uint32
4178 switch p.As {
4179 case ALAA:
4180 opcode = op_LAA
4181 case ALAAG:
4182 opcode = op_LAAG
4183 case ALAAL:
4184 opcode = op_LAAL
4185 case ALAALG:
4186 opcode = op_LAALG
4187 case ALAN:
4188 opcode = op_LAN
4189 case ALANG:
4190 opcode = op_LANG
4191 case ALAX:
4192 opcode = op_LAX
4193 case ALAXG:
4194 opcode = op_LAXG
4195 case ALAO:
4196 opcode = op_LAO
4197 case ALAOG:
4198 opcode = op_LAOG
4199 }
4200 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm)
4201
4202 case 100:
4203 op, m3, _ := vop(p.As)
4204 v1 := p.From.Reg
4205 if p.Reg != 0 {
4206 m3 = uint32(c.vregoff(&p.From))
4207 v1 = p.Reg
4208 }
4209 b2 := p.To.Reg
4210 if b2 == 0 {
4211 b2 = REGSP
4212 }
4213 d2 := uint32(c.vregoff(&p.To))
4214 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4215
4216 case 101:
4217 op, m3, _ := vop(p.As)
4218 src := &p.From
4219 if p.GetFrom3() != nil {
4220 m3 = uint32(c.vregoff(&p.From))
4221 src = p.GetFrom3()
4222 }
4223 b2 := src.Reg
4224 if b2 == 0 {
4225 b2 = REGSP
4226 }
4227 d2 := uint32(c.vregoff(src))
4228 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm)
4229
4230 case 102:
4231 op, _, _ := vop(p.As)
4232 m3 := uint32(c.vregoff(&p.From))
4233 b2 := p.To.Reg
4234 if b2 == 0 {
4235 b2 = REGSP
4236 }
4237 d2 := uint32(c.vregoff(&p.To))
4238 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4239
4240 case 103:
4241 op, _, _ := vop(p.As)
4242 m3 := uint32(c.vregoff(&p.From))
4243 b2 := p.GetFrom3().Reg
4244 if b2 == 0 {
4245 b2 = REGSP
4246 }
4247 d2 := uint32(c.vregoff(p.GetFrom3()))
4248 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm)
4249
4250 case 104:
4251 op, m4, _ := vop(p.As)
4252 fr := p.Reg
4253 if fr == 0 {
4254 fr = p.To.Reg
4255 }
4256 bits := uint32(c.vregoff(&p.From))
4257 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm)
4258
4259 case 105:
4260 op, _, _ := vop(p.As)
4261 offset := uint32(c.vregoff(&p.To))
4262 reg := p.To.Reg
4263 if reg == 0 {
4264 reg = REGSP
4265 }
4266 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm)
4267
4268 case 106:
4269 op, _, _ := vop(p.As)
4270 offset := uint32(c.vregoff(&p.From))
4271 reg := p.From.Reg
4272 if reg == 0 {
4273 reg = REGSP
4274 }
4275 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm)
4276
4277 case 107:
4278 op, _, _ := vop(p.As)
4279 offset := uint32(c.vregoff(&p.To))
4280 reg := p.To.Reg
4281 if reg == 0 {
4282 reg = REGSP
4283 }
4284 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4285
4286 case 108:
4287 op, _, _ := vop(p.As)
4288 offset := uint32(c.vregoff(p.GetFrom3()))
4289 reg := p.GetFrom3().Reg
4290 if reg == 0 {
4291 reg = REGSP
4292 }
4293 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4294
4295 case 109:
4296 op, m3, _ := vop(p.As)
4297 i2 := uint32(c.vregoff(&p.From))
4298 if p.GetFrom3() != nil {
4299 m3 = uint32(c.vregoff(&p.From))
4300 i2 = uint32(c.vregoff(p.GetFrom3()))
4301 }
4302 switch p.As {
4303 case AVZERO:
4304 i2 = 0
4305 case AVONE:
4306 i2 = 0xffff
4307 }
4308 zVRIa(op, uint32(p.To.Reg), i2, m3, asm)
4309
4310 case 110:
4311 op, m4, _ := vop(p.As)
4312 i2 := uint32(c.vregoff(&p.From))
4313 i3 := uint32(c.vregoff(p.GetFrom3()))
4314 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm)
4315
4316 case 111:
4317 op, m4, _ := vop(p.As)
4318 i2 := uint32(c.vregoff(&p.From))
4319 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm)
4320
4321 case 112:
4322 op, m5, _ := vop(p.As)
4323 i4 := uint32(c.vregoff(&p.From))
4324 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm)
4325
4326 case 113:
4327 op, m4, _ := vop(p.As)
4328 m5 := singleElementMask(p.As)
4329 i3 := uint32(c.vregoff(&p.From))
4330 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm)
4331
4332 case 114:
4333 op, m3, m5 := vop(p.As)
4334 m4 := singleElementMask(p.As)
4335 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm)
4336
4337 case 115:
4338 op, m3, m5 := vop(p.As)
4339 m4 := singleElementMask(p.As)
4340 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm)
4341
4342 case 117:
4343 op, m4, m5 := vop(p.As)
4344 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm)
4345
4346 case 118:
4347 op, m4, m6 := vop(p.As)
4348 m5 := singleElementMask(p.As)
4349 v3 := p.Reg
4350 if v3 == 0 {
4351 v3 = p.To.Reg
4352 }
4353 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm)
4354
4355 case 119:
4356 op, m4, m6 := vop(p.As)
4357 m5 := singleElementMask(p.As)
4358 v2 := p.Reg
4359 if v2 == 0 {
4360 v2 = p.To.Reg
4361 }
4362 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
4363
4364 case 120:
4365 op, m6, m5 := vop(p.As)
4366 v1 := uint32(p.To.Reg)
4367 v2 := uint32(p.From.Reg)
4368 v3 := uint32(p.Reg)
4369 v4 := uint32(p.GetFrom3().Reg)
4370 zVRRd(op, v1, v2, v3, m6, m5, v4, asm)
4371
4372 case 121:
4373 op, m6, _ := vop(p.As)
4374 m5 := singleElementMask(p.As)
4375 v1 := uint32(p.To.Reg)
4376 v2 := uint32(p.From.Reg)
4377 v3 := uint32(p.Reg)
4378 v4 := uint32(p.GetFrom3().Reg)
4379 zVRRe(op, v1, v2, v3, m6, m5, v4, asm)
4380
4381 case 122:
4382 op, _, _ := vop(p.As)
4383 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
4384
4385 case 123:
4386 op, _, _ := vop(p.As)
4387 m4 := c.regoff(&p.From)
4388 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm)
4389
4390 case 124:
4391 var opcode uint32
4392 switch p.As {
4393 default:
4394 c.ctxt.Diag("unexpected opcode %v", p.As)
4395 case AKM, AKMC, AKLMD:
4396 if p.From.Reg == REG_R0 {
4397 c.ctxt.Diag("input must not be R0 in %v", p)
4398 }
4399 if p.From.Reg&1 != 0 {
4400 c.ctxt.Diag("input must be even register in %v", p)
4401 }
4402 if p.To.Reg == REG_R0 {
4403 c.ctxt.Diag("second argument must not be R0 in %v", p)
4404 }
4405 if p.To.Reg&1 != 0 {
4406 c.ctxt.Diag("second argument must be even register in %v", p)
4407 }
4408 if p.As == AKM {
4409 opcode = op_KM
4410 } else if p.As == AKMC {
4411 opcode = op_KMC
4412 } else {
4413 opcode = op_KLMD
4414 }
4415 case AKIMD:
4416 if p.To.Reg == REG_R0 {
4417 c.ctxt.Diag("second argument must not be R0 in %v", p)
4418 }
4419 if p.To.Reg&1 != 0 {
4420 c.ctxt.Diag("second argument must be even register in %v", p)
4421 }
4422 opcode = op_KIMD
4423 }
4424 zRRE(opcode, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4425
4426 case 125:
4427 if p.To.Reg == REG_R0 {
4428 c.ctxt.Diag("second argument must not be R0 in %v", p)
4429 }
4430 if p.To.Reg&1 != 0 {
4431 c.ctxt.Diag("second argument must be an even register in %v", p)
4432 }
4433 zRRE(op_KDSA, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4434
4435 case 126:
4436 var opcode uint32
4437 switch p.As {
4438 default:
4439 c.ctxt.Diag("unexpected opcode %v", p.As)
4440 case AKMA, AKMCTR:
4441 if p.From.Reg == REG_R0 {
4442 c.ctxt.Diag("input argument must not be R0 in %v", p)
4443 }
4444 if p.From.Reg&1 != 0 {
4445 c.ctxt.Diag("input argument must be even register in %v", p)
4446 }
4447 if p.To.Reg == REG_R0 {
4448 c.ctxt.Diag("output argument must not be R0 in %v", p)
4449 }
4450 if p.To.Reg&1 != 0 {
4451 c.ctxt.Diag("output argument must be an even register in %v", p)
4452 }
4453 if p.Reg == REG_R0 {
4454 c.ctxt.Diag("third argument must not be R0 in %v", p)
4455 }
4456 if p.Reg&1 != 0 {
4457 c.ctxt.Diag("third argument must be even register in %v", p)
4458 }
4459 if p.As == AKMA {
4460 opcode = op_KMA
4461 } else if p.As == AKMCTR {
4462 opcode = op_KMCTR
4463 }
4464 }
4465 zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4466
4467 case 127:
4468
4469
4470
4471
4472
4473 d2 := c.regoff(&p.From)
4474 if p.To.Reg&1 != 0 {
4475 c.ctxt.Diag("output argument must be even register in %v", p)
4476 }
4477 if p.Reg&1 != 0 {
4478 c.ctxt.Diag("input argument must be an even register in %v", p)
4479 }
4480 if (p.From.Reg == p.To.Reg) || (p.From.Reg == p.Reg) {
4481 c.ctxt.Diag("padding byte register cannot be same as input or output register %v", p)
4482 }
4483 zRS(op_MVCLE, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), uint32(d2), asm)
4484
4485 case 128:
4486 op, m4, _ := vop(p.As)
4487 m5 := singleElementMask(p.As)
4488 m6 := uint32(c.vregoff(&p.From))
4489 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), m6, m5, m4, asm)
4490
4491 case 129:
4492 op, _, _ := vop(p.As)
4493 v1 := p.From.Reg
4494 b2 := p.To.Reg
4495 if b2 == 0 {
4496 b2 = REGSP
4497 }
4498 d2 := uint32(c.vregoff(&p.To))
4499 i3 := uint32(c.vregoff(p.GetFrom3()))
4500 zVSI(op, uint32(v1), uint32(b2), d2, i3, asm)
4501 }
4502 }
4503
4504 func (c *ctxtz) vregoff(a *obj.Addr) int64 {
4505 c.instoffset = 0
4506 if a != nil {
4507 c.aclass(a)
4508 }
4509 return c.instoffset
4510 }
4511
4512 func (c *ctxtz) regoff(a *obj.Addr) int32 {
4513 return int32(c.vregoff(a))
4514 }
4515
4516
4517 func isU12(displacement int32) bool {
4518 return displacement >= 0 && displacement < DISP12
4519 }
4520
4521
4522 func (c *ctxtz) zopload12(a obj.As) (uint32, bool) {
4523 switch a {
4524 case AFMOVD:
4525 return op_LD, true
4526 case AFMOVS:
4527 return op_LE, true
4528 }
4529 return 0, false
4530 }
4531
4532
4533 func (c *ctxtz) zopload(a obj.As) uint32 {
4534 switch a {
4535
4536 case AMOVD:
4537 return op_LG
4538 case AMOVW:
4539 return op_LGF
4540 case AMOVWZ:
4541 return op_LLGF
4542 case AMOVH:
4543 return op_LGH
4544 case AMOVHZ:
4545 return op_LLGH
4546 case AMOVB:
4547 return op_LGB
4548 case AMOVBZ:
4549 return op_LLGC
4550
4551
4552 case AFMOVD:
4553 return op_LDY
4554 case AFMOVS:
4555 return op_LEY
4556
4557
4558 case AMOVDBR:
4559 return op_LRVG
4560 case AMOVWBR:
4561 return op_LRV
4562 case AMOVHBR:
4563 return op_LRVH
4564 }
4565
4566 c.ctxt.Diag("unknown zopload opcode %v", a)
4567 return 0
4568 }
4569
4570
4571 func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) {
4572 switch a {
4573 case AFMOVD:
4574 return op_STD, true
4575 case AFMOVS:
4576 return op_STE, true
4577 case AMOVW, AMOVWZ:
4578 return op_ST, true
4579 case AMOVH, AMOVHZ:
4580 return op_STH, true
4581 case AMOVB, AMOVBZ:
4582 return op_STC, true
4583 }
4584 return 0, false
4585 }
4586
4587
4588 func (c *ctxtz) zopstore(a obj.As) uint32 {
4589 switch a {
4590
4591 case AMOVD:
4592 return op_STG
4593 case AMOVW, AMOVWZ:
4594 return op_STY
4595 case AMOVH, AMOVHZ:
4596 return op_STHY
4597 case AMOVB, AMOVBZ:
4598 return op_STCY
4599
4600
4601 case AFMOVD:
4602 return op_STDY
4603 case AFMOVS:
4604 return op_STEY
4605
4606
4607 case AMOVDBR:
4608 return op_STRVG
4609 case AMOVWBR:
4610 return op_STRV
4611 case AMOVHBR:
4612 return op_STRVH
4613 }
4614
4615 c.ctxt.Diag("unknown store opcode %v", a)
4616 return 0
4617 }
4618
4619
4620 func (c *ctxtz) zoprre(a obj.As) uint32 {
4621 switch a {
4622 case ACMP:
4623 return op_CGR
4624 case ACMPU:
4625 return op_CLGR
4626 case AFCMPO:
4627 return op_KDBR
4628 case AFCMPU:
4629 return op_CDBR
4630 case ACEBR:
4631 return op_CEBR
4632 }
4633 c.ctxt.Diag("unknown rre opcode %v", a)
4634 return 0
4635 }
4636
4637
4638 func (c *ctxtz) zoprr(a obj.As) uint32 {
4639 switch a {
4640 case ACMPW:
4641 return op_CR
4642 case ACMPWU:
4643 return op_CLR
4644 }
4645 c.ctxt.Diag("unknown rr opcode %v", a)
4646 return 0
4647 }
4648
4649
4650 func (c *ctxtz) zopril(a obj.As) uint32 {
4651 switch a {
4652 case ACMP:
4653 return op_CGFI
4654 case ACMPU:
4655 return op_CLGFI
4656 case ACMPW:
4657 return op_CFI
4658 case ACMPWU:
4659 return op_CLFI
4660 }
4661 c.ctxt.Diag("unknown ril opcode %v", a)
4662 return 0
4663 }
4664
4665
4666 const (
4667 sizeE = 2
4668 sizeI = 2
4669 sizeIE = 4
4670 sizeMII = 6
4671 sizeRI = 4
4672 sizeRI1 = 4
4673 sizeRI2 = 4
4674 sizeRI3 = 4
4675 sizeRIE = 6
4676 sizeRIE1 = 6
4677 sizeRIE2 = 6
4678 sizeRIE3 = 6
4679 sizeRIE4 = 6
4680 sizeRIE5 = 6
4681 sizeRIE6 = 6
4682 sizeRIL = 6
4683 sizeRIL1 = 6
4684 sizeRIL2 = 6
4685 sizeRIL3 = 6
4686 sizeRIS = 6
4687 sizeRR = 2
4688 sizeRRD = 4
4689 sizeRRE = 4
4690 sizeRRF = 4
4691 sizeRRF1 = 4
4692 sizeRRF2 = 4
4693 sizeRRF3 = 4
4694 sizeRRF4 = 4
4695 sizeRRF5 = 4
4696 sizeRRR = 2
4697 sizeRRS = 6
4698 sizeRS = 4
4699 sizeRS1 = 4
4700 sizeRS2 = 4
4701 sizeRSI = 4
4702 sizeRSL = 6
4703 sizeRSY = 6
4704 sizeRSY1 = 6
4705 sizeRSY2 = 6
4706 sizeRX = 4
4707 sizeRX1 = 4
4708 sizeRX2 = 4
4709 sizeRXE = 6
4710 sizeRXF = 6
4711 sizeRXY = 6
4712 sizeRXY1 = 6
4713 sizeRXY2 = 6
4714 sizeS = 4
4715 sizeSI = 4
4716 sizeSIL = 6
4717 sizeSIY = 6
4718 sizeSMI = 6
4719 sizeSS = 6
4720 sizeSS1 = 6
4721 sizeSS2 = 6
4722 sizeSS3 = 6
4723 sizeSS4 = 6
4724 sizeSS5 = 6
4725 sizeSS6 = 6
4726 sizeSSE = 6
4727 sizeSSF = 6
4728 )
4729
4730
4731 type form int
4732
4733 const (
4734 _a form = iota
4735 _b
4736 _c
4737 _d
4738 _e
4739 _f
4740 )
4741
4742 func zE(op uint32, asm *[]byte) {
4743 *asm = append(*asm, uint8(op>>8), uint8(op))
4744 }
4745
4746 func zI(op, i1 uint32, asm *[]byte) {
4747 *asm = append(*asm, uint8(op>>8), uint8(i1))
4748 }
4749
4750 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4751 *asm = append(*asm,
4752 uint8(op>>8),
4753 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4754 uint8(i2_ri2>>8),
4755 uint8(i2_ri2))
4756 }
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) {
4770 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F))
4771
4772 switch f {
4773 default:
4774 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2))
4775 case _f:
4776 *asm = append(*asm, uint8(i3), uint8(i4))
4777 }
4778
4779 switch f {
4780 case _a, _b:
4781 *asm = append(*asm, uint8(m3)<<4)
4782 default:
4783 *asm = append(*asm, uint8(i2_i5))
4784 }
4785
4786 *asm = append(*asm, uint8(op))
4787 }
4788
4789 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4790 if f == _a || f == _b {
4791 r1_m1 = r1_m1 - obj.RBaseS390X
4792 }
4793 *asm = append(*asm,
4794 uint8(op>>8),
4795 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4796 uint8(i2_ri2>>24),
4797 uint8(i2_ri2>>16),
4798 uint8(i2_ri2>>8),
4799 uint8(i2_ri2))
4800 }
4801
4802 func zRR(op, r1, r2 uint32, asm *[]byte) {
4803 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F))
4804 }
4805
4806 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) {
4807 *asm = append(*asm,
4808 uint8(op>>8),
4809 uint8(op),
4810 uint8(r1)<<4,
4811 (uint8(r3)<<4)|uint8(r2&0x0F))
4812 }
4813
4814 func zRRE(op, r1, r2 uint32, asm *[]byte) {
4815 *asm = append(*asm,
4816 uint8(op>>8),
4817 uint8(op),
4818 0,
4819 (uint8(r1)<<4)|uint8(r2&0x0F))
4820 }
4821
4822 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) {
4823 *asm = append(*asm,
4824 uint8(op>>8),
4825 uint8(op),
4826 (uint8(r3_m3)<<4)|uint8(m4&0x0F),
4827 (uint8(r1)<<4)|uint8(r2&0x0F))
4828 }
4829
4830 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4831 *asm = append(*asm,
4832 uint8(op>>8),
4833 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4834 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4835 uint8(d2))
4836 }
4837
4838 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4839 dl2 := uint16(d2) & 0x0FFF
4840 *asm = append(*asm,
4841 uint8(op>>8),
4842 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4843 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4844 uint8(dl2),
4845 uint8(d2>>12),
4846 uint8(op))
4847 }
4848
4849 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4850 *asm = append(*asm,
4851 uint8(op>>8),
4852 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4853 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4854 uint8(d2))
4855 }
4856
4857 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) {
4858 *asm = append(*asm,
4859 uint8(op>>8),
4860 (uint8(r1)<<4)|uint8(x2&0x0F),
4861 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4862 uint8(d2),
4863 uint8(m3)<<4,
4864 uint8(op))
4865 }
4866
4867 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4868 dl2 := uint16(d2) & 0x0FFF
4869 *asm = append(*asm,
4870 uint8(op>>8),
4871 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4872 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4873 uint8(dl2),
4874 uint8(d2>>12),
4875 uint8(op))
4876 }
4877
4878 func zS(op, b2, d2 uint32, asm *[]byte) {
4879 *asm = append(*asm,
4880 uint8(op>>8),
4881 uint8(op),
4882 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4883 uint8(d2))
4884 }
4885
4886 func zSI(op, i2, b1, d1 uint32, asm *[]byte) {
4887 *asm = append(*asm,
4888 uint8(op>>8),
4889 uint8(i2),
4890 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4891 uint8(d1))
4892 }
4893
4894 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) {
4895 *asm = append(*asm,
4896 uint8(op>>8),
4897 uint8(op),
4898 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4899 uint8(d1),
4900 uint8(i2>>8),
4901 uint8(i2))
4902 }
4903
4904 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) {
4905 dl1 := uint16(d1) & 0x0FFF
4906 *asm = append(*asm,
4907 uint8(op>>8),
4908 uint8(i2),
4909 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F),
4910 uint8(dl1),
4911 uint8(d1>>12),
4912 uint8(op))
4913 }
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) {
4926 *asm = append(*asm, uint8(op>>8))
4927
4928 switch f {
4929 case _a:
4930 *asm = append(*asm, uint8(l1_r1))
4931 case _b, _c, _d, _e:
4932 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F))
4933 case _f:
4934 *asm = append(*asm, uint8(l2_i3_r3))
4935 }
4936
4937 *asm = append(*asm,
4938 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F),
4939 uint8(d1_d2),
4940 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F),
4941 uint8(d2_d4))
4942 }
4943
4944 func rxb(va, vb, vc, vd uint32) uint8 {
4945 mask := uint8(0)
4946 if va >= REG_V16 && va <= REG_V31 {
4947 mask |= 0x8
4948 }
4949 if vb >= REG_V16 && vb <= REG_V31 {
4950 mask |= 0x4
4951 }
4952 if vc >= REG_V16 && vc <= REG_V31 {
4953 mask |= 0x2
4954 }
4955 if vd >= REG_V16 && vd <= REG_V31 {
4956 mask |= 0x1
4957 }
4958 return mask
4959 }
4960
4961 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) {
4962 *asm = append(*asm,
4963 uint8(op>>8),
4964 (uint8(v1)<<4)|(uint8(x2)&0xf),
4965 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4966 uint8(d2),
4967 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
4968 uint8(op))
4969 }
4970
4971 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) {
4972 *asm = append(*asm,
4973 uint8(op>>8),
4974 (uint8(v1)<<4)|(uint8(v2)&0xf),
4975 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4976 uint8(d2),
4977 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4978 uint8(op))
4979 }
4980
4981 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) {
4982 *asm = append(*asm,
4983 uint8(op>>8),
4984 (uint8(v1)<<4)|(uint8(v3_r3)&0xf),
4985 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4986 uint8(d2),
4987 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0),
4988 uint8(op))
4989 }
4990
4991 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) {
4992 *asm = append(*asm,
4993 uint8(op>>8),
4994 (uint8(v1)<<4)|(uint8(v2)&0xf),
4995 0,
4996 (uint8(m5)<<4)|(uint8(m4)&0xf),
4997 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4998 uint8(op))
4999 }
5000
5001 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) {
5002 *asm = append(*asm,
5003 uint8(op>>8),
5004 (uint8(v1)<<4)|(uint8(v2)&0xf),
5005 uint8(v3)<<4,
5006 uint8(m5)<<4,
5007 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5008 uint8(op))
5009 }
5010
5011 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) {
5012 *asm = append(*asm,
5013 uint8(op>>8),
5014 (uint8(v1)<<4)|(uint8(v2)&0xf),
5015 uint8(v3)<<4,
5016 (uint8(m6)<<4)|(uint8(m5)&0xf),
5017 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5018 uint8(op))
5019 }
5020
5021 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) {
5022 *asm = append(*asm,
5023 uint8(op>>8),
5024 (uint8(v1)<<4)|(uint8(v2)&0xf),
5025 (uint8(v3)<<4)|(uint8(m5)&0xf),
5026 uint8(m6)<<4,
5027 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5028 uint8(op))
5029 }
5030
5031 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) {
5032 *asm = append(*asm,
5033 uint8(op>>8),
5034 (uint8(v1)<<4)|(uint8(v2)&0xf),
5035 (uint8(v3)<<4)|(uint8(m6)&0xf),
5036 uint8(m5),
5037 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5038 uint8(op))
5039 }
5040
5041 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) {
5042 *asm = append(*asm,
5043 uint8(op>>8),
5044 (uint8(v1)<<4)|(uint8(r2)&0xf),
5045 uint8(r3)<<4,
5046 0,
5047 rxb(v1, 0, 0, 0),
5048 uint8(op))
5049 }
5050
5051 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) {
5052 *asm = append(*asm,
5053 uint8(op>>8),
5054 uint8(v1)<<4,
5055 uint8(i2>>8),
5056 uint8(i2),
5057 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5058 uint8(op))
5059 }
5060
5061 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) {
5062 *asm = append(*asm,
5063 uint8(op>>8),
5064 uint8(v1)<<4,
5065 uint8(i2),
5066 uint8(i3),
5067 (uint8(m4)<<4)|rxb(v1, 0, 0, 0),
5068 uint8(op))
5069 }
5070
5071 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) {
5072 *asm = append(*asm,
5073 uint8(op>>8),
5074 (uint8(v1)<<4)|(uint8(v3)&0xf),
5075 uint8(i2>>8),
5076 uint8(i2),
5077 (uint8(m4)<<4)|rxb(v1, v3, 0, 0),
5078 uint8(op))
5079 }
5080
5081 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) {
5082 *asm = append(*asm,
5083 uint8(op>>8),
5084 (uint8(v1)<<4)|(uint8(v2)&0xf),
5085 uint8(v3)<<4,
5086 uint8(i4),
5087 (uint8(m5)<<4)|rxb(v1, v2, v3, 0),
5088 uint8(op))
5089 }
5090
5091 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) {
5092 *asm = append(*asm,
5093 uint8(op>>8),
5094 (uint8(v1)<<4)|(uint8(v2)&0xf),
5095 uint8(i3>>4),
5096 (uint8(i3)<<4)|(uint8(m5)&0xf),
5097 (uint8(m4)<<4)|rxb(v1, v2, 0, 0),
5098 uint8(op))
5099 }
5100
5101 func zVSI(op, v1, b2, d2, i3 uint32, asm *[]byte) {
5102 *asm = append(*asm,
5103 uint8(op>>8),
5104 uint8(i3),
5105 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5106 uint8(d2),
5107 (uint8(v1)<<4)|rxb(v1, 0, 0, 0),
5108 uint8(op))
5109 }
5110
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