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31 package x86
32
33 import "cmd/internal/obj"
34
35 const (
36 REG_NONE = 0
37 )
38
39 const (
40 REG_AL = obj.RBaseAMD64 + iota
41 REG_CL
42 REG_DL
43 REG_BL
44 REG_SPB
45 REG_BPB
46 REG_SIB
47 REG_DIB
48 REG_R8B
49 REG_R9B
50 REG_R10B
51 REG_R11B
52 REG_R12B
53 REG_R13B
54 REG_R14B
55 REG_R15B
56
57 REG_AX
58 REG_CX
59 REG_DX
60 REG_BX
61 REG_SP
62 REG_BP
63 REG_SI
64 REG_DI
65 REG_R8
66 REG_R9
67 REG_R10
68 REG_R11
69 REG_R12
70 REG_R13
71 REG_R14
72 REG_R15
73
74 REG_AH
75 REG_CH
76 REG_DH
77 REG_BH
78
79 REG_F0
80 REG_F1
81 REG_F2
82 REG_F3
83 REG_F4
84 REG_F5
85 REG_F6
86 REG_F7
87
88 REG_M0
89 REG_M1
90 REG_M2
91 REG_M3
92 REG_M4
93 REG_M5
94 REG_M6
95 REG_M7
96
97 REG_K0
98 REG_K1
99 REG_K2
100 REG_K3
101 REG_K4
102 REG_K5
103 REG_K6
104 REG_K7
105
106 REG_X0
107 REG_X1
108 REG_X2
109 REG_X3
110 REG_X4
111 REG_X5
112 REG_X6
113 REG_X7
114 REG_X8
115 REG_X9
116 REG_X10
117 REG_X11
118 REG_X12
119 REG_X13
120 REG_X14
121 REG_X15
122 REG_X16
123 REG_X17
124 REG_X18
125 REG_X19
126 REG_X20
127 REG_X21
128 REG_X22
129 REG_X23
130 REG_X24
131 REG_X25
132 REG_X26
133 REG_X27
134 REG_X28
135 REG_X29
136 REG_X30
137 REG_X31
138
139 REG_Y0
140 REG_Y1
141 REG_Y2
142 REG_Y3
143 REG_Y4
144 REG_Y5
145 REG_Y6
146 REG_Y7
147 REG_Y8
148 REG_Y9
149 REG_Y10
150 REG_Y11
151 REG_Y12
152 REG_Y13
153 REG_Y14
154 REG_Y15
155 REG_Y16
156 REG_Y17
157 REG_Y18
158 REG_Y19
159 REG_Y20
160 REG_Y21
161 REG_Y22
162 REG_Y23
163 REG_Y24
164 REG_Y25
165 REG_Y26
166 REG_Y27
167 REG_Y28
168 REG_Y29
169 REG_Y30
170 REG_Y31
171
172 REG_Z0
173 REG_Z1
174 REG_Z2
175 REG_Z3
176 REG_Z4
177 REG_Z5
178 REG_Z6
179 REG_Z7
180 REG_Z8
181 REG_Z9
182 REG_Z10
183 REG_Z11
184 REG_Z12
185 REG_Z13
186 REG_Z14
187 REG_Z15
188 REG_Z16
189 REG_Z17
190 REG_Z18
191 REG_Z19
192 REG_Z20
193 REG_Z21
194 REG_Z22
195 REG_Z23
196 REG_Z24
197 REG_Z25
198 REG_Z26
199 REG_Z27
200 REG_Z28
201 REG_Z29
202 REG_Z30
203 REG_Z31
204
205 REG_CS
206 REG_SS
207 REG_DS
208 REG_ES
209 REG_FS
210 REG_GS
211
212 REG_GDTR
213 REG_IDTR
214 REG_LDTR
215 REG_MSW
216 REG_TASK
217
218 REG_CR0
219 REG_CR1
220 REG_CR2
221 REG_CR3
222 REG_CR4
223 REG_CR5
224 REG_CR6
225 REG_CR7
226 REG_CR8
227 REG_CR9
228 REG_CR10
229 REG_CR11
230 REG_CR12
231 REG_CR13
232 REG_CR14
233 REG_CR15
234
235 REG_DR0
236 REG_DR1
237 REG_DR2
238 REG_DR3
239 REG_DR4
240 REG_DR5
241 REG_DR6
242 REG_DR7
243
244 REG_TR0
245 REG_TR1
246 REG_TR2
247 REG_TR3
248 REG_TR4
249 REG_TR5
250 REG_TR6
251 REG_TR7
252
253 REG_TLS
254
255 MAXREG
256
257 REG_CR = REG_CR0
258 REG_DR = REG_DR0
259 REG_TR = REG_TR0
260
261 REGARG = -1
262 REGRET = REG_AX
263 FREGRET = REG_X0
264 REGSP = REG_SP
265 REGCTXT = REG_DX
266 REGENTRYTMP0 = REG_R12
267 REGENTRYTMP1 = REG_R13
268 REGG = REG_R14
269 REGEXT = REG_R15
270 FREGMIN = REG_X0 + 5
271 FREGEXT = REG_X0 + 15
272 T_TYPE = 1 << 0
273 T_INDEX = 1 << 1
274 T_OFFSET = 1 << 2
275 T_FCONST = 1 << 3
276 T_SYM = 1 << 4
277 T_SCONST = 1 << 5
278 T_64 = 1 << 6
279 T_GOTYPE = 1 << 7
280 )
281
282
283 var AMD64DWARFRegisters = map[int16]int16{
284 REG_AX: 0,
285 REG_DX: 1,
286 REG_CX: 2,
287 REG_BX: 3,
288 REG_SI: 4,
289 REG_DI: 5,
290 REG_BP: 6,
291 REG_SP: 7,
292 REG_R8: 8,
293 REG_R9: 9,
294 REG_R10: 10,
295 REG_R11: 11,
296 REG_R12: 12,
297 REG_R13: 13,
298 REG_R14: 14,
299 REG_R15: 15,
300
301
302 REG_X0: 17,
303 REG_X1: 18,
304 REG_X2: 19,
305 REG_X3: 20,
306 REG_X4: 21,
307 REG_X5: 22,
308 REG_X6: 23,
309 REG_X7: 24,
310
311 REG_X8: 25,
312 REG_X9: 26,
313 REG_X10: 27,
314 REG_X11: 28,
315 REG_X12: 29,
316 REG_X13: 30,
317 REG_X14: 31,
318 REG_X15: 32,
319
320 REG_F0: 33,
321 REG_F1: 34,
322 REG_F2: 35,
323 REG_F3: 36,
324 REG_F4: 37,
325 REG_F5: 38,
326 REG_F6: 39,
327 REG_F7: 40,
328
329 REG_M0: 41,
330 REG_M1: 42,
331 REG_M2: 43,
332 REG_M3: 44,
333 REG_M4: 45,
334 REG_M5: 46,
335 REG_M6: 47,
336 REG_M7: 48,
337
338 REG_ES: 50,
339 REG_CS: 51,
340 REG_SS: 52,
341 REG_DS: 53,
342 REG_FS: 54,
343 REG_GS: 55,
344
345 REG_TR: 62,
346 REG_LDTR: 63,
347
348
349
350 REG_X16: 67,
351 REG_X17: 68,
352 REG_X18: 69,
353 REG_X19: 70,
354 REG_X20: 71,
355 REG_X21: 72,
356 REG_X22: 73,
357 REG_X23: 74,
358 REG_X24: 75,
359 REG_X25: 76,
360 REG_X26: 77,
361 REG_X27: 78,
362 REG_X28: 79,
363 REG_X29: 80,
364 REG_X30: 81,
365 REG_X31: 82,
366
367
368 REG_K0: 118,
369 REG_K1: 119,
370 REG_K2: 120,
371 REG_K3: 121,
372 REG_K4: 122,
373 REG_K5: 123,
374 REG_K6: 124,
375 REG_K7: 125,
376 }
377
378
379 var X86DWARFRegisters = map[int16]int16{
380 REG_AX: 0,
381 REG_CX: 1,
382 REG_DX: 2,
383 REG_BX: 3,
384 REG_SP: 4,
385 REG_BP: 5,
386 REG_SI: 6,
387 REG_DI: 7,
388
389
390
391 REG_F0: 11,
392 REG_F1: 12,
393 REG_F2: 13,
394 REG_F3: 14,
395 REG_F4: 15,
396 REG_F5: 16,
397 REG_F6: 17,
398 REG_F7: 18,
399
400 REG_X0: 21,
401 REG_X1: 22,
402 REG_X2: 23,
403 REG_X3: 24,
404 REG_X4: 25,
405 REG_X5: 26,
406 REG_X6: 27,
407 REG_X7: 28,
408
409 REG_M0: 29,
410 REG_M1: 30,
411 REG_M2: 31,
412 REG_M3: 32,
413 REG_M4: 33,
414 REG_M5: 34,
415 REG_M6: 35,
416 REG_M7: 36,
417
418 REG_ES: 40,
419 REG_CS: 41,
420 REG_SS: 42,
421 REG_DS: 43,
422 REG_FS: 44,
423 REG_GS: 45,
424 REG_TR: 48,
425 REG_LDTR: 49,
426 }
427
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