Source file src/cmd/internal/obj/x86/asm_test.go

     1  // Copyright 2018 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package x86
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  	"cmd/internal/objabi"
    10  	"internal/testenv"
    11  	"os"
    12  	"path/filepath"
    13  	"regexp"
    14  	"testing"
    15  )
    16  
    17  type oclassTest struct {
    18  	arg  *obj.Addr
    19  	want int // Expected oclass return value for a given arg
    20  }
    21  
    22  // Filled inside init, because it's easier to do with helper functions.
    23  var (
    24  	oclassTestsAMD64 []*oclassTest
    25  	oclassTests386   []*oclassTest
    26  )
    27  
    28  func init() {
    29  	// Required for tests that access any of
    30  	// opindex/ycover/reg/regrex global tables.
    31  	var ctxt obj.Link
    32  	instinit(&ctxt)
    33  
    34  	regAddr := func(reg int16) *obj.Addr {
    35  		return &obj.Addr{Type: obj.TYPE_REG, Reg: reg}
    36  	}
    37  	immAddr := func(v int64) *obj.Addr {
    38  		return &obj.Addr{Type: obj.TYPE_CONST, Offset: v}
    39  	}
    40  	regListAddr := func(regFrom, regTo int16) *obj.Addr {
    41  		return &obj.Addr{Type: obj.TYPE_REGLIST, Offset: EncodeRegisterRange(regFrom, regTo)}
    42  	}
    43  	memAddr := func(base, index int16) *obj.Addr {
    44  		return &obj.Addr{Type: obj.TYPE_MEM, Reg: base, Index: index}
    45  	}
    46  
    47  	// TODO(quasilyte): oclass doesn't return Yxxx for X/Y regs with
    48  	// ID higher than 7. We don't encode such instructions, but this
    49  	// behavior seems inconsistent. It should probably either
    50  	// never check for arch or do it in all cases.
    51  
    52  	oclassTestsCommon := []*oclassTest{
    53  		{&obj.Addr{Type: obj.TYPE_NONE}, Ynone},
    54  		{&obj.Addr{Type: obj.TYPE_BRANCH}, Ybr},
    55  		{&obj.Addr{Type: obj.TYPE_TEXTSIZE}, Ytextsize},
    56  
    57  		{&obj.Addr{Type: obj.TYPE_INDIR, Name: obj.NAME_EXTERN}, Yindir},
    58  		{&obj.Addr{Type: obj.TYPE_INDIR, Name: obj.NAME_GOTREF}, Yindir},
    59  
    60  		{&obj.Addr{Type: obj.TYPE_ADDR, Name: obj.NAME_AUTO}, Yiauto},
    61  		{&obj.Addr{Type: obj.TYPE_ADDR, Name: obj.NAME_PARAM}, Yiauto},
    62  		{&obj.Addr{Type: obj.TYPE_ADDR, Name: obj.NAME_EXTERN}, Yiauto},
    63  		{&obj.Addr{Type: obj.TYPE_ADDR, Sym: &obj.LSym{Name: "runtime.duff"}}, Yi32},
    64  		{&obj.Addr{Type: obj.TYPE_ADDR, Offset: 4}, Yu7},
    65  		{&obj.Addr{Type: obj.TYPE_ADDR, Offset: 255}, Yu8},
    66  
    67  		{immAddr(0), Yi0},
    68  		{immAddr(1), Yi1},
    69  		{immAddr(2), Yu2},
    70  		{immAddr(3), Yu2},
    71  		{immAddr(4), Yu7},
    72  		{immAddr(86), Yu7},
    73  		{immAddr(127), Yu7},
    74  		{immAddr(128), Yu8},
    75  		{immAddr(200), Yu8},
    76  		{immAddr(255), Yu8},
    77  		{immAddr(-1), Yi8},
    78  		{immAddr(-100), Yi8},
    79  		{immAddr(-128), Yi8},
    80  
    81  		{regAddr(REG_AL), Yal},
    82  		{regAddr(REG_AX), Yax},
    83  		{regAddr(REG_DL), Yrb},
    84  		{regAddr(REG_DH), Yrb},
    85  		{regAddr(REG_BH), Yrb},
    86  		{regAddr(REG_CL), Ycl},
    87  		{regAddr(REG_CX), Ycx},
    88  		{regAddr(REG_DX), Yrx},
    89  		{regAddr(REG_BX), Yrx},
    90  		{regAddr(REG_F0), Yf0},
    91  		{regAddr(REG_F3), Yrf},
    92  		{regAddr(REG_F7), Yrf},
    93  		{regAddr(REG_M0), Ymr},
    94  		{regAddr(REG_M3), Ymr},
    95  		{regAddr(REG_M7), Ymr},
    96  		{regAddr(REG_X0), Yxr0},
    97  		{regAddr(REG_X6), Yxr},
    98  		{regAddr(REG_X13), Yxr},
    99  		{regAddr(REG_X20), YxrEvex},
   100  		{regAddr(REG_X31), YxrEvex},
   101  		{regAddr(REG_Y0), Yyr},
   102  		{regAddr(REG_Y6), Yyr},
   103  		{regAddr(REG_Y13), Yyr},
   104  		{regAddr(REG_Y20), YyrEvex},
   105  		{regAddr(REG_Y31), YyrEvex},
   106  		{regAddr(REG_Z0), Yzr},
   107  		{regAddr(REG_Z6), Yzr},
   108  		{regAddr(REG_K0), Yk0},
   109  		{regAddr(REG_K5), Yknot0},
   110  		{regAddr(REG_K7), Yknot0},
   111  		{regAddr(REG_CS), Ycs},
   112  		{regAddr(REG_SS), Yss},
   113  		{regAddr(REG_DS), Yds},
   114  		{regAddr(REG_ES), Yes},
   115  		{regAddr(REG_FS), Yfs},
   116  		{regAddr(REG_GS), Ygs},
   117  		{regAddr(REG_TLS), Ytls},
   118  		{regAddr(REG_GDTR), Ygdtr},
   119  		{regAddr(REG_IDTR), Yidtr},
   120  		{regAddr(REG_LDTR), Yldtr},
   121  		{regAddr(REG_MSW), Ymsw},
   122  		{regAddr(REG_TASK), Ytask},
   123  		{regAddr(REG_CR0), Ycr0},
   124  		{regAddr(REG_CR5), Ycr5},
   125  		{regAddr(REG_CR8), Ycr8},
   126  		{regAddr(REG_DR0), Ydr0},
   127  		{regAddr(REG_DR5), Ydr5},
   128  		{regAddr(REG_DR7), Ydr7},
   129  		{regAddr(REG_TR0), Ytr0},
   130  		{regAddr(REG_TR5), Ytr5},
   131  		{regAddr(REG_TR7), Ytr7},
   132  
   133  		{regListAddr(REG_X0, REG_X3), YxrEvexMulti4},
   134  		{regListAddr(REG_X4, REG_X7), YxrEvexMulti4},
   135  		{regListAddr(REG_Y0, REG_Y3), YyrEvexMulti4},
   136  		{regListAddr(REG_Y4, REG_Y7), YyrEvexMulti4},
   137  		{regListAddr(REG_Z0, REG_Z3), YzrMulti4},
   138  		{regListAddr(REG_Z4, REG_Z7), YzrMulti4},
   139  
   140  		{memAddr(REG_AL, REG_NONE), Ym},
   141  		{memAddr(REG_AL, REG_SI), Ym},
   142  		{memAddr(REG_SI, REG_CX), Ym},
   143  		{memAddr(REG_DI, REG_X0), Yxvm},
   144  		{memAddr(REG_DI, REG_X7), Yxvm},
   145  		{memAddr(REG_DI, REG_Y0), Yyvm},
   146  		{memAddr(REG_DI, REG_Y7), Yyvm},
   147  		{memAddr(REG_DI, REG_Z0), Yzvm},
   148  		{memAddr(REG_DI, REG_Z7), Yzvm},
   149  	}
   150  
   151  	oclassTestsAMD64 = []*oclassTest{
   152  		{immAddr(-200), Ys32},
   153  		{immAddr(500), Ys32},
   154  		{immAddr(0x7FFFFFFF), Ys32},
   155  		{immAddr(0x7FFFFFFF + 1), Yi32},
   156  		{immAddr(0xFFFFFFFF), Yi32},
   157  		{immAddr(0xFFFFFFFF + 1), Yi64},
   158  
   159  		{regAddr(REG_BPB), Yrb},
   160  		{regAddr(REG_SIB), Yrb},
   161  		{regAddr(REG_DIB), Yrb},
   162  		{regAddr(REG_R8B), Yrb},
   163  		{regAddr(REG_R12B), Yrb},
   164  		{regAddr(REG_R8), Yrl},
   165  		{regAddr(REG_R13), Yrl},
   166  		{regAddr(REG_R15), Yrl},
   167  		{regAddr(REG_SP), Yrl},
   168  		{regAddr(REG_SI), Yrl},
   169  		{regAddr(REG_DI), Yrl},
   170  		{regAddr(REG_Z13), Yzr},
   171  		{regAddr(REG_Z20), Yzr},
   172  		{regAddr(REG_Z31), Yzr},
   173  
   174  		{regListAddr(REG_X10, REG_X13), YxrEvexMulti4},
   175  		{regListAddr(REG_X24, REG_X27), YxrEvexMulti4},
   176  		{regListAddr(REG_Y10, REG_Y13), YyrEvexMulti4},
   177  		{regListAddr(REG_Y24, REG_Y27), YyrEvexMulti4},
   178  		{regListAddr(REG_Z10, REG_Z13), YzrMulti4},
   179  		{regListAddr(REG_Z24, REG_Z27), YzrMulti4},
   180  
   181  		{memAddr(REG_DI, REG_X20), YxvmEvex},
   182  		{memAddr(REG_DI, REG_X27), YxvmEvex},
   183  		{memAddr(REG_DI, REG_Y20), YyvmEvex},
   184  		{memAddr(REG_DI, REG_Y27), YyvmEvex},
   185  		{memAddr(REG_DI, REG_Z20), Yzvm},
   186  		{memAddr(REG_DI, REG_Z27), Yzvm},
   187  	}
   188  
   189  	oclassTests386 = []*oclassTest{
   190  		{&obj.Addr{Type: obj.TYPE_ADDR, Name: obj.NAME_EXTERN, Sym: &obj.LSym{}}, Yi32},
   191  
   192  		{immAddr(-200), Yi32},
   193  
   194  		{regAddr(REG_SP), Yrl32},
   195  		{regAddr(REG_SI), Yrl32},
   196  		{regAddr(REG_DI), Yrl32},
   197  	}
   198  
   199  	// Add tests that are arch-independent for all sets.
   200  	oclassTestsAMD64 = append(oclassTestsAMD64, oclassTestsCommon...)
   201  	oclassTests386 = append(oclassTests386, oclassTestsCommon...)
   202  }
   203  
   204  func TestOclass(t *testing.T) {
   205  	runTest := func(t *testing.T, ctxt *obj.Link, tests []*oclassTest) {
   206  		var p obj.Prog
   207  		for _, test := range tests {
   208  			have := oclass(ctxt, &p, test.arg)
   209  			if have != test.want {
   210  				t.Errorf("oclass(%q):\nhave: %d\nwant: %d",
   211  					obj.Dconv(&p, test.arg), have, test.want)
   212  			}
   213  		}
   214  	}
   215  
   216  	// TODO(quasilyte): test edge cases for Hsolaris, etc?
   217  
   218  	t.Run("linux/AMD64", func(t *testing.T) {
   219  		ctxtAMD64 := obj.Linknew(&Linkamd64)
   220  		ctxtAMD64.Headtype = objabi.Hlinux // See #32028
   221  		runTest(t, ctxtAMD64, oclassTestsAMD64)
   222  	})
   223  
   224  	t.Run("linux/386", func(t *testing.T) {
   225  		ctxt386 := obj.Linknew(&Link386)
   226  		ctxt386.Headtype = objabi.Hlinux // See #32028
   227  		runTest(t, ctxt386, oclassTests386)
   228  	})
   229  }
   230  
   231  func TestRegisterListEncDec(t *testing.T) {
   232  	tests := []struct {
   233  		printed string
   234  		reg0    int16
   235  		reg1    int16
   236  	}{
   237  		{"[R10-R13]", REG_R10, REG_R13},
   238  		{"[X0-AX]", REG_X0, REG_AX},
   239  
   240  		{"[X0-X3]", REG_X0, REG_X3},
   241  		{"[X21-X24]", REG_X21, REG_X24},
   242  
   243  		{"[Y0-Y3]", REG_Y0, REG_Y3},
   244  		{"[Y21-Y24]", REG_Y21, REG_Y24},
   245  
   246  		{"[Z0-Z3]", REG_Z0, REG_Z3},
   247  		{"[Z21-Z24]", REG_Z21, REG_Z24},
   248  	}
   249  
   250  	for _, test := range tests {
   251  		enc := EncodeRegisterRange(test.reg0, test.reg1)
   252  		reg0, reg1 := decodeRegisterRange(enc)
   253  
   254  		if int16(reg0) != test.reg0 {
   255  			t.Errorf("%s reg0 mismatch: have %d, want %d",
   256  				test.printed, reg0, test.reg0)
   257  		}
   258  		if int16(reg1) != test.reg1 {
   259  			t.Errorf("%s reg1 mismatch: have %d, want %d",
   260  				test.printed, reg1, test.reg1)
   261  		}
   262  		wantPrinted := test.printed
   263  		if rlconv(enc) != wantPrinted {
   264  			t.Errorf("%s string mismatch: have %s, want %s",
   265  				test.printed, rlconv(enc), wantPrinted)
   266  		}
   267  	}
   268  }
   269  
   270  func TestRegIndex(t *testing.T) {
   271  	tests := []struct {
   272  		regFrom int
   273  		regTo   int
   274  	}{
   275  		{REG_AL, REG_R15B},
   276  		{REG_AX, REG_R15},
   277  		{REG_M0, REG_M7},
   278  		{REG_K0, REG_K7},
   279  		{REG_X0, REG_X31},
   280  		{REG_Y0, REG_Y31},
   281  		{REG_Z0, REG_Z31},
   282  	}
   283  
   284  	for _, test := range tests {
   285  		for index, reg := 0, test.regFrom; reg <= test.regTo; index, reg = index+1, reg+1 {
   286  			have := regIndex(int16(reg))
   287  			want := index
   288  			if have != want {
   289  				regName := rconv(int(reg))
   290  				t.Errorf("regIndex(%s):\nhave: %d\nwant: %d",
   291  					regName, have, want)
   292  			}
   293  		}
   294  	}
   295  }
   296  
   297  // TestPCALIGN verifies the correctness of the PCALIGN by checking if the
   298  // code can be aligned to the alignment value.
   299  func TestPCALIGN(t *testing.T) {
   300  	testenv.MustHaveGoBuild(t)
   301  	dir := t.TempDir()
   302  	tmpfile := filepath.Join(dir, "test.s")
   303  	tmpout := filepath.Join(dir, "test.o")
   304  
   305  	var testCases = []struct {
   306  		name string
   307  		code string
   308  		out  string
   309  	}{
   310  		{
   311  			name: "8-byte alignment",
   312  			code: "TEXT ·foo(SB),$0-0\nMOVQ $0, AX\nPCALIGN $8\nMOVQ $1, BX\nRET\n",
   313  			out:  `0x0008\s00008\s\(.*\)\tMOVQ\t\$1,\sBX`,
   314  		},
   315  		{
   316  			name: "16-byte alignment",
   317  			code: "TEXT ·foo(SB),$0-0\nMOVQ $0, AX\nPCALIGN $16\nMOVQ $2, CX\nRET\n",
   318  			out:  `0x0010\s00016\s\(.*\)\tMOVQ\t\$2,\sCX`,
   319  		},
   320  	}
   321  
   322  	for _, test := range testCases {
   323  		if err := os.WriteFile(tmpfile, []byte(test.code), 0644); err != nil {
   324  			t.Fatal(err)
   325  		}
   326  		cmd := testenv.Command(t, testenv.GoToolPath(t), "tool", "asm", "-S", "-o", tmpout, tmpfile)
   327  		cmd.Env = append(os.Environ(), "GOARCH=amd64", "GOOS=linux")
   328  		out, err := cmd.CombinedOutput()
   329  		if err != nil {
   330  			t.Errorf("The %s build failed: %v, output: %s", test.name, err, out)
   331  			continue
   332  		}
   333  
   334  		matched, err := regexp.MatchString(test.out, string(out))
   335  		if err != nil {
   336  			t.Fatal(err)
   337  		}
   338  		if !matched {
   339  			t.Errorf("The %s testing failed!\ninput: %s\noutput: %s\n", test.name, test.code, out)
   340  		}
   341  	}
   342  }
   343  

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