Source file src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

     1  // Code generated by ppc64map -fmt=decoder ../pp64.csv DO NOT EDIT.
     2  
     3  package ppc64asm
     4  
     5  const (
     6  	_ Op = iota
     7  	HASHCHK
     8  	HASHCHKP
     9  	HASHST
    10  	HASHSTP
    11  	BRD
    12  	BRH
    13  	BRW
    14  	CFUGED
    15  	CNTLZDM
    16  	CNTTZDM
    17  	DCFFIXQQ
    18  	DCTFIXQQ
    19  	LXVKQ
    20  	LXVP
    21  	LXVPX
    22  	LXVRBX
    23  	LXVRDX
    24  	LXVRHX
    25  	LXVRWX
    26  	MTVSRBM
    27  	MTVSRBMI
    28  	MTVSRDM
    29  	MTVSRHM
    30  	MTVSRQM
    31  	MTVSRWM
    32  	PADDI
    33  	PDEPD
    34  	PEXTD
    35  	PLBZ
    36  	PLD
    37  	PLFD
    38  	PLFS
    39  	PLHA
    40  	PLHZ
    41  	PLQ
    42  	PLWA
    43  	PLWZ
    44  	PLXSD
    45  	PLXSSP
    46  	PLXV
    47  	PLXVP
    48  	PMXVBF16GER2
    49  	PMXVBF16GER2NN
    50  	PMXVBF16GER2NP
    51  	PMXVBF16GER2PN
    52  	PMXVBF16GER2PP
    53  	PMXVF16GER2
    54  	PMXVF16GER2NN
    55  	PMXVF16GER2NP
    56  	PMXVF16GER2PN
    57  	PMXVF16GER2PP
    58  	PMXVF32GER
    59  	PMXVF32GERNN
    60  	PMXVF32GERNP
    61  	PMXVF32GERPN
    62  	PMXVF32GERPP
    63  	PMXVF64GER
    64  	PMXVF64GERNN
    65  	PMXVF64GERNP
    66  	PMXVF64GERPN
    67  	PMXVF64GERPP
    68  	PMXVI16GER2
    69  	PMXVI16GER2PP
    70  	PMXVI16GER2S
    71  	PMXVI16GER2SPP
    72  	PMXVI4GER8
    73  	PMXVI4GER8PP
    74  	PMXVI8GER4
    75  	PMXVI8GER4PP
    76  	PMXVI8GER4SPP
    77  	PNOP
    78  	PSTB
    79  	PSTD
    80  	PSTFD
    81  	PSTFS
    82  	PSTH
    83  	PSTQ
    84  	PSTW
    85  	PSTXSD
    86  	PSTXSSP
    87  	PSTXV
    88  	PSTXVP
    89  	SETBC
    90  	SETBCR
    91  	SETNBC
    92  	SETNBCR
    93  	STXVP
    94  	STXVPX
    95  	STXVRBX
    96  	STXVRDX
    97  	STXVRHX
    98  	STXVRWX
    99  	VCFUGED
   100  	VCLRLB
   101  	VCLRRB
   102  	VCLZDM
   103  	VCMPEQUQ
   104  	VCMPEQUQCC
   105  	VCMPGTSQ
   106  	VCMPGTSQCC
   107  	VCMPGTUQ
   108  	VCMPGTUQCC
   109  	VCMPSQ
   110  	VCMPUQ
   111  	VCNTMBB
   112  	VCNTMBD
   113  	VCNTMBH
   114  	VCNTMBW
   115  	VCTZDM
   116  	VDIVESD
   117  	VDIVESQ
   118  	VDIVESW
   119  	VDIVEUD
   120  	VDIVEUQ
   121  	VDIVEUW
   122  	VDIVSD
   123  	VDIVSQ
   124  	VDIVSW
   125  	VDIVUD
   126  	VDIVUQ
   127  	VDIVUW
   128  	VEXPANDBM
   129  	VEXPANDDM
   130  	VEXPANDHM
   131  	VEXPANDQM
   132  	VEXPANDWM
   133  	VEXTDDVLX
   134  	VEXTDDVRX
   135  	VEXTDUBVLX
   136  	VEXTDUBVRX
   137  	VEXTDUHVLX
   138  	VEXTDUHVRX
   139  	VEXTDUWVLX
   140  	VEXTDUWVRX
   141  	VEXTRACTBM
   142  	VEXTRACTDM
   143  	VEXTRACTHM
   144  	VEXTRACTQM
   145  	VEXTRACTWM
   146  	VEXTSD2Q
   147  	VGNB
   148  	VINSBLX
   149  	VINSBRX
   150  	VINSBVLX
   151  	VINSBVRX
   152  	VINSD
   153  	VINSDLX
   154  	VINSDRX
   155  	VINSHLX
   156  	VINSHRX
   157  	VINSHVLX
   158  	VINSHVRX
   159  	VINSW
   160  	VINSWLX
   161  	VINSWRX
   162  	VINSWVLX
   163  	VINSWVRX
   164  	VMODSD
   165  	VMODSQ
   166  	VMODSW
   167  	VMODUD
   168  	VMODUQ
   169  	VMODUW
   170  	VMSUMCUD
   171  	VMULESD
   172  	VMULEUD
   173  	VMULHSD
   174  	VMULHSW
   175  	VMULHUD
   176  	VMULHUW
   177  	VMULLD
   178  	VMULOSD
   179  	VMULOUD
   180  	VPDEPD
   181  	VPEXTD
   182  	VRLQ
   183  	VRLQMI
   184  	VRLQNM
   185  	VSLDBI
   186  	VSLQ
   187  	VSRAQ
   188  	VSRDBI
   189  	VSRQ
   190  	VSTRIBL
   191  	VSTRIBLCC
   192  	VSTRIBR
   193  	VSTRIBRCC
   194  	VSTRIHL
   195  	VSTRIHLCC
   196  	VSTRIHR
   197  	VSTRIHRCC
   198  	XSCMPEQQP
   199  	XSCMPGEQP
   200  	XSCMPGTQP
   201  	XSCVQPSQZ
   202  	XSCVQPUQZ
   203  	XSCVSQQP
   204  	XSCVUQQP
   205  	XSMAXCQP
   206  	XSMINCQP
   207  	XVBF16GER2
   208  	XVBF16GER2NN
   209  	XVBF16GER2NP
   210  	XVBF16GER2PN
   211  	XVBF16GER2PP
   212  	XVCVBF16SPN
   213  	XVCVSPBF16
   214  	XVF16GER2
   215  	XVF16GER2NN
   216  	XVF16GER2NP
   217  	XVF16GER2PN
   218  	XVF16GER2PP
   219  	XVF32GER
   220  	XVF32GERNN
   221  	XVF32GERNP
   222  	XVF32GERPN
   223  	XVF32GERPP
   224  	XVF64GER
   225  	XVF64GERNN
   226  	XVF64GERNP
   227  	XVF64GERPN
   228  	XVF64GERPP
   229  	XVI16GER2
   230  	XVI16GER2PP
   231  	XVI16GER2S
   232  	XVI16GER2SPP
   233  	XVI4GER8
   234  	XVI4GER8PP
   235  	XVI8GER4
   236  	XVI8GER4PP
   237  	XVI8GER4SPP
   238  	XVTLSBB
   239  	XXBLENDVB
   240  	XXBLENDVD
   241  	XXBLENDVH
   242  	XXBLENDVW
   243  	XXEVAL
   244  	XXGENPCVBM
   245  	XXGENPCVDM
   246  	XXGENPCVHM
   247  	XXGENPCVWM
   248  	XXMFACC
   249  	XXMTACC
   250  	XXPERMX
   251  	XXSETACCZ
   252  	XXSPLTI32DX
   253  	XXSPLTIDP
   254  	XXSPLTIW
   255  	MSGCLRU
   256  	MSGSNDU
   257  	URFID
   258  	ADDEX
   259  	MFFSCDRN
   260  	MFFSCDRNI
   261  	MFFSCE
   262  	MFFSCRN
   263  	MFFSCRNI
   264  	MFFSL
   265  	SLBIAG
   266  	VMSUMUDM
   267  	ADDPCIS
   268  	BCDCFNCC
   269  	BCDCFSQCC
   270  	BCDCFZCC
   271  	BCDCPSGNCC
   272  	BCDCTNCC
   273  	BCDCTSQCC
   274  	BCDCTZCC
   275  	BCDSCC
   276  	BCDSETSGNCC
   277  	BCDSRCC
   278  	BCDTRUNCCC
   279  	BCDUSCC
   280  	BCDUTRUNCCC
   281  	CMPEQB
   282  	CMPRB
   283  	CNTTZD
   284  	CNTTZDCC
   285  	CNTTZW
   286  	CNTTZWCC
   287  	COPY
   288  	CPABORT
   289  	DARN
   290  	DTSTSFI
   291  	DTSTSFIQ
   292  	EXTSWSLI
   293  	EXTSWSLICC
   294  	LDAT
   295  	LWAT
   296  	LXSD
   297  	LXSIBZX
   298  	LXSIHZX
   299  	LXSSP
   300  	LXV
   301  	LXVB16X
   302  	LXVH8X
   303  	LXVL
   304  	LXVLL
   305  	LXVWSX
   306  	LXVX
   307  	MADDHD
   308  	MADDHDU
   309  	MADDLD
   310  	MCRXRX
   311  	MFVSRLD
   312  	MODSD
   313  	MODSW
   314  	MODUD
   315  	MODUW
   316  	MSGSYNC
   317  	MTVSRDD
   318  	MTVSRWS
   319  	PASTECC
   320  	SETB
   321  	SLBIEG
   322  	SLBSYNC
   323  	STDAT
   324  	STOP
   325  	STWAT
   326  	STXSD
   327  	STXSIBX
   328  	STXSIHX
   329  	STXSSP
   330  	STXV
   331  	STXVB16X
   332  	STXVH8X
   333  	STXVL
   334  	STXVLL
   335  	STXVX
   336  	VABSDUB
   337  	VABSDUH
   338  	VABSDUW
   339  	VBPERMD
   340  	VCLZLSBB
   341  	VCMPNEB
   342  	VCMPNEBCC
   343  	VCMPNEH
   344  	VCMPNEHCC
   345  	VCMPNEW
   346  	VCMPNEWCC
   347  	VCMPNEZB
   348  	VCMPNEZBCC
   349  	VCMPNEZH
   350  	VCMPNEZHCC
   351  	VCMPNEZW
   352  	VCMPNEZWCC
   353  	VCTZB
   354  	VCTZD
   355  	VCTZH
   356  	VCTZLSBB
   357  	VCTZW
   358  	VEXTRACTD
   359  	VEXTRACTUB
   360  	VEXTRACTUH
   361  	VEXTRACTUW
   362  	VEXTSB2D
   363  	VEXTSB2W
   364  	VEXTSH2D
   365  	VEXTSH2W
   366  	VEXTSW2D
   367  	VEXTUBLX
   368  	VEXTUBRX
   369  	VEXTUHLX
   370  	VEXTUHRX
   371  	VEXTUWLX
   372  	VEXTUWRX
   373  	VINSERTB
   374  	VINSERTD
   375  	VINSERTH
   376  	VINSERTW
   377  	VMUL10CUQ
   378  	VMUL10ECUQ
   379  	VMUL10EUQ
   380  	VMUL10UQ
   381  	VNEGD
   382  	VNEGW
   383  	VPERMR
   384  	VPRTYBD
   385  	VPRTYBQ
   386  	VPRTYBW
   387  	VRLDMI
   388  	VRLDNM
   389  	VRLWMI
   390  	VRLWNM
   391  	VSLV
   392  	VSRV
   393  	WAIT
   394  	XSABSQP
   395  	XSADDQP
   396  	XSADDQPO
   397  	XSCMPEQDP
   398  	XSCMPEXPDP
   399  	XSCMPEXPQP
   400  	XSCMPGEDP
   401  	XSCMPGTDP
   402  	XSCMPOQP
   403  	XSCMPUQP
   404  	XSCPSGNQP
   405  	XSCVDPHP
   406  	XSCVDPQP
   407  	XSCVHPDP
   408  	XSCVQPDP
   409  	XSCVQPDPO
   410  	XSCVQPSDZ
   411  	XSCVQPSWZ
   412  	XSCVQPUDZ
   413  	XSCVQPUWZ
   414  	XSCVSDQP
   415  	XSCVUDQP
   416  	XSDIVQP
   417  	XSDIVQPO
   418  	XSIEXPDP
   419  	XSIEXPQP
   420  	XSMADDQP
   421  	XSMADDQPO
   422  	XSMAXCDP
   423  	XSMAXJDP
   424  	XSMINCDP
   425  	XSMINJDP
   426  	XSMSUBQP
   427  	XSMSUBQPO
   428  	XSMULQP
   429  	XSMULQPO
   430  	XSNABSQP
   431  	XSNEGQP
   432  	XSNMADDQP
   433  	XSNMADDQPO
   434  	XSNMSUBQP
   435  	XSNMSUBQPO
   436  	XSRQPI
   437  	XSRQPIX
   438  	XSRQPXP
   439  	XSSQRTQP
   440  	XSSQRTQPO
   441  	XSSUBQP
   442  	XSSUBQPO
   443  	XSTSTDCDP
   444  	XSTSTDCQP
   445  	XSTSTDCSP
   446  	XSXEXPDP
   447  	XSXEXPQP
   448  	XSXSIGDP
   449  	XSXSIGQP
   450  	XVCVHPSP
   451  	XVCVSPHP
   452  	XVIEXPDP
   453  	XVIEXPSP
   454  	XVTSTDCDP
   455  	XVTSTDCSP
   456  	XVXEXPDP
   457  	XVXEXPSP
   458  	XVXSIGDP
   459  	XVXSIGSP
   460  	XXBRD
   461  	XXBRH
   462  	XXBRQ
   463  	XXBRW
   464  	XXEXTRACTUW
   465  	XXINSERTW
   466  	XXPERM
   467  	XXPERMR
   468  	XXSPLTIB
   469  	BCDADDCC
   470  	BCDSUBCC
   471  	BCTAR
   472  	BCTARL
   473  	CLRBHRB
   474  	FMRGEW
   475  	FMRGOW
   476  	ICBT
   477  	LQARX
   478  	LXSIWAX
   479  	LXSIWZX
   480  	LXSSPX
   481  	MFBHRBE
   482  	MFVSRD
   483  	MFVSRWZ
   484  	MSGCLR
   485  	MSGCLRP
   486  	MSGSND
   487  	MSGSNDP
   488  	MTVSRD
   489  	MTVSRWA
   490  	MTVSRWZ
   491  	RFEBB
   492  	STQCXCC
   493  	STXSIWX
   494  	STXSSPX
   495  	VADDCUQ
   496  	VADDECUQ
   497  	VADDEUQM
   498  	VADDUDM
   499  	VADDUQM
   500  	VBPERMQ
   501  	VCIPHER
   502  	VCIPHERLAST
   503  	VCLZB
   504  	VCLZD
   505  	VCLZH
   506  	VCLZW
   507  	VCMPEQUD
   508  	VCMPEQUDCC
   509  	VCMPGTSD
   510  	VCMPGTSDCC
   511  	VCMPGTUD
   512  	VCMPGTUDCC
   513  	VEQV
   514  	VGBBD
   515  	VMAXSD
   516  	VMAXUD
   517  	VMINSD
   518  	VMINUD
   519  	VMRGEW
   520  	VMRGOW
   521  	VMULESW
   522  	VMULEUW
   523  	VMULOSW
   524  	VMULOUW
   525  	VMULUWM
   526  	VNAND
   527  	VNCIPHER
   528  	VNCIPHERLAST
   529  	VORC
   530  	VPERMXOR
   531  	VPKSDSS
   532  	VPKSDUS
   533  	VPKUDUM
   534  	VPKUDUS
   535  	VPMSUMB
   536  	VPMSUMD
   537  	VPMSUMH
   538  	VPMSUMW
   539  	VPOPCNTB
   540  	VPOPCNTD
   541  	VPOPCNTH
   542  	VPOPCNTW
   543  	VRLD
   544  	VSBOX
   545  	VSHASIGMAD
   546  	VSHASIGMAW
   547  	VSLD
   548  	VSRAD
   549  	VSRD
   550  	VSUBCUQ
   551  	VSUBECUQ
   552  	VSUBEUQM
   553  	VSUBUDM
   554  	VSUBUQM
   555  	VUPKHSW
   556  	VUPKLSW
   557  	XSADDSP
   558  	XSCVDPSPN
   559  	XSCVSPDPN
   560  	XSCVSXDSP
   561  	XSCVUXDSP
   562  	XSDIVSP
   563  	XSMADDASP
   564  	XSMADDMSP
   565  	XSMSUBASP
   566  	XSMSUBMSP
   567  	XSMULSP
   568  	XSNMADDASP
   569  	XSNMADDMSP
   570  	XSNMSUBASP
   571  	XSNMSUBMSP
   572  	XSRESP
   573  	XSRSP
   574  	XSRSQRTESP
   575  	XSSQRTSP
   576  	XSSUBSP
   577  	XXLEQV
   578  	XXLNAND
   579  	XXLORC
   580  	ADDG6S
   581  	BPERMD
   582  	CBCDTD
   583  	CDTBCD
   584  	DCFFIX
   585  	DCFFIXCC
   586  	DIVDE
   587  	DIVDECC
   588  	DIVDEO
   589  	DIVDEOCC
   590  	DIVDEU
   591  	DIVDEUCC
   592  	DIVDEUO
   593  	DIVDEUOCC
   594  	DIVWE
   595  	DIVWECC
   596  	DIVWEO
   597  	DIVWEOCC
   598  	DIVWEU
   599  	DIVWEUCC
   600  	DIVWEUO
   601  	DIVWEUOCC
   602  	FCFIDS
   603  	FCFIDSCC
   604  	FCFIDU
   605  	FCFIDUCC
   606  	FCFIDUS
   607  	FCFIDUSCC
   608  	FCTIDU
   609  	FCTIDUCC
   610  	FCTIDUZ
   611  	FCTIDUZCC
   612  	FCTIWU
   613  	FCTIWUCC
   614  	FCTIWUZ
   615  	FCTIWUZCC
   616  	FTDIV
   617  	FTSQRT
   618  	LBARX
   619  	LDBRX
   620  	LFIWZX
   621  	LHARX
   622  	LXSDX
   623  	LXVD2X
   624  	LXVDSX
   625  	LXVW4X
   626  	POPCNTD
   627  	POPCNTW
   628  	STBCXCC
   629  	STDBRX
   630  	STHCXCC
   631  	STXSDX
   632  	STXVD2X
   633  	STXVW4X
   634  	XSABSDP
   635  	XSADDDP
   636  	XSCMPODP
   637  	XSCMPUDP
   638  	XSCPSGNDP
   639  	XSCVDPSP
   640  	XSCVDPSXDS
   641  	XSCVDPSXWS
   642  	XSCVDPUXDS
   643  	XSCVDPUXWS
   644  	XSCVSPDP
   645  	XSCVSXDDP
   646  	XSCVUXDDP
   647  	XSDIVDP
   648  	XSMADDADP
   649  	XSMADDMDP
   650  	XSMAXDP
   651  	XSMINDP
   652  	XSMSUBADP
   653  	XSMSUBMDP
   654  	XSMULDP
   655  	XSNABSDP
   656  	XSNEGDP
   657  	XSNMADDADP
   658  	XSNMADDMDP
   659  	XSNMSUBADP
   660  	XSNMSUBMDP
   661  	XSRDPI
   662  	XSRDPIC
   663  	XSRDPIM
   664  	XSRDPIP
   665  	XSRDPIZ
   666  	XSREDP
   667  	XSRSQRTEDP
   668  	XSSQRTDP
   669  	XSSUBDP
   670  	XSTDIVDP
   671  	XSTSQRTDP
   672  	XVABSDP
   673  	XVABSSP
   674  	XVADDDP
   675  	XVADDSP
   676  	XVCMPEQDP
   677  	XVCMPEQDPCC
   678  	XVCMPEQSP
   679  	XVCMPEQSPCC
   680  	XVCMPGEDP
   681  	XVCMPGEDPCC
   682  	XVCMPGESP
   683  	XVCMPGESPCC
   684  	XVCMPGTDP
   685  	XVCMPGTDPCC
   686  	XVCMPGTSP
   687  	XVCMPGTSPCC
   688  	XVCPSGNDP
   689  	XVCPSGNSP
   690  	XVCVDPSP
   691  	XVCVDPSXDS
   692  	XVCVDPSXWS
   693  	XVCVDPUXDS
   694  	XVCVDPUXWS
   695  	XVCVSPDP
   696  	XVCVSPSXDS
   697  	XVCVSPSXWS
   698  	XVCVSPUXDS
   699  	XVCVSPUXWS
   700  	XVCVSXDDP
   701  	XVCVSXDSP
   702  	XVCVSXWDP
   703  	XVCVSXWSP
   704  	XVCVUXDDP
   705  	XVCVUXDSP
   706  	XVCVUXWDP
   707  	XVCVUXWSP
   708  	XVDIVDP
   709  	XVDIVSP
   710  	XVMADDADP
   711  	XVMADDASP
   712  	XVMADDMDP
   713  	XVMADDMSP
   714  	XVMAXDP
   715  	XVMAXSP
   716  	XVMINDP
   717  	XVMINSP
   718  	XVMSUBADP
   719  	XVMSUBASP
   720  	XVMSUBMDP
   721  	XVMSUBMSP
   722  	XVMULDP
   723  	XVMULSP
   724  	XVNABSDP
   725  	XVNABSSP
   726  	XVNEGDP
   727  	XVNEGSP
   728  	XVNMADDADP
   729  	XVNMADDASP
   730  	XVNMADDMDP
   731  	XVNMADDMSP
   732  	XVNMSUBADP
   733  	XVNMSUBASP
   734  	XVNMSUBMDP
   735  	XVNMSUBMSP
   736  	XVRDPI
   737  	XVRDPIC
   738  	XVRDPIM
   739  	XVRDPIP
   740  	XVRDPIZ
   741  	XVREDP
   742  	XVRESP
   743  	XVRSPI
   744  	XVRSPIC
   745  	XVRSPIM
   746  	XVRSPIP
   747  	XVRSPIZ
   748  	XVRSQRTEDP
   749  	XVRSQRTESP
   750  	XVSQRTDP
   751  	XVSQRTSP
   752  	XVSUBDP
   753  	XVSUBSP
   754  	XVTDIVDP
   755  	XVTDIVSP
   756  	XVTSQRTDP
   757  	XVTSQRTSP
   758  	XXLAND
   759  	XXLANDC
   760  	XXLNOR
   761  	XXLOR
   762  	XXLXOR
   763  	XXMRGHW
   764  	XXMRGLW
   765  	XXPERMDI
   766  	XXSEL
   767  	XXSLDWI
   768  	XXSPLTW
   769  	CMPB
   770  	DADD
   771  	DADDCC
   772  	DADDQ
   773  	DADDQCC
   774  	DCFFIXQ
   775  	DCFFIXQCC
   776  	DCMPO
   777  	DCMPOQ
   778  	DCMPU
   779  	DCMPUQ
   780  	DCTDP
   781  	DCTDPCC
   782  	DCTFIX
   783  	DCTFIXCC
   784  	DCTFIXQ
   785  	DCTFIXQCC
   786  	DCTQPQ
   787  	DCTQPQCC
   788  	DDEDPD
   789  	DDEDPDCC
   790  	DDEDPDQ
   791  	DDEDPDQCC
   792  	DDIV
   793  	DDIVCC
   794  	DDIVQ
   795  	DDIVQCC
   796  	DENBCD
   797  	DENBCDCC
   798  	DENBCDQ
   799  	DENBCDQCC
   800  	DIEX
   801  	DIEXCC
   802  	DIEXQCC
   803  	DIEXQ
   804  	DMUL
   805  	DMULCC
   806  	DMULQ
   807  	DMULQCC
   808  	DQUA
   809  	DQUACC
   810  	DQUAI
   811  	DQUAICC
   812  	DQUAIQ
   813  	DQUAIQCC
   814  	DQUAQ
   815  	DQUAQCC
   816  	DRDPQ
   817  	DRDPQCC
   818  	DRINTN
   819  	DRINTNCC
   820  	DRINTNQ
   821  	DRINTNQCC
   822  	DRINTX
   823  	DRINTXCC
   824  	DRINTXQ
   825  	DRINTXQCC
   826  	DRRND
   827  	DRRNDCC
   828  	DRRNDQ
   829  	DRRNDQCC
   830  	DRSP
   831  	DRSPCC
   832  	DSCLI
   833  	DSCLICC
   834  	DSCLIQ
   835  	DSCLIQCC
   836  	DSCRI
   837  	DSCRICC
   838  	DSCRIQ
   839  	DSCRIQCC
   840  	DSUB
   841  	DSUBCC
   842  	DSUBQ
   843  	DSUBQCC
   844  	DTSTDC
   845  	DTSTDCQ
   846  	DTSTDG
   847  	DTSTDGQ
   848  	DTSTEX
   849  	DTSTEXQ
   850  	DTSTSF
   851  	DTSTSFQ
   852  	DXEX
   853  	DXEXCC
   854  	DXEXQ
   855  	DXEXQCC
   856  	FCPSGN
   857  	FCPSGNCC
   858  	LBZCIX
   859  	LDCIX
   860  	LFDP
   861  	LFDPX
   862  	LFIWAX
   863  	LHZCIX
   864  	LWZCIX
   865  	PRTYD
   866  	PRTYW
   867  	SLBFEECC
   868  	STBCIX
   869  	STDCIX
   870  	STFDP
   871  	STFDPX
   872  	STHCIX
   873  	STWCIX
   874  	ISEL
   875  	LVEBX
   876  	LVEHX
   877  	LVEWX
   878  	LVSL
   879  	LVSR
   880  	LVX
   881  	LVXL
   882  	MFVSCR
   883  	MTVSCR
   884  	STVEBX
   885  	STVEHX
   886  	STVEWX
   887  	STVX
   888  	STVXL
   889  	TLBIEL
   890  	VADDCUW
   891  	VADDFP
   892  	VADDSBS
   893  	VADDSHS
   894  	VADDSWS
   895  	VADDUBM
   896  	VADDUBS
   897  	VADDUHM
   898  	VADDUHS
   899  	VADDUWM
   900  	VADDUWS
   901  	VAND
   902  	VANDC
   903  	VAVGSB
   904  	VAVGSH
   905  	VAVGSW
   906  	VAVGUB
   907  	VAVGUH
   908  	VAVGUW
   909  	VCFSX
   910  	VCFUX
   911  	VCMPBFP
   912  	VCMPBFPCC
   913  	VCMPEQFP
   914  	VCMPEQFPCC
   915  	VCMPEQUB
   916  	VCMPEQUBCC
   917  	VCMPEQUH
   918  	VCMPEQUHCC
   919  	VCMPEQUW
   920  	VCMPEQUWCC
   921  	VCMPGEFP
   922  	VCMPGEFPCC
   923  	VCMPGTFP
   924  	VCMPGTFPCC
   925  	VCMPGTSB
   926  	VCMPGTSBCC
   927  	VCMPGTSH
   928  	VCMPGTSHCC
   929  	VCMPGTSW
   930  	VCMPGTSWCC
   931  	VCMPGTUB
   932  	VCMPGTUBCC
   933  	VCMPGTUH
   934  	VCMPGTUHCC
   935  	VCMPGTUW
   936  	VCMPGTUWCC
   937  	VCTSXS
   938  	VCTUXS
   939  	VEXPTEFP
   940  	VLOGEFP
   941  	VMADDFP
   942  	VMAXFP
   943  	VMAXSB
   944  	VMAXSH
   945  	VMAXSW
   946  	VMAXUB
   947  	VMAXUH
   948  	VMAXUW
   949  	VMHADDSHS
   950  	VMHRADDSHS
   951  	VMINFP
   952  	VMINSB
   953  	VMINSH
   954  	VMINSW
   955  	VMINUB
   956  	VMINUH
   957  	VMINUW
   958  	VMLADDUHM
   959  	VMRGHB
   960  	VMRGHH
   961  	VMRGHW
   962  	VMRGLB
   963  	VMRGLH
   964  	VMRGLW
   965  	VMSUMMBM
   966  	VMSUMSHM
   967  	VMSUMSHS
   968  	VMSUMUBM
   969  	VMSUMUHM
   970  	VMSUMUHS
   971  	VMULESB
   972  	VMULESH
   973  	VMULEUB
   974  	VMULEUH
   975  	VMULOSB
   976  	VMULOSH
   977  	VMULOUB
   978  	VMULOUH
   979  	VNMSUBFP
   980  	VNOR
   981  	VOR
   982  	VPERM
   983  	VPKPX
   984  	VPKSHSS
   985  	VPKSHUS
   986  	VPKSWSS
   987  	VPKSWUS
   988  	VPKUHUM
   989  	VPKUHUS
   990  	VPKUWUM
   991  	VPKUWUS
   992  	VREFP
   993  	VRFIM
   994  	VRFIN
   995  	VRFIP
   996  	VRFIZ
   997  	VRLB
   998  	VRLH
   999  	VRLW
  1000  	VRSQRTEFP
  1001  	VSEL
  1002  	VSL
  1003  	VSLB
  1004  	VSLDOI
  1005  	VSLH
  1006  	VSLO
  1007  	VSLW
  1008  	VSPLTB
  1009  	VSPLTH
  1010  	VSPLTISB
  1011  	VSPLTISH
  1012  	VSPLTISW
  1013  	VSPLTW
  1014  	VSR
  1015  	VSRAB
  1016  	VSRAH
  1017  	VSRAW
  1018  	VSRB
  1019  	VSRH
  1020  	VSRO
  1021  	VSRW
  1022  	VSUBCUW
  1023  	VSUBFP
  1024  	VSUBSBS
  1025  	VSUBSHS
  1026  	VSUBSWS
  1027  	VSUBUBM
  1028  	VSUBUBS
  1029  	VSUBUHM
  1030  	VSUBUHS
  1031  	VSUBUWM
  1032  	VSUBUWS
  1033  	VSUM2SWS
  1034  	VSUM4SBS
  1035  	VSUM4SHS
  1036  	VSUM4UBS
  1037  	VSUMSWS
  1038  	VUPKHPX
  1039  	VUPKHSB
  1040  	VUPKHSH
  1041  	VUPKLPX
  1042  	VUPKLSB
  1043  	VUPKLSH
  1044  	VXOR
  1045  	FRE
  1046  	FRECC
  1047  	FRIM
  1048  	FRIMCC
  1049  	FRIN
  1050  	FRINCC
  1051  	FRIP
  1052  	FRIPCC
  1053  	FRIZ
  1054  	FRIZCC
  1055  	FRSQRTES
  1056  	FRSQRTESCC
  1057  	HRFID
  1058  	POPCNTB
  1059  	MFOCRF
  1060  	MTOCRF
  1061  	SLBMFEE
  1062  	SLBMFEV
  1063  	SLBMTE
  1064  	RFSCV
  1065  	SCV
  1066  	LQ
  1067  	STQ
  1068  	CNTLZD
  1069  	CNTLZDCC
  1070  	DCBF
  1071  	DCBST
  1072  	DCBT
  1073  	DCBTST
  1074  	DIVD
  1075  	DIVDCC
  1076  	DIVDO
  1077  	DIVDOCC
  1078  	DIVDU
  1079  	DIVDUCC
  1080  	DIVDUO
  1081  	DIVDUOCC
  1082  	DIVW
  1083  	DIVWCC
  1084  	DIVWO
  1085  	DIVWOCC
  1086  	DIVWU
  1087  	DIVWUCC
  1088  	DIVWUO
  1089  	DIVWUOCC
  1090  	EIEIO
  1091  	EXTSB
  1092  	EXTSBCC
  1093  	EXTSW
  1094  	EXTSWCC
  1095  	FADDS
  1096  	FADDSCC
  1097  	FCFID
  1098  	FCFIDCC
  1099  	FCTID
  1100  	FCTIDCC
  1101  	FCTIDZ
  1102  	FCTIDZCC
  1103  	FDIVS
  1104  	FDIVSCC
  1105  	FMADDS
  1106  	FMADDSCC
  1107  	FMSUBS
  1108  	FMSUBSCC
  1109  	FMULS
  1110  	FMULSCC
  1111  	FNMADDS
  1112  	FNMADDSCC
  1113  	FNMSUBS
  1114  	FNMSUBSCC
  1115  	FRES
  1116  	FRESCC
  1117  	FRSQRTE
  1118  	FRSQRTECC
  1119  	FSEL
  1120  	FSELCC
  1121  	FSQRTS
  1122  	FSQRTSCC
  1123  	FSUBS
  1124  	FSUBSCC
  1125  	ICBI
  1126  	LD
  1127  	LDARX
  1128  	LDU
  1129  	LDUX
  1130  	LDX
  1131  	LWA
  1132  	LWARX
  1133  	LWAUX
  1134  	LWAX
  1135  	MFTB
  1136  	MTMSRD
  1137  	MULHD
  1138  	MULHDCC
  1139  	MULHDU
  1140  	MULHDUCC
  1141  	MULHW
  1142  	MULHWCC
  1143  	MULHWU
  1144  	MULHWUCC
  1145  	MULLD
  1146  	MULLDCC
  1147  	MULLDO
  1148  	MULLDOCC
  1149  	RFID
  1150  	RLDCL
  1151  	RLDCLCC
  1152  	RLDCR
  1153  	RLDCRCC
  1154  	RLDIC
  1155  	RLDICCC
  1156  	RLDICL
  1157  	RLDICLCC
  1158  	RLDICR
  1159  	RLDICRCC
  1160  	RLDIMI
  1161  	RLDIMICC
  1162  	SC
  1163  	SLBIA
  1164  	SLBIE
  1165  	SLD
  1166  	SLDCC
  1167  	SRAD
  1168  	SRADCC
  1169  	SRADI
  1170  	SRADICC
  1171  	SRD
  1172  	SRDCC
  1173  	STD
  1174  	STDCXCC
  1175  	STDU
  1176  	STDUX
  1177  	STDX
  1178  	STFIWX
  1179  	STWCXCC
  1180  	SUBF
  1181  	SUBFCC
  1182  	SUBFO
  1183  	SUBFOCC
  1184  	TD
  1185  	TDI
  1186  	TLBSYNC
  1187  	FCTIW
  1188  	FCTIWCC
  1189  	FCTIWZ
  1190  	FCTIWZCC
  1191  	FSQRT
  1192  	FSQRTCC
  1193  	ADD
  1194  	ADDCC
  1195  	ADDO
  1196  	ADDOCC
  1197  	ADDC
  1198  	ADDCCC
  1199  	ADDCO
  1200  	ADDCOCC
  1201  	ADDE
  1202  	ADDECC
  1203  	ADDEO
  1204  	ADDEOCC
  1205  	LI
  1206  	ADDI
  1207  	ADDIC
  1208  	ADDICCC
  1209  	LIS
  1210  	ADDIS
  1211  	ADDME
  1212  	ADDMECC
  1213  	ADDMEO
  1214  	ADDMEOCC
  1215  	ADDZE
  1216  	ADDZECC
  1217  	ADDZEO
  1218  	ADDZEOCC
  1219  	AND
  1220  	ANDCC
  1221  	ANDC
  1222  	ANDCCC
  1223  	ANDICC
  1224  	ANDISCC
  1225  	B
  1226  	BA
  1227  	BL
  1228  	BLA
  1229  	BC
  1230  	BCA
  1231  	BCL
  1232  	BCLA
  1233  	BCCTR
  1234  	BCCTRL
  1235  	BCLR
  1236  	BCLRL
  1237  	CMPW
  1238  	CMPD
  1239  	CMP
  1240  	CMPWI
  1241  	CMPDI
  1242  	CMPI
  1243  	CMPLW
  1244  	CMPLD
  1245  	CMPL
  1246  	CMPLWI
  1247  	CMPLDI
  1248  	CMPLI
  1249  	CNTLZW
  1250  	CNTLZWCC
  1251  	CRAND
  1252  	CRANDC
  1253  	CREQV
  1254  	CRNAND
  1255  	CRNOR
  1256  	CROR
  1257  	CRORC
  1258  	CRXOR
  1259  	DCBZ
  1260  	EQV
  1261  	EQVCC
  1262  	EXTSH
  1263  	EXTSHCC
  1264  	FABS
  1265  	FABSCC
  1266  	FADD
  1267  	FADDCC
  1268  	FCMPO
  1269  	FCMPU
  1270  	FDIV
  1271  	FDIVCC
  1272  	FMADD
  1273  	FMADDCC
  1274  	FMR
  1275  	FMRCC
  1276  	FMSUB
  1277  	FMSUBCC
  1278  	FMUL
  1279  	FMULCC
  1280  	FNABS
  1281  	FNABSCC
  1282  	FNEG
  1283  	FNEGCC
  1284  	FNMADD
  1285  	FNMADDCC
  1286  	FNMSUB
  1287  	FNMSUBCC
  1288  	FRSP
  1289  	FRSPCC
  1290  	FSUB
  1291  	FSUBCC
  1292  	ISYNC
  1293  	LBZ
  1294  	LBZU
  1295  	LBZUX
  1296  	LBZX
  1297  	LFD
  1298  	LFDU
  1299  	LFDUX
  1300  	LFDX
  1301  	LFS
  1302  	LFSU
  1303  	LFSUX
  1304  	LFSX
  1305  	LHA
  1306  	LHAU
  1307  	LHAUX
  1308  	LHAX
  1309  	LHBRX
  1310  	LHZ
  1311  	LHZU
  1312  	LHZUX
  1313  	LHZX
  1314  	LMW
  1315  	LSWI
  1316  	LSWX
  1317  	LWBRX
  1318  	LWZ
  1319  	LWZU
  1320  	LWZUX
  1321  	LWZX
  1322  	MCRF
  1323  	MCRFS
  1324  	MFCR
  1325  	MFFS
  1326  	MFFSCC
  1327  	MFMSR
  1328  	MFSPR
  1329  	MTCRF
  1330  	MTFSB0
  1331  	MTFSB0CC
  1332  	MTFSB1
  1333  	MTFSB1CC
  1334  	MTFSF
  1335  	MTFSFCC
  1336  	MTFSFI
  1337  	MTFSFICC
  1338  	MTMSR
  1339  	MTSPR
  1340  	MULLI
  1341  	MULLW
  1342  	MULLWCC
  1343  	MULLWO
  1344  	MULLWOCC
  1345  	NAND
  1346  	NANDCC
  1347  	NEG
  1348  	NEGCC
  1349  	NEGO
  1350  	NEGOCC
  1351  	NOR
  1352  	NORCC
  1353  	OR
  1354  	ORCC
  1355  	ORC
  1356  	ORCCC
  1357  	NOP
  1358  	ORI
  1359  	ORIS
  1360  	RLWIMI
  1361  	RLWIMICC
  1362  	RLWINM
  1363  	RLWINMCC
  1364  	RLWNM
  1365  	RLWNMCC
  1366  	SLW
  1367  	SLWCC
  1368  	SRAW
  1369  	SRAWCC
  1370  	SRAWI
  1371  	SRAWICC
  1372  	SRW
  1373  	SRWCC
  1374  	STB
  1375  	STBU
  1376  	STBUX
  1377  	STBX
  1378  	STFD
  1379  	STFDU
  1380  	STFDUX
  1381  	STFDX
  1382  	STFS
  1383  	STFSU
  1384  	STFSUX
  1385  	STFSX
  1386  	STH
  1387  	STHBRX
  1388  	STHU
  1389  	STHUX
  1390  	STHX
  1391  	STMW
  1392  	STSWI
  1393  	STSWX
  1394  	STW
  1395  	STWBRX
  1396  	STWU
  1397  	STWUX
  1398  	STWX
  1399  	SUBFC
  1400  	SUBFCCC
  1401  	SUBFCO
  1402  	SUBFCOCC
  1403  	SUBFE
  1404  	SUBFECC
  1405  	SUBFEO
  1406  	SUBFEOCC
  1407  	SUBFIC
  1408  	SUBFME
  1409  	SUBFMECC
  1410  	SUBFMEO
  1411  	SUBFMEOCC
  1412  	SUBFZE
  1413  	SUBFZECC
  1414  	SUBFZEO
  1415  	SUBFZEOCC
  1416  	SYNC
  1417  	TLBIE
  1418  	TW
  1419  	TWI
  1420  	XOR
  1421  	XORCC
  1422  	XORI
  1423  	XORIS
  1424  )
  1425  
  1426  var opstr = [...]string{
  1427  	HASHCHK:        "hashchk",
  1428  	HASHCHKP:       "hashchkp",
  1429  	HASHST:         "hashst",
  1430  	HASHSTP:        "hashstp",
  1431  	BRD:            "brd",
  1432  	BRH:            "brh",
  1433  	BRW:            "brw",
  1434  	CFUGED:         "cfuged",
  1435  	CNTLZDM:        "cntlzdm",
  1436  	CNTTZDM:        "cnttzdm",
  1437  	DCFFIXQQ:       "dcffixqq",
  1438  	DCTFIXQQ:       "dctfixqq",
  1439  	LXVKQ:          "lxvkq",
  1440  	LXVP:           "lxvp",
  1441  	LXVPX:          "lxvpx",
  1442  	LXVRBX:         "lxvrbx",
  1443  	LXVRDX:         "lxvrdx",
  1444  	LXVRHX:         "lxvrhx",
  1445  	LXVRWX:         "lxvrwx",
  1446  	MTVSRBM:        "mtvsrbm",
  1447  	MTVSRBMI:       "mtvsrbmi",
  1448  	MTVSRDM:        "mtvsrdm",
  1449  	MTVSRHM:        "mtvsrhm",
  1450  	MTVSRQM:        "mtvsrqm",
  1451  	MTVSRWM:        "mtvsrwm",
  1452  	PADDI:          "paddi",
  1453  	PDEPD:          "pdepd",
  1454  	PEXTD:          "pextd",
  1455  	PLBZ:           "plbz",
  1456  	PLD:            "pld",
  1457  	PLFD:           "plfd",
  1458  	PLFS:           "plfs",
  1459  	PLHA:           "plha",
  1460  	PLHZ:           "plhz",
  1461  	PLQ:            "plq",
  1462  	PLWA:           "plwa",
  1463  	PLWZ:           "plwz",
  1464  	PLXSD:          "plxsd",
  1465  	PLXSSP:         "plxssp",
  1466  	PLXV:           "plxv",
  1467  	PLXVP:          "plxvp",
  1468  	PMXVBF16GER2:   "pmxvbf16ger2",
  1469  	PMXVBF16GER2NN: "pmxvbf16ger2nn",
  1470  	PMXVBF16GER2NP: "pmxvbf16ger2np",
  1471  	PMXVBF16GER2PN: "pmxvbf16ger2pn",
  1472  	PMXVBF16GER2PP: "pmxvbf16ger2pp",
  1473  	PMXVF16GER2:    "pmxvf16ger2",
  1474  	PMXVF16GER2NN:  "pmxvf16ger2nn",
  1475  	PMXVF16GER2NP:  "pmxvf16ger2np",
  1476  	PMXVF16GER2PN:  "pmxvf16ger2pn",
  1477  	PMXVF16GER2PP:  "pmxvf16ger2pp",
  1478  	PMXVF32GER:     "pmxvf32ger",
  1479  	PMXVF32GERNN:   "pmxvf32gernn",
  1480  	PMXVF32GERNP:   "pmxvf32gernp",
  1481  	PMXVF32GERPN:   "pmxvf32gerpn",
  1482  	PMXVF32GERPP:   "pmxvf32gerpp",
  1483  	PMXVF64GER:     "pmxvf64ger",
  1484  	PMXVF64GERNN:   "pmxvf64gernn",
  1485  	PMXVF64GERNP:   "pmxvf64gernp",
  1486  	PMXVF64GERPN:   "pmxvf64gerpn",
  1487  	PMXVF64GERPP:   "pmxvf64gerpp",
  1488  	PMXVI16GER2:    "pmxvi16ger2",
  1489  	PMXVI16GER2PP:  "pmxvi16ger2pp",
  1490  	PMXVI16GER2S:   "pmxvi16ger2s",
  1491  	PMXVI16GER2SPP: "pmxvi16ger2spp",
  1492  	PMXVI4GER8:     "pmxvi4ger8",
  1493  	PMXVI4GER8PP:   "pmxvi4ger8pp",
  1494  	PMXVI8GER4:     "pmxvi8ger4",
  1495  	PMXVI8GER4PP:   "pmxvi8ger4pp",
  1496  	PMXVI8GER4SPP:  "pmxvi8ger4spp",
  1497  	PNOP:           "pnop",
  1498  	PSTB:           "pstb",
  1499  	PSTD:           "pstd",
  1500  	PSTFD:          "pstfd",
  1501  	PSTFS:          "pstfs",
  1502  	PSTH:           "psth",
  1503  	PSTQ:           "pstq",
  1504  	PSTW:           "pstw",
  1505  	PSTXSD:         "pstxsd",
  1506  	PSTXSSP:        "pstxssp",
  1507  	PSTXV:          "pstxv",
  1508  	PSTXVP:         "pstxvp",
  1509  	SETBC:          "setbc",
  1510  	SETBCR:         "setbcr",
  1511  	SETNBC:         "setnbc",
  1512  	SETNBCR:        "setnbcr",
  1513  	STXVP:          "stxvp",
  1514  	STXVPX:         "stxvpx",
  1515  	STXVRBX:        "stxvrbx",
  1516  	STXVRDX:        "stxvrdx",
  1517  	STXVRHX:        "stxvrhx",
  1518  	STXVRWX:        "stxvrwx",
  1519  	VCFUGED:        "vcfuged",
  1520  	VCLRLB:         "vclrlb",
  1521  	VCLRRB:         "vclrrb",
  1522  	VCLZDM:         "vclzdm",
  1523  	VCMPEQUQ:       "vcmpequq",
  1524  	VCMPEQUQCC:     "vcmpequq.",
  1525  	VCMPGTSQ:       "vcmpgtsq",
  1526  	VCMPGTSQCC:     "vcmpgtsq.",
  1527  	VCMPGTUQ:       "vcmpgtuq",
  1528  	VCMPGTUQCC:     "vcmpgtuq.",
  1529  	VCMPSQ:         "vcmpsq",
  1530  	VCMPUQ:         "vcmpuq",
  1531  	VCNTMBB:        "vcntmbb",
  1532  	VCNTMBD:        "vcntmbd",
  1533  	VCNTMBH:        "vcntmbh",
  1534  	VCNTMBW:        "vcntmbw",
  1535  	VCTZDM:         "vctzdm",
  1536  	VDIVESD:        "vdivesd",
  1537  	VDIVESQ:        "vdivesq",
  1538  	VDIVESW:        "vdivesw",
  1539  	VDIVEUD:        "vdiveud",
  1540  	VDIVEUQ:        "vdiveuq",
  1541  	VDIVEUW:        "vdiveuw",
  1542  	VDIVSD:         "vdivsd",
  1543  	VDIVSQ:         "vdivsq",
  1544  	VDIVSW:         "vdivsw",
  1545  	VDIVUD:         "vdivud",
  1546  	VDIVUQ:         "vdivuq",
  1547  	VDIVUW:         "vdivuw",
  1548  	VEXPANDBM:      "vexpandbm",
  1549  	VEXPANDDM:      "vexpanddm",
  1550  	VEXPANDHM:      "vexpandhm",
  1551  	VEXPANDQM:      "vexpandqm",
  1552  	VEXPANDWM:      "vexpandwm",
  1553  	VEXTDDVLX:      "vextddvlx",
  1554  	VEXTDDVRX:      "vextddvrx",
  1555  	VEXTDUBVLX:     "vextdubvlx",
  1556  	VEXTDUBVRX:     "vextdubvrx",
  1557  	VEXTDUHVLX:     "vextduhvlx",
  1558  	VEXTDUHVRX:     "vextduhvrx",
  1559  	VEXTDUWVLX:     "vextduwvlx",
  1560  	VEXTDUWVRX:     "vextduwvrx",
  1561  	VEXTRACTBM:     "vextractbm",
  1562  	VEXTRACTDM:     "vextractdm",
  1563  	VEXTRACTHM:     "vextracthm",
  1564  	VEXTRACTQM:     "vextractqm",
  1565  	VEXTRACTWM:     "vextractwm",
  1566  	VEXTSD2Q:       "vextsd2q",
  1567  	VGNB:           "vgnb",
  1568  	VINSBLX:        "vinsblx",
  1569  	VINSBRX:        "vinsbrx",
  1570  	VINSBVLX:       "vinsbvlx",
  1571  	VINSBVRX:       "vinsbvrx",
  1572  	VINSD:          "vinsd",
  1573  	VINSDLX:        "vinsdlx",
  1574  	VINSDRX:        "vinsdrx",
  1575  	VINSHLX:        "vinshlx",
  1576  	VINSHRX:        "vinshrx",
  1577  	VINSHVLX:       "vinshvlx",
  1578  	VINSHVRX:       "vinshvrx",
  1579  	VINSW:          "vinsw",
  1580  	VINSWLX:        "vinswlx",
  1581  	VINSWRX:        "vinswrx",
  1582  	VINSWVLX:       "vinswvlx",
  1583  	VINSWVRX:       "vinswvrx",
  1584  	VMODSD:         "vmodsd",
  1585  	VMODSQ:         "vmodsq",
  1586  	VMODSW:         "vmodsw",
  1587  	VMODUD:         "vmodud",
  1588  	VMODUQ:         "vmoduq",
  1589  	VMODUW:         "vmoduw",
  1590  	VMSUMCUD:       "vmsumcud",
  1591  	VMULESD:        "vmulesd",
  1592  	VMULEUD:        "vmuleud",
  1593  	VMULHSD:        "vmulhsd",
  1594  	VMULHSW:        "vmulhsw",
  1595  	VMULHUD:        "vmulhud",
  1596  	VMULHUW:        "vmulhuw",
  1597  	VMULLD:         "vmulld",
  1598  	VMULOSD:        "vmulosd",
  1599  	VMULOUD:        "vmuloud",
  1600  	VPDEPD:         "vpdepd",
  1601  	VPEXTD:         "vpextd",
  1602  	VRLQ:           "vrlq",
  1603  	VRLQMI:         "vrlqmi",
  1604  	VRLQNM:         "vrlqnm",
  1605  	VSLDBI:         "vsldbi",
  1606  	VSLQ:           "vslq",
  1607  	VSRAQ:          "vsraq",
  1608  	VSRDBI:         "vsrdbi",
  1609  	VSRQ:           "vsrq",
  1610  	VSTRIBL:        "vstribl",
  1611  	VSTRIBLCC:      "vstribl.",
  1612  	VSTRIBR:        "vstribr",
  1613  	VSTRIBRCC:      "vstribr.",
  1614  	VSTRIHL:        "vstrihl",
  1615  	VSTRIHLCC:      "vstrihl.",
  1616  	VSTRIHR:        "vstrihr",
  1617  	VSTRIHRCC:      "vstrihr.",
  1618  	XSCMPEQQP:      "xscmpeqqp",
  1619  	XSCMPGEQP:      "xscmpgeqp",
  1620  	XSCMPGTQP:      "xscmpgtqp",
  1621  	XSCVQPSQZ:      "xscvqpsqz",
  1622  	XSCVQPUQZ:      "xscvqpuqz",
  1623  	XSCVSQQP:       "xscvsqqp",
  1624  	XSCVUQQP:       "xscvuqqp",
  1625  	XSMAXCQP:       "xsmaxcqp",
  1626  	XSMINCQP:       "xsmincqp",
  1627  	XVBF16GER2:     "xvbf16ger2",
  1628  	XVBF16GER2NN:   "xvbf16ger2nn",
  1629  	XVBF16GER2NP:   "xvbf16ger2np",
  1630  	XVBF16GER2PN:   "xvbf16ger2pn",
  1631  	XVBF16GER2PP:   "xvbf16ger2pp",
  1632  	XVCVBF16SPN:    "xvcvbf16spn",
  1633  	XVCVSPBF16:     "xvcvspbf16",
  1634  	XVF16GER2:      "xvf16ger2",
  1635  	XVF16GER2NN:    "xvf16ger2nn",
  1636  	XVF16GER2NP:    "xvf16ger2np",
  1637  	XVF16GER2PN:    "xvf16ger2pn",
  1638  	XVF16GER2PP:    "xvf16ger2pp",
  1639  	XVF32GER:       "xvf32ger",
  1640  	XVF32GERNN:     "xvf32gernn",
  1641  	XVF32GERNP:     "xvf32gernp",
  1642  	XVF32GERPN:     "xvf32gerpn",
  1643  	XVF32GERPP:     "xvf32gerpp",
  1644  	XVF64GER:       "xvf64ger",
  1645  	XVF64GERNN:     "xvf64gernn",
  1646  	XVF64GERNP:     "xvf64gernp",
  1647  	XVF64GERPN:     "xvf64gerpn",
  1648  	XVF64GERPP:     "xvf64gerpp",
  1649  	XVI16GER2:      "xvi16ger2",
  1650  	XVI16GER2PP:    "xvi16ger2pp",
  1651  	XVI16GER2S:     "xvi16ger2s",
  1652  	XVI16GER2SPP:   "xvi16ger2spp",
  1653  	XVI4GER8:       "xvi4ger8",
  1654  	XVI4GER8PP:     "xvi4ger8pp",
  1655  	XVI8GER4:       "xvi8ger4",
  1656  	XVI8GER4PP:     "xvi8ger4pp",
  1657  	XVI8GER4SPP:    "xvi8ger4spp",
  1658  	XVTLSBB:        "xvtlsbb",
  1659  	XXBLENDVB:      "xxblendvb",
  1660  	XXBLENDVD:      "xxblendvd",
  1661  	XXBLENDVH:      "xxblendvh",
  1662  	XXBLENDVW:      "xxblendvw",
  1663  	XXEVAL:         "xxeval",
  1664  	XXGENPCVBM:     "xxgenpcvbm",
  1665  	XXGENPCVDM:     "xxgenpcvdm",
  1666  	XXGENPCVHM:     "xxgenpcvhm",
  1667  	XXGENPCVWM:     "xxgenpcvwm",
  1668  	XXMFACC:        "xxmfacc",
  1669  	XXMTACC:        "xxmtacc",
  1670  	XXPERMX:        "xxpermx",
  1671  	XXSETACCZ:      "xxsetaccz",
  1672  	XXSPLTI32DX:    "xxsplti32dx",
  1673  	XXSPLTIDP:      "xxspltidp",
  1674  	XXSPLTIW:       "xxspltiw",
  1675  	MSGCLRU:        "msgclru",
  1676  	MSGSNDU:        "msgsndu",
  1677  	URFID:          "urfid",
  1678  	ADDEX:          "addex",
  1679  	MFFSCDRN:       "mffscdrn",
  1680  	MFFSCDRNI:      "mffscdrni",
  1681  	MFFSCE:         "mffsce",
  1682  	MFFSCRN:        "mffscrn",
  1683  	MFFSCRNI:       "mffscrni",
  1684  	MFFSL:          "mffsl",
  1685  	SLBIAG:         "slbiag",
  1686  	VMSUMUDM:       "vmsumudm",
  1687  	ADDPCIS:        "addpcis",
  1688  	BCDCFNCC:       "bcdcfn.",
  1689  	BCDCFSQCC:      "bcdcfsq.",
  1690  	BCDCFZCC:       "bcdcfz.",
  1691  	BCDCPSGNCC:     "bcdcpsgn.",
  1692  	BCDCTNCC:       "bcdctn.",
  1693  	BCDCTSQCC:      "bcdctsq.",
  1694  	BCDCTZCC:       "bcdctz.",
  1695  	BCDSCC:         "bcds.",
  1696  	BCDSETSGNCC:    "bcdsetsgn.",
  1697  	BCDSRCC:        "bcdsr.",
  1698  	BCDTRUNCCC:     "bcdtrunc.",
  1699  	BCDUSCC:        "bcdus.",
  1700  	BCDUTRUNCCC:    "bcdutrunc.",
  1701  	CMPEQB:         "cmpeqb",
  1702  	CMPRB:          "cmprb",
  1703  	CNTTZD:         "cnttzd",
  1704  	CNTTZDCC:       "cnttzd.",
  1705  	CNTTZW:         "cnttzw",
  1706  	CNTTZWCC:       "cnttzw.",
  1707  	COPY:           "copy",
  1708  	CPABORT:        "cpabort",
  1709  	DARN:           "darn",
  1710  	DTSTSFI:        "dtstsfi",
  1711  	DTSTSFIQ:       "dtstsfiq",
  1712  	EXTSWSLI:       "extswsli",
  1713  	EXTSWSLICC:     "extswsli.",
  1714  	LDAT:           "ldat",
  1715  	LWAT:           "lwat",
  1716  	LXSD:           "lxsd",
  1717  	LXSIBZX:        "lxsibzx",
  1718  	LXSIHZX:        "lxsihzx",
  1719  	LXSSP:          "lxssp",
  1720  	LXV:            "lxv",
  1721  	LXVB16X:        "lxvb16x",
  1722  	LXVH8X:         "lxvh8x",
  1723  	LXVL:           "lxvl",
  1724  	LXVLL:          "lxvll",
  1725  	LXVWSX:         "lxvwsx",
  1726  	LXVX:           "lxvx",
  1727  	MADDHD:         "maddhd",
  1728  	MADDHDU:        "maddhdu",
  1729  	MADDLD:         "maddld",
  1730  	MCRXRX:         "mcrxrx",
  1731  	MFVSRLD:        "mfvsrld",
  1732  	MODSD:          "modsd",
  1733  	MODSW:          "modsw",
  1734  	MODUD:          "modud",
  1735  	MODUW:          "moduw",
  1736  	MSGSYNC:        "msgsync",
  1737  	MTVSRDD:        "mtvsrdd",
  1738  	MTVSRWS:        "mtvsrws",
  1739  	PASTECC:        "paste.",
  1740  	SETB:           "setb",
  1741  	SLBIEG:         "slbieg",
  1742  	SLBSYNC:        "slbsync",
  1743  	STDAT:          "stdat",
  1744  	STOP:           "stop",
  1745  	STWAT:          "stwat",
  1746  	STXSD:          "stxsd",
  1747  	STXSIBX:        "stxsibx",
  1748  	STXSIHX:        "stxsihx",
  1749  	STXSSP:         "stxssp",
  1750  	STXV:           "stxv",
  1751  	STXVB16X:       "stxvb16x",
  1752  	STXVH8X:        "stxvh8x",
  1753  	STXVL:          "stxvl",
  1754  	STXVLL:         "stxvll",
  1755  	STXVX:          "stxvx",
  1756  	VABSDUB:        "vabsdub",
  1757  	VABSDUH:        "vabsduh",
  1758  	VABSDUW:        "vabsduw",
  1759  	VBPERMD:        "vbpermd",
  1760  	VCLZLSBB:       "vclzlsbb",
  1761  	VCMPNEB:        "vcmpneb",
  1762  	VCMPNEBCC:      "vcmpneb.",
  1763  	VCMPNEH:        "vcmpneh",
  1764  	VCMPNEHCC:      "vcmpneh.",
  1765  	VCMPNEW:        "vcmpnew",
  1766  	VCMPNEWCC:      "vcmpnew.",
  1767  	VCMPNEZB:       "vcmpnezb",
  1768  	VCMPNEZBCC:     "vcmpnezb.",
  1769  	VCMPNEZH:       "vcmpnezh",
  1770  	VCMPNEZHCC:     "vcmpnezh.",
  1771  	VCMPNEZW:       "vcmpnezw",
  1772  	VCMPNEZWCC:     "vcmpnezw.",
  1773  	VCTZB:          "vctzb",
  1774  	VCTZD:          "vctzd",
  1775  	VCTZH:          "vctzh",
  1776  	VCTZLSBB:       "vctzlsbb",
  1777  	VCTZW:          "vctzw",
  1778  	VEXTRACTD:      "vextractd",
  1779  	VEXTRACTUB:     "vextractub",
  1780  	VEXTRACTUH:     "vextractuh",
  1781  	VEXTRACTUW:     "vextractuw",
  1782  	VEXTSB2D:       "vextsb2d",
  1783  	VEXTSB2W:       "vextsb2w",
  1784  	VEXTSH2D:       "vextsh2d",
  1785  	VEXTSH2W:       "vextsh2w",
  1786  	VEXTSW2D:       "vextsw2d",
  1787  	VEXTUBLX:       "vextublx",
  1788  	VEXTUBRX:       "vextubrx",
  1789  	VEXTUHLX:       "vextuhlx",
  1790  	VEXTUHRX:       "vextuhrx",
  1791  	VEXTUWLX:       "vextuwlx",
  1792  	VEXTUWRX:       "vextuwrx",
  1793  	VINSERTB:       "vinsertb",
  1794  	VINSERTD:       "vinsertd",
  1795  	VINSERTH:       "vinserth",
  1796  	VINSERTW:       "vinsertw",
  1797  	VMUL10CUQ:      "vmul10cuq",
  1798  	VMUL10ECUQ:     "vmul10ecuq",
  1799  	VMUL10EUQ:      "vmul10euq",
  1800  	VMUL10UQ:       "vmul10uq",
  1801  	VNEGD:          "vnegd",
  1802  	VNEGW:          "vnegw",
  1803  	VPERMR:         "vpermr",
  1804  	VPRTYBD:        "vprtybd",
  1805  	VPRTYBQ:        "vprtybq",
  1806  	VPRTYBW:        "vprtybw",
  1807  	VRLDMI:         "vrldmi",
  1808  	VRLDNM:         "vrldnm",
  1809  	VRLWMI:         "vrlwmi",
  1810  	VRLWNM:         "vrlwnm",
  1811  	VSLV:           "vslv",
  1812  	VSRV:           "vsrv",
  1813  	WAIT:           "wait",
  1814  	XSABSQP:        "xsabsqp",
  1815  	XSADDQP:        "xsaddqp",
  1816  	XSADDQPO:       "xsaddqpo",
  1817  	XSCMPEQDP:      "xscmpeqdp",
  1818  	XSCMPEXPDP:     "xscmpexpdp",
  1819  	XSCMPEXPQP:     "xscmpexpqp",
  1820  	XSCMPGEDP:      "xscmpgedp",
  1821  	XSCMPGTDP:      "xscmpgtdp",
  1822  	XSCMPOQP:       "xscmpoqp",
  1823  	XSCMPUQP:       "xscmpuqp",
  1824  	XSCPSGNQP:      "xscpsgnqp",
  1825  	XSCVDPHP:       "xscvdphp",
  1826  	XSCVDPQP:       "xscvdpqp",
  1827  	XSCVHPDP:       "xscvhpdp",
  1828  	XSCVQPDP:       "xscvqpdp",
  1829  	XSCVQPDPO:      "xscvqpdpo",
  1830  	XSCVQPSDZ:      "xscvqpsdz",
  1831  	XSCVQPSWZ:      "xscvqpswz",
  1832  	XSCVQPUDZ:      "xscvqpudz",
  1833  	XSCVQPUWZ:      "xscvqpuwz",
  1834  	XSCVSDQP:       "xscvsdqp",
  1835  	XSCVUDQP:       "xscvudqp",
  1836  	XSDIVQP:        "xsdivqp",
  1837  	XSDIVQPO:       "xsdivqpo",
  1838  	XSIEXPDP:       "xsiexpdp",
  1839  	XSIEXPQP:       "xsiexpqp",
  1840  	XSMADDQP:       "xsmaddqp",
  1841  	XSMADDQPO:      "xsmaddqpo",
  1842  	XSMAXCDP:       "xsmaxcdp",
  1843  	XSMAXJDP:       "xsmaxjdp",
  1844  	XSMINCDP:       "xsmincdp",
  1845  	XSMINJDP:       "xsminjdp",
  1846  	XSMSUBQP:       "xsmsubqp",
  1847  	XSMSUBQPO:      "xsmsubqpo",
  1848  	XSMULQP:        "xsmulqp",
  1849  	XSMULQPO:       "xsmulqpo",
  1850  	XSNABSQP:       "xsnabsqp",
  1851  	XSNEGQP:        "xsnegqp",
  1852  	XSNMADDQP:      "xsnmaddqp",
  1853  	XSNMADDQPO:     "xsnmaddqpo",
  1854  	XSNMSUBQP:      "xsnmsubqp",
  1855  	XSNMSUBQPO:     "xsnmsubqpo",
  1856  	XSRQPI:         "xsrqpi",
  1857  	XSRQPIX:        "xsrqpix",
  1858  	XSRQPXP:        "xsrqpxp",
  1859  	XSSQRTQP:       "xssqrtqp",
  1860  	XSSQRTQPO:      "xssqrtqpo",
  1861  	XSSUBQP:        "xssubqp",
  1862  	XSSUBQPO:       "xssubqpo",
  1863  	XSTSTDCDP:      "xststdcdp",
  1864  	XSTSTDCQP:      "xststdcqp",
  1865  	XSTSTDCSP:      "xststdcsp",
  1866  	XSXEXPDP:       "xsxexpdp",
  1867  	XSXEXPQP:       "xsxexpqp",
  1868  	XSXSIGDP:       "xsxsigdp",
  1869  	XSXSIGQP:       "xsxsigqp",
  1870  	XVCVHPSP:       "xvcvhpsp",
  1871  	XVCVSPHP:       "xvcvsphp",
  1872  	XVIEXPDP:       "xviexpdp",
  1873  	XVIEXPSP:       "xviexpsp",
  1874  	XVTSTDCDP:      "xvtstdcdp",
  1875  	XVTSTDCSP:      "xvtstdcsp",
  1876  	XVXEXPDP:       "xvxexpdp",
  1877  	XVXEXPSP:       "xvxexpsp",
  1878  	XVXSIGDP:       "xvxsigdp",
  1879  	XVXSIGSP:       "xvxsigsp",
  1880  	XXBRD:          "xxbrd",
  1881  	XXBRH:          "xxbrh",
  1882  	XXBRQ:          "xxbrq",
  1883  	XXBRW:          "xxbrw",
  1884  	XXEXTRACTUW:    "xxextractuw",
  1885  	XXINSERTW:      "xxinsertw",
  1886  	XXPERM:         "xxperm",
  1887  	XXPERMR:        "xxpermr",
  1888  	XXSPLTIB:       "xxspltib",
  1889  	BCDADDCC:       "bcdadd.",
  1890  	BCDSUBCC:       "bcdsub.",
  1891  	BCTAR:          "bctar",
  1892  	BCTARL:         "bctarl",
  1893  	CLRBHRB:        "clrbhrb",
  1894  	FMRGEW:         "fmrgew",
  1895  	FMRGOW:         "fmrgow",
  1896  	ICBT:           "icbt",
  1897  	LQARX:          "lqarx",
  1898  	LXSIWAX:        "lxsiwax",
  1899  	LXSIWZX:        "lxsiwzx",
  1900  	LXSSPX:         "lxsspx",
  1901  	MFBHRBE:        "mfbhrbe",
  1902  	MFVSRD:         "mfvsrd",
  1903  	MFVSRWZ:        "mfvsrwz",
  1904  	MSGCLR:         "msgclr",
  1905  	MSGCLRP:        "msgclrp",
  1906  	MSGSND:         "msgsnd",
  1907  	MSGSNDP:        "msgsndp",
  1908  	MTVSRD:         "mtvsrd",
  1909  	MTVSRWA:        "mtvsrwa",
  1910  	MTVSRWZ:        "mtvsrwz",
  1911  	RFEBB:          "rfebb",
  1912  	STQCXCC:        "stqcx.",
  1913  	STXSIWX:        "stxsiwx",
  1914  	STXSSPX:        "stxsspx",
  1915  	VADDCUQ:        "vaddcuq",
  1916  	VADDECUQ:       "vaddecuq",
  1917  	VADDEUQM:       "vaddeuqm",
  1918  	VADDUDM:        "vaddudm",
  1919  	VADDUQM:        "vadduqm",
  1920  	VBPERMQ:        "vbpermq",
  1921  	VCIPHER:        "vcipher",
  1922  	VCIPHERLAST:    "vcipherlast",
  1923  	VCLZB:          "vclzb",
  1924  	VCLZD:          "vclzd",
  1925  	VCLZH:          "vclzh",
  1926  	VCLZW:          "vclzw",
  1927  	VCMPEQUD:       "vcmpequd",
  1928  	VCMPEQUDCC:     "vcmpequd.",
  1929  	VCMPGTSD:       "vcmpgtsd",
  1930  	VCMPGTSDCC:     "vcmpgtsd.",
  1931  	VCMPGTUD:       "vcmpgtud",
  1932  	VCMPGTUDCC:     "vcmpgtud.",
  1933  	VEQV:           "veqv",
  1934  	VGBBD:          "vgbbd",
  1935  	VMAXSD:         "vmaxsd",
  1936  	VMAXUD:         "vmaxud",
  1937  	VMINSD:         "vminsd",
  1938  	VMINUD:         "vminud",
  1939  	VMRGEW:         "vmrgew",
  1940  	VMRGOW:         "vmrgow",
  1941  	VMULESW:        "vmulesw",
  1942  	VMULEUW:        "vmuleuw",
  1943  	VMULOSW:        "vmulosw",
  1944  	VMULOUW:        "vmulouw",
  1945  	VMULUWM:        "vmuluwm",
  1946  	VNAND:          "vnand",
  1947  	VNCIPHER:       "vncipher",
  1948  	VNCIPHERLAST:   "vncipherlast",
  1949  	VORC:           "vorc",
  1950  	VPERMXOR:       "vpermxor",
  1951  	VPKSDSS:        "vpksdss",
  1952  	VPKSDUS:        "vpksdus",
  1953  	VPKUDUM:        "vpkudum",
  1954  	VPKUDUS:        "vpkudus",
  1955  	VPMSUMB:        "vpmsumb",
  1956  	VPMSUMD:        "vpmsumd",
  1957  	VPMSUMH:        "vpmsumh",
  1958  	VPMSUMW:        "vpmsumw",
  1959  	VPOPCNTB:       "vpopcntb",
  1960  	VPOPCNTD:       "vpopcntd",
  1961  	VPOPCNTH:       "vpopcnth",
  1962  	VPOPCNTW:       "vpopcntw",
  1963  	VRLD:           "vrld",
  1964  	VSBOX:          "vsbox",
  1965  	VSHASIGMAD:     "vshasigmad",
  1966  	VSHASIGMAW:     "vshasigmaw",
  1967  	VSLD:           "vsld",
  1968  	VSRAD:          "vsrad",
  1969  	VSRD:           "vsrd",
  1970  	VSUBCUQ:        "vsubcuq",
  1971  	VSUBECUQ:       "vsubecuq",
  1972  	VSUBEUQM:       "vsubeuqm",
  1973  	VSUBUDM:        "vsubudm",
  1974  	VSUBUQM:        "vsubuqm",
  1975  	VUPKHSW:        "vupkhsw",
  1976  	VUPKLSW:        "vupklsw",
  1977  	XSADDSP:        "xsaddsp",
  1978  	XSCVDPSPN:      "xscvdpspn",
  1979  	XSCVSPDPN:      "xscvspdpn",
  1980  	XSCVSXDSP:      "xscvsxdsp",
  1981  	XSCVUXDSP:      "xscvuxdsp",
  1982  	XSDIVSP:        "xsdivsp",
  1983  	XSMADDASP:      "xsmaddasp",
  1984  	XSMADDMSP:      "xsmaddmsp",
  1985  	XSMSUBASP:      "xsmsubasp",
  1986  	XSMSUBMSP:      "xsmsubmsp",
  1987  	XSMULSP:        "xsmulsp",
  1988  	XSNMADDASP:     "xsnmaddasp",
  1989  	XSNMADDMSP:     "xsnmaddmsp",
  1990  	XSNMSUBASP:     "xsnmsubasp",
  1991  	XSNMSUBMSP:     "xsnmsubmsp",
  1992  	XSRESP:         "xsresp",
  1993  	XSRSP:          "xsrsp",
  1994  	XSRSQRTESP:     "xsrsqrtesp",
  1995  	XSSQRTSP:       "xssqrtsp",
  1996  	XSSUBSP:        "xssubsp",
  1997  	XXLEQV:         "xxleqv",
  1998  	XXLNAND:        "xxlnand",
  1999  	XXLORC:         "xxlorc",
  2000  	ADDG6S:         "addg6s",
  2001  	BPERMD:         "bpermd",
  2002  	CBCDTD:         "cbcdtd",
  2003  	CDTBCD:         "cdtbcd",
  2004  	DCFFIX:         "dcffix",
  2005  	DCFFIXCC:       "dcffix.",
  2006  	DIVDE:          "divde",
  2007  	DIVDECC:        "divde.",
  2008  	DIVDEO:         "divdeo",
  2009  	DIVDEOCC:       "divdeo.",
  2010  	DIVDEU:         "divdeu",
  2011  	DIVDEUCC:       "divdeu.",
  2012  	DIVDEUO:        "divdeuo",
  2013  	DIVDEUOCC:      "divdeuo.",
  2014  	DIVWE:          "divwe",
  2015  	DIVWECC:        "divwe.",
  2016  	DIVWEO:         "divweo",
  2017  	DIVWEOCC:       "divweo.",
  2018  	DIVWEU:         "divweu",
  2019  	DIVWEUCC:       "divweu.",
  2020  	DIVWEUO:        "divweuo",
  2021  	DIVWEUOCC:      "divweuo.",
  2022  	FCFIDS:         "fcfids",
  2023  	FCFIDSCC:       "fcfids.",
  2024  	FCFIDU:         "fcfidu",
  2025  	FCFIDUCC:       "fcfidu.",
  2026  	FCFIDUS:        "fcfidus",
  2027  	FCFIDUSCC:      "fcfidus.",
  2028  	FCTIDU:         "fctidu",
  2029  	FCTIDUCC:       "fctidu.",
  2030  	FCTIDUZ:        "fctiduz",
  2031  	FCTIDUZCC:      "fctiduz.",
  2032  	FCTIWU:         "fctiwu",
  2033  	FCTIWUCC:       "fctiwu.",
  2034  	FCTIWUZ:        "fctiwuz",
  2035  	FCTIWUZCC:      "fctiwuz.",
  2036  	FTDIV:          "ftdiv",
  2037  	FTSQRT:         "ftsqrt",
  2038  	LBARX:          "lbarx",
  2039  	LDBRX:          "ldbrx",
  2040  	LFIWZX:         "lfiwzx",
  2041  	LHARX:          "lharx",
  2042  	LXSDX:          "lxsdx",
  2043  	LXVD2X:         "lxvd2x",
  2044  	LXVDSX:         "lxvdsx",
  2045  	LXVW4X:         "lxvw4x",
  2046  	POPCNTD:        "popcntd",
  2047  	POPCNTW:        "popcntw",
  2048  	STBCXCC:        "stbcx.",
  2049  	STDBRX:         "stdbrx",
  2050  	STHCXCC:        "sthcx.",
  2051  	STXSDX:         "stxsdx",
  2052  	STXVD2X:        "stxvd2x",
  2053  	STXVW4X:        "stxvw4x",
  2054  	XSABSDP:        "xsabsdp",
  2055  	XSADDDP:        "xsadddp",
  2056  	XSCMPODP:       "xscmpodp",
  2057  	XSCMPUDP:       "xscmpudp",
  2058  	XSCPSGNDP:      "xscpsgndp",
  2059  	XSCVDPSP:       "xscvdpsp",
  2060  	XSCVDPSXDS:     "xscvdpsxds",
  2061  	XSCVDPSXWS:     "xscvdpsxws",
  2062  	XSCVDPUXDS:     "xscvdpuxds",
  2063  	XSCVDPUXWS:     "xscvdpuxws",
  2064  	XSCVSPDP:       "xscvspdp",
  2065  	XSCVSXDDP:      "xscvsxddp",
  2066  	XSCVUXDDP:      "xscvuxddp",
  2067  	XSDIVDP:        "xsdivdp",
  2068  	XSMADDADP:      "xsmaddadp",
  2069  	XSMADDMDP:      "xsmaddmdp",
  2070  	XSMAXDP:        "xsmaxdp",
  2071  	XSMINDP:        "xsmindp",
  2072  	XSMSUBADP:      "xsmsubadp",
  2073  	XSMSUBMDP:      "xsmsubmdp",
  2074  	XSMULDP:        "xsmuldp",
  2075  	XSNABSDP:       "xsnabsdp",
  2076  	XSNEGDP:        "xsnegdp",
  2077  	XSNMADDADP:     "xsnmaddadp",
  2078  	XSNMADDMDP:     "xsnmaddmdp",
  2079  	XSNMSUBADP:     "xsnmsubadp",
  2080  	XSNMSUBMDP:     "xsnmsubmdp",
  2081  	XSRDPI:         "xsrdpi",
  2082  	XSRDPIC:        "xsrdpic",
  2083  	XSRDPIM:        "xsrdpim",
  2084  	XSRDPIP:        "xsrdpip",
  2085  	XSRDPIZ:        "xsrdpiz",
  2086  	XSREDP:         "xsredp",
  2087  	XSRSQRTEDP:     "xsrsqrtedp",
  2088  	XSSQRTDP:       "xssqrtdp",
  2089  	XSSUBDP:        "xssubdp",
  2090  	XSTDIVDP:       "xstdivdp",
  2091  	XSTSQRTDP:      "xstsqrtdp",
  2092  	XVABSDP:        "xvabsdp",
  2093  	XVABSSP:        "xvabssp",
  2094  	XVADDDP:        "xvadddp",
  2095  	XVADDSP:        "xvaddsp",
  2096  	XVCMPEQDP:      "xvcmpeqdp",
  2097  	XVCMPEQDPCC:    "xvcmpeqdp.",
  2098  	XVCMPEQSP:      "xvcmpeqsp",
  2099  	XVCMPEQSPCC:    "xvcmpeqsp.",
  2100  	XVCMPGEDP:      "xvcmpgedp",
  2101  	XVCMPGEDPCC:    "xvcmpgedp.",
  2102  	XVCMPGESP:      "xvcmpgesp",
  2103  	XVCMPGESPCC:    "xvcmpgesp.",
  2104  	XVCMPGTDP:      "xvcmpgtdp",
  2105  	XVCMPGTDPCC:    "xvcmpgtdp.",
  2106  	XVCMPGTSP:      "xvcmpgtsp",
  2107  	XVCMPGTSPCC:    "xvcmpgtsp.",
  2108  	XVCPSGNDP:      "xvcpsgndp",
  2109  	XVCPSGNSP:      "xvcpsgnsp",
  2110  	XVCVDPSP:       "xvcvdpsp",
  2111  	XVCVDPSXDS:     "xvcvdpsxds",
  2112  	XVCVDPSXWS:     "xvcvdpsxws",
  2113  	XVCVDPUXDS:     "xvcvdpuxds",
  2114  	XVCVDPUXWS:     "xvcvdpuxws",
  2115  	XVCVSPDP:       "xvcvspdp",
  2116  	XVCVSPSXDS:     "xvcvspsxds",
  2117  	XVCVSPSXWS:     "xvcvspsxws",
  2118  	XVCVSPUXDS:     "xvcvspuxds",
  2119  	XVCVSPUXWS:     "xvcvspuxws",
  2120  	XVCVSXDDP:      "xvcvsxddp",
  2121  	XVCVSXDSP:      "xvcvsxdsp",
  2122  	XVCVSXWDP:      "xvcvsxwdp",
  2123  	XVCVSXWSP:      "xvcvsxwsp",
  2124  	XVCVUXDDP:      "xvcvuxddp",
  2125  	XVCVUXDSP:      "xvcvuxdsp",
  2126  	XVCVUXWDP:      "xvcvuxwdp",
  2127  	XVCVUXWSP:      "xvcvuxwsp",
  2128  	XVDIVDP:        "xvdivdp",
  2129  	XVDIVSP:        "xvdivsp",
  2130  	XVMADDADP:      "xvmaddadp",
  2131  	XVMADDASP:      "xvmaddasp",
  2132  	XVMADDMDP:      "xvmaddmdp",
  2133  	XVMADDMSP:      "xvmaddmsp",
  2134  	XVMAXDP:        "xvmaxdp",
  2135  	XVMAXSP:        "xvmaxsp",
  2136  	XVMINDP:        "xvmindp",
  2137  	XVMINSP:        "xvminsp",
  2138  	XVMSUBADP:      "xvmsubadp",
  2139  	XVMSUBASP:      "xvmsubasp",
  2140  	XVMSUBMDP:      "xvmsubmdp",
  2141  	XVMSUBMSP:      "xvmsubmsp",
  2142  	XVMULDP:        "xvmuldp",
  2143  	XVMULSP:        "xvmulsp",
  2144  	XVNABSDP:       "xvnabsdp",
  2145  	XVNABSSP:       "xvnabssp",
  2146  	XVNEGDP:        "xvnegdp",
  2147  	XVNEGSP:        "xvnegsp",
  2148  	XVNMADDADP:     "xvnmaddadp",
  2149  	XVNMADDASP:     "xvnmaddasp",
  2150  	XVNMADDMDP:     "xvnmaddmdp",
  2151  	XVNMADDMSP:     "xvnmaddmsp",
  2152  	XVNMSUBADP:     "xvnmsubadp",
  2153  	XVNMSUBASP:     "xvnmsubasp",
  2154  	XVNMSUBMDP:     "xvnmsubmdp",
  2155  	XVNMSUBMSP:     "xvnmsubmsp",
  2156  	XVRDPI:         "xvrdpi",
  2157  	XVRDPIC:        "xvrdpic",
  2158  	XVRDPIM:        "xvrdpim",
  2159  	XVRDPIP:        "xvrdpip",
  2160  	XVRDPIZ:        "xvrdpiz",
  2161  	XVREDP:         "xvredp",
  2162  	XVRESP:         "xvresp",
  2163  	XVRSPI:         "xvrspi",
  2164  	XVRSPIC:        "xvrspic",
  2165  	XVRSPIM:        "xvrspim",
  2166  	XVRSPIP:        "xvrspip",
  2167  	XVRSPIZ:        "xvrspiz",
  2168  	XVRSQRTEDP:     "xvrsqrtedp",
  2169  	XVRSQRTESP:     "xvrsqrtesp",
  2170  	XVSQRTDP:       "xvsqrtdp",
  2171  	XVSQRTSP:       "xvsqrtsp",
  2172  	XVSUBDP:        "xvsubdp",
  2173  	XVSUBSP:        "xvsubsp",
  2174  	XVTDIVDP:       "xvtdivdp",
  2175  	XVTDIVSP:       "xvtdivsp",
  2176  	XVTSQRTDP:      "xvtsqrtdp",
  2177  	XVTSQRTSP:      "xvtsqrtsp",
  2178  	XXLAND:         "xxland",
  2179  	XXLANDC:        "xxlandc",
  2180  	XXLNOR:         "xxlnor",
  2181  	XXLOR:          "xxlor",
  2182  	XXLXOR:         "xxlxor",
  2183  	XXMRGHW:        "xxmrghw",
  2184  	XXMRGLW:        "xxmrglw",
  2185  	XXPERMDI:       "xxpermdi",
  2186  	XXSEL:          "xxsel",
  2187  	XXSLDWI:        "xxsldwi",
  2188  	XXSPLTW:        "xxspltw",
  2189  	CMPB:           "cmpb",
  2190  	DADD:           "dadd",
  2191  	DADDCC:         "dadd.",
  2192  	DADDQ:          "daddq",
  2193  	DADDQCC:        "daddq.",
  2194  	DCFFIXQ:        "dcffixq",
  2195  	DCFFIXQCC:      "dcffixq.",
  2196  	DCMPO:          "dcmpo",
  2197  	DCMPOQ:         "dcmpoq",
  2198  	DCMPU:          "dcmpu",
  2199  	DCMPUQ:         "dcmpuq",
  2200  	DCTDP:          "dctdp",
  2201  	DCTDPCC:        "dctdp.",
  2202  	DCTFIX:         "dctfix",
  2203  	DCTFIXCC:       "dctfix.",
  2204  	DCTFIXQ:        "dctfixq",
  2205  	DCTFIXQCC:      "dctfixq.",
  2206  	DCTQPQ:         "dctqpq",
  2207  	DCTQPQCC:       "dctqpq.",
  2208  	DDEDPD:         "ddedpd",
  2209  	DDEDPDCC:       "ddedpd.",
  2210  	DDEDPDQ:        "ddedpdq",
  2211  	DDEDPDQCC:      "ddedpdq.",
  2212  	DDIV:           "ddiv",
  2213  	DDIVCC:         "ddiv.",
  2214  	DDIVQ:          "ddivq",
  2215  	DDIVQCC:        "ddivq.",
  2216  	DENBCD:         "denbcd",
  2217  	DENBCDCC:       "denbcd.",
  2218  	DENBCDQ:        "denbcdq",
  2219  	DENBCDQCC:      "denbcdq.",
  2220  	DIEX:           "diex",
  2221  	DIEXCC:         "diex.",
  2222  	DIEXQCC:        "diexq.",
  2223  	DIEXQ:          "diexq",
  2224  	DMUL:           "dmul",
  2225  	DMULCC:         "dmul.",
  2226  	DMULQ:          "dmulq",
  2227  	DMULQCC:        "dmulq.",
  2228  	DQUA:           "dqua",
  2229  	DQUACC:         "dqua.",
  2230  	DQUAI:          "dquai",
  2231  	DQUAICC:        "dquai.",
  2232  	DQUAIQ:         "dquaiq",
  2233  	DQUAIQCC:       "dquaiq.",
  2234  	DQUAQ:          "dquaq",
  2235  	DQUAQCC:        "dquaq.",
  2236  	DRDPQ:          "drdpq",
  2237  	DRDPQCC:        "drdpq.",
  2238  	DRINTN:         "drintn",
  2239  	DRINTNCC:       "drintn.",
  2240  	DRINTNQ:        "drintnq",
  2241  	DRINTNQCC:      "drintnq.",
  2242  	DRINTX:         "drintx",
  2243  	DRINTXCC:       "drintx.",
  2244  	DRINTXQ:        "drintxq",
  2245  	DRINTXQCC:      "drintxq.",
  2246  	DRRND:          "drrnd",
  2247  	DRRNDCC:        "drrnd.",
  2248  	DRRNDQ:         "drrndq",
  2249  	DRRNDQCC:       "drrndq.",
  2250  	DRSP:           "drsp",
  2251  	DRSPCC:         "drsp.",
  2252  	DSCLI:          "dscli",
  2253  	DSCLICC:        "dscli.",
  2254  	DSCLIQ:         "dscliq",
  2255  	DSCLIQCC:       "dscliq.",
  2256  	DSCRI:          "dscri",
  2257  	DSCRICC:        "dscri.",
  2258  	DSCRIQ:         "dscriq",
  2259  	DSCRIQCC:       "dscriq.",
  2260  	DSUB:           "dsub",
  2261  	DSUBCC:         "dsub.",
  2262  	DSUBQ:          "dsubq",
  2263  	DSUBQCC:        "dsubq.",
  2264  	DTSTDC:         "dtstdc",
  2265  	DTSTDCQ:        "dtstdcq",
  2266  	DTSTDG:         "dtstdg",
  2267  	DTSTDGQ:        "dtstdgq",
  2268  	DTSTEX:         "dtstex",
  2269  	DTSTEXQ:        "dtstexq",
  2270  	DTSTSF:         "dtstsf",
  2271  	DTSTSFQ:        "dtstsfq",
  2272  	DXEX:           "dxex",
  2273  	DXEXCC:         "dxex.",
  2274  	DXEXQ:          "dxexq",
  2275  	DXEXQCC:        "dxexq.",
  2276  	FCPSGN:         "fcpsgn",
  2277  	FCPSGNCC:       "fcpsgn.",
  2278  	LBZCIX:         "lbzcix",
  2279  	LDCIX:          "ldcix",
  2280  	LFDP:           "lfdp",
  2281  	LFDPX:          "lfdpx",
  2282  	LFIWAX:         "lfiwax",
  2283  	LHZCIX:         "lhzcix",
  2284  	LWZCIX:         "lwzcix",
  2285  	PRTYD:          "prtyd",
  2286  	PRTYW:          "prtyw",
  2287  	SLBFEECC:       "slbfee.",
  2288  	STBCIX:         "stbcix",
  2289  	STDCIX:         "stdcix",
  2290  	STFDP:          "stfdp",
  2291  	STFDPX:         "stfdpx",
  2292  	STHCIX:         "sthcix",
  2293  	STWCIX:         "stwcix",
  2294  	ISEL:           "isel",
  2295  	LVEBX:          "lvebx",
  2296  	LVEHX:          "lvehx",
  2297  	LVEWX:          "lvewx",
  2298  	LVSL:           "lvsl",
  2299  	LVSR:           "lvsr",
  2300  	LVX:            "lvx",
  2301  	LVXL:           "lvxl",
  2302  	MFVSCR:         "mfvscr",
  2303  	MTVSCR:         "mtvscr",
  2304  	STVEBX:         "stvebx",
  2305  	STVEHX:         "stvehx",
  2306  	STVEWX:         "stvewx",
  2307  	STVX:           "stvx",
  2308  	STVXL:          "stvxl",
  2309  	TLBIEL:         "tlbiel",
  2310  	VADDCUW:        "vaddcuw",
  2311  	VADDFP:         "vaddfp",
  2312  	VADDSBS:        "vaddsbs",
  2313  	VADDSHS:        "vaddshs",
  2314  	VADDSWS:        "vaddsws",
  2315  	VADDUBM:        "vaddubm",
  2316  	VADDUBS:        "vaddubs",
  2317  	VADDUHM:        "vadduhm",
  2318  	VADDUHS:        "vadduhs",
  2319  	VADDUWM:        "vadduwm",
  2320  	VADDUWS:        "vadduws",
  2321  	VAND:           "vand",
  2322  	VANDC:          "vandc",
  2323  	VAVGSB:         "vavgsb",
  2324  	VAVGSH:         "vavgsh",
  2325  	VAVGSW:         "vavgsw",
  2326  	VAVGUB:         "vavgub",
  2327  	VAVGUH:         "vavguh",
  2328  	VAVGUW:         "vavguw",
  2329  	VCFSX:          "vcfsx",
  2330  	VCFUX:          "vcfux",
  2331  	VCMPBFP:        "vcmpbfp",
  2332  	VCMPBFPCC:      "vcmpbfp.",
  2333  	VCMPEQFP:       "vcmpeqfp",
  2334  	VCMPEQFPCC:     "vcmpeqfp.",
  2335  	VCMPEQUB:       "vcmpequb",
  2336  	VCMPEQUBCC:     "vcmpequb.",
  2337  	VCMPEQUH:       "vcmpequh",
  2338  	VCMPEQUHCC:     "vcmpequh.",
  2339  	VCMPEQUW:       "vcmpequw",
  2340  	VCMPEQUWCC:     "vcmpequw.",
  2341  	VCMPGEFP:       "vcmpgefp",
  2342  	VCMPGEFPCC:     "vcmpgefp.",
  2343  	VCMPGTFP:       "vcmpgtfp",
  2344  	VCMPGTFPCC:     "vcmpgtfp.",
  2345  	VCMPGTSB:       "vcmpgtsb",
  2346  	VCMPGTSBCC:     "vcmpgtsb.",
  2347  	VCMPGTSH:       "vcmpgtsh",
  2348  	VCMPGTSHCC:     "vcmpgtsh.",
  2349  	VCMPGTSW:       "vcmpgtsw",
  2350  	VCMPGTSWCC:     "vcmpgtsw.",
  2351  	VCMPGTUB:       "vcmpgtub",
  2352  	VCMPGTUBCC:     "vcmpgtub.",
  2353  	VCMPGTUH:       "vcmpgtuh",
  2354  	VCMPGTUHCC:     "vcmpgtuh.",
  2355  	VCMPGTUW:       "vcmpgtuw",
  2356  	VCMPGTUWCC:     "vcmpgtuw.",
  2357  	VCTSXS:         "vctsxs",
  2358  	VCTUXS:         "vctuxs",
  2359  	VEXPTEFP:       "vexptefp",
  2360  	VLOGEFP:        "vlogefp",
  2361  	VMADDFP:        "vmaddfp",
  2362  	VMAXFP:         "vmaxfp",
  2363  	VMAXSB:         "vmaxsb",
  2364  	VMAXSH:         "vmaxsh",
  2365  	VMAXSW:         "vmaxsw",
  2366  	VMAXUB:         "vmaxub",
  2367  	VMAXUH:         "vmaxuh",
  2368  	VMAXUW:         "vmaxuw",
  2369  	VMHADDSHS:      "vmhaddshs",
  2370  	VMHRADDSHS:     "vmhraddshs",
  2371  	VMINFP:         "vminfp",
  2372  	VMINSB:         "vminsb",
  2373  	VMINSH:         "vminsh",
  2374  	VMINSW:         "vminsw",
  2375  	VMINUB:         "vminub",
  2376  	VMINUH:         "vminuh",
  2377  	VMINUW:         "vminuw",
  2378  	VMLADDUHM:      "vmladduhm",
  2379  	VMRGHB:         "vmrghb",
  2380  	VMRGHH:         "vmrghh",
  2381  	VMRGHW:         "vmrghw",
  2382  	VMRGLB:         "vmrglb",
  2383  	VMRGLH:         "vmrglh",
  2384  	VMRGLW:         "vmrglw",
  2385  	VMSUMMBM:       "vmsummbm",
  2386  	VMSUMSHM:       "vmsumshm",
  2387  	VMSUMSHS:       "vmsumshs",
  2388  	VMSUMUBM:       "vmsumubm",
  2389  	VMSUMUHM:       "vmsumuhm",
  2390  	VMSUMUHS:       "vmsumuhs",
  2391  	VMULESB:        "vmulesb",
  2392  	VMULESH:        "vmulesh",
  2393  	VMULEUB:        "vmuleub",
  2394  	VMULEUH:        "vmuleuh",
  2395  	VMULOSB:        "vmulosb",
  2396  	VMULOSH:        "vmulosh",
  2397  	VMULOUB:        "vmuloub",
  2398  	VMULOUH:        "vmulouh",
  2399  	VNMSUBFP:       "vnmsubfp",
  2400  	VNOR:           "vnor",
  2401  	VOR:            "vor",
  2402  	VPERM:          "vperm",
  2403  	VPKPX:          "vpkpx",
  2404  	VPKSHSS:        "vpkshss",
  2405  	VPKSHUS:        "vpkshus",
  2406  	VPKSWSS:        "vpkswss",
  2407  	VPKSWUS:        "vpkswus",
  2408  	VPKUHUM:        "vpkuhum",
  2409  	VPKUHUS:        "vpkuhus",
  2410  	VPKUWUM:        "vpkuwum",
  2411  	VPKUWUS:        "vpkuwus",
  2412  	VREFP:          "vrefp",
  2413  	VRFIM:          "vrfim",
  2414  	VRFIN:          "vrfin",
  2415  	VRFIP:          "vrfip",
  2416  	VRFIZ:          "vrfiz",
  2417  	VRLB:           "vrlb",
  2418  	VRLH:           "vrlh",
  2419  	VRLW:           "vrlw",
  2420  	VRSQRTEFP:      "vrsqrtefp",
  2421  	VSEL:           "vsel",
  2422  	VSL:            "vsl",
  2423  	VSLB:           "vslb",
  2424  	VSLDOI:         "vsldoi",
  2425  	VSLH:           "vslh",
  2426  	VSLO:           "vslo",
  2427  	VSLW:           "vslw",
  2428  	VSPLTB:         "vspltb",
  2429  	VSPLTH:         "vsplth",
  2430  	VSPLTISB:       "vspltisb",
  2431  	VSPLTISH:       "vspltish",
  2432  	VSPLTISW:       "vspltisw",
  2433  	VSPLTW:         "vspltw",
  2434  	VSR:            "vsr",
  2435  	VSRAB:          "vsrab",
  2436  	VSRAH:          "vsrah",
  2437  	VSRAW:          "vsraw",
  2438  	VSRB:           "vsrb",
  2439  	VSRH:           "vsrh",
  2440  	VSRO:           "vsro",
  2441  	VSRW:           "vsrw",
  2442  	VSUBCUW:        "vsubcuw",
  2443  	VSUBFP:         "vsubfp",
  2444  	VSUBSBS:        "vsubsbs",
  2445  	VSUBSHS:        "vsubshs",
  2446  	VSUBSWS:        "vsubsws",
  2447  	VSUBUBM:        "vsububm",
  2448  	VSUBUBS:        "vsububs",
  2449  	VSUBUHM:        "vsubuhm",
  2450  	VSUBUHS:        "vsubuhs",
  2451  	VSUBUWM:        "vsubuwm",
  2452  	VSUBUWS:        "vsubuws",
  2453  	VSUM2SWS:       "vsum2sws",
  2454  	VSUM4SBS:       "vsum4sbs",
  2455  	VSUM4SHS:       "vsum4shs",
  2456  	VSUM4UBS:       "vsum4ubs",
  2457  	VSUMSWS:        "vsumsws",
  2458  	VUPKHPX:        "vupkhpx",
  2459  	VUPKHSB:        "vupkhsb",
  2460  	VUPKHSH:        "vupkhsh",
  2461  	VUPKLPX:        "vupklpx",
  2462  	VUPKLSB:        "vupklsb",
  2463  	VUPKLSH:        "vupklsh",
  2464  	VXOR:           "vxor",
  2465  	FRE:            "fre",
  2466  	FRECC:          "fre.",
  2467  	FRIM:           "frim",
  2468  	FRIMCC:         "frim.",
  2469  	FRIN:           "frin",
  2470  	FRINCC:         "frin.",
  2471  	FRIP:           "frip",
  2472  	FRIPCC:         "frip.",
  2473  	FRIZ:           "friz",
  2474  	FRIZCC:         "friz.",
  2475  	FRSQRTES:       "frsqrtes",
  2476  	FRSQRTESCC:     "frsqrtes.",
  2477  	HRFID:          "hrfid",
  2478  	POPCNTB:        "popcntb",
  2479  	MFOCRF:         "mfocrf",
  2480  	MTOCRF:         "mtocrf",
  2481  	SLBMFEE:        "slbmfee",
  2482  	SLBMFEV:        "slbmfev",
  2483  	SLBMTE:         "slbmte",
  2484  	RFSCV:          "rfscv",
  2485  	SCV:            "scv",
  2486  	LQ:             "lq",
  2487  	STQ:            "stq",
  2488  	CNTLZD:         "cntlzd",
  2489  	CNTLZDCC:       "cntlzd.",
  2490  	DCBF:           "dcbf",
  2491  	DCBST:          "dcbst",
  2492  	DCBT:           "dcbt",
  2493  	DCBTST:         "dcbtst",
  2494  	DIVD:           "divd",
  2495  	DIVDCC:         "divd.",
  2496  	DIVDO:          "divdo",
  2497  	DIVDOCC:        "divdo.",
  2498  	DIVDU:          "divdu",
  2499  	DIVDUCC:        "divdu.",
  2500  	DIVDUO:         "divduo",
  2501  	DIVDUOCC:       "divduo.",
  2502  	DIVW:           "divw",
  2503  	DIVWCC:         "divw.",
  2504  	DIVWO:          "divwo",
  2505  	DIVWOCC:        "divwo.",
  2506  	DIVWU:          "divwu",
  2507  	DIVWUCC:        "divwu.",
  2508  	DIVWUO:         "divwuo",
  2509  	DIVWUOCC:       "divwuo.",
  2510  	EIEIO:          "eieio",
  2511  	EXTSB:          "extsb",
  2512  	EXTSBCC:        "extsb.",
  2513  	EXTSW:          "extsw",
  2514  	EXTSWCC:        "extsw.",
  2515  	FADDS:          "fadds",
  2516  	FADDSCC:        "fadds.",
  2517  	FCFID:          "fcfid",
  2518  	FCFIDCC:        "fcfid.",
  2519  	FCTID:          "fctid",
  2520  	FCTIDCC:        "fctid.",
  2521  	FCTIDZ:         "fctidz",
  2522  	FCTIDZCC:       "fctidz.",
  2523  	FDIVS:          "fdivs",
  2524  	FDIVSCC:        "fdivs.",
  2525  	FMADDS:         "fmadds",
  2526  	FMADDSCC:       "fmadds.",
  2527  	FMSUBS:         "fmsubs",
  2528  	FMSUBSCC:       "fmsubs.",
  2529  	FMULS:          "fmuls",
  2530  	FMULSCC:        "fmuls.",
  2531  	FNMADDS:        "fnmadds",
  2532  	FNMADDSCC:      "fnmadds.",
  2533  	FNMSUBS:        "fnmsubs",
  2534  	FNMSUBSCC:      "fnmsubs.",
  2535  	FRES:           "fres",
  2536  	FRESCC:         "fres.",
  2537  	FRSQRTE:        "frsqrte",
  2538  	FRSQRTECC:      "frsqrte.",
  2539  	FSEL:           "fsel",
  2540  	FSELCC:         "fsel.",
  2541  	FSQRTS:         "fsqrts",
  2542  	FSQRTSCC:       "fsqrts.",
  2543  	FSUBS:          "fsubs",
  2544  	FSUBSCC:        "fsubs.",
  2545  	ICBI:           "icbi",
  2546  	LD:             "ld",
  2547  	LDARX:          "ldarx",
  2548  	LDU:            "ldu",
  2549  	LDUX:           "ldux",
  2550  	LDX:            "ldx",
  2551  	LWA:            "lwa",
  2552  	LWARX:          "lwarx",
  2553  	LWAUX:          "lwaux",
  2554  	LWAX:           "lwax",
  2555  	MFTB:           "mftb",
  2556  	MTMSRD:         "mtmsrd",
  2557  	MULHD:          "mulhd",
  2558  	MULHDCC:        "mulhd.",
  2559  	MULHDU:         "mulhdu",
  2560  	MULHDUCC:       "mulhdu.",
  2561  	MULHW:          "mulhw",
  2562  	MULHWCC:        "mulhw.",
  2563  	MULHWU:         "mulhwu",
  2564  	MULHWUCC:       "mulhwu.",
  2565  	MULLD:          "mulld",
  2566  	MULLDCC:        "mulld.",
  2567  	MULLDO:         "mulldo",
  2568  	MULLDOCC:       "mulldo.",
  2569  	RFID:           "rfid",
  2570  	RLDCL:          "rldcl",
  2571  	RLDCLCC:        "rldcl.",
  2572  	RLDCR:          "rldcr",
  2573  	RLDCRCC:        "rldcr.",
  2574  	RLDIC:          "rldic",
  2575  	RLDICCC:        "rldic.",
  2576  	RLDICL:         "rldicl",
  2577  	RLDICLCC:       "rldicl.",
  2578  	RLDICR:         "rldicr",
  2579  	RLDICRCC:       "rldicr.",
  2580  	RLDIMI:         "rldimi",
  2581  	RLDIMICC:       "rldimi.",
  2582  	SC:             "sc",
  2583  	SLBIA:          "slbia",
  2584  	SLBIE:          "slbie",
  2585  	SLD:            "sld",
  2586  	SLDCC:          "sld.",
  2587  	SRAD:           "srad",
  2588  	SRADCC:         "srad.",
  2589  	SRADI:          "sradi",
  2590  	SRADICC:        "sradi.",
  2591  	SRD:            "srd",
  2592  	SRDCC:          "srd.",
  2593  	STD:            "std",
  2594  	STDCXCC:        "stdcx.",
  2595  	STDU:           "stdu",
  2596  	STDUX:          "stdux",
  2597  	STDX:           "stdx",
  2598  	STFIWX:         "stfiwx",
  2599  	STWCXCC:        "stwcx.",
  2600  	SUBF:           "subf",
  2601  	SUBFCC:         "subf.",
  2602  	SUBFO:          "subfo",
  2603  	SUBFOCC:        "subfo.",
  2604  	TD:             "td",
  2605  	TDI:            "tdi",
  2606  	TLBSYNC:        "tlbsync",
  2607  	FCTIW:          "fctiw",
  2608  	FCTIWCC:        "fctiw.",
  2609  	FCTIWZ:         "fctiwz",
  2610  	FCTIWZCC:       "fctiwz.",
  2611  	FSQRT:          "fsqrt",
  2612  	FSQRTCC:        "fsqrt.",
  2613  	ADD:            "add",
  2614  	ADDCC:          "add.",
  2615  	ADDO:           "addo",
  2616  	ADDOCC:         "addo.",
  2617  	ADDC:           "addc",
  2618  	ADDCCC:         "addc.",
  2619  	ADDCO:          "addco",
  2620  	ADDCOCC:        "addco.",
  2621  	ADDE:           "adde",
  2622  	ADDECC:         "adde.",
  2623  	ADDEO:          "addeo",
  2624  	ADDEOCC:        "addeo.",
  2625  	LI:             "li",
  2626  	ADDI:           "addi",
  2627  	ADDIC:          "addic",
  2628  	ADDICCC:        "addic.",
  2629  	LIS:            "lis",
  2630  	ADDIS:          "addis",
  2631  	ADDME:          "addme",
  2632  	ADDMECC:        "addme.",
  2633  	ADDMEO:         "addmeo",
  2634  	ADDMEOCC:       "addmeo.",
  2635  	ADDZE:          "addze",
  2636  	ADDZECC:        "addze.",
  2637  	ADDZEO:         "addzeo",
  2638  	ADDZEOCC:       "addzeo.",
  2639  	AND:            "and",
  2640  	ANDCC:          "and.",
  2641  	ANDC:           "andc",
  2642  	ANDCCC:         "andc.",
  2643  	ANDICC:         "andi.",
  2644  	ANDISCC:        "andis.",
  2645  	B:              "b",
  2646  	BA:             "ba",
  2647  	BL:             "bl",
  2648  	BLA:            "bla",
  2649  	BC:             "bc",
  2650  	BCA:            "bca",
  2651  	BCL:            "bcl",
  2652  	BCLA:           "bcla",
  2653  	BCCTR:          "bcctr",
  2654  	BCCTRL:         "bcctrl",
  2655  	BCLR:           "bclr",
  2656  	BCLRL:          "bclrl",
  2657  	CMPW:           "cmpw",
  2658  	CMPD:           "cmpd",
  2659  	CMP:            "cmp",
  2660  	CMPWI:          "cmpwi",
  2661  	CMPDI:          "cmpdi",
  2662  	CMPI:           "cmpi",
  2663  	CMPLW:          "cmplw",
  2664  	CMPLD:          "cmpld",
  2665  	CMPL:           "cmpl",
  2666  	CMPLWI:         "cmplwi",
  2667  	CMPLDI:         "cmpldi",
  2668  	CMPLI:          "cmpli",
  2669  	CNTLZW:         "cntlzw",
  2670  	CNTLZWCC:       "cntlzw.",
  2671  	CRAND:          "crand",
  2672  	CRANDC:         "crandc",
  2673  	CREQV:          "creqv",
  2674  	CRNAND:         "crnand",
  2675  	CRNOR:          "crnor",
  2676  	CROR:           "cror",
  2677  	CRORC:          "crorc",
  2678  	CRXOR:          "crxor",
  2679  	DCBZ:           "dcbz",
  2680  	EQV:            "eqv",
  2681  	EQVCC:          "eqv.",
  2682  	EXTSH:          "extsh",
  2683  	EXTSHCC:        "extsh.",
  2684  	FABS:           "fabs",
  2685  	FABSCC:         "fabs.",
  2686  	FADD:           "fadd",
  2687  	FADDCC:         "fadd.",
  2688  	FCMPO:          "fcmpo",
  2689  	FCMPU:          "fcmpu",
  2690  	FDIV:           "fdiv",
  2691  	FDIVCC:         "fdiv.",
  2692  	FMADD:          "fmadd",
  2693  	FMADDCC:        "fmadd.",
  2694  	FMR:            "fmr",
  2695  	FMRCC:          "fmr.",
  2696  	FMSUB:          "fmsub",
  2697  	FMSUBCC:        "fmsub.",
  2698  	FMUL:           "fmul",
  2699  	FMULCC:         "fmul.",
  2700  	FNABS:          "fnabs",
  2701  	FNABSCC:        "fnabs.",
  2702  	FNEG:           "fneg",
  2703  	FNEGCC:         "fneg.",
  2704  	FNMADD:         "fnmadd",
  2705  	FNMADDCC:       "fnmadd.",
  2706  	FNMSUB:         "fnmsub",
  2707  	FNMSUBCC:       "fnmsub.",
  2708  	FRSP:           "frsp",
  2709  	FRSPCC:         "frsp.",
  2710  	FSUB:           "fsub",
  2711  	FSUBCC:         "fsub.",
  2712  	ISYNC:          "isync",
  2713  	LBZ:            "lbz",
  2714  	LBZU:           "lbzu",
  2715  	LBZUX:          "lbzux",
  2716  	LBZX:           "lbzx",
  2717  	LFD:            "lfd",
  2718  	LFDU:           "lfdu",
  2719  	LFDUX:          "lfdux",
  2720  	LFDX:           "lfdx",
  2721  	LFS:            "lfs",
  2722  	LFSU:           "lfsu",
  2723  	LFSUX:          "lfsux",
  2724  	LFSX:           "lfsx",
  2725  	LHA:            "lha",
  2726  	LHAU:           "lhau",
  2727  	LHAUX:          "lhaux",
  2728  	LHAX:           "lhax",
  2729  	LHBRX:          "lhbrx",
  2730  	LHZ:            "lhz",
  2731  	LHZU:           "lhzu",
  2732  	LHZUX:          "lhzux",
  2733  	LHZX:           "lhzx",
  2734  	LMW:            "lmw",
  2735  	LSWI:           "lswi",
  2736  	LSWX:           "lswx",
  2737  	LWBRX:          "lwbrx",
  2738  	LWZ:            "lwz",
  2739  	LWZU:           "lwzu",
  2740  	LWZUX:          "lwzux",
  2741  	LWZX:           "lwzx",
  2742  	MCRF:           "mcrf",
  2743  	MCRFS:          "mcrfs",
  2744  	MFCR:           "mfcr",
  2745  	MFFS:           "mffs",
  2746  	MFFSCC:         "mffs.",
  2747  	MFMSR:          "mfmsr",
  2748  	MFSPR:          "mfspr",
  2749  	MTCRF:          "mtcrf",
  2750  	MTFSB0:         "mtfsb0",
  2751  	MTFSB0CC:       "mtfsb0.",
  2752  	MTFSB1:         "mtfsb1",
  2753  	MTFSB1CC:       "mtfsb1.",
  2754  	MTFSF:          "mtfsf",
  2755  	MTFSFCC:        "mtfsf.",
  2756  	MTFSFI:         "mtfsfi",
  2757  	MTFSFICC:       "mtfsfi.",
  2758  	MTMSR:          "mtmsr",
  2759  	MTSPR:          "mtspr",
  2760  	MULLI:          "mulli",
  2761  	MULLW:          "mullw",
  2762  	MULLWCC:        "mullw.",
  2763  	MULLWO:         "mullwo",
  2764  	MULLWOCC:       "mullwo.",
  2765  	NAND:           "nand",
  2766  	NANDCC:         "nand.",
  2767  	NEG:            "neg",
  2768  	NEGCC:          "neg.",
  2769  	NEGO:           "nego",
  2770  	NEGOCC:         "nego.",
  2771  	NOR:            "nor",
  2772  	NORCC:          "nor.",
  2773  	OR:             "or",
  2774  	ORCC:           "or.",
  2775  	ORC:            "orc",
  2776  	ORCCC:          "orc.",
  2777  	NOP:            "nop",
  2778  	ORI:            "ori",
  2779  	ORIS:           "oris",
  2780  	RLWIMI:         "rlwimi",
  2781  	RLWIMICC:       "rlwimi.",
  2782  	RLWINM:         "rlwinm",
  2783  	RLWINMCC:       "rlwinm.",
  2784  	RLWNM:          "rlwnm",
  2785  	RLWNMCC:        "rlwnm.",
  2786  	SLW:            "slw",
  2787  	SLWCC:          "slw.",
  2788  	SRAW:           "sraw",
  2789  	SRAWCC:         "sraw.",
  2790  	SRAWI:          "srawi",
  2791  	SRAWICC:        "srawi.",
  2792  	SRW:            "srw",
  2793  	SRWCC:          "srw.",
  2794  	STB:            "stb",
  2795  	STBU:           "stbu",
  2796  	STBUX:          "stbux",
  2797  	STBX:           "stbx",
  2798  	STFD:           "stfd",
  2799  	STFDU:          "stfdu",
  2800  	STFDUX:         "stfdux",
  2801  	STFDX:          "stfdx",
  2802  	STFS:           "stfs",
  2803  	STFSU:          "stfsu",
  2804  	STFSUX:         "stfsux",
  2805  	STFSX:          "stfsx",
  2806  	STH:            "sth",
  2807  	STHBRX:         "sthbrx",
  2808  	STHU:           "sthu",
  2809  	STHUX:          "sthux",
  2810  	STHX:           "sthx",
  2811  	STMW:           "stmw",
  2812  	STSWI:          "stswi",
  2813  	STSWX:          "stswx",
  2814  	STW:            "stw",
  2815  	STWBRX:         "stwbrx",
  2816  	STWU:           "stwu",
  2817  	STWUX:          "stwux",
  2818  	STWX:           "stwx",
  2819  	SUBFC:          "subfc",
  2820  	SUBFCCC:        "subfc.",
  2821  	SUBFCO:         "subfco",
  2822  	SUBFCOCC:       "subfco.",
  2823  	SUBFE:          "subfe",
  2824  	SUBFECC:        "subfe.",
  2825  	SUBFEO:         "subfeo",
  2826  	SUBFEOCC:       "subfeo.",
  2827  	SUBFIC:         "subfic",
  2828  	SUBFME:         "subfme",
  2829  	SUBFMECC:       "subfme.",
  2830  	SUBFMEO:        "subfmeo",
  2831  	SUBFMEOCC:      "subfmeo.",
  2832  	SUBFZE:         "subfze",
  2833  	SUBFZECC:       "subfze.",
  2834  	SUBFZEO:        "subfzeo",
  2835  	SUBFZEOCC:      "subfzeo.",
  2836  	SYNC:           "sync",
  2837  	TLBIE:          "tlbie",
  2838  	TW:             "tw",
  2839  	TWI:            "twi",
  2840  	XOR:            "xor",
  2841  	XORCC:          "xor.",
  2842  	XORI:           "xori",
  2843  	XORIS:          "xoris",
  2844  }
  2845  
  2846  var (
  2847  	ap_Reg_16_20                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
  2848  	ap_NegOffset_31_31_6_10_shift3   = &argField{Type: TypeNegOffset, Shift: 3, BitFields: BitFields{{31, 1, 0}, {6, 5, 0}}}
  2849  	ap_Reg_11_15                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
  2850  	ap_Reg_6_10                      = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
  2851  	ap_FPReg_6_10                    = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
  2852  	ap_VecReg_16_20                  = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
  2853  	ap_VecReg_6_10                   = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
  2854  	ap_FPReg_16_20                   = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
  2855  	ap_VecSReg_31_31_6_10            = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1, 0}, {6, 5, 0}}}
  2856  	ap_ImmUnsigned_16_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
  2857  	ap_VecSpReg_10_10_6_9            = &argField{Type: TypeVecSpReg, Shift: 0, BitFields: BitFields{{10, 1, 0}, {6, 4, 0}}}
  2858  	ap_Offset_16_27_shift4           = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12, 0}}}
  2859  	ap_ImmUnsigned_16_25_11_15_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 10, 0}, {11, 5, 0}, {31, 1, 0}}}
  2860  	ap_Reg_38_42                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}}
  2861  	ap_Reg_43_47                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5, 1}}}
  2862  	ap_ImmSigned_14_31_48_63         = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{14, 18, 0}, {16, 16, 1}}}
  2863  	ap_ImmUnsigned_11_11             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1, 0}}}
  2864  	ap_Offset_14_31_48_63            = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{14, 18, 0}, {16, 16, 1}}}
  2865  	ap_FPReg_38_42                   = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}}
  2866  	ap_VecReg_38_42                  = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}}
  2867  	ap_VecSReg_37_37_38_42           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{5, 1, 1}, {6, 5, 1}}}
  2868  	ap_VecSpReg_42_42_38_41          = &argField{Type: TypeVecSpReg, Shift: 0, BitFields: BitFields{{10, 1, 1}, {6, 4, 1}}}
  2869  	ap_MMAReg_38_40                  = &argField{Type: TypeMMAReg, Shift: 0, BitFields: BitFields{{6, 3, 1}}}
  2870  	ap_VecSReg_61_61_43_47           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1, 1}, {11, 5, 1}}}
  2871  	ap_VecSReg_62_62_48_52           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1, 1}, {16, 5, 1}}}
  2872  	ap_ImmUnsigned_24_27             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{24, 4, 0}}}
  2873  	ap_ImmUnsigned_28_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{28, 4, 0}}}
  2874  	ap_ImmUnsigned_16_17             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 2, 0}}}
  2875  	ap_ImmUnsigned_28_29             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{28, 2, 0}}}
  2876  	ap_ImmUnsigned_16_23             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 8, 0}}}
  2877  	ap_ImmUnsigned_16_19             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4, 0}}}
  2878  	ap_CondRegBit_11_15              = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
  2879  	ap_VecReg_11_15                  = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
  2880  	ap_CondRegField_6_8              = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3, 0}}}
  2881  	ap_ImmUnsigned_15_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1, 0}}}
  2882  	ap_Reg_21_25                     = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
  2883  	ap_ImmUnsigned_13_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3, 0}}}
  2884  	ap_ImmUnsigned_12_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4, 0}}}
  2885  	ap_VecReg_21_25                  = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
  2886  	ap_ImmUnsigned_23_25             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{23, 3, 0}}}
  2887  	ap_MMAReg_6_8                    = &argField{Type: TypeMMAReg, Shift: 0, BitFields: BitFields{{6, 3, 0}}}
  2888  	ap_VecSReg_29_29_11_15           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1, 0}, {11, 5, 0}}}
  2889  	ap_VecSReg_30_30_16_20           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1, 0}, {16, 5, 0}}}
  2890  	ap_VecSReg_63_63_38_42           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1, 1}, {6, 5, 1}}}
  2891  	ap_VecSReg_60_60_53_57           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 1}, {21, 5, 1}}}
  2892  	ap_ImmUnsigned_24_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{24, 8, 0}}}
  2893  	ap_ImmUnsigned_11_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
  2894  	ap_ImmUnsigned_29_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{29, 3, 0}}}
  2895  	ap_VecSReg_47_47_38_42           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{15, 1, 1}, {6, 5, 1}}}
  2896  	ap_ImmUnsigned_46_46             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 1, 1}}}
  2897  	ap_ImmUnsigned_16_31_48_63       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16, 0}, {16, 16, 1}}}
  2898  	ap_ImmUnsigned_21_22             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2, 0}}}
  2899  	ap_ImmUnsigned_18_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{18, 3, 0}}}
  2900  	ap_ImmUnsigned_19_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2, 0}}}
  2901  	ap_ImmSigned_16_25_11_15_31_31   = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 10, 0}, {11, 5, 0}, {31, 1, 0}}}
  2902  	ap_ImmUnsigned_22_22             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1, 0}}}
  2903  	ap_ImmUnsigned_10_10             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1, 0}}}
  2904  	ap_ImmUnsigned_14_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2, 0}}}
  2905  	ap_ImmUnsigned_10_15             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 6, 0}}}
  2906  	ap_ImmUnsigned_30_30_16_20       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1, 0}, {16, 5, 0}}}
  2907  	ap_Offset_16_29_shift2           = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14, 0}}}
  2908  	ap_VecSReg_28_28_6_10            = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 0}, {6, 5, 0}}}
  2909  	ap_CondRegField_11_13            = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3, 0}}}
  2910  	ap_ImmUnsigned_9_10              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2, 0}}}
  2911  	ap_ImmUnsigned_9_15              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 7, 0}}}
  2912  	ap_ImmUnsigned_25_25_29_29_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{25, 1, 0}, {29, 1, 0}, {11, 5, 0}}}
  2913  	ap_ImmUnsigned_13_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 8, 0}}}
  2914  	ap_ImmUnsigned_6_10              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
  2915  	ap_FPReg_11_15                   = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
  2916  	ap_ImmUnsigned_7_10              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4, 0}}}
  2917  	ap_ImmUnsigned_31_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1, 0}}}
  2918  	ap_ImmUnsigned_11_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10, 0}}}
  2919  	ap_ImmUnsigned_20_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1, 0}}}
  2920  	ap_ImmUnsigned_16_16             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1, 0}}}
  2921  	ap_ImmUnsigned_17_20             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4, 0}}}
  2922  	ap_ImmUnsigned_22_23             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2, 0}}}
  2923  	ap_VecSReg_28_28_21_25           = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 0}, {21, 5, 0}}}
  2924  	ap_ImmUnsigned_11_12             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2, 0}}}
  2925  	ap_ImmSigned_11_15               = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5, 0}}}
  2926  	ap_ImmUnsigned_16_21             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6, 0}}}
  2927  	ap_CondRegBit_21_25              = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
  2928  	ap_ImmUnsigned_12_13             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 2, 0}}}
  2929  	ap_ImmUnsigned_14_14             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 1, 0}}}
  2930  	ap_ImmUnsigned_22_25             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4, 0}}}
  2931  	ap_ImmUnsigned_12_19             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8, 0}}}
  2932  	ap_ImmUnsigned_20_26             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7, 0}}}
  2933  	ap_ImmUnsigned_8_10              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3, 0}}}
  2934  	ap_FPReg_21_25                   = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
  2935  	ap_SpReg_16_20_11_15             = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5, 0}, {11, 5, 0}}}
  2936  	ap_ImmUnsigned_26_26_21_25       = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1, 0}, {21, 5, 0}}}
  2937  	ap_ImmSigned_16_31               = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16, 0}}}
  2938  	ap_ImmUnsigned_16_31             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16, 0}}}
  2939  	ap_PCRel_6_29_shift2             = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24, 0}}}
  2940  	ap_Label_6_29_shift2             = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24, 0}}}
  2941  	ap_PCRel_16_29_shift2            = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14, 0}}}
  2942  	ap_Label_16_29_shift2            = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14, 0}}}
  2943  	ap_CondRegBit_6_10               = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5, 0}}}
  2944  	ap_CondRegBit_16_20              = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5, 0}}}
  2945  	ap_Offset_16_31                  = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16, 0}}}
  2946  	ap_ImmUnsigned_7_14              = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8, 0}}}
  2947  	ap_ImmUnsigned_6_6               = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1, 0}}}
  2948  	ap_ImmUnsigned_6_8               = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 3, 0}}}
  2949  	ap_ImmUnsigned_21_25             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5, 0}}}
  2950  	ap_ImmUnsigned_26_30             = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5, 0}}}
  2951  )
  2952  
  2953  var instFormats = [...]instFormat{
  2954  	{HASHCHK, 0xfc0007fe00000000, 0x7c0005e400000000, 0x0, // Hash Check X-form (hashchk RB,offset(RA))
  2955  		[6]*argField{ap_Reg_16_20, ap_NegOffset_31_31_6_10_shift3, ap_Reg_11_15}},
  2956  	{HASHCHKP, 0xfc0007fe00000000, 0x7c00056400000000, 0x0, // Hash Check Privileged X-form (hashchkp RB,offset(RA))
  2957  		[6]*argField{ap_Reg_16_20, ap_NegOffset_31_31_6_10_shift3, ap_Reg_11_15}},
  2958  	{HASHST, 0xfc0007fe00000000, 0x7c0005a400000000, 0x0, // Hash Store X-form (hashst RB,offset(RA))
  2959  		[6]*argField{ap_Reg_16_20, ap_NegOffset_31_31_6_10_shift3, ap_Reg_11_15}},
  2960  	{HASHSTP, 0xfc0007fe00000000, 0x7c00052400000000, 0x0, // Hash Store Privileged X-form (hashstp RB,offset(RA))
  2961  		[6]*argField{ap_Reg_16_20, ap_NegOffset_31_31_6_10_shift3, ap_Reg_11_15}},
  2962  	{BRD, 0xfc0007fe00000000, 0x7c00017600000000, 0xf80100000000, // Byte-Reverse Doubleword X-form (brd RA,RS)
  2963  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  2964  	{BRH, 0xfc0007fe00000000, 0x7c0001b600000000, 0xf80100000000, // Byte-Reverse Halfword X-form (brh RA,RS)
  2965  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  2966  	{BRW, 0xfc0007fe00000000, 0x7c00013600000000, 0xf80100000000, // Byte-Reverse Word X-form (brw RA,RS)
  2967  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  2968  	{CFUGED, 0xfc0007fe00000000, 0x7c0001b800000000, 0x100000000, // Centrifuge Doubleword X-form (cfuged RA,RS,RB)
  2969  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  2970  	{CNTLZDM, 0xfc0007fe00000000, 0x7c00007600000000, 0x100000000, // Count Leading Zeros Doubleword under bit Mask X-form (cntlzdm RA,RS,RB)
  2971  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  2972  	{CNTTZDM, 0xfc0007fe00000000, 0x7c00047600000000, 0x100000000, // Count Trailing Zeros Doubleword under bit Mask X-form (cnttzdm RA,RS,RB)
  2973  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  2974  	{DCFFIXQQ, 0xfc1f07fe00000000, 0xfc0007c400000000, 0x100000000, // DFP Convert From Fixed Quadword Quad X-form (dcffixqq FRTp,VRB)
  2975  		[6]*argField{ap_FPReg_6_10, ap_VecReg_16_20}},
  2976  	{DCTFIXQQ, 0xfc1f07fe00000000, 0xfc0107c400000000, 0x100000000, // DFP Convert To Fixed Quadword Quad X-form (dctfixqq VRT,FRBp)
  2977  		[6]*argField{ap_VecReg_6_10, ap_FPReg_16_20}},
  2978  	{LXVKQ, 0xfc1f07fe00000000, 0xf01f02d000000000, 0x0, // Load VSX Vector Special Value Quadword X-form (lxvkq XT,UIM)
  2979  		[6]*argField{ap_VecSReg_31_31_6_10, ap_ImmUnsigned_16_20}},
  2980  	{LXVP, 0xfc00000f00000000, 0x1800000000000000, 0x0, // Load VSX Vector Paired DQ-form (lxvp XTp,DQ(RA))
  2981  		[6]*argField{ap_VecSpReg_10_10_6_9, ap_Offset_16_27_shift4, ap_Reg_11_15}},
  2982  	{LXVPX, 0xfc0007fe00000000, 0x7c00029a00000000, 0x100000000, // Load VSX Vector Paired Indexed X-form (lxvpx XTp,RA,RB)
  2983  		[6]*argField{ap_VecSpReg_10_10_6_9, ap_Reg_11_15, ap_Reg_16_20}},
  2984  	{LXVRBX, 0xfc0007fe00000000, 0x7c00001a00000000, 0x0, // Load VSX Vector Rightmost Byte Indexed X-form (lxvrbx XT,RA,RB)
  2985  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  2986  	{LXVRDX, 0xfc0007fe00000000, 0x7c0000da00000000, 0x0, // Load VSX Vector Rightmost Doubleword Indexed X-form (lxvrdx XT,RA,RB)
  2987  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  2988  	{LXVRHX, 0xfc0007fe00000000, 0x7c00005a00000000, 0x0, // Load VSX Vector Rightmost Halfword Indexed X-form (lxvrhx XT,RA,RB)
  2989  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  2990  	{LXVRWX, 0xfc0007fe00000000, 0x7c00009a00000000, 0x0, // Load VSX Vector Rightmost Word Indexed X-form (lxvrwx XT,RA,RB)
  2991  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  2992  	{MTVSRBM, 0xfc1f07ff00000000, 0x1010064200000000, 0x0, // Move to VSR Byte Mask VX-form (mtvsrbm VRT,RB)
  2993  		[6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
  2994  	{MTVSRBMI, 0xfc00003e00000000, 0x1000001400000000, 0x0, // Move To VSR Byte Mask Immediate DX-form (mtvsrbmi VRT,bm)
  2995  		[6]*argField{ap_VecReg_6_10, ap_ImmUnsigned_16_25_11_15_31_31}},
  2996  	{MTVSRDM, 0xfc1f07ff00000000, 0x1013064200000000, 0x0, // Move to VSR Doubleword Mask VX-form (mtvsrdm VRT,RB)
  2997  		[6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
  2998  	{MTVSRHM, 0xfc1f07ff00000000, 0x1011064200000000, 0x0, // Move to VSR Halfword Mask VX-form (mtvsrhm VRT,RB)
  2999  		[6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
  3000  	{MTVSRQM, 0xfc1f07ff00000000, 0x1014064200000000, 0x0, // Move to VSR Quadword Mask VX-form (mtvsrqm VRT,RB)
  3001  		[6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
  3002  	{MTVSRWM, 0xfc1f07ff00000000, 0x1012064200000000, 0x0, // Move to VSR Word Mask VX-form (mtvsrwm VRT,RB)
  3003  		[6]*argField{ap_VecReg_6_10, ap_Reg_16_20}},
  3004  	{PADDI, 0xff800000fc000000, 0x600000038000000, 0x6c000000000000, // Prefixed Add Immediate MLS:D-form (paddi RT,RA,SI,R)
  3005  		[6]*argField{ap_Reg_38_42, ap_Reg_43_47, ap_ImmSigned_14_31_48_63, ap_ImmUnsigned_11_11}},
  3006  	{PDEPD, 0xfc0007fe00000000, 0x7c00013800000000, 0x100000000, // Parallel Bits Deposit Doubleword X-form (pdepd RA,RS,RB)
  3007  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  3008  	{PEXTD, 0xfc0007fe00000000, 0x7c00017800000000, 0x100000000, // Parallel Bits Extract Doubleword X-form (pextd RA,RS,RB)
  3009  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  3010  	{PLBZ, 0xff800000fc000000, 0x600000088000000, 0x6c000000000000, // Prefixed Load Byte and Zero MLS:D-form (plbz RT,D(RA),R)
  3011  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3012  	{PLD, 0xff800000fc000000, 0x4000000e4000000, 0x6c000000000000, // Prefixed Load Doubleword 8LS:D-form (pld RT,D(RA),R)
  3013  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3014  	{PLFD, 0xff800000fc000000, 0x6000000c8000000, 0x6c000000000000, // Prefixed Load Floating-Point Double MLS:D-form (plfd FRT,D(RA),R)
  3015  		[6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3016  	{PLFS, 0xff800000fc000000, 0x6000000c0000000, 0x6c000000000000, // Prefixed Load Floating-Point Single MLS:D-form (plfs FRT,D(RA),R)
  3017  		[6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3018  	{PLHA, 0xff800000fc000000, 0x6000000a8000000, 0x6c000000000000, // Prefixed Load Halfword Algebraic MLS:D-form (plha RT,D(RA),R)
  3019  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3020  	{PLHZ, 0xff800000fc000000, 0x6000000a0000000, 0x6c000000000000, // Prefixed Load Halfword and Zero MLS:D-form (plhz RT,D(RA),R)
  3021  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3022  	{PLQ, 0xff800000fc000000, 0x4000000e0000000, 0x6c000000000000, // Prefixed Load Quadword 8LS:D-form (plq RTp,D(RA),R)
  3023  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3024  	{PLWA, 0xff800000fc000000, 0x4000000a4000000, 0x6c000000000000, // Prefixed Load Word Algebraic 8LS:D-form (plwa RT,D(RA),R)
  3025  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3026  	{PLWZ, 0xff800000fc000000, 0x600000080000000, 0x6c000000000000, // Prefixed Load Word and Zero MLS:D-form (plwz RT,D(RA),R)
  3027  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3028  	{PLXSD, 0xff800000fc000000, 0x4000000a8000000, 0x6c000000000000, // Prefixed Load VSX Scalar Doubleword 8LS:D-form (plxsd VRT,D(RA),R)
  3029  		[6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3030  	{PLXSSP, 0xff800000fc000000, 0x4000000ac000000, 0x6c000000000000, // Prefixed Load VSX Scalar Single-Precision 8LS:D-form (plxssp VRT,D(RA),R)
  3031  		[6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3032  	{PLXV, 0xff800000f8000000, 0x4000000c8000000, 0x6c000000000000, // Prefixed Load VSX Vector 8LS:D-form (plxv XT,D(RA),R)
  3033  		[6]*argField{ap_VecSReg_37_37_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3034  	{PLXVP, 0xff800000fc000000, 0x4000000e8000000, 0x6c000000000000, // Prefixed Load VSX Vector Paired 8LS:D-form (plxvp XTp,D(RA),R)
  3035  		[6]*argField{ap_VecSpReg_42_42_38_41, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3036  	{PMXVBF16GER2, 0xfff00000fc0007f8, 0x7900000ec000198, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) MMIRR:XX3-form (pmxvbf16ger2 AT,XA,XB,XMSK,YMSK,PMSK)
  3037  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3038  	{PMXVBF16GER2NN, 0xfff00000fc0007f8, 0x7900000ec000790, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvbf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK)
  3039  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3040  	{PMXVBF16GER2NP, 0xfff00000fc0007f8, 0x7900000ec000390, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvbf16ger2np AT,XA,XB,XMSK,YMSK,PMSK)
  3041  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3042  	{PMXVBF16GER2PN, 0xfff00000fc0007f8, 0x7900000ec000590, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvbf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK)
  3043  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3044  	{PMXVBF16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000190, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvbf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK)
  3045  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3046  	{PMXVF16GER2, 0xfff00000fc0007f8, 0x7900000ec000098, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) MMIRR:XX3-form (pmxvf16ger2 AT,XA,XB,XMSK,YMSK,PMSK)
  3047  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3048  	{PMXVF16GER2NN, 0xfff00000fc0007f8, 0x7900000ec000690, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK)
  3049  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3050  	{PMXVF16GER2NP, 0xfff00000fc0007f8, 0x7900000ec000290, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf16ger2np AT,XA,XB,XMSK,YMSK,PMSK)
  3051  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3052  	{PMXVF16GER2PN, 0xfff00000fc0007f8, 0x7900000ec000490, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK)
  3053  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3054  	{PMXVF16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000090, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK)
  3055  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3056  	{PMXVF32GER, 0xfff00000fc0007f8, 0x7900000ec0000d8, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) MMIRR:XX3-form (pmxvf32ger AT,XA,XB,XMSK,YMSK)
  3057  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
  3058  	{PMXVF32GERNN, 0xfff00000fc0007f8, 0x7900000ec0006d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf32gernn AT,XA,XB,XMSK,YMSK)
  3059  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
  3060  	{PMXVF32GERNP, 0xfff00000fc0007f8, 0x7900000ec0002d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf32gernp AT,XA,XB,XMSK,YMSK)
  3061  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
  3062  	{PMXVF32GERPN, 0xfff00000fc0007f8, 0x7900000ec0004d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf32gerpn AT,XA,XB,XMSK,YMSK)
  3063  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
  3064  	{PMXVF32GERPP, 0xfff00000fc0007f8, 0x7900000ec0000d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf32gerpp AT,XA,XB,XMSK,YMSK)
  3065  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}},
  3066  	{PMXVF64GER, 0xfff00000fc0007f8, 0x7900000ec0001d8, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) MMIRR:XX3-form (pmxvf64ger AT,XAp,XB,XMSK,YMSK)
  3067  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
  3068  	{PMXVF64GERNN, 0xfff00000fc0007f8, 0x7900000ec0007d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf64gernn AT,XAp,XB,XMSK,YMSK)
  3069  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
  3070  	{PMXVF64GERNP, 0xfff00000fc0007f8, 0x7900000ec0003d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf64gernp AT,XAp,XB,XMSK,YMSK)
  3071  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
  3072  	{PMXVF64GERPN, 0xfff00000fc0007f8, 0x7900000ec0005d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf64gerpn AT,XAp,XB,XMSK,YMSK)
  3073  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
  3074  	{PMXVF64GERPP, 0xfff00000fc0007f8, 0x7900000ec0001d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf64gerpp AT,XAp,XB,XMSK,YMSK)
  3075  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}},
  3076  	{PMXVI16GER2, 0xfff00000fc0007f8, 0x7900000ec000258, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) MMIRR:XX3-form (pmxvi16ger2 AT,XA,XB,XMSK,YMSK,PMSK)
  3077  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3078  	{PMXVI16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000358, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi16ger2pp AT,XA,XB,XMSK,YMSK,PMSK)
  3079  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3080  	{PMXVI16GER2S, 0xfff00000fc0007f8, 0x7900000ec000158, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation MMIRR:XX3-form (pmxvi16ger2s AT,XA,XB,XMSK,YMSK,PMSK)
  3081  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3082  	{PMXVI16GER2SPP, 0xfff00000fc0007f8, 0x7900000ec000150, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi16ger2spp AT,XA,XB,XMSK,YMSK,PMSK)
  3083  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}},
  3084  	{PMXVI4GER8, 0xfff00000fc0007f8, 0x7900000ec000118, 0xf000000000000, // Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) MMIRR:XX3-form (pmxvi4ger8 AT,XA,XB,XMSK,YMSK,PMSK)
  3085  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_23}},
  3086  	{PMXVI4GER8PP, 0xfff00000fc0007f8, 0x7900000ec000110, 0xf000000000000, // Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi4ger8pp AT,XA,XB,XMSK,YMSK,PMSK)
  3087  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_23}},
  3088  	{PMXVI8GER4, 0xfff00000fc0007f8, 0x7900000ec000018, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) MMIRR:XX3-form (pmxvi8ger4 AT,XA,XB,XMSK,YMSK,PMSK)
  3089  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}},
  3090  	{PMXVI8GER4PP, 0xfff00000fc0007f8, 0x7900000ec000010, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi8ger4pp AT,XA,XB,XMSK,YMSK,PMSK)
  3091  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}},
  3092  	{PMXVI8GER4SPP, 0xfff00000fc0007f8, 0x7900000ec000318, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi8ger4spp AT,XA,XB,XMSK,YMSK,PMSK)
  3093  		[6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}},
  3094  	{PNOP, 0xfff3fffe00000000, 0x700000000000000, 0xc000100000000, // Prefixed Nop MRR:*-form (pnop)
  3095  		[6]*argField{}},
  3096  	{PSTB, 0xff800000fc000000, 0x600000098000000, 0x6c000000000000, // Prefixed Store Byte MLS:D-form (pstb RS,D(RA),R)
  3097  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3098  	{PSTD, 0xff800000fc000000, 0x4000000f4000000, 0x6c000000000000, // Prefixed Store Doubleword 8LS:D-form (pstd RS,D(RA),R)
  3099  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3100  	{PSTFD, 0xff800000fc000000, 0x6000000d8000000, 0x6c000000000000, // Prefixed Store Floating-Point Double MLS:D-form (pstfd FRS,D(RA),R)
  3101  		[6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3102  	{PSTFS, 0xff800000fc000000, 0x6000000d0000000, 0x6c000000000000, // Prefixed Store Floating-Point Single MLS:D-form (pstfs FRS,D(RA),R)
  3103  		[6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3104  	{PSTH, 0xff800000fc000000, 0x6000000b0000000, 0x6c000000000000, // Prefixed Store Halfword MLS:D-form (psth RS,D(RA),R)
  3105  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3106  	{PSTQ, 0xff800000fc000000, 0x4000000f0000000, 0x6c000000000000, // Prefixed Store Quadword 8LS:D-form (pstq RSp,D(RA),R)
  3107  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3108  	{PSTW, 0xff800000fc000000, 0x600000090000000, 0x6c000000000000, // Prefixed Store Word MLS:D-form (pstw RS,D(RA),R)
  3109  		[6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3110  	{PSTXSD, 0xff800000fc000000, 0x4000000b8000000, 0x6c000000000000, // Prefixed Store VSX Scalar Doubleword 8LS:D-form (pstxsd VRS,D(RA),R)
  3111  		[6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3112  	{PSTXSSP, 0xff800000fc000000, 0x4000000bc000000, 0x6c000000000000, // Prefixed Store VSX Scalar Single-Precision 8LS:D-form (pstxssp VRS,D(RA),R)
  3113  		[6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3114  	{PSTXV, 0xff800000f8000000, 0x4000000d8000000, 0x6c000000000000, // Prefixed Store VSX Vector 8LS:D-form (pstxv XS,D(RA),R)
  3115  		[6]*argField{ap_VecSReg_37_37_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3116  	{PSTXVP, 0xff800000fc000000, 0x4000000f8000000, 0x6c000000000000, // Prefixed Store VSX Vector Paired 8LS:D-form (pstxvp XSp,D(RA),R)
  3117  		[6]*argField{ap_VecSpReg_42_42_38_41, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}},
  3118  	{SETBC, 0xfc0007fe00000000, 0x7c00030000000000, 0xf80100000000, // Set Boolean Condition X-form (setbc RT,BI)
  3119  		[6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}},
  3120  	{SETBCR, 0xfc0007fe00000000, 0x7c00034000000000, 0xf80100000000, // Set Boolean Condition Reverse X-form (setbcr RT,BI)
  3121  		[6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}},
  3122  	{SETNBC, 0xfc0007fe00000000, 0x7c00038000000000, 0xf80100000000, // Set Negative Boolean Condition X-form (setnbc RT,BI)
  3123  		[6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}},
  3124  	{SETNBCR, 0xfc0007fe00000000, 0x7c0003c000000000, 0xf80100000000, // Set Negative Boolean Condition Reverse X-form (setnbcr RT,BI)
  3125  		[6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}},
  3126  	{STXVP, 0xfc00000f00000000, 0x1800000100000000, 0x0, // Store VSX Vector Paired DQ-form (stxvp XSp,DQ(RA))
  3127  		[6]*argField{ap_VecSpReg_10_10_6_9, ap_Offset_16_27_shift4, ap_Reg_11_15}},
  3128  	{STXVPX, 0xfc0007fe00000000, 0x7c00039a00000000, 0x100000000, // Store VSX Vector Paired Indexed X-form (stxvpx XSp,RA,RB)
  3129  		[6]*argField{ap_VecSpReg_10_10_6_9, ap_Reg_11_15, ap_Reg_16_20}},
  3130  	{STXVRBX, 0xfc0007fe00000000, 0x7c00011a00000000, 0x0, // Store VSX Vector Rightmost Byte Indexed X-form (stxvrbx XS,RA,RB)
  3131  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3132  	{STXVRDX, 0xfc0007fe00000000, 0x7c0001da00000000, 0x0, // Store VSX Vector Rightmost Doubleword Indexed X-form (stxvrdx XS,RA,RB)
  3133  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3134  	{STXVRHX, 0xfc0007fe00000000, 0x7c00015a00000000, 0x0, // Store VSX Vector Rightmost Halfword Indexed X-form (stxvrhx XS,RA,RB)
  3135  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3136  	{STXVRWX, 0xfc0007fe00000000, 0x7c00019a00000000, 0x0, // Store VSX Vector Rightmost Word Indexed X-form (stxvrwx XS,RA,RB)
  3137  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3138  	{VCFUGED, 0xfc0007ff00000000, 0x1000054d00000000, 0x0, // Vector Centrifuge Doubleword VX-form (vcfuged VRT,VRA,VRB)
  3139  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3140  	{VCLRLB, 0xfc0007ff00000000, 0x1000018d00000000, 0x0, // Vector Clear Leftmost Bytes VX-form (vclrlb VRT,VRA,RB)
  3141  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_Reg_16_20}},
  3142  	{VCLRRB, 0xfc0007ff00000000, 0x100001cd00000000, 0x0, // Vector Clear Rightmost Bytes VX-form (vclrrb VRT,VRA,RB)
  3143  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_Reg_16_20}},
  3144  	{VCLZDM, 0xfc0007ff00000000, 0x1000078400000000, 0x0, // Vector Count Leading Zeros Doubleword under bit Mask VX-form (vclzdm VRT,VRA,VRB)
  3145  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3146  	{VCMPEQUQ, 0xfc0007ff00000000, 0x100001c700000000, 0x0, // Vector Compare Equal Quadword VC-form (vcmpequq VRT,VRA,VRB)
  3147  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3148  	{VCMPEQUQCC, 0xfc0007ff00000000, 0x100005c700000000, 0x0, // Vector Compare Equal Quadword VC-form (vcmpequq. VRT,VRA,VRB)
  3149  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3150  	{VCMPGTSQ, 0xfc0007ff00000000, 0x1000038700000000, 0x0, // Vector Compare Greater Than Signed Quadword VC-form (vcmpgtsq VRT,VRA,VRB)
  3151  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3152  	{VCMPGTSQCC, 0xfc0007ff00000000, 0x1000078700000000, 0x0, // Vector Compare Greater Than Signed Quadword VC-form (vcmpgtsq. VRT,VRA,VRB)
  3153  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3154  	{VCMPGTUQ, 0xfc0007ff00000000, 0x1000028700000000, 0x0, // Vector Compare Greater Than Unsigned Quadword VC-form (vcmpgtuq VRT,VRA,VRB)
  3155  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3156  	{VCMPGTUQCC, 0xfc0007ff00000000, 0x1000068700000000, 0x0, // Vector Compare Greater Than Unsigned Quadword VC-form (vcmpgtuq. VRT,VRA,VRB)
  3157  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3158  	{VCMPSQ, 0xfc0007ff00000000, 0x1000014100000000, 0x60000000000000, // Vector Compare Signed Quadword VX-form (vcmpsq BF,VRA,VRB)
  3159  		[6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
  3160  	{VCMPUQ, 0xfc0007ff00000000, 0x1000010100000000, 0x60000000000000, // Vector Compare Unsigned Quadword VX-form (vcmpuq BF,VRA,VRB)
  3161  		[6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
  3162  	{VCNTMBB, 0xfc1e07ff00000000, 0x1018064200000000, 0x0, // Vector Count Mask Bits Byte VX-form (vcntmbb RT,VRB,MP)
  3163  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}},
  3164  	{VCNTMBD, 0xfc1e07ff00000000, 0x101e064200000000, 0x0, // Vector Count Mask Bits Doubleword VX-form (vcntmbd RT,VRB,MP)
  3165  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}},
  3166  	{VCNTMBH, 0xfc1e07ff00000000, 0x101a064200000000, 0x0, // Vector Count Mask Bits Halfword VX-form (vcntmbh RT,VRB,MP)
  3167  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}},
  3168  	{VCNTMBW, 0xfc1e07ff00000000, 0x101c064200000000, 0x0, // Vector Count Mask Bits Word VX-form (vcntmbw RT,VRB,MP)
  3169  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}},
  3170  	{VCTZDM, 0xfc0007ff00000000, 0x100007c400000000, 0x0, // Vector Count Trailing Zeros Doubleword under bit Mask VX-form (vctzdm VRT,VRA,VRB)
  3171  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3172  	{VDIVESD, 0xfc0007ff00000000, 0x100003cb00000000, 0x0, // Vector Divide Extended Signed Doubleword VX-form (vdivesd VRT,VRA,VRB)
  3173  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3174  	{VDIVESQ, 0xfc0007ff00000000, 0x1000030b00000000, 0x0, // Vector Divide Extended Signed Quadword VX-form (vdivesq VRT,VRA,VRB)
  3175  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3176  	{VDIVESW, 0xfc0007ff00000000, 0x1000038b00000000, 0x0, // Vector Divide Extended Signed Word VX-form (vdivesw VRT,VRA,VRB)
  3177  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3178  	{VDIVEUD, 0xfc0007ff00000000, 0x100002cb00000000, 0x0, // Vector Divide Extended Unsigned Doubleword VX-form (vdiveud VRT,VRA,VRB)
  3179  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3180  	{VDIVEUQ, 0xfc0007ff00000000, 0x1000020b00000000, 0x0, // Vector Divide Extended Unsigned Quadword VX-form (vdiveuq VRT,VRA,VRB)
  3181  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3182  	{VDIVEUW, 0xfc0007ff00000000, 0x1000028b00000000, 0x0, // Vector Divide Extended Unsigned Word VX-form (vdiveuw VRT,VRA,VRB)
  3183  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3184  	{VDIVSD, 0xfc0007ff00000000, 0x100001cb00000000, 0x0, // Vector Divide Signed Doubleword VX-form (vdivsd VRT,VRA,VRB)
  3185  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3186  	{VDIVSQ, 0xfc0007ff00000000, 0x1000010b00000000, 0x0, // Vector Divide Signed Quadword VX-form (vdivsq VRT,VRA,VRB)
  3187  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3188  	{VDIVSW, 0xfc0007ff00000000, 0x1000018b00000000, 0x0, // Vector Divide Signed Word VX-form (vdivsw VRT,VRA,VRB)
  3189  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3190  	{VDIVUD, 0xfc0007ff00000000, 0x100000cb00000000, 0x0, // Vector Divide Unsigned Doubleword VX-form (vdivud VRT,VRA,VRB)
  3191  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3192  	{VDIVUQ, 0xfc0007ff00000000, 0x1000000b00000000, 0x0, // Vector Divide Unsigned Quadword VX-form (vdivuq VRT,VRA,VRB)
  3193  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3194  	{VDIVUW, 0xfc0007ff00000000, 0x1000008b00000000, 0x0, // Vector Divide Unsigned Word VX-form (vdivuw VRT,VRA,VRB)
  3195  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3196  	{VEXPANDBM, 0xfc1f07ff00000000, 0x1000064200000000, 0x0, // Vector Expand Byte Mask VX-form (vexpandbm VRT,VRB)
  3197  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3198  	{VEXPANDDM, 0xfc1f07ff00000000, 0x1003064200000000, 0x0, // Vector Expand Doubleword Mask VX-form (vexpanddm VRT,VRB)
  3199  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3200  	{VEXPANDHM, 0xfc1f07ff00000000, 0x1001064200000000, 0x0, // Vector Expand Halfword Mask VX-form (vexpandhm VRT,VRB)
  3201  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3202  	{VEXPANDQM, 0xfc1f07ff00000000, 0x1004064200000000, 0x0, // Vector Expand Quadword Mask VX-form (vexpandqm VRT,VRB)
  3203  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3204  	{VEXPANDWM, 0xfc1f07ff00000000, 0x1002064200000000, 0x0, // Vector Expand Word Mask VX-form (vexpandwm VRT,VRB)
  3205  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3206  	{VEXTDDVLX, 0xfc00003f00000000, 0x1000001e00000000, 0x0, // Vector Extract Double Doubleword to VSR using GPR-specified Left-Index VA-form (vextddvlx VRT,VRA,VRB,RC)
  3207  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
  3208  	{VEXTDDVRX, 0xfc00003f00000000, 0x1000001f00000000, 0x0, // Vector Extract Double Doubleword to VSR using GPR-specified Right-Index VA-form (vextddvrx VRT,VRA,VRB,RC)
  3209  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
  3210  	{VEXTDUBVLX, 0xfc00003f00000000, 0x1000001800000000, 0x0, // Vector Extract Double Unsigned Byte to VSR using GPR-specified Left-Index VA-form (vextdubvlx VRT,VRA,VRB,RC)
  3211  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
  3212  	{VEXTDUBVRX, 0xfc00003f00000000, 0x1000001900000000, 0x0, // Vector Extract Double Unsigned Byte to VSR using GPR-specified Right-Index VA-form (vextdubvrx VRT,VRA,VRB,RC)
  3213  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
  3214  	{VEXTDUHVLX, 0xfc00003f00000000, 0x1000001a00000000, 0x0, // Vector Extract Double Unsigned Halfword to VSR using GPR-specified Left-Index VA-form (vextduhvlx VRT,VRA,VRB,RC)
  3215  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
  3216  	{VEXTDUHVRX, 0xfc00003f00000000, 0x1000001b00000000, 0x0, // Vector Extract Double Unsigned Halfword to VSR using GPR-specified Right-Index VA-form (vextduhvrx VRT,VRA,VRB,RC)
  3217  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
  3218  	{VEXTDUWVLX, 0xfc00003f00000000, 0x1000001c00000000, 0x0, // Vector Extract Double Unsigned Word to VSR using GPR-specified Left-Index VA-form (vextduwvlx VRT,VRA,VRB,RC)
  3219  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
  3220  	{VEXTDUWVRX, 0xfc00003f00000000, 0x1000001d00000000, 0x0, // Vector Extract Double Unsigned Word to VSR using GPR-specified Right-Index VA-form (vextduwvrx VRT,VRA,VRB,RC)
  3221  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}},
  3222  	{VEXTRACTBM, 0xfc1f07ff00000000, 0x1008064200000000, 0x0, // Vector Extract Byte Mask VX-form (vextractbm RT,VRB)
  3223  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
  3224  	{VEXTRACTDM, 0xfc1f07ff00000000, 0x100b064200000000, 0x0, // Vector Extract Doubleword Mask VX-form (vextractdm RT,VRB)
  3225  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
  3226  	{VEXTRACTHM, 0xfc1f07ff00000000, 0x1009064200000000, 0x0, // Vector Extract Halfword Mask VX-form (vextracthm RT,VRB)
  3227  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
  3228  	{VEXTRACTQM, 0xfc1f07ff00000000, 0x100c064200000000, 0x0, // Vector Extract Quadword Mask VX-form (vextractqm RT,VRB)
  3229  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
  3230  	{VEXTRACTWM, 0xfc1f07ff00000000, 0x100a064200000000, 0x0, // Vector Extract Word Mask VX-form (vextractwm RT,VRB)
  3231  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
  3232  	{VEXTSD2Q, 0xfc1f07ff00000000, 0x101b060200000000, 0x0, // Vector Extend Sign Doubleword to Quadword VX-form (vextsd2q VRT,VRB)
  3233  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3234  	{VGNB, 0xfc0007ff00000000, 0x100004cc00000000, 0x18000000000000, // Vector Gather every Nth Bit VX-form (vgnb RT,VRB,N)
  3235  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}},
  3236  	{VINSBLX, 0xfc0007ff00000000, 0x1000020f00000000, 0x0, // Vector Insert Byte from GPR using GPR-specified Left-Index VX-form (vinsblx VRT,RA,RB)
  3237  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3238  	{VINSBRX, 0xfc0007ff00000000, 0x1000030f00000000, 0x0, // Vector Insert Byte from GPR using GPR-specified Right-Index VX-form (vinsbrx VRT,RA,RB)
  3239  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3240  	{VINSBVLX, 0xfc0007ff00000000, 0x1000000f00000000, 0x0, // Vector Insert Byte from VSR using GPR-specified Left-Index VX-form (vinsbvlx VRT,RA,VRB)
  3241  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3242  	{VINSBVRX, 0xfc0007ff00000000, 0x1000010f00000000, 0x0, // Vector Insert Byte from VSR using GPR-specified Right-Index VX-form (vinsbvrx VRT,RA,VRB)
  3243  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3244  	{VINSD, 0xfc0007ff00000000, 0x100001cf00000000, 0x10000000000000, // Vector Insert Doubleword from GPR using immediate-specified index VX-form (vinsd VRT,RB,UIM)
  3245  		[6]*argField{ap_VecReg_6_10, ap_Reg_16_20, ap_ImmUnsigned_12_15}},
  3246  	{VINSDLX, 0xfc0007ff00000000, 0x100002cf00000000, 0x0, // Vector Insert Doubleword from GPR using GPR-specified Left-Index VX-form (vinsdlx VRT,RA,RB)
  3247  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3248  	{VINSDRX, 0xfc0007ff00000000, 0x100003cf00000000, 0x0, // Vector Insert Doubleword from GPR using GPR-specified Right-Index VX-form (vinsdrx VRT,RA,RB)
  3249  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3250  	{VINSHLX, 0xfc0007ff00000000, 0x1000024f00000000, 0x0, // Vector Insert Halfword from GPR using GPR-specified Left-Index VX-form (vinshlx VRT,RA,RB)
  3251  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3252  	{VINSHRX, 0xfc0007ff00000000, 0x1000034f00000000, 0x0, // Vector Insert Halfword from GPR using GPR-specified Right-Index VX-form (vinshrx VRT,RA,RB)
  3253  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3254  	{VINSHVLX, 0xfc0007ff00000000, 0x1000004f00000000, 0x0, // Vector Insert Halfword from VSR using GPR-specified Left-Index VX-form (vinshvlx VRT,RA,VRB)
  3255  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3256  	{VINSHVRX, 0xfc0007ff00000000, 0x1000014f00000000, 0x0, // Vector Insert Halfword from VSR using GPR-specified Right-Index VX-form (vinshvrx VRT,RA,VRB)
  3257  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3258  	{VINSW, 0xfc0007ff00000000, 0x100000cf00000000, 0x10000000000000, // Vector Insert Word from GPR using immediate-specified index VX-form (vinsw VRT,RB,UIM)
  3259  		[6]*argField{ap_VecReg_6_10, ap_Reg_16_20, ap_ImmUnsigned_12_15}},
  3260  	{VINSWLX, 0xfc0007ff00000000, 0x1000028f00000000, 0x0, // Vector Insert Word from GPR using GPR-specified Left-Index VX-form (vinswlx VRT,RA,RB)
  3261  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3262  	{VINSWRX, 0xfc0007ff00000000, 0x1000038f00000000, 0x0, // Vector Insert Word from GPR using GPR-specified Right-Index VX-form (vinswrx VRT,RA,RB)
  3263  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3264  	{VINSWVLX, 0xfc0007ff00000000, 0x1000008f00000000, 0x0, // Vector Insert Word from VSR using GPR-specified Left-Index VX-form (vinswvlx VRT,RA,VRB)
  3265  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3266  	{VINSWVRX, 0xfc0007ff00000000, 0x1000018f00000000, 0x0, // Vector Insert Word from VSR using GPR-specified Left-Index VX-form (vinswvrx VRT,RA,VRB)
  3267  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3268  	{VMODSD, 0xfc0007ff00000000, 0x100007cb00000000, 0x0, // Vector Modulo Signed Doubleword VX-form (vmodsd VRT,VRA,VRB)
  3269  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3270  	{VMODSQ, 0xfc0007ff00000000, 0x1000070b00000000, 0x0, // Vector Modulo Signed Quadword VX-form (vmodsq VRT,VRA,VRB)
  3271  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3272  	{VMODSW, 0xfc0007ff00000000, 0x1000078b00000000, 0x0, // Vector Modulo Signed Word VX-form (vmodsw VRT,VRA,VRB)
  3273  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3274  	{VMODUD, 0xfc0007ff00000000, 0x100006cb00000000, 0x0, // Vector Modulo Unsigned Doubleword VX-form (vmodud VRT,VRA,VRB)
  3275  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3276  	{VMODUQ, 0xfc0007ff00000000, 0x1000060b00000000, 0x0, // Vector Modulo Unsigned Quadword VX-form (vmoduq VRT,VRA,VRB)
  3277  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3278  	{VMODUW, 0xfc0007ff00000000, 0x1000068b00000000, 0x0, // Vector Modulo Unsigned Word VX-form (vmoduw VRT,VRA,VRB)
  3279  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3280  	{VMSUMCUD, 0xfc00003f00000000, 0x1000001700000000, 0x0, // Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form (vmsumcud VRT,VRA,VRB,VRC)
  3281  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  3282  	{VMULESD, 0xfc0007ff00000000, 0x100003c800000000, 0x0, // Vector Multiply Even Signed Doubleword VX-form (vmulesd VRT,VRA,VRB)
  3283  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3284  	{VMULEUD, 0xfc0007ff00000000, 0x100002c800000000, 0x0, // Vector Multiply Even Unsigned Doubleword VX-form (vmuleud VRT,VRA,VRB)
  3285  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3286  	{VMULHSD, 0xfc0007ff00000000, 0x100003c900000000, 0x0, // Vector Multiply High Signed Doubleword VX-form (vmulhsd VRT,VRA,VRB)
  3287  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3288  	{VMULHSW, 0xfc0007ff00000000, 0x1000038900000000, 0x0, // Vector Multiply High Signed Word VX-form (vmulhsw VRT,VRA,VRB)
  3289  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3290  	{VMULHUD, 0xfc0007ff00000000, 0x100002c900000000, 0x0, // Vector Multiply High Unsigned Doubleword VX-form (vmulhud VRT,VRA,VRB)
  3291  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3292  	{VMULHUW, 0xfc0007ff00000000, 0x1000028900000000, 0x0, // Vector Multiply High Unsigned Word VX-form (vmulhuw VRT,VRA,VRB)
  3293  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3294  	{VMULLD, 0xfc0007ff00000000, 0x100001c900000000, 0x0, // Vector Multiply Low Doubleword VX-form (vmulld VRT,VRA,VRB)
  3295  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3296  	{VMULOSD, 0xfc0007ff00000000, 0x100001c800000000, 0x0, // Vector Multiply Odd Signed Doubleword VX-form (vmulosd VRT,VRA,VRB)
  3297  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3298  	{VMULOUD, 0xfc0007ff00000000, 0x100000c800000000, 0x0, // Vector Multiply Odd Unsigned Doubleword VX-form (vmuloud VRT,VRA,VRB)
  3299  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3300  	{VPDEPD, 0xfc0007ff00000000, 0x100005cd00000000, 0x0, // Vector Parallel Bits Deposit Doubleword VX-form (vpdepd VRT,VRA,VRB)
  3301  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3302  	{VPEXTD, 0xfc0007ff00000000, 0x1000058d00000000, 0x0, // Vector Parallel Bits Extract Doubleword VX-form (vpextd VRT,VRA,VRB)
  3303  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3304  	{VRLQ, 0xfc0007ff00000000, 0x1000000500000000, 0x0, // Vector Rotate Left Quadword VX-form (vrlq VRT,VRA,VRB)
  3305  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3306  	{VRLQMI, 0xfc0007ff00000000, 0x1000004500000000, 0x0, // Vector Rotate Left Quadword then Mask Insert VX-form (vrlqmi VRT,VRA,VRB)
  3307  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3308  	{VRLQNM, 0xfc0007ff00000000, 0x1000014500000000, 0x0, // Vector Rotate Left Quadword then AND with Mask VX-form (vrlqnm VRT,VRA,VRB)
  3309  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3310  	{VSLDBI, 0xfc00063f00000000, 0x1000001600000000, 0x0, // Vector Shift Left Double by Bit Immediate VN-form (vsldbi VRT,VRA,VRB,SH)
  3311  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_23_25}},
  3312  	{VSLQ, 0xfc0007ff00000000, 0x1000010500000000, 0x0, // Vector Shift Left Quadword VX-form (vslq VRT,VRA,VRB)
  3313  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3314  	{VSRAQ, 0xfc0007ff00000000, 0x1000030500000000, 0x0, // Vector Shift Right Algebraic Quadword VX-form (vsraq VRT,VRA,VRB)
  3315  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3316  	{VSRDBI, 0xfc00063f00000000, 0x1000021600000000, 0x0, // Vector Shift Right Double by Bit Immediate VN-form (vsrdbi VRT,VRA,VRB,SH)
  3317  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_23_25}},
  3318  	{VSRQ, 0xfc0007ff00000000, 0x1000020500000000, 0x0, // Vector Shift Right Quadword VX-form (vsrq VRT,VRA,VRB)
  3319  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3320  	{VSTRIBL, 0xfc1f07ff00000000, 0x1000000d00000000, 0x0, // Vector String Isolate Byte Left-justified VX-form (vstribl VRT,VRB)
  3321  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3322  	{VSTRIBLCC, 0xfc1f07ff00000000, 0x1000040d00000000, 0x0, // Vector String Isolate Byte Left-justified VX-form (vstribl. VRT,VRB)
  3323  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3324  	{VSTRIBR, 0xfc1f07ff00000000, 0x1001000d00000000, 0x0, // Vector String Isolate Byte Right-justified VX-form (vstribr VRT,VRB)
  3325  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3326  	{VSTRIBRCC, 0xfc1f07ff00000000, 0x1001040d00000000, 0x0, // Vector String Isolate Byte Right-justified VX-form (vstribr. VRT,VRB)
  3327  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3328  	{VSTRIHL, 0xfc1f07ff00000000, 0x1002000d00000000, 0x0, // Vector String Isolate Halfword Left-justified VX-form (vstrihl VRT,VRB)
  3329  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3330  	{VSTRIHLCC, 0xfc1f07ff00000000, 0x1002040d00000000, 0x0, // Vector String Isolate Halfword Left-justified VX-form (vstrihl. VRT,VRB)
  3331  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3332  	{VSTRIHR, 0xfc1f07ff00000000, 0x1003000d00000000, 0x0, // Vector String Isolate Halfword Right-justified VX-form (vstrihr VRT,VRB)
  3333  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3334  	{VSTRIHRCC, 0xfc1f07ff00000000, 0x1003040d00000000, 0x0, // Vector String Isolate Halfword Right-justified VX-form (vstrihr. VRT,VRB)
  3335  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3336  	{XSCMPEQQP, 0xfc0007fe00000000, 0xfc00008800000000, 0x100000000, // VSX Scalar Compare Equal Quad-Precision X-form (xscmpeqqp VRT,VRA,VRB)
  3337  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3338  	{XSCMPGEQP, 0xfc0007fe00000000, 0xfc00018800000000, 0x100000000, // VSX Scalar Compare Greater Than or Equal Quad-Precision X-form (xscmpgeqp VRT,VRA,VRB)
  3339  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3340  	{XSCMPGTQP, 0xfc0007fe00000000, 0xfc0001c800000000, 0x100000000, // VSX Scalar Compare Greater Than Quad-Precision X-form (xscmpgtqp VRT,VRA,VRB)
  3341  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3342  	{XSCVQPSQZ, 0xfc1f07fe00000000, 0xfc08068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword X-form (xscvqpsqz VRT,VRB)
  3343  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3344  	{XSCVQPUQZ, 0xfc1f07fe00000000, 0xfc00068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword X-form (xscvqpuqz VRT,VRB)
  3345  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3346  	{XSCVSQQP, 0xfc1f07fe00000000, 0xfc0b068800000000, 0x100000000, // VSX Scalar Convert with round Signed Quadword to Quad-Precision X-form (xscvsqqp VRT,VRB)
  3347  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3348  	{XSCVUQQP, 0xfc1f07fe00000000, 0xfc03068800000000, 0x100000000, // VSX Scalar Convert with round Unsigned Quadword to Quad-Precision X-form (xscvuqqp VRT,VRB)
  3349  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3350  	{XSMAXCQP, 0xfc0007fe00000000, 0xfc00054800000000, 0x100000000, // VSX Scalar Maximum Type-C Quad-Precision X-form (xsmaxcqp VRT,VRA,VRB)
  3351  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3352  	{XSMINCQP, 0xfc0007fe00000000, 0xfc0005c800000000, 0x100000000, // VSX Scalar Minimum Type-C Quad-Precision X-form (xsmincqp VRT,VRA,VRB)
  3353  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3354  	{XVBF16GER2, 0xfc0007f800000000, 0xec00019800000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) XX3-form (xvbf16ger2 AT,XA,XB)
  3355  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3356  	{XVBF16GER2NN, 0xfc0007f800000000, 0xec00079000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate XX3-form (xvbf16ger2nn AT,XA,XB)
  3357  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3358  	{XVBF16GER2NP, 0xfc0007f800000000, 0xec00039000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate XX3-form (xvbf16ger2np AT,XA,XB)
  3359  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3360  	{XVBF16GER2PN, 0xfc0007f800000000, 0xec00059000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate XX3-form (xvbf16ger2pn AT,XA,XB)
  3361  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3362  	{XVBF16GER2PP, 0xfc0007f800000000, 0xec00019000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate XX3-form (xvbf16ger2pp AT,XA,XB)
  3363  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3364  	{XVCVBF16SPN, 0xfc1f07fc00000000, 0xf010076c00000000, 0x0, // VSX Vector Convert bfloat16 to Single-Precision format Non-signaling XX2-form (xvcvbf16spn XT,XB)
  3365  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3366  	{XVCVSPBF16, 0xfc1f07fc00000000, 0xf011076c00000000, 0x0, // VSX Vector Convert with round Single-Precision to bfloat16 format XX2-form (xvcvspbf16 XT,XB)
  3367  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3368  	{XVF16GER2, 0xfc0007f800000000, 0xec00009800000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) XX3-form (xvf16ger2 AT,XA,XB)
  3369  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3370  	{XVF16GER2NN, 0xfc0007f800000000, 0xec00069000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate XX3-form (xvf16ger2nn AT,XA,XB)
  3371  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3372  	{XVF16GER2NP, 0xfc0007f800000000, 0xec00029000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate XX3-form (xvf16ger2np AT,XA,XB)
  3373  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3374  	{XVF16GER2PN, 0xfc0007f800000000, 0xec00049000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate XX3-form (xvf16ger2pn AT,XA,XB)
  3375  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3376  	{XVF16GER2PP, 0xfc0007f800000000, 0xec00009000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate XX3-form (xvf16ger2pp AT,XA,XB)
  3377  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3378  	{XVF32GER, 0xfc0007f800000000, 0xec0000d800000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) XX3-form (xvf32ger AT,XA,XB)
  3379  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3380  	{XVF32GERNN, 0xfc0007f800000000, 0xec0006d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form (xvf32gernn AT,XA,XB)
  3381  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3382  	{XVF32GERNP, 0xfc0007f800000000, 0xec0002d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-form (xvf32gernp AT,XA,XB)
  3383  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3384  	{XVF32GERPN, 0xfc0007f800000000, 0xec0004d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-form (xvf32gerpn AT,XA,XB)
  3385  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3386  	{XVF32GERPP, 0xfc0007f800000000, 0xec0000d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-form (xvf32gerpp AT,XA,XB)
  3387  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3388  	{XVF64GER, 0xfc0007f800000000, 0xec0001d800000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) XX3-form (xvf64ger AT,XAp,XB)
  3389  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3390  	{XVF64GERNN, 0xfc0007f800000000, 0xec0007d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form (xvf64gernn AT,XAp,XB)
  3391  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3392  	{XVF64GERNP, 0xfc0007f800000000, 0xec0003d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-form (xvf64gernp AT,XAp,XB)
  3393  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3394  	{XVF64GERPN, 0xfc0007f800000000, 0xec0005d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-form (xvf64gerpn AT,XAp,XB)
  3395  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3396  	{XVF64GERPP, 0xfc0007f800000000, 0xec0001d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-form (xvf64gerpp AT,XAp,XB)
  3397  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3398  	{XVI16GER2, 0xfc0007f800000000, 0xec00025800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) XX3-form (xvi16ger2 AT,XA,XB)
  3399  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3400  	{XVI16GER2PP, 0xfc0007f800000000, 0xec00035800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate XX3-form (xvi16ger2pp AT,XA,XB)
  3401  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3402  	{XVI16GER2S, 0xfc0007f800000000, 0xec00015800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation XX3-form (xvi16ger2s AT,XA,XB)
  3403  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3404  	{XVI16GER2SPP, 0xfc0007f800000000, 0xec00015000000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate XX3-form (xvi16ger2spp AT,XA,XB)
  3405  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3406  	{XVI4GER8, 0xfc0007f800000000, 0xec00011800000000, 0x60000100000000, // VSX Vector 4-bit Signed Integer GER (rank-8 update) XX3-form (xvi4ger8 AT,XA,XB)
  3407  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3408  	{XVI4GER8PP, 0xfc0007f800000000, 0xec00011000000000, 0x60000100000000, // VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate XX3-form (xvi4ger8pp AT,XA,XB)
  3409  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3410  	{XVI8GER4, 0xfc0007f800000000, 0xec00001800000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) XX3-form (xvi8ger4 AT,XA,XB)
  3411  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3412  	{XVI8GER4PP, 0xfc0007f800000000, 0xec00001000000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate XX3-form (xvi8ger4pp AT,XA,XB)
  3413  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3414  	{XVI8GER4SPP, 0xfc0007f800000000, 0xec00031800000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate XX3-form (xvi8ger4spp AT,XA,XB)
  3415  		[6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3416  	{XVTLSBB, 0xfc1f07fc00000000, 0xf002076c00000000, 0x60000100000000, // VSX Vector Test Least-Significant Bit by Byte XX2-form (xvtlsbb BF,XB)
  3417  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
  3418  	{XXBLENDVB, 0xfff00000fc000030, 0x500000084000000, 0xfffff00000000, // VSX Vector Blend Variable Byte 8RR:XX4-form (xxblendvb XT,XA,XB,XC)
  3419  		[6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}},
  3420  	{XXBLENDVD, 0xfff00000fc000030, 0x500000084000030, 0xfffff00000000, // VSX Vector Blend Variable Doubleword 8RR:XX4-form (xxblendvd XT,XA,XB,XC)
  3421  		[6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}},
  3422  	{XXBLENDVH, 0xfff00000fc000030, 0x500000084000010, 0xfffff00000000, // VSX Vector Blend Variable Halfword 8RR:XX4-form (xxblendvh XT,XA,XB,XC)
  3423  		[6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}},
  3424  	{XXBLENDVW, 0xfff00000fc000030, 0x500000084000020, 0xfffff00000000, // VSX Vector Blend Variable Word 8RR:XX4-form (xxblendvw XT,XA,XB,XC)
  3425  		[6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}},
  3426  	{XXEVAL, 0xfff00000fc000030, 0x500000088000010, 0xfff0000000000, // VSX Vector Evaluate 8RR-XX4-form (xxeval XT,XA,XB,XC,IMM)
  3427  		[6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57, ap_ImmUnsigned_24_31}},
  3428  	{XXGENPCVBM, 0xfc0007fe00000000, 0xf000072800000000, 0x0, // VSX Vector Generate PCV from Byte Mask X-form (xxgenpcvbm XT,VRB,IMM)
  3429  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
  3430  	{XXGENPCVDM, 0xfc0007fe00000000, 0xf000076a00000000, 0x0, // VSX Vector Generate PCV from Doubleword Mask X-form (xxgenpcvdm XT,VRB,IMM)
  3431  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
  3432  	{XXGENPCVHM, 0xfc0007fe00000000, 0xf000072a00000000, 0x0, // VSX Vector Generate PCV from Halfword Mask X-form (xxgenpcvhm XT,VRB,IMM)
  3433  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
  3434  	{XXGENPCVWM, 0xfc0007fe00000000, 0xf000076800000000, 0x0, // VSX Vector Generate PCV from Word Mask X-form (xxgenpcvwm XT,VRB,IMM)
  3435  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
  3436  	{XXMFACC, 0xfc1f07fe00000000, 0x7c00016200000000, 0x60f80100000000, // VSX Move From Accumulator X-form (xxmfacc AS)
  3437  		[6]*argField{ap_MMAReg_6_8}},
  3438  	{XXMTACC, 0xfc1f07fe00000000, 0x7c01016200000000, 0x60f80100000000, // VSX Move To Accumulator X-form (xxmtacc AT)
  3439  		[6]*argField{ap_MMAReg_6_8}},
  3440  	{XXPERMX, 0xfff00000fc000030, 0x500000088000000, 0xffff800000000, // VSX Vector Permute Extended 8RR:XX4-form (xxpermx XT,XA,XB,XC,UIM)
  3441  		[6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57, ap_ImmUnsigned_29_31}},
  3442  	{XXSETACCZ, 0xfc1f07fe00000000, 0x7c03016200000000, 0x60f80100000000, // VSX Set Accumulator to Zero X-form (xxsetaccz AT)
  3443  		[6]*argField{ap_MMAReg_6_8}},
  3444  	{XXSPLTI32DX, 0xfff00000fc1c0000, 0x500000080000000, 0xf000000000000, // VSX Vector Splat Immediate32 Doubleword Indexed 8RR:D-form (xxsplti32dx XT,IX,IMM32)
  3445  		[6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_46_46, ap_ImmUnsigned_16_31_48_63}},
  3446  	{XXSPLTIDP, 0xfff00000fc1e0000, 0x500000080040000, 0xf000000000000, // VSX Vector Splat Immediate Double-Precision 8RR:D-form (xxspltidp XT,IMM32)
  3447  		[6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_16_31_48_63}},
  3448  	{XXSPLTIW, 0xfff00000fc1e0000, 0x500000080060000, 0xf000000000000, // VSX Vector Splat Immediate Word 8RR:D-form (xxspltiw XT,IMM32)
  3449  		[6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_16_31_48_63}},
  3450  	{MSGCLRU, 0xfc0007fe00000000, 0x7c0000dc00000000, 0x3ff000100000000, // Ultravisor Message Clear X-form (msgclru RB)
  3451  		[6]*argField{ap_Reg_16_20}},
  3452  	{MSGSNDU, 0xfc0007fe00000000, 0x7c00009c00000000, 0x3ff000100000000, // Ultravisor Message SendX-form (msgsndu RB)
  3453  		[6]*argField{ap_Reg_16_20}},
  3454  	{URFID, 0xfc0007fe00000000, 0x4c00026400000000, 0x3fff80100000000, // Ultravisor Return From Interrupt Doubleword XL-form (urfid)
  3455  		[6]*argField{}},
  3456  	{ADDEX, 0xfc0001fe00000000, 0x7c00015400000000, 0x100000000, // Add Extended using alternate carry bit Z23-form (addex RT,RA,RB,CY)
  3457  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_21_22}},
  3458  	{MFFSCDRN, 0xfc1f07fe00000000, 0xfc14048e00000000, 0x100000000, // Move From FPSCR Control & Set DRN X-form (mffscdrn FRT,FRB)
  3459  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  3460  	{MFFSCDRNI, 0xfc1f07fe00000000, 0xfc15048e00000000, 0xc00100000000, // Move From FPSCR Control & Set DRN Immediate X-form (mffscdrni FRT,DRM)
  3461  		[6]*argField{ap_FPReg_6_10, ap_ImmUnsigned_18_20}},
  3462  	{MFFSCE, 0xfc1f07fe00000000, 0xfc01048e00000000, 0xf80100000000, // Move From FPSCR & Clear Enables X-form (mffsce FRT)
  3463  		[6]*argField{ap_FPReg_6_10}},
  3464  	{MFFSCRN, 0xfc1f07fe00000000, 0xfc16048e00000000, 0x100000000, // Move From FPSCR Control & Set RN X-form (mffscrn FRT,FRB)
  3465  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  3466  	{MFFSCRNI, 0xfc1f07fe00000000, 0xfc17048e00000000, 0xe00100000000, // Move From FPSCR Control & Set RN Immediate X-form (mffscrni FRT,RM)
  3467  		[6]*argField{ap_FPReg_6_10, ap_ImmUnsigned_19_20}},
  3468  	{MFFSL, 0xfc1f07fe00000000, 0xfc18048e00000000, 0xf80100000000, // Move From FPSCR Lightweight X-form (mffsl FRT)
  3469  		[6]*argField{ap_FPReg_6_10}},
  3470  	{SLBIAG, 0xfc0007fe00000000, 0x7c0006a400000000, 0x1ef80100000000, // SLB Invalidate All Global X-form (slbiag RS, L)
  3471  		[6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
  3472  	{VMSUMUDM, 0xfc00003f00000000, 0x1000002300000000, 0x0, // Vector Multiply-Sum Unsigned Doubleword Modulo VA-form (vmsumudm VRT,VRA,VRB,VRC)
  3473  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  3474  	{ADDPCIS, 0xfc00003e00000000, 0x4c00000400000000, 0x0, // Add PC Immediate Shifted DX-form (addpcis RT,D)
  3475  		[6]*argField{ap_Reg_6_10, ap_ImmSigned_16_25_11_15_31_31}},
  3476  	{BCDCFNCC, 0xfc1f05ff00000000, 0x1007058100000000, 0x0, // Decimal Convert From National VX-form (bcdcfn. VRT,VRB,PS)
  3477  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3478  	{BCDCFSQCC, 0xfc1f05ff00000000, 0x1002058100000000, 0x0, // Decimal Convert From Signed Quadword VX-form (bcdcfsq. VRT,VRB,PS)
  3479  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3480  	{BCDCFZCC, 0xfc1f05ff00000000, 0x1006058100000000, 0x0, // Decimal Convert From Zoned VX-form (bcdcfz. VRT,VRB,PS)
  3481  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3482  	{BCDCPSGNCC, 0xfc0007ff00000000, 0x1000034100000000, 0x0, // Decimal Copy Sign VX-form (bcdcpsgn. VRT,VRA,VRB)
  3483  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3484  	{BCDCTNCC, 0xfc1f05ff00000000, 0x1005058100000000, 0x20000000000, // Decimal Convert To National VX-form (bcdctn. VRT,VRB)
  3485  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3486  	{BCDCTSQCC, 0xfc1f05ff00000000, 0x1000058100000000, 0x20000000000, // Decimal Convert To Signed Quadword VX-form (bcdctsq. VRT,VRB)
  3487  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3488  	{BCDCTZCC, 0xfc1f05ff00000000, 0x1004058100000000, 0x0, // Decimal Convert To Zoned VX-form (bcdctz. VRT,VRB,PS)
  3489  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3490  	{BCDSCC, 0xfc0005ff00000000, 0x100004c100000000, 0x0, // Decimal Shift VX-form (bcds. VRT,VRA,VRB,PS)
  3491  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3492  	{BCDSETSGNCC, 0xfc1f05ff00000000, 0x101f058100000000, 0x0, // Decimal Set Sign VX-form (bcdsetsgn. VRT,VRB,PS)
  3493  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3494  	{BCDSRCC, 0xfc0005ff00000000, 0x100005c100000000, 0x0, // Decimal Shift and Round VX-form (bcdsr. VRT,VRA,VRB,PS)
  3495  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3496  	{BCDTRUNCCC, 0xfc0005ff00000000, 0x1000050100000000, 0x0, // Decimal Truncate VX-form (bcdtrunc. VRT,VRA,VRB,PS)
  3497  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3498  	{BCDUSCC, 0xfc0005ff00000000, 0x1000048100000000, 0x20000000000, // Decimal Unsigned Shift VX-form (bcdus. VRT,VRA,VRB)
  3499  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3500  	{BCDUTRUNCCC, 0xfc0005ff00000000, 0x1000054100000000, 0x20000000000, // Decimal Unsigned Truncate VX-form (bcdutrunc. VRT,VRA,VRB)
  3501  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3502  	{CMPEQB, 0xfc0007fe00000000, 0x7c0001c000000000, 0x60000100000000, // Compare Equal Byte X-form (cmpeqb BF,RA,RB)
  3503  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
  3504  	{CMPRB, 0xfc0007fe00000000, 0x7c00018000000000, 0x40000100000000, // Compare Ranged Byte X-form (cmprb BF,L,RA,RB)
  3505  		[6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
  3506  	{CNTTZD, 0xfc0007ff00000000, 0x7c00047400000000, 0xf80000000000, // Count Trailing Zeros Doubleword X-form (cnttzd RA,RS)
  3507  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  3508  	{CNTTZDCC, 0xfc0007ff00000000, 0x7c00047500000000, 0xf80000000000, // Count Trailing Zeros Doubleword X-form (cnttzd. RA,RS)
  3509  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  3510  	{CNTTZW, 0xfc0007ff00000000, 0x7c00043400000000, 0xf80000000000, // Count Trailing Zeros Word X-form (cnttzw RA,RS)
  3511  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  3512  	{CNTTZWCC, 0xfc0007ff00000000, 0x7c00043500000000, 0xf80000000000, // Count Trailing Zeros Word X-form (cnttzw. RA,RS)
  3513  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  3514  	{COPY, 0xfc2007fe00000000, 0x7c20060c00000000, 0x3c0000100000000, // Copy X-form (copy RA,RB)
  3515  		[6]*argField{ap_Reg_11_15, ap_Reg_16_20}},
  3516  	{CPABORT, 0xfc0007fe00000000, 0x7c00068c00000000, 0x3fff80100000000, // Copy-Paste Abort X-form (cpabort)
  3517  		[6]*argField{}},
  3518  	{DARN, 0xfc0007fe00000000, 0x7c0005e600000000, 0x1cf80100000000, // Deliver A Random Number X-form (darn RT,L)
  3519  		[6]*argField{ap_Reg_6_10, ap_ImmUnsigned_14_15}},
  3520  	{DTSTSFI, 0xfc0007fe00000000, 0xec00054600000000, 0x40000100000000, // DFP Test Significance Immediate X-form (dtstsfi BF,UIM,FRB)
  3521  		[6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_15, ap_FPReg_16_20}},
  3522  	{DTSTSFIQ, 0xfc0007fe00000000, 0xfc00054600000000, 0x40000100000000, // DFP Test Significance Immediate Quad X-form (dtstsfiq BF,UIM,FRBp)
  3523  		[6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_15, ap_FPReg_16_20}},
  3524  	{EXTSWSLI, 0xfc0007fd00000000, 0x7c0006f400000000, 0x0, // Extend Sign Word and Shift Left Immediate XS-form (extswsli RA,RS,SH)
  3525  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
  3526  	{EXTSWSLICC, 0xfc0007fd00000000, 0x7c0006f500000000, 0x0, // Extend Sign Word and Shift Left Immediate XS-form (extswsli. RA,RS,SH)
  3527  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
  3528  	{LDAT, 0xfc0007fe00000000, 0x7c0004cc00000000, 0x100000000, // Load Doubleword ATomic X-form (ldat RT,RA,FC)
  3529  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
  3530  	{LWAT, 0xfc0007fe00000000, 0x7c00048c00000000, 0x100000000, // Load Word ATomic X-form (lwat RT,RA,FC)
  3531  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
  3532  	{LXSD, 0xfc00000300000000, 0xe400000200000000, 0x0, // Load VSX Scalar Doubleword DS-form (lxsd VRT,DS(RA))
  3533  		[6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  3534  	{LXSIBZX, 0xfc0007fe00000000, 0x7c00061a00000000, 0x0, // Load VSX Scalar as Integer Byte & Zero Indexed X-form (lxsibzx XT,RA,RB)
  3535  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3536  	{LXSIHZX, 0xfc0007fe00000000, 0x7c00065a00000000, 0x0, // Load VSX Scalar as Integer Halfword & Zero Indexed X-form (lxsihzx XT,RA,RB)
  3537  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3538  	{LXSSP, 0xfc00000300000000, 0xe400000300000000, 0x0, // Load VSX Scalar Single-Precision DS-form (lxssp VRT,DS(RA))
  3539  		[6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  3540  	{LXV, 0xfc00000700000000, 0xf400000100000000, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA))
  3541  		[6]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
  3542  	{LXVB16X, 0xfc0007fe00000000, 0x7c0006d800000000, 0x0, // Load VSX Vector Byte*16 Indexed X-form (lxvb16x XT,RA,RB)
  3543  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3544  	{LXVH8X, 0xfc0007fe00000000, 0x7c00065800000000, 0x0, // Load VSX Vector Halfword*8 Indexed X-form (lxvh8x XT,RA,RB)
  3545  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3546  	{LXVL, 0xfc0007fe00000000, 0x7c00021a00000000, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB)
  3547  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3548  	{LXVLL, 0xfc0007fe00000000, 0x7c00025a00000000, 0x0, // Load VSX Vector with Length Left-justified X-form (lxvll XT,RA,RB)
  3549  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3550  	{LXVWSX, 0xfc0007fe00000000, 0x7c0002d800000000, 0x0, // Load VSX Vector Word & Splat Indexed X-form (lxvwsx XT,RA,RB)
  3551  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3552  	{LXVX, 0xfc0007be00000000, 0x7c00021800000000, 0x4000000000, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB)
  3553  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3554  	{MADDHD, 0xfc00003f00000000, 0x1000003000000000, 0x0, // Multiply-Add High Doubleword VA-form (maddhd RT,RA,RB,RC)
  3555  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
  3556  	{MADDHDU, 0xfc00003f00000000, 0x1000003100000000, 0x0, // Multiply-Add High Doubleword Unsigned VA-form (maddhdu RT,RA,RB,RC)
  3557  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
  3558  	{MADDLD, 0xfc00003f00000000, 0x1000003300000000, 0x0, // Multiply-Add Low Doubleword VA-form (maddld RT,RA,RB,RC)
  3559  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
  3560  	{MCRXRX, 0xfc0007fe00000000, 0x7c00048000000000, 0x7ff80100000000, // Move to CR from XER Extended X-form (mcrxrx BF)
  3561  		[6]*argField{ap_CondRegField_6_8}},
  3562  	{MFVSRLD, 0xfc0007fe00000000, 0x7c00026600000000, 0xf80000000000, // Move From VSR Lower Doubleword X-form (mfvsrld RA,XS)
  3563  		[6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
  3564  	{MODSD, 0xfc0007fe00000000, 0x7c00061200000000, 0x100000000, // Modulo Signed Doubleword X-form (modsd RT,RA,RB)
  3565  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3566  	{MODSW, 0xfc0007fe00000000, 0x7c00061600000000, 0x100000000, // Modulo Signed Word X-form (modsw RT,RA,RB)
  3567  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3568  	{MODUD, 0xfc0007fe00000000, 0x7c00021200000000, 0x100000000, // Modulo Unsigned Doubleword X-form (modud RT,RA,RB)
  3569  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3570  	{MODUW, 0xfc0007fe00000000, 0x7c00021600000000, 0x100000000, // Modulo Unsigned Word X-form (moduw RT,RA,RB)
  3571  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3572  	{MSGSYNC, 0xfc0007fe00000000, 0x7c0006ec00000000, 0x3fff80100000000, // Message Synchronize X-form (msgsync)
  3573  		[6]*argField{}},
  3574  	{MTVSRDD, 0xfc0007fe00000000, 0x7c00036600000000, 0x0, // Move To VSR Double Doubleword X-form (mtvsrdd XT,RA,RB)
  3575  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3576  	{MTVSRWS, 0xfc0007fe00000000, 0x7c00032600000000, 0xf80000000000, // Move To VSR Word & Splat X-form (mtvsrws XT,RA)
  3577  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
  3578  	{PASTECC, 0xfc0007ff00000000, 0x7c00070d00000000, 0x3c0000000000000, // Paste X-form (paste. RA,RB,L)
  3579  		[6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_10_10}},
  3580  	{SETB, 0xfc0007fe00000000, 0x7c00010000000000, 0x3f80100000000, // Set Boolean X-form (setb RT,BFA)
  3581  		[6]*argField{ap_Reg_6_10, ap_CondRegField_11_13}},
  3582  	{SLBIEG, 0xfc0007fe00000000, 0x7c0003a400000000, 0x1f000100000000, // SLB Invalidate Entry Global X-form (slbieg RS,RB)
  3583  		[6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
  3584  	{SLBSYNC, 0xfc0007fe00000000, 0x7c0002a400000000, 0x3fff80100000000, // SLB Synchronize X-form (slbsync)
  3585  		[6]*argField{}},
  3586  	{STDAT, 0xfc0007fe00000000, 0x7c0005cc00000000, 0x100000000, // Store Doubleword ATomic X-form (stdat RS,RA,FC)
  3587  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
  3588  	{STOP, 0xfc0007fe00000000, 0x4c0002e400000000, 0x3fff80100000000, // Stop XL-form (stop)
  3589  		[6]*argField{}},
  3590  	{STWAT, 0xfc0007fe00000000, 0x7c00058c00000000, 0x100000000, // Store Word ATomic X-form (stwat RS,RA,FC)
  3591  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
  3592  	{STXSD, 0xfc00000300000000, 0xf400000200000000, 0x0, // Store VSX Scalar Doubleword DS-form (stxsd VRS,DS(RA))
  3593  		[6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  3594  	{STXSIBX, 0xfc0007fe00000000, 0x7c00071a00000000, 0x0, // Store VSX Scalar as Integer Byte Indexed X-form (stxsibx XS,RA,RB)
  3595  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3596  	{STXSIHX, 0xfc0007fe00000000, 0x7c00075a00000000, 0x0, // Store VSX Scalar as Integer Halfword Indexed X-form (stxsihx XS,RA,RB)
  3597  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3598  	{STXSSP, 0xfc00000300000000, 0xf400000300000000, 0x0, // Store VSX Scalar Single DS-form (stxssp VRS,DS(RA))
  3599  		[6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  3600  	{STXV, 0xfc00000700000000, 0xf400000500000000, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA))
  3601  		[6]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
  3602  	{STXVB16X, 0xfc0007fe00000000, 0x7c0007d800000000, 0x0, // Store VSX Vector Byte*16 Indexed X-form (stxvb16x XS,RA,RB)
  3603  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3604  	{STXVH8X, 0xfc0007fe00000000, 0x7c00075800000000, 0x0, // Store VSX Vector Halfword*8 Indexed X-form (stxvh8x XS,RA,RB)
  3605  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3606  	{STXVL, 0xfc0007fe00000000, 0x7c00031a00000000, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB)
  3607  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3608  	{STXVLL, 0xfc0007fe00000000, 0x7c00035a00000000, 0x0, // Store VSX Vector with Length Left-justified X-form (stxvll XS,RA,RB)
  3609  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3610  	{STXVX, 0xfc0007fe00000000, 0x7c00031800000000, 0x0, // Store VSX Vector Indexed X-form (stxvx XS,RA,RB)
  3611  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3612  	{VABSDUB, 0xfc0007ff00000000, 0x1000040300000000, 0x0, // Vector Absolute Difference Unsigned Byte VX-form (vabsdub VRT,VRA,VRB)
  3613  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3614  	{VABSDUH, 0xfc0007ff00000000, 0x1000044300000000, 0x0, // Vector Absolute Difference Unsigned Halfword VX-form (vabsduh VRT,VRA,VRB)
  3615  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3616  	{VABSDUW, 0xfc0007ff00000000, 0x1000048300000000, 0x0, // Vector Absolute Difference Unsigned Word VX-form (vabsduw VRT,VRA,VRB)
  3617  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3618  	{VBPERMD, 0xfc0007ff00000000, 0x100005cc00000000, 0x0, // Vector Bit Permute Doubleword VX-form (vbpermd VRT,VRA,VRB)
  3619  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3620  	{VCLZLSBB, 0xfc1f07ff00000000, 0x1000060200000000, 0x0, // Vector Count Leading Zero Least-Significant Bits Byte VX-form (vclzlsbb RT,VRB)
  3621  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
  3622  	{VCMPNEB, 0xfc0007ff00000000, 0x1000000700000000, 0x0, // Vector Compare Not Equal Byte VC-form (vcmpneb VRT,VRA,VRB)
  3623  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3624  	{VCMPNEBCC, 0xfc0007ff00000000, 0x1000040700000000, 0x0, // Vector Compare Not Equal Byte VC-form (vcmpneb. VRT,VRA,VRB)
  3625  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3626  	{VCMPNEH, 0xfc0007ff00000000, 0x1000004700000000, 0x0, // Vector Compare Not Equal Halfword VC-form (vcmpneh VRT,VRA,VRB)
  3627  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3628  	{VCMPNEHCC, 0xfc0007ff00000000, 0x1000044700000000, 0x0, // Vector Compare Not Equal Halfword VC-form (vcmpneh. VRT,VRA,VRB)
  3629  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3630  	{VCMPNEW, 0xfc0007ff00000000, 0x1000008700000000, 0x0, // Vector Compare Not Equal Word VC-form (vcmpnew VRT,VRA,VRB)
  3631  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3632  	{VCMPNEWCC, 0xfc0007ff00000000, 0x1000048700000000, 0x0, // Vector Compare Not Equal Word VC-form (vcmpnew. VRT,VRA,VRB)
  3633  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3634  	{VCMPNEZB, 0xfc0007ff00000000, 0x1000010700000000, 0x0, // Vector Compare Not Equal or Zero Byte VC-form (vcmpnezb VRT,VRA,VRB)
  3635  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3636  	{VCMPNEZBCC, 0xfc0007ff00000000, 0x1000050700000000, 0x0, // Vector Compare Not Equal or Zero Byte VC-form (vcmpnezb. VRT,VRA,VRB)
  3637  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3638  	{VCMPNEZH, 0xfc0007ff00000000, 0x1000014700000000, 0x0, // Vector Compare Not Equal or Zero Halfword VC-form (vcmpnezh VRT,VRA,VRB)
  3639  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3640  	{VCMPNEZHCC, 0xfc0007ff00000000, 0x1000054700000000, 0x0, // Vector Compare Not Equal or Zero Halfword VC-form (vcmpnezh. VRT,VRA,VRB)
  3641  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3642  	{VCMPNEZW, 0xfc0007ff00000000, 0x1000018700000000, 0x0, // Vector Compare Not Equal or Zero Word VC-form (vcmpnezw VRT,VRA,VRB)
  3643  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3644  	{VCMPNEZWCC, 0xfc0007ff00000000, 0x1000058700000000, 0x0, // Vector Compare Not Equal or Zero Word VC-form (vcmpnezw. VRT,VRA,VRB)
  3645  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3646  	{VCTZB, 0xfc1f07ff00000000, 0x101c060200000000, 0x0, // Vector Count Trailing Zeros Byte VX-form (vctzb VRT,VRB)
  3647  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3648  	{VCTZD, 0xfc1f07ff00000000, 0x101f060200000000, 0x0, // Vector Count Trailing Zeros Doubleword VX-form (vctzd VRT,VRB)
  3649  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3650  	{VCTZH, 0xfc1f07ff00000000, 0x101d060200000000, 0x0, // Vector Count Trailing Zeros Halfword VX-form (vctzh VRT,VRB)
  3651  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3652  	{VCTZLSBB, 0xfc1f07ff00000000, 0x1001060200000000, 0x0, // Vector Count Trailing Zero Least-Significant Bits Byte VX-form (vctzlsbb RT,VRB)
  3653  		[6]*argField{ap_Reg_6_10, ap_VecReg_16_20}},
  3654  	{VCTZW, 0xfc1f07ff00000000, 0x101e060200000000, 0x0, // Vector Count Trailing Zeros Word VX-form (vctzw VRT,VRB)
  3655  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3656  	{VEXTRACTD, 0xfc0007ff00000000, 0x100002cd00000000, 0x10000000000000, // Vector Extract Doubleword to VSR using immediate-specified index VX-form (vextractd VRT,VRB,UIM)
  3657  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  3658  	{VEXTRACTUB, 0xfc0007ff00000000, 0x1000020d00000000, 0x10000000000000, // Vector Extract Unsigned Byte to VSR using immediate-specified index VX-form (vextractub VRT,VRB,UIM)
  3659  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  3660  	{VEXTRACTUH, 0xfc0007ff00000000, 0x1000024d00000000, 0x10000000000000, // Vector Extract Unsigned Halfword to VSR using immediate-specified index VX-form (vextractuh VRT,VRB,UIM)
  3661  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  3662  	{VEXTRACTUW, 0xfc0007ff00000000, 0x1000028d00000000, 0x10000000000000, // Vector Extract Unsigned Word to VSR using immediate-specified index VX-form (vextractuw VRT,VRB,UIM)
  3663  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  3664  	{VEXTSB2D, 0xfc1f07ff00000000, 0x1018060200000000, 0x0, // Vector Extend Sign Byte To Doubleword VX-form (vextsb2d VRT,VRB)
  3665  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3666  	{VEXTSB2W, 0xfc1f07ff00000000, 0x1010060200000000, 0x0, // Vector Extend Sign Byte To Word VX-form (vextsb2w VRT,VRB)
  3667  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3668  	{VEXTSH2D, 0xfc1f07ff00000000, 0x1019060200000000, 0x0, // Vector Extend Sign Halfword To Doubleword VX-form (vextsh2d VRT,VRB)
  3669  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3670  	{VEXTSH2W, 0xfc1f07ff00000000, 0x1011060200000000, 0x0, // Vector Extend Sign Halfword To Word VX-form (vextsh2w VRT,VRB)
  3671  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3672  	{VEXTSW2D, 0xfc1f07ff00000000, 0x101a060200000000, 0x0, // Vector Extend Sign Word To Doubleword VX-form (vextsw2d VRT,VRB)
  3673  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3674  	{VEXTUBLX, 0xfc0007ff00000000, 0x1000060d00000000, 0x0, // Vector Extract Unsigned Byte to GPR using GPR-specified Left-Index VX-form (vextublx RT,RA,VRB)
  3675  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3676  	{VEXTUBRX, 0xfc0007ff00000000, 0x1000070d00000000, 0x0, // Vector Extract Unsigned Byte to GPR using GPR-specified Right-Index VX-form (vextubrx RT,RA,VRB)
  3677  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3678  	{VEXTUHLX, 0xfc0007ff00000000, 0x1000064d00000000, 0x0, // Vector Extract Unsigned Halfword to GPR using GPR-specified Left-Index VX-form (vextuhlx RT,RA,VRB)
  3679  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3680  	{VEXTUHRX, 0xfc0007ff00000000, 0x1000074d00000000, 0x0, // Vector Extract Unsigned Halfword to GPR using GPR-specified Right-Index VX-form (vextuhrx RT,RA,VRB)
  3681  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3682  	{VEXTUWLX, 0xfc0007ff00000000, 0x1000068d00000000, 0x0, // Vector Extract Unsigned Word to GPR using GPR-specified Left-Index VX-form (vextuwlx RT,RA,VRB)
  3683  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3684  	{VEXTUWRX, 0xfc0007ff00000000, 0x1000078d00000000, 0x0, // Vector Extract Unsigned Word to GPR using GPR-specified Right-Index VX-form (vextuwrx RT,RA,VRB)
  3685  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}},
  3686  	{VINSERTB, 0xfc0007ff00000000, 0x1000030d00000000, 0x10000000000000, // Vector Insert Byte from VSR using immediate-specified index VX-form (vinsertb VRT,VRB,UIM)
  3687  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  3688  	{VINSERTD, 0xfc0007ff00000000, 0x100003cd00000000, 0x10000000000000, // Vector Insert Doubleword from VSR using immediate-specified index VX-form (vinsertd VRT,VRB,UIM)
  3689  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  3690  	{VINSERTH, 0xfc0007ff00000000, 0x1000034d00000000, 0x10000000000000, // Vector Insert Halfword from VSR using immediate-specified index VX-form (vinserth VRT,VRB,UIM)
  3691  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  3692  	{VINSERTW, 0xfc0007ff00000000, 0x1000038d00000000, 0x10000000000000, // Vector Insert Word from VSR using immediate-specified index VX-form (vinsertw VRT,VRB,UIM)
  3693  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  3694  	{VMUL10CUQ, 0xfc0007ff00000000, 0x1000000100000000, 0xf80000000000, // Vector Multiply-by-10 & write Carry-out Unsigned Quadword VX-form (vmul10cuq VRT,VRA)
  3695  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
  3696  	{VMUL10ECUQ, 0xfc0007ff00000000, 0x1000004100000000, 0x0, // Vector Multiply-by-10 Extended & write Carry-out Unsigned Quadword VX-form (vmul10ecuq VRT,VRA,VRB)
  3697  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3698  	{VMUL10EUQ, 0xfc0007ff00000000, 0x1000024100000000, 0x0, // Vector Multiply-by-10 Extended Unsigned Quadword VX-form (vmul10euq VRT,VRA,VRB)
  3699  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3700  	{VMUL10UQ, 0xfc0007ff00000000, 0x1000020100000000, 0xf80000000000, // Vector Multiply-by-10 Unsigned Quadword VX-form (vmul10uq VRT,VRA)
  3701  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
  3702  	{VNEGD, 0xfc1f07ff00000000, 0x1007060200000000, 0x0, // Vector Negate Doubleword VX-form (vnegd VRT,VRB)
  3703  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3704  	{VNEGW, 0xfc1f07ff00000000, 0x1006060200000000, 0x0, // Vector Negate Word VX-form (vnegw VRT,VRB)
  3705  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3706  	{VPERMR, 0xfc00003f00000000, 0x1000003b00000000, 0x0, // Vector Permute Right-indexed VA-form (vpermr VRT,VRA,VRB,VRC)
  3707  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  3708  	{VPRTYBD, 0xfc1f07ff00000000, 0x1009060200000000, 0x0, // Vector Parity Byte Doubleword VX-form (vprtybd VRT,VRB)
  3709  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3710  	{VPRTYBQ, 0xfc1f07ff00000000, 0x100a060200000000, 0x0, // Vector Parity Byte Quadword VX-form (vprtybq VRT,VRB)
  3711  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3712  	{VPRTYBW, 0xfc1f07ff00000000, 0x1008060200000000, 0x0, // Vector Parity Byte Word VX-form (vprtybw VRT,VRB)
  3713  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3714  	{VRLDMI, 0xfc0007ff00000000, 0x100000c500000000, 0x0, // Vector Rotate Left Doubleword then Mask Insert VX-form (vrldmi VRT,VRA,VRB)
  3715  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3716  	{VRLDNM, 0xfc0007ff00000000, 0x100001c500000000, 0x0, // Vector Rotate Left Doubleword then AND with Mask VX-form (vrldnm VRT,VRA,VRB)
  3717  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3718  	{VRLWMI, 0xfc0007ff00000000, 0x1000008500000000, 0x0, // Vector Rotate Left Word then Mask Insert VX-form (vrlwmi VRT,VRA,VRB)
  3719  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3720  	{VRLWNM, 0xfc0007ff00000000, 0x1000018500000000, 0x0, // Vector Rotate Left Word then AND with Mask VX-form (vrlwnm VRT,VRA,VRB)
  3721  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3722  	{VSLV, 0xfc0007ff00000000, 0x1000074400000000, 0x0, // Vector Shift Left Variable VX-form (vslv VRT,VRA,VRB)
  3723  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3724  	{VSRV, 0xfc0007ff00000000, 0x1000070400000000, 0x0, // Vector Shift Right Variable VX-form (vsrv VRT,VRA,VRB)
  3725  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3726  	{WAIT, 0xfc0007fe00000000, 0x7c00003c00000000, 0x9cf80100000000, // Wait X-form (wait WC,PL)
  3727  		[6]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_14_15}},
  3728  	{XSABSQP, 0xfc1f07fe00000000, 0xfc00064800000000, 0x100000000, // VSX Scalar Absolute Quad-Precision X-form (xsabsqp VRT,VRB)
  3729  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3730  	{XSADDQP, 0xfc0007ff00000000, 0xfc00000800000000, 0x0, // VSX Scalar Add Quad-Precision [using round to Odd] X-form (xsaddqp VRT,VRA,VRB)
  3731  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3732  	{XSADDQPO, 0xfc0007ff00000000, 0xfc00000900000000, 0x0, // VSX Scalar Add Quad-Precision [using round to Odd] X-form (xsaddqpo VRT,VRA,VRB)
  3733  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3734  	{XSCMPEQDP, 0xfc0007f800000000, 0xf000001800000000, 0x0, // VSX Scalar Compare Equal Double-Precision XX3-form (xscmpeqdp XT,XA,XB)
  3735  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3736  	{XSCMPEXPDP, 0xfc0007f800000000, 0xf00001d800000000, 0x60000100000000, // VSX Scalar Compare Exponents Double-Precision XX3-form (xscmpexpdp BF,XA,XB)
  3737  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3738  	{XSCMPEXPQP, 0xfc0007fe00000000, 0xfc00014800000000, 0x60000100000000, // VSX Scalar Compare Exponents Quad-Precision X-form (xscmpexpqp BF,VRA,VRB)
  3739  		[6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
  3740  	{XSCMPGEDP, 0xfc0007f800000000, 0xf000009800000000, 0x0, // VSX Scalar Compare Greater Than or Equal Double-Precision XX3-form (xscmpgedp XT,XA,XB)
  3741  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3742  	{XSCMPGTDP, 0xfc0007f800000000, 0xf000005800000000, 0x0, // VSX Scalar Compare Greater Than Double-Precision XX3-form (xscmpgtdp XT,XA,XB)
  3743  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3744  	{XSCMPOQP, 0xfc0007fe00000000, 0xfc00010800000000, 0x60000100000000, // VSX Scalar Compare Ordered Quad-Precision X-form (xscmpoqp BF,VRA,VRB)
  3745  		[6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
  3746  	{XSCMPUQP, 0xfc0007fe00000000, 0xfc00050800000000, 0x60000100000000, // VSX Scalar Compare Unordered Quad-Precision X-form (xscmpuqp BF,VRA,VRB)
  3747  		[6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}},
  3748  	{XSCPSGNQP, 0xfc0007fe00000000, 0xfc0000c800000000, 0x100000000, // VSX Scalar Copy Sign Quad-Precision X-form (xscpsgnqp VRT,VRA,VRB)
  3749  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3750  	{XSCVDPHP, 0xfc1f07fc00000000, 0xf011056c00000000, 0x0, // VSX Scalar Convert with round Double-Precision to Half-Precision format XX2-form (xscvdphp XT,XB)
  3751  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3752  	{XSCVDPQP, 0xfc1f07fe00000000, 0xfc16068800000000, 0x100000000, // VSX Scalar Convert Double-Precision to Quad-Precision format X-form (xscvdpqp VRT,VRB)
  3753  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3754  	{XSCVHPDP, 0xfc1f07fc00000000, 0xf010056c00000000, 0x0, // VSX Scalar Convert Half-Precision to Double-Precision format XX2-form (xscvhpdp XT,XB)
  3755  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3756  	{XSCVQPDP, 0xfc1f07ff00000000, 0xfc14068800000000, 0x0, // VSX Scalar Convert with round Quad-Precision to Double-Precision format [using round to Odd] X-form (xscvqpdp VRT,VRB)
  3757  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3758  	{XSCVQPDPO, 0xfc1f07ff00000000, 0xfc14068900000000, 0x0, // VSX Scalar Convert with round Quad-Precision to Double-Precision format [using round to Odd] X-form (xscvqpdpo VRT,VRB)
  3759  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3760  	{XSCVQPSDZ, 0xfc1f07fe00000000, 0xfc19068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format X-form (xscvqpsdz VRT,VRB)
  3761  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3762  	{XSCVQPSWZ, 0xfc1f07fe00000000, 0xfc09068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Word format X-form (xscvqpswz VRT,VRB)
  3763  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3764  	{XSCVQPUDZ, 0xfc1f07fe00000000, 0xfc11068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format X-form (xscvqpudz VRT,VRB)
  3765  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3766  	{XSCVQPUWZ, 0xfc1f07fe00000000, 0xfc01068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format X-form (xscvqpuwz VRT,VRB)
  3767  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3768  	{XSCVSDQP, 0xfc1f07fe00000000, 0xfc0a068800000000, 0x100000000, // VSX Scalar Convert Signed Doubleword to Quad-Precision format X-form (xscvsdqp VRT,VRB)
  3769  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3770  	{XSCVUDQP, 0xfc1f07fe00000000, 0xfc02068800000000, 0x100000000, // VSX Scalar Convert Unsigned Doubleword to Quad-Precision format X-form (xscvudqp VRT,VRB)
  3771  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3772  	{XSDIVQP, 0xfc0007ff00000000, 0xfc00044800000000, 0x0, // VSX Scalar Divide Quad-Precision [using round to Odd] X-form (xsdivqp VRT,VRA,VRB)
  3773  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3774  	{XSDIVQPO, 0xfc0007ff00000000, 0xfc00044900000000, 0x0, // VSX Scalar Divide Quad-Precision [using round to Odd] X-form (xsdivqpo VRT,VRA,VRB)
  3775  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3776  	{XSIEXPDP, 0xfc0007fe00000000, 0xf000072c00000000, 0x0, // VSX Scalar Insert Exponent Double-Precision X-form (xsiexpdp XT,RA,RB)
  3777  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3778  	{XSIEXPQP, 0xfc0007fe00000000, 0xfc0006c800000000, 0x100000000, // VSX Scalar Insert Exponent Quad-Precision X-form (xsiexpqp VRT,VRA,VRB)
  3779  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3780  	{XSMADDQP, 0xfc0007ff00000000, 0xfc00030800000000, 0x0, // VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-form (xsmaddqp VRT,VRA,VRB)
  3781  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3782  	{XSMADDQPO, 0xfc0007ff00000000, 0xfc00030900000000, 0x0, // VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-form (xsmaddqpo VRT,VRA,VRB)
  3783  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3784  	{XSMAXCDP, 0xfc0007f800000000, 0xf000040000000000, 0x0, // VSX Scalar Maximum Type-C Double-Precision XX3-form (xsmaxcdp XT,XA,XB)
  3785  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3786  	{XSMAXJDP, 0xfc0007f800000000, 0xf000048000000000, 0x0, // VSX Scalar Maximum Type-J Double-Precision XX3-form (xsmaxjdp XT,XA,XB)
  3787  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3788  	{XSMINCDP, 0xfc0007f800000000, 0xf000044000000000, 0x0, // VSX Scalar Minimum Type-C Double-Precision XX3-form (xsmincdp XT,XA,XB)
  3789  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3790  	{XSMINJDP, 0xfc0007f800000000, 0xf00004c000000000, 0x0, // VSX Scalar Minimum Type-J Double-Precision XX3-form (xsminjdp XT,XA,XB)
  3791  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3792  	{XSMSUBQP, 0xfc0007ff00000000, 0xfc00034800000000, 0x0, // VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsmsubqp VRT,VRA,VRB)
  3793  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3794  	{XSMSUBQPO, 0xfc0007ff00000000, 0xfc00034900000000, 0x0, // VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsmsubqpo VRT,VRA,VRB)
  3795  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3796  	{XSMULQP, 0xfc0007ff00000000, 0xfc00004800000000, 0x0, // VSX Scalar Multiply Quad-Precision [using round to Odd] X-form (xsmulqp VRT,VRA,VRB)
  3797  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3798  	{XSMULQPO, 0xfc0007ff00000000, 0xfc00004900000000, 0x0, // VSX Scalar Multiply Quad-Precision [using round to Odd] X-form (xsmulqpo VRT,VRA,VRB)
  3799  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3800  	{XSNABSQP, 0xfc1f07fe00000000, 0xfc08064800000000, 0x0, // VSX Scalar Negative Absolute Quad-Precision X-form (xsnabsqp VRT,VRB)
  3801  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3802  	{XSNEGQP, 0xfc1f07fe00000000, 0xfc10064800000000, 0x100000000, // VSX Scalar Negate Quad-Precision X-form (xsnegqp VRT,VRB)
  3803  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3804  	{XSNMADDQP, 0xfc0007ff00000000, 0xfc00038800000000, 0x0, // VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-form (xsnmaddqp VRT,VRA,VRB)
  3805  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3806  	{XSNMADDQPO, 0xfc0007ff00000000, 0xfc00038900000000, 0x0, // VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-form (xsnmaddqpo VRT,VRA,VRB)
  3807  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3808  	{XSNMSUBQP, 0xfc0007ff00000000, 0xfc0003c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsnmsubqp VRT,VRA,VRB)
  3809  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3810  	{XSNMSUBQPO, 0xfc0007ff00000000, 0xfc0003c900000000, 0x0, // VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsnmsubqpo VRT,VRA,VRB)
  3811  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3812  	{XSRQPI, 0xfc0001ff00000000, 0xfc00000a00000000, 0x1e000000000000, // VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-form (xsrqpi R,VRT,VRB,RMC)
  3813  		[6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}},
  3814  	{XSRQPIX, 0xfc0001ff00000000, 0xfc00000b00000000, 0x1e000000000000, // VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-form (xsrqpix R,VRT,VRB,RMC)
  3815  		[6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}},
  3816  	{XSRQPXP, 0xfc0001fe00000000, 0xfc00004a00000000, 0x1e000100000000, // VSX Scalar Round Quad-Precision to Double-Extended Precision Z23-form (xsrqpxp R,VRT,VRB,RMC)
  3817  		[6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}},
  3818  	{XSSQRTQP, 0xfc1f07ff00000000, 0xfc1b064800000000, 0x0, // VSX Scalar Square Root Quad-Precision [using round to Odd] X-form (xssqrtqp VRT,VRB)
  3819  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3820  	{XSSQRTQPO, 0xfc1f07ff00000000, 0xfc1b064900000000, 0x0, // VSX Scalar Square Root Quad-Precision [using round to Odd] X-form (xssqrtqpo VRT,VRB)
  3821  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3822  	{XSSUBQP, 0xfc0007ff00000000, 0xfc00040800000000, 0x0, // VSX Scalar Subtract Quad-Precision [using round to Odd] X-form (xssubqp VRT,VRA,VRB)
  3823  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3824  	{XSSUBQPO, 0xfc0007ff00000000, 0xfc00040900000000, 0x0, // VSX Scalar Subtract Quad-Precision [using round to Odd] X-form (xssubqpo VRT,VRA,VRB)
  3825  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3826  	{XSTSTDCDP, 0xfc0007fc00000000, 0xf00005a800000000, 0x100000000, // VSX Scalar Test Data Class Double-Precision XX2-form (xststdcdp BF,XB,DCMX)
  3827  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_9_15}},
  3828  	{XSTSTDCQP, 0xfc0007fe00000000, 0xfc00058800000000, 0x100000000, // VSX Scalar Test Data Class Quad-Precision X-form (xststdcqp BF,VRB,DCMX)
  3829  		[6]*argField{ap_CondRegField_6_8, ap_VecReg_16_20, ap_ImmUnsigned_9_15}},
  3830  	{XSTSTDCSP, 0xfc0007fc00000000, 0xf00004a800000000, 0x100000000, // VSX Scalar Test Data Class Single-Precision XX2-form (xststdcsp BF,XB,DCMX)
  3831  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_9_15}},
  3832  	{XSXEXPDP, 0xfc1f07fc00000000, 0xf000056c00000000, 0x100000000, // VSX Scalar Extract Exponent Double-Precision XX2-form (xsxexpdp RT,XB)
  3833  		[6]*argField{ap_Reg_6_10, ap_VecSReg_30_30_16_20}},
  3834  	{XSXEXPQP, 0xfc1f07fe00000000, 0xfc02064800000000, 0x100000000, // VSX Scalar Extract Exponent Quad-Precision X-form (xsxexpqp VRT,VRB)
  3835  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3836  	{XSXSIGDP, 0xfc1f07fc00000000, 0xf001056c00000000, 0x100000000, // VSX Scalar Extract Significand Double-Precision XX2-form (xsxsigdp RT,XB)
  3837  		[6]*argField{ap_Reg_6_10, ap_VecSReg_30_30_16_20}},
  3838  	{XSXSIGQP, 0xfc1f07fe00000000, 0xfc12064800000000, 0x100000000, // VSX Scalar Extract Significand Quad-Precision X-form (xsxsigqp VRT,VRB)
  3839  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3840  	{XVCVHPSP, 0xfc1f07fc00000000, 0xf018076c00000000, 0x0, // VSX Vector Convert Half-Precision to Single-Precision format XX2-form (xvcvhpsp XT,XB)
  3841  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3842  	{XVCVSPHP, 0xfc1f07fc00000000, 0xf019076c00000000, 0x0, // VSX Vector Convert with round Single-Precision to Half-Precision format XX2-form (xvcvsphp XT,XB)
  3843  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3844  	{XVIEXPDP, 0xfc0007f800000000, 0xf00007c000000000, 0x0, // VSX Vector Insert Exponent Double-Precision XX3-form (xviexpdp XT,XA,XB)
  3845  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3846  	{XVIEXPSP, 0xfc0007f800000000, 0xf00006c000000000, 0x0, // VSX Vector Insert Exponent Single-Precision XX3-form (xviexpsp XT,XA,XB)
  3847  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3848  	{XVTSTDCDP, 0xfc0007b800000000, 0xf00007a800000000, 0x0, // VSX Vector Test Data Class Double-Precision XX2-form (xvtstdcdp XT,XB,DCMX)
  3849  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_25_25_29_29_11_15}},
  3850  	{XVTSTDCSP, 0xfc0007b800000000, 0xf00006a800000000, 0x0, // VSX Vector Test Data Class Single-Precision XX2-form (xvtstdcsp XT,XB,DCMX)
  3851  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_25_25_29_29_11_15}},
  3852  	{XVXEXPDP, 0xfc1f07fc00000000, 0xf000076c00000000, 0x0, // VSX Vector Extract Exponent Double-Precision XX2-form (xvxexpdp XT,XB)
  3853  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3854  	{XVXEXPSP, 0xfc1f07fc00000000, 0xf008076c00000000, 0x0, // VSX Vector Extract Exponent Single-Precision XX2-form (xvxexpsp XT,XB)
  3855  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3856  	{XVXSIGDP, 0xfc1f07fc00000000, 0xf001076c00000000, 0x0, // VSX Vector Extract Significand Double-Precision XX2-form (xvxsigdp XT,XB)
  3857  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3858  	{XVXSIGSP, 0xfc1f07fc00000000, 0xf009076c00000000, 0x0, // VSX Vector Extract Significand Single-Precision XX2-form (xvxsigsp XT,XB)
  3859  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3860  	{XXBRD, 0xfc1f07fc00000000, 0xf017076c00000000, 0x0, // VSX Vector Byte-Reverse Doubleword XX2-form (xxbrd XT,XB)
  3861  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3862  	{XXBRH, 0xfc1f07fc00000000, 0xf007076c00000000, 0x0, // VSX Vector Byte-Reverse Halfword XX2-form (xxbrh XT,XB)
  3863  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3864  	{XXBRQ, 0xfc1f07fc00000000, 0xf01f076c00000000, 0x0, // VSX Vector Byte-Reverse Quadword XX2-form (xxbrq XT,XB)
  3865  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3866  	{XXBRW, 0xfc1f07fc00000000, 0xf00f076c00000000, 0x0, // VSX Vector Byte-Reverse Word XX2-form (xxbrw XT,XB)
  3867  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  3868  	{XXEXTRACTUW, 0xfc0007fc00000000, 0xf000029400000000, 0x10000000000000, // VSX Vector Extract Unsigned Word XX2-form (xxextractuw XT,XB,UIM)
  3869  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_12_15}},
  3870  	{XXINSERTW, 0xfc0007fc00000000, 0xf00002d400000000, 0x10000000000000, // VSX Vector Insert Word XX2-form (xxinsertw XT,XB,UIM)
  3871  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_12_15}},
  3872  	{XXPERM, 0xfc0007f800000000, 0xf00000d000000000, 0x0, // VSX Vector Permute XX3-form (xxperm XT,XA,XB)
  3873  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3874  	{XXPERMR, 0xfc0007f800000000, 0xf00001d000000000, 0x0, // VSX Vector Permute Right-indexed XX3-form (xxpermr XT,XA,XB)
  3875  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  3876  	{XXSPLTIB, 0xfc1807fe00000000, 0xf00002d000000000, 0x0, // VSX Vector Splat Immediate Byte X-form (xxspltib XT,IMM8)
  3877  		[6]*argField{ap_VecSReg_31_31_6_10, ap_ImmUnsigned_13_20}},
  3878  	{BCDADDCC, 0xfc0005ff00000000, 0x1000040100000000, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS)
  3879  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3880  	{BCDSUBCC, 0xfc0005ff00000000, 0x1000044100000000, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS)
  3881  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
  3882  	{BCTAR, 0xfc0007ff00000000, 0x4c00046000000000, 0xe00000000000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH)
  3883  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
  3884  	{BCTARL, 0xfc0007ff00000000, 0x4c00046100000000, 0xe00000000000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH)
  3885  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
  3886  	{CLRBHRB, 0xfc0007fe00000000, 0x7c00035c00000000, 0x3fff80100000000, // Clear BHRB X-form (clrbhrb)
  3887  		[6]*argField{}},
  3888  	{FMRGEW, 0xfc0007fe00000000, 0xfc00078c00000000, 0x100000000, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB)
  3889  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  3890  	{FMRGOW, 0xfc0007fe00000000, 0xfc00068c00000000, 0x100000000, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB)
  3891  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  3892  	{ICBT, 0xfc0007fe00000000, 0x7c00002c00000000, 0x200000100000000, // Instruction Cache Block Touch X-form (icbt CT, RA, RB)
  3893  		[6]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
  3894  	{LQARX, 0xfc0007fe00000000, 0x7c00022800000000, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH)
  3895  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
  3896  	{LXSIWAX, 0xfc0007fe00000000, 0x7c00009800000000, 0x0, // Load VSX Scalar as Integer Word Algebraic Indexed X-form (lxsiwax XT,RA,RB)
  3897  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3898  	{LXSIWZX, 0xfc0007fe00000000, 0x7c00001800000000, 0x0, // Load VSX Scalar as Integer Word & Zero Indexed X-form (lxsiwzx XT,RA,RB)
  3899  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3900  	{LXSSPX, 0xfc0007fe00000000, 0x7c00041800000000, 0x0, // Load VSX Scalar Single-Precision Indexed X-form (lxsspx XT,RA,RB)
  3901  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3902  	{MFBHRBE, 0xfc0007fe00000000, 0x7c00025c00000000, 0x100000000, // Move From BHRB XFX-form (mfbhrbe RT,BHRBE)
  3903  		[6]*argField{ap_Reg_6_10, ap_ImmUnsigned_11_20}},
  3904  	{MFVSRD, 0xfc0007fe00000000, 0x7c00006600000000, 0xf80000000000, // Move From VSR Doubleword X-form (mfvsrd RA,XS)
  3905  		[6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
  3906  	{MFVSRWZ, 0xfc0007fe00000000, 0x7c0000e600000000, 0xf80000000000, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS)
  3907  		[6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
  3908  	{MSGCLR, 0xfc0007fe00000000, 0x7c0001dc00000000, 0x3ff000100000000, // Message Clear X-form (msgclr RB)
  3909  		[6]*argField{ap_Reg_16_20}},
  3910  	{MSGCLRP, 0xfc0007fe00000000, 0x7c00015c00000000, 0x3ff000100000000, // Message Clear Privileged X-form (msgclrp RB)
  3911  		[6]*argField{ap_Reg_16_20}},
  3912  	{MSGSND, 0xfc0007fe00000000, 0x7c00019c00000000, 0x3ff000100000000, // Message Send X-form (msgsnd RB)
  3913  		[6]*argField{ap_Reg_16_20}},
  3914  	{MSGSNDP, 0xfc0007fe00000000, 0x7c00011c00000000, 0x3ff000100000000, // Message Send Privileged X-form (msgsndp RB)
  3915  		[6]*argField{ap_Reg_16_20}},
  3916  	{MTVSRD, 0xfc0007fe00000000, 0x7c00016600000000, 0xf80000000000, // Move To VSR Doubleword X-form (mtvsrd XT,RA)
  3917  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
  3918  	{MTVSRWA, 0xfc0007fe00000000, 0x7c0001a600000000, 0xf80000000000, // Move To VSR Word Algebraic X-form (mtvsrwa XT,RA)
  3919  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
  3920  	{MTVSRWZ, 0xfc0007fe00000000, 0x7c0001e600000000, 0xf80000000000, // Move To VSR Word and Zero X-form (mtvsrwz XT,RA)
  3921  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
  3922  	{RFEBB, 0xfc0007fe00000000, 0x4c00012400000000, 0x3fff00100000000, // Return from Event Based Branch XL-form (rfebb S)
  3923  		[6]*argField{ap_ImmUnsigned_20_20}},
  3924  	{STQCXCC, 0xfc0007ff00000000, 0x7c00016d00000000, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB)
  3925  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3926  	{STXSIWX, 0xfc0007fe00000000, 0x7c00011800000000, 0x0, // Store VSX Scalar as Integer Word Indexed X-form (stxsiwx XS,RA,RB)
  3927  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3928  	{STXSSPX, 0xfc0007fe00000000, 0x7c00051800000000, 0x0, // Store VSX Scalar Single-Precision Indexed X-form (stxsspx XS,RA,RB)
  3929  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  3930  	{VADDCUQ, 0xfc0007ff00000000, 0x1000014000000000, 0x0, // Vector Add & write Carry Unsigned Quadword VX-form (vaddcuq VRT,VRA,VRB)
  3931  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3932  	{VADDECUQ, 0xfc00003f00000000, 0x1000003d00000000, 0x0, // Vector Add Extended & write Carry Unsigned Quadword VA-form (vaddecuq VRT,VRA,VRB,VRC)
  3933  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  3934  	{VADDEUQM, 0xfc00003f00000000, 0x1000003c00000000, 0x0, // Vector Add Extended Unsigned Quadword Modulo VA-form (vaddeuqm VRT,VRA,VRB,VRC)
  3935  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  3936  	{VADDUDM, 0xfc0007ff00000000, 0x100000c000000000, 0x0, // Vector Add Unsigned Doubleword Modulo VX-form (vaddudm VRT,VRA,VRB)
  3937  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3938  	{VADDUQM, 0xfc0007ff00000000, 0x1000010000000000, 0x0, // Vector Add Unsigned Quadword Modulo VX-form (vadduqm VRT,VRA,VRB)
  3939  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3940  	{VBPERMQ, 0xfc0007ff00000000, 0x1000054c00000000, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB)
  3941  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3942  	{VCIPHER, 0xfc0007ff00000000, 0x1000050800000000, 0x0, // Vector AES Cipher VX-form (vcipher VRT,VRA,VRB)
  3943  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3944  	{VCIPHERLAST, 0xfc0007ff00000000, 0x1000050900000000, 0x0, // Vector AES Cipher Last VX-form (vcipherlast VRT,VRA,VRB)
  3945  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3946  	{VCLZB, 0xfc0007ff00000000, 0x1000070200000000, 0x1f000000000000, // Vector Count Leading Zeros Byte VX-form (vclzb VRT,VRB)
  3947  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3948  	{VCLZD, 0xfc0007ff00000000, 0x100007c200000000, 0x1f000000000000, // Vector Count Leading Zeros Doubleword VX-form (vclzd VRT,VRB)
  3949  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3950  	{VCLZH, 0xfc0007ff00000000, 0x1000074200000000, 0x1f000000000000, // Vector Count Leading Zeros Halfword VX-form (vclzh VRT,VRB)
  3951  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3952  	{VCLZW, 0xfc0007ff00000000, 0x1000078200000000, 0x1f000000000000, // Vector Count Leading Zeros Word VX-form (vclzw VRT,VRB)
  3953  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3954  	{VCMPEQUD, 0xfc0007ff00000000, 0x100000c700000000, 0x0, // Vector Compare Equal Unsigned Doubleword VC-form (vcmpequd VRT,VRA,VRB)
  3955  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3956  	{VCMPEQUDCC, 0xfc0007ff00000000, 0x100004c700000000, 0x0, // Vector Compare Equal Unsigned Doubleword VC-form (vcmpequd. VRT,VRA,VRB)
  3957  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3958  	{VCMPGTSD, 0xfc0007ff00000000, 0x100003c700000000, 0x0, // Vector Compare Greater Than Signed Doubleword VC-form (vcmpgtsd VRT,VRA,VRB)
  3959  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3960  	{VCMPGTSDCC, 0xfc0007ff00000000, 0x100007c700000000, 0x0, // Vector Compare Greater Than Signed Doubleword VC-form (vcmpgtsd. VRT,VRA,VRB)
  3961  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3962  	{VCMPGTUD, 0xfc0007ff00000000, 0x100002c700000000, 0x0, // Vector Compare Greater Than Unsigned Doubleword VC-form (vcmpgtud VRT,VRA,VRB)
  3963  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3964  	{VCMPGTUDCC, 0xfc0007ff00000000, 0x100006c700000000, 0x0, // Vector Compare Greater Than Unsigned Doubleword VC-form (vcmpgtud. VRT,VRA,VRB)
  3965  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3966  	{VEQV, 0xfc0007ff00000000, 0x1000068400000000, 0x0, // Vector Logical Equivalence VX-form (veqv VRT,VRA,VRB)
  3967  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3968  	{VGBBD, 0xfc0007ff00000000, 0x1000050c00000000, 0x1f000000000000, // Vector Gather Bits by Bytes by Doubleword VX-form (vgbbd VRT,VRB)
  3969  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  3970  	{VMAXSD, 0xfc0007ff00000000, 0x100001c200000000, 0x0, // Vector Maximum Signed Doubleword VX-form (vmaxsd VRT,VRA,VRB)
  3971  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3972  	{VMAXUD, 0xfc0007ff00000000, 0x100000c200000000, 0x0, // Vector Maximum Unsigned Doubleword VX-form (vmaxud VRT,VRA,VRB)
  3973  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3974  	{VMINSD, 0xfc0007ff00000000, 0x100003c200000000, 0x0, // Vector Minimum Signed Doubleword VX-form (vminsd VRT,VRA,VRB)
  3975  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3976  	{VMINUD, 0xfc0007ff00000000, 0x100002c200000000, 0x0, // Vector Minimum Unsigned Doubleword VX-form (vminud VRT,VRA,VRB)
  3977  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3978  	{VMRGEW, 0xfc0007ff00000000, 0x1000078c00000000, 0x0, // Vector Merge Even Word VX-form (vmrgew VRT,VRA,VRB)
  3979  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3980  	{VMRGOW, 0xfc0007ff00000000, 0x1000068c00000000, 0x0, // Vector Merge Odd Word VX-form (vmrgow VRT,VRA,VRB)
  3981  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3982  	{VMULESW, 0xfc0007ff00000000, 0x1000038800000000, 0x0, // Vector Multiply Even Signed Word VX-form (vmulesw VRT,VRA,VRB)
  3983  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3984  	{VMULEUW, 0xfc0007ff00000000, 0x1000028800000000, 0x0, // Vector Multiply Even Unsigned Word VX-form (vmuleuw VRT,VRA,VRB)
  3985  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3986  	{VMULOSW, 0xfc0007ff00000000, 0x1000018800000000, 0x0, // Vector Multiply Odd Signed Word VX-form (vmulosw VRT,VRA,VRB)
  3987  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3988  	{VMULOUW, 0xfc0007ff00000000, 0x1000008800000000, 0x0, // Vector Multiply Odd Unsigned Word VX-form (vmulouw VRT,VRA,VRB)
  3989  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3990  	{VMULUWM, 0xfc0007ff00000000, 0x1000008900000000, 0x0, // Vector Multiply Unsigned Word Modulo VX-form (vmuluwm VRT,VRA,VRB)
  3991  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3992  	{VNAND, 0xfc0007ff00000000, 0x1000058400000000, 0x0, // Vector Logical NAND VX-form (vnand VRT,VRA,VRB)
  3993  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3994  	{VNCIPHER, 0xfc0007ff00000000, 0x1000054800000000, 0x0, // Vector AES Inverse Cipher VX-form (vncipher VRT,VRA,VRB)
  3995  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3996  	{VNCIPHERLAST, 0xfc0007ff00000000, 0x1000054900000000, 0x0, // Vector AES Inverse Cipher Last VX-form (vncipherlast VRT,VRA,VRB)
  3997  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  3998  	{VORC, 0xfc0007ff00000000, 0x1000054400000000, 0x0, // Vector Logical OR with Complement VX-form (vorc VRT,VRA,VRB)
  3999  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4000  	{VPERMXOR, 0xfc00003f00000000, 0x1000002d00000000, 0x0, // Vector Permute & Exclusive-OR VA-form (vpermxor VRT,VRA,VRB,VRC)
  4001  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4002  	{VPKSDSS, 0xfc0007ff00000000, 0x100005ce00000000, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB)
  4003  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4004  	{VPKSDUS, 0xfc0007ff00000000, 0x1000054e00000000, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB)
  4005  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4006  	{VPKUDUM, 0xfc0007ff00000000, 0x1000044e00000000, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB)
  4007  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4008  	{VPKUDUS, 0xfc0007ff00000000, 0x100004ce00000000, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB)
  4009  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4010  	{VPMSUMB, 0xfc0007ff00000000, 0x1000040800000000, 0x0, // Vector Polynomial Multiply-Sum Byte VX-form (vpmsumb VRT,VRA,VRB)
  4011  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4012  	{VPMSUMD, 0xfc0007ff00000000, 0x100004c800000000, 0x0, // Vector Polynomial Multiply-Sum Doubleword VX-form (vpmsumd VRT,VRA,VRB)
  4013  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4014  	{VPMSUMH, 0xfc0007ff00000000, 0x1000044800000000, 0x0, // Vector Polynomial Multiply-Sum Halfword VX-form (vpmsumh VRT,VRA,VRB)
  4015  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4016  	{VPMSUMW, 0xfc0007ff00000000, 0x1000048800000000, 0x0, // Vector Polynomial Multiply-Sum Word VX-form (vpmsumw VRT,VRA,VRB)
  4017  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4018  	{VPOPCNTB, 0xfc0007ff00000000, 0x1000070300000000, 0x1f000000000000, // Vector Population Count Byte VX-form (vpopcntb VRT,VRB)
  4019  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4020  	{VPOPCNTD, 0xfc0007ff00000000, 0x100007c300000000, 0x1f000000000000, // Vector Population Count Doubleword VX-form (vpopcntd VRT,VRB)
  4021  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4022  	{VPOPCNTH, 0xfc0007ff00000000, 0x1000074300000000, 0x1f000000000000, // Vector Population Count Halfword VX-form (vpopcnth VRT,VRB)
  4023  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4024  	{VPOPCNTW, 0xfc0007ff00000000, 0x1000078300000000, 0x1f000000000000, // Vector Population Count Word VX-form (vpopcntw VRT,VRB)
  4025  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4026  	{VRLD, 0xfc0007ff00000000, 0x100000c400000000, 0x0, // Vector Rotate Left Doubleword VX-form (vrld VRT,VRA,VRB)
  4027  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4028  	{VSBOX, 0xfc0007ff00000000, 0x100005c800000000, 0xf80000000000, // Vector AES SubBytes VX-form (vsbox VRT,VRA)
  4029  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
  4030  	{VSHASIGMAD, 0xfc0007ff00000000, 0x100006c200000000, 0x0, // Vector SHA-512 Sigma Doubleword VX-form (vshasigmad VRT,VRA,ST,SIX)
  4031  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
  4032  	{VSHASIGMAW, 0xfc0007ff00000000, 0x1000068200000000, 0x0, // Vector SHA-256 Sigma Word VX-form (vshasigmaw VRT,VRA,ST,SIX)
  4033  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
  4034  	{VSLD, 0xfc0007ff00000000, 0x100005c400000000, 0x0, // Vector Shift Left Doubleword VX-form (vsld VRT,VRA,VRB)
  4035  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4036  	{VSRAD, 0xfc0007ff00000000, 0x100003c400000000, 0x0, // Vector Shift Right Algebraic Doubleword VX-form (vsrad VRT,VRA,VRB)
  4037  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4038  	{VSRD, 0xfc0007ff00000000, 0x100006c400000000, 0x0, // Vector Shift Right Doubleword VX-form (vsrd VRT,VRA,VRB)
  4039  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4040  	{VSUBCUQ, 0xfc0007ff00000000, 0x1000054000000000, 0x0, // Vector Subtract & write Carry-out Unsigned Quadword VX-form (vsubcuq VRT,VRA,VRB)
  4041  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4042  	{VSUBECUQ, 0xfc00003f00000000, 0x1000003f00000000, 0x0, // Vector Subtract Extended & write Carry-out Unsigned Quadword VA-form (vsubecuq VRT,VRA,VRB,VRC)
  4043  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4044  	{VSUBEUQM, 0xfc00003f00000000, 0x1000003e00000000, 0x0, // Vector Subtract Extended Unsigned Quadword Modulo VA-form (vsubeuqm VRT,VRA,VRB,VRC)
  4045  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4046  	{VSUBUDM, 0xfc0007ff00000000, 0x100004c000000000, 0x0, // Vector Subtract Unsigned Doubleword Modulo VX-form (vsubudm VRT,VRA,VRB)
  4047  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4048  	{VSUBUQM, 0xfc0007ff00000000, 0x1000050000000000, 0x0, // Vector Subtract Unsigned Quadword Modulo VX-form (vsubuqm VRT,VRA,VRB)
  4049  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4050  	{VUPKHSW, 0xfc0007ff00000000, 0x1000064e00000000, 0x1f000000000000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB)
  4051  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4052  	{VUPKLSW, 0xfc0007ff00000000, 0x100006ce00000000, 0x1f000000000000, // Vector Unpack Low Signed Word VX-form (vupklsw VRT,VRB)
  4053  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4054  	{XSADDSP, 0xfc0007f800000000, 0xf000000000000000, 0x0, // VSX Scalar Add Single-Precision XX3-form (xsaddsp XT,XA,XB)
  4055  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4056  	{XSCVDPSPN, 0xfc0007fc00000000, 0xf000042c00000000, 0x1f000000000000, // VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form (xscvdpspn XT,XB)
  4057  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4058  	{XSCVSPDPN, 0xfc0007fc00000000, 0xf000052c00000000, 0x1f000000000000, // VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form (xscvspdpn XT,XB)
  4059  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4060  	{XSCVSXDSP, 0xfc0007fc00000000, 0xf00004e000000000, 0x1f000000000000, // VSX Scalar Convert with round Signed Doubleword to Single-Precision format XX2-form (xscvsxdsp XT,XB)
  4061  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4062  	{XSCVUXDSP, 0xfc0007fc00000000, 0xf00004a000000000, 0x1f000000000000, // VSX Scalar Convert with round Unsigned Doubleword to Single-Precision XX2-form (xscvuxdsp XT,XB)
  4063  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4064  	{XSDIVSP, 0xfc0007f800000000, 0xf00000c000000000, 0x0, // VSX Scalar Divide Single-Precision XX3-form (xsdivsp XT,XA,XB)
  4065  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4066  	{XSMADDASP, 0xfc0007f800000000, 0xf000000800000000, 0x0, // VSX Scalar Multiply-Add Type-A Single-Precision XX3-form (xsmaddasp XT,XA,XB)
  4067  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4068  	{XSMADDMSP, 0xfc0007f800000000, 0xf000004800000000, 0x0, // VSX Scalar Multiply-Add Type-M Single-Precision XX3-form (xsmaddmsp XT,XA,XB)
  4069  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4070  	{XSMSUBASP, 0xfc0007f800000000, 0xf000008800000000, 0x0, // VSX Scalar Multiply-Subtract Type-A Single-Precision XX3-form (xsmsubasp XT,XA,XB)
  4071  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4072  	{XSMSUBMSP, 0xfc0007f800000000, 0xf00000c800000000, 0x0, // VSX Scalar Multiply-Subtract Type-M Single-Precision XX3-form (xsmsubmsp XT,XA,XB)
  4073  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4074  	{XSMULSP, 0xfc0007f800000000, 0xf000008000000000, 0x0, // VSX Scalar Multiply Single-Precision XX3-form (xsmulsp XT,XA,XB)
  4075  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4076  	{XSNMADDASP, 0xfc0007f800000000, 0xf000040800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-A Single-Precision XX3-form (xsnmaddasp XT,XA,XB)
  4077  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4078  	{XSNMADDMSP, 0xfc0007f800000000, 0xf000044800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-M Single-Precision XX3-form (xsnmaddmsp XT,XA,XB)
  4079  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4080  	{XSNMSUBASP, 0xfc0007f800000000, 0xf000048800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-A Single-Precision XX3-form (xsnmsubasp XT,XA,XB)
  4081  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4082  	{XSNMSUBMSP, 0xfc0007f800000000, 0xf00004c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-M Single-Precision XX3-form (xsnmsubmsp XT,XA,XB)
  4083  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4084  	{XSRESP, 0xfc0007fc00000000, 0xf000006800000000, 0x1f000000000000, // VSX Scalar Reciprocal Estimate Single-Precision XX2-form (xsresp XT,XB)
  4085  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4086  	{XSRSP, 0xfc0007fc00000000, 0xf000046400000000, 0x1f000000000000, // VSX Scalar Round to Single-Precision XX2-form (xsrsp XT,XB)
  4087  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4088  	{XSRSQRTESP, 0xfc0007fc00000000, 0xf000002800000000, 0x1f000000000000, // VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form (xsrsqrtesp XT,XB)
  4089  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4090  	{XSSQRTSP, 0xfc0007fc00000000, 0xf000002c00000000, 0x1f000000000000, // VSX Scalar Square Root Single-Precision XX2-form (xssqrtsp XT,XB)
  4091  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4092  	{XSSUBSP, 0xfc0007f800000000, 0xf000004000000000, 0x0, // VSX Scalar Subtract Single-Precision XX3-form (xssubsp XT,XA,XB)
  4093  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4094  	{XXLEQV, 0xfc0007f800000000, 0xf00005d000000000, 0x0, // VSX Vector Logical Equivalence XX3-form (xxleqv XT,XA,XB)
  4095  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4096  	{XXLNAND, 0xfc0007f800000000, 0xf000059000000000, 0x0, // VSX Vector Logical NAND XX3-form (xxlnand XT,XA,XB)
  4097  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4098  	{XXLORC, 0xfc0007f800000000, 0xf000055000000000, 0x0, // VSX Vector Logical OR with Complement XX3-form (xxlorc XT,XA,XB)
  4099  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4100  	{ADDG6S, 0xfc0003fe00000000, 0x7c00009400000000, 0x40100000000, // Add and Generate Sixes XO-form (addg6s RT,RA,RB)
  4101  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4102  	{BPERMD, 0xfc0007fe00000000, 0x7c0001f800000000, 0x100000000, // Bit Permute Doubleword X-form (bpermd RA,RS,RB)
  4103  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  4104  	{CBCDTD, 0xfc0007fe00000000, 0x7c00027400000000, 0xf80100000000, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS)
  4105  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  4106  	{CDTBCD, 0xfc0007fe00000000, 0x7c00023400000000, 0xf80100000000, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS)
  4107  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  4108  	{DCFFIX, 0xfc0007ff00000000, 0xec00064400000000, 0x1f000000000000, // DFP Convert From Fixed X-form (dcffix FRT,FRB)
  4109  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4110  	{DCFFIXCC, 0xfc0007ff00000000, 0xec00064500000000, 0x1f000000000000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB)
  4111  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4112  	{DIVDE, 0xfc0007ff00000000, 0x7c00035200000000, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB)
  4113  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4114  	{DIVDECC, 0xfc0007ff00000000, 0x7c00035300000000, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB)
  4115  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4116  	{DIVDEO, 0xfc0007ff00000000, 0x7c00075200000000, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB)
  4117  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4118  	{DIVDEOCC, 0xfc0007ff00000000, 0x7c00075300000000, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB)
  4119  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4120  	{DIVDEU, 0xfc0007ff00000000, 0x7c00031200000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB)
  4121  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4122  	{DIVDEUCC, 0xfc0007ff00000000, 0x7c00031300000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB)
  4123  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4124  	{DIVDEUO, 0xfc0007ff00000000, 0x7c00071200000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB)
  4125  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4126  	{DIVDEUOCC, 0xfc0007ff00000000, 0x7c00071300000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB)
  4127  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4128  	{DIVWE, 0xfc0007ff00000000, 0x7c00035600000000, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB)
  4129  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4130  	{DIVWECC, 0xfc0007ff00000000, 0x7c00035700000000, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB)
  4131  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4132  	{DIVWEO, 0xfc0007ff00000000, 0x7c00075600000000, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB)
  4133  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4134  	{DIVWEOCC, 0xfc0007ff00000000, 0x7c00075700000000, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB)
  4135  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4136  	{DIVWEU, 0xfc0007ff00000000, 0x7c00031600000000, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB)
  4137  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4138  	{DIVWEUCC, 0xfc0007ff00000000, 0x7c00031700000000, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB)
  4139  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4140  	{DIVWEUO, 0xfc0007ff00000000, 0x7c00071600000000, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB)
  4141  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4142  	{DIVWEUOCC, 0xfc0007ff00000000, 0x7c00071700000000, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB)
  4143  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4144  	{FCFIDS, 0xfc0007ff00000000, 0xec00069c00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Single-Precision format X-form (fcfids FRT,FRB)
  4145  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4146  	{FCFIDSCC, 0xfc0007ff00000000, 0xec00069d00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Single-Precision format X-form (fcfids. FRT,FRB)
  4147  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4148  	{FCFIDU, 0xfc0007ff00000000, 0xfc00079c00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Double-Precision format X-form (fcfidu FRT,FRB)
  4149  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4150  	{FCFIDUCC, 0xfc0007ff00000000, 0xfc00079d00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Double-Precision format X-form (fcfidu. FRT,FRB)
  4151  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4152  	{FCFIDUS, 0xfc0007ff00000000, 0xec00079c00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Single-Precision format X-form (fcfidus FRT,FRB)
  4153  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4154  	{FCFIDUSCC, 0xfc0007ff00000000, 0xec00079d00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Single-Precision format X-form (fcfidus. FRT,FRB)
  4155  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4156  	{FCTIDU, 0xfc0007ff00000000, 0xfc00075c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Doubleword format X-form (fctidu FRT,FRB)
  4157  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4158  	{FCTIDUCC, 0xfc0007ff00000000, 0xfc00075d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Doubleword format X-form (fctidu. FRT,FRB)
  4159  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4160  	{FCTIDUZ, 0xfc0007ff00000000, 0xfc00075e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form (fctiduz FRT,FRB)
  4161  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4162  	{FCTIDUZCC, 0xfc0007ff00000000, 0xfc00075f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form (fctiduz. FRT,FRB)
  4163  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4164  	{FCTIWU, 0xfc0007ff00000000, 0xfc00011c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Word format X-form (fctiwu FRT,FRB)
  4165  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4166  	{FCTIWUCC, 0xfc0007ff00000000, 0xfc00011d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Word format X-form (fctiwu. FRT,FRB)
  4167  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4168  	{FCTIWUZ, 0xfc0007ff00000000, 0xfc00011e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Word format X-form (fctiwuz FRT,FRB)
  4169  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4170  	{FCTIWUZCC, 0xfc0007ff00000000, 0xfc00011f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Word format X-form (fctiwuz. FRT,FRB)
  4171  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4172  	{FTDIV, 0xfc0007fe00000000, 0xfc00010000000000, 0x60000100000000, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB)
  4173  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4174  	{FTSQRT, 0xfc0007fe00000000, 0xfc00014000000000, 0x7f000100000000, // Floating Test for software Square Root X-form (ftsqrt BF,FRB)
  4175  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}},
  4176  	{LBARX, 0xfc0007fe00000000, 0x7c00006800000000, 0x0, // Load Byte And Reserve Indexed X-form (lbarx RT,RA,RB,EH)
  4177  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
  4178  	{LDBRX, 0xfc0007fe00000000, 0x7c00042800000000, 0x100000000, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB)
  4179  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4180  	{LFIWZX, 0xfc0007fe00000000, 0x7c0006ee00000000, 0x100000000, // Load Floating-Point as Integer Word & Zero Indexed X-form (lfiwzx FRT,RA,RB)
  4181  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4182  	{LHARX, 0xfc0007fe00000000, 0x7c0000e800000000, 0x0, // Load Halfword And Reserve Indexed Xform (lharx RT,RA,RB,EH)
  4183  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
  4184  	{LXSDX, 0xfc0007fe00000000, 0x7c00049800000000, 0x0, // Load VSX Scalar Doubleword Indexed X-form (lxsdx XT,RA,RB)
  4185  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4186  	{LXVD2X, 0xfc0007fe00000000, 0x7c00069800000000, 0x0, // Load VSX Vector Doubleword*2 Indexed X-form (lxvd2x XT,RA,RB)
  4187  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4188  	{LXVDSX, 0xfc0007fe00000000, 0x7c00029800000000, 0x0, // Load VSX Vector Doubleword & Splat Indexed X-form (lxvdsx XT,RA,RB)
  4189  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4190  	{LXVW4X, 0xfc0007fe00000000, 0x7c00061800000000, 0x0, // Load VSX Vector Word*4 Indexed X-form (lxvw4x XT,RA,RB)
  4191  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4192  	{POPCNTD, 0xfc0007fe00000000, 0x7c0003f400000000, 0xf80100000000, // Population Count Doubleword X-form (popcntd RA, RS)
  4193  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  4194  	{POPCNTW, 0xfc0007fe00000000, 0x7c0002f400000000, 0xf80100000000, // Population Count Words X-form (popcntw RA, RS)
  4195  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  4196  	{STBCXCC, 0xfc0007ff00000000, 0x7c00056d00000000, 0x0, // Store Byte Conditional Indexed X-form (stbcx. RS,RA,RB)
  4197  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4198  	{STDBRX, 0xfc0007fe00000000, 0x7c00052800000000, 0x100000000, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB)
  4199  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4200  	{STHCXCC, 0xfc0007ff00000000, 0x7c0005ad00000000, 0x0, // Store Halfword Conditional Indexed X-form (sthcx. RS,RA,RB)
  4201  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4202  	{STXSDX, 0xfc0007fe00000000, 0x7c00059800000000, 0x0, // Store VSX Scalar Doubleword Indexed X-form (stxsdx XS,RA,RB)
  4203  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4204  	{STXVD2X, 0xfc0007fe00000000, 0x7c00079800000000, 0x0, // Store VSX Vector Doubleword*2 Indexed X-form (stxvd2x XS,RA,RB)
  4205  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4206  	{STXVW4X, 0xfc0007fe00000000, 0x7c00071800000000, 0x0, // Store VSX Vector Word*4 Indexed X-form (stxvw4x XS,RA,RB)
  4207  		[6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4208  	{XSABSDP, 0xfc0007fc00000000, 0xf000056400000000, 0x1f000000000000, // VSX Scalar Absolute Double-Precision XX2-form (xsabsdp XT,XB)
  4209  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4210  	{XSADDDP, 0xfc0007f800000000, 0xf000010000000000, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB)
  4211  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4212  	{XSCMPODP, 0xfc0007f800000000, 0xf000015800000000, 0x60000100000000, // VSX Scalar Compare Ordered Double-Precision XX3-form (xscmpodp BF,XA,XB)
  4213  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4214  	{XSCMPUDP, 0xfc0007f800000000, 0xf000011800000000, 0x60000100000000, // VSX Scalar Compare Unordered Double-Precision XX3-form (xscmpudp BF,XA,XB)
  4215  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4216  	{XSCPSGNDP, 0xfc0007f800000000, 0xf000058000000000, 0x0, // VSX Scalar Copy Sign Double-Precision XX3-form (xscpsgndp XT,XA,XB)
  4217  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4218  	{XSCVDPSP, 0xfc0007fc00000000, 0xf000042400000000, 0x1f000000000000, // VSX Scalar Convert with round Double-Precision to Single-Precision format XX2-form (xscvdpsp XT,XB)
  4219  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4220  	{XSCVDPSXDS, 0xfc0007fc00000000, 0xf000056000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Signed Doubleword format XX2-form (xscvdpsxds XT,XB)
  4221  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4222  	{XSCVDPSXWS, 0xfc0007fc00000000, 0xf000016000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Signed Word format XX2-form (xscvdpsxws XT,XB)
  4223  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4224  	{XSCVDPUXDS, 0xfc0007fc00000000, 0xf000052000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-form (xscvdpuxds XT,XB)
  4225  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4226  	{XSCVDPUXWS, 0xfc0007fc00000000, 0xf000012000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Unsigned Word format XX2-form (xscvdpuxws XT,XB)
  4227  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4228  	{XSCVSPDP, 0xfc0007fc00000000, 0xf000052400000000, 0x1f000000000000, // VSX Scalar Convert Single-Precision to Double-Precision format XX2-form (xscvspdp XT,XB)
  4229  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4230  	{XSCVSXDDP, 0xfc0007fc00000000, 0xf00005e000000000, 0x1f000000000000, // VSX Scalar Convert with round Signed Doubleword to Double-Precision format XX2-form (xscvsxddp XT,XB)
  4231  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4232  	{XSCVUXDDP, 0xfc0007fc00000000, 0xf00005a000000000, 0x1f000000000000, // VSX Scalar Convert with round Unsigned Doubleword to Double-Precision format XX2-form (xscvuxddp XT,XB)
  4233  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4234  	{XSDIVDP, 0xfc0007f800000000, 0xf00001c000000000, 0x0, // VSX Scalar Divide Double-Precision XX3-form (xsdivdp XT,XA,XB)
  4235  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4236  	{XSMADDADP, 0xfc0007f800000000, 0xf000010800000000, 0x0, // VSX Scalar Multiply-Add Type-A Double-Precision XX3-form (xsmaddadp XT,XA,XB)
  4237  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4238  	{XSMADDMDP, 0xfc0007f800000000, 0xf000014800000000, 0x0, // VSX Scalar Multiply-Add Type-M Double-Precision XX3-form (xsmaddmdp XT,XA,XB)
  4239  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4240  	{XSMAXDP, 0xfc0007f800000000, 0xf000050000000000, 0x0, // VSX Scalar Maximum Double-Precision XX3-form (xsmaxdp XT,XA,XB)
  4241  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4242  	{XSMINDP, 0xfc0007f800000000, 0xf000054000000000, 0x0, // VSX Scalar Minimum Double-Precision XX3-form (xsmindp XT,XA,XB)
  4243  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4244  	{XSMSUBADP, 0xfc0007f800000000, 0xf000018800000000, 0x0, // VSX Scalar Multiply-Subtract Type-A Double-Precision XX3-form (xsmsubadp XT,XA,XB)
  4245  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4246  	{XSMSUBMDP, 0xfc0007f800000000, 0xf00001c800000000, 0x0, // VSX Scalar Multiply-Subtract Type-M Double-Precision XX3-form (xsmsubmdp XT,XA,XB)
  4247  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4248  	{XSMULDP, 0xfc0007f800000000, 0xf000018000000000, 0x0, // VSX Scalar Multiply Double-Precision XX3-form (xsmuldp XT,XA,XB)
  4249  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4250  	{XSNABSDP, 0xfc0007fc00000000, 0xf00005a400000000, 0x1f000000000000, // VSX Scalar Negative Absolute Double-Precision XX2-form (xsnabsdp XT,XB)
  4251  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4252  	{XSNEGDP, 0xfc0007fc00000000, 0xf00005e400000000, 0x1f000000000000, // VSX Scalar Negate Double-Precision XX2-form (xsnegdp XT,XB)
  4253  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4254  	{XSNMADDADP, 0xfc0007f800000000, 0xf000050800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-A Double-Precision XX3-form (xsnmaddadp XT,XA,XB)
  4255  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4256  	{XSNMADDMDP, 0xfc0007f800000000, 0xf000054800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-M Double-Precision XX3-form (xsnmaddmdp XT,XA,XB)
  4257  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4258  	{XSNMSUBADP, 0xfc0007f800000000, 0xf000058800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-A Double-Precision XX3-form (xsnmsubadp XT,XA,XB)
  4259  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4260  	{XSNMSUBMDP, 0xfc0007f800000000, 0xf00005c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-M Double-Precision XX3-form (xsnmsubmdp XT,XA,XB)
  4261  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4262  	{XSRDPI, 0xfc0007fc00000000, 0xf000012400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form (xsrdpi XT,XB)
  4263  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4264  	{XSRDPIC, 0xfc0007fc00000000, 0xf00001ac00000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form (xsrdpic XT,XB)
  4265  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4266  	{XSRDPIM, 0xfc0007fc00000000, 0xf00001e400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form (xsrdpim XT,XB)
  4267  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4268  	{XSRDPIP, 0xfc0007fc00000000, 0xf00001a400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form (xsrdpip XT,XB)
  4269  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4270  	{XSRDPIZ, 0xfc0007fc00000000, 0xf000016400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form (xsrdpiz XT,XB)
  4271  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4272  	{XSREDP, 0xfc0007fc00000000, 0xf000016800000000, 0x1f000000000000, // VSX Scalar Reciprocal Estimate Double-Precision XX2-form (xsredp XT,XB)
  4273  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4274  	{XSRSQRTEDP, 0xfc0007fc00000000, 0xf000012800000000, 0x1f000000000000, // VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form (xsrsqrtedp XT,XB)
  4275  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4276  	{XSSQRTDP, 0xfc0007fc00000000, 0xf000012c00000000, 0x1f000000000000, // VSX Scalar Square Root Double-Precision XX2-form (xssqrtdp XT,XB)
  4277  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4278  	{XSSUBDP, 0xfc0007f800000000, 0xf000014000000000, 0x0, // VSX Scalar Subtract Double-Precision XX3-form (xssubdp XT,XA,XB)
  4279  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4280  	{XSTDIVDP, 0xfc0007f800000000, 0xf00001e800000000, 0x60000100000000, // VSX Scalar Test for software Divide Double-Precision XX3-form (xstdivdp BF,XA,XB)
  4281  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4282  	{XSTSQRTDP, 0xfc0007fc00000000, 0xf00001a800000000, 0x7f000100000000, // VSX Scalar Test for software Square Root Double-Precision XX2-form (xstsqrtdp BF,XB)
  4283  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
  4284  	{XVABSDP, 0xfc0007fc00000000, 0xf000076400000000, 0x1f000000000000, // VSX Vector Absolute Value Double-Precision XX2-form (xvabsdp XT,XB)
  4285  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4286  	{XVABSSP, 0xfc0007fc00000000, 0xf000066400000000, 0x1f000000000000, // VSX Vector Absolute Value Single-Precision XX2-form (xvabssp XT,XB)
  4287  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4288  	{XVADDDP, 0xfc0007f800000000, 0xf000030000000000, 0x0, // VSX Vector Add Double-Precision XX3-form (xvadddp XT,XA,XB)
  4289  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4290  	{XVADDSP, 0xfc0007f800000000, 0xf000020000000000, 0x0, // VSX Vector Add Single-Precision XX3-form (xvaddsp XT,XA,XB)
  4291  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4292  	{XVCMPEQDP, 0xfc0007f800000000, 0xf000031800000000, 0x0, // VSX Vector Compare Equal To Double-Precision XX3-form (xvcmpeqdp XT,XA,XB)
  4293  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4294  	{XVCMPEQDPCC, 0xfc0007f800000000, 0xf000071800000000, 0x0, // VSX Vector Compare Equal To Double-Precision XX3-form (xvcmpeqdp. XT,XA,XB)
  4295  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4296  	{XVCMPEQSP, 0xfc0007f800000000, 0xf000021800000000, 0x0, // VSX Vector Compare Equal To Single-Precision XX3-form (xvcmpeqsp XT,XA,XB)
  4297  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4298  	{XVCMPEQSPCC, 0xfc0007f800000000, 0xf000061800000000, 0x0, // VSX Vector Compare Equal To Single-Precision XX3-form (xvcmpeqsp. XT,XA,XB)
  4299  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4300  	{XVCMPGEDP, 0xfc0007f800000000, 0xf000039800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision XX3-form (xvcmpgedp XT,XA,XB)
  4301  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4302  	{XVCMPGEDPCC, 0xfc0007f800000000, 0xf000079800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision XX3-form (xvcmpgedp. XT,XA,XB)
  4303  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4304  	{XVCMPGESP, 0xfc0007f800000000, 0xf000029800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision XX3-form (xvcmpgesp XT,XA,XB)
  4305  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4306  	{XVCMPGESPCC, 0xfc0007f800000000, 0xf000069800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision XX3-form (xvcmpgesp. XT,XA,XB)
  4307  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4308  	{XVCMPGTDP, 0xfc0007f800000000, 0xf000035800000000, 0x0, // VSX Vector Compare Greater Than Double-Precision XX3-form (xvcmpgtdp XT,XA,XB)
  4309  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4310  	{XVCMPGTDPCC, 0xfc0007f800000000, 0xf000075800000000, 0x0, // VSX Vector Compare Greater Than Double-Precision XX3-form (xvcmpgtdp. XT,XA,XB)
  4311  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4312  	{XVCMPGTSP, 0xfc0007f800000000, 0xf000025800000000, 0x0, // VSX Vector Compare Greater Than Single-Precision XX3-form (xvcmpgtsp XT,XA,XB)
  4313  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4314  	{XVCMPGTSPCC, 0xfc0007f800000000, 0xf000065800000000, 0x0, // VSX Vector Compare Greater Than Single-Precision XX3-form (xvcmpgtsp. XT,XA,XB)
  4315  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4316  	{XVCPSGNDP, 0xfc0007f800000000, 0xf000078000000000, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB)
  4317  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4318  	{XVCPSGNSP, 0xfc0007f800000000, 0xf000068000000000, 0x0, // VSX Vector Copy Sign Single-Precision XX3-form (xvcpsgnsp XT,XA,XB)
  4319  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4320  	{XVCVDPSP, 0xfc0007fc00000000, 0xf000062400000000, 0x1f000000000000, // VSX Vector Convert with round Double-Precision to Single-Precision format XX2-form (xvcvdpsp XT,XB)
  4321  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4322  	{XVCVDPSXDS, 0xfc0007fc00000000, 0xf000076000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Signed Doubleword format XX2-form (xvcvdpsxds XT,XB)
  4323  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4324  	{XVCVDPSXWS, 0xfc0007fc00000000, 0xf000036000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Signed Word format XX2-form (xvcvdpsxws XT,XB)
  4325  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4326  	{XVCVDPUXDS, 0xfc0007fc00000000, 0xf000072000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-form (xvcvdpuxds XT,XB)
  4327  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4328  	{XVCVDPUXWS, 0xfc0007fc00000000, 0xf000032000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Unsigned Word format XX2-form (xvcvdpuxws XT,XB)
  4329  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4330  	{XVCVSPDP, 0xfc0007fc00000000, 0xf000072400000000, 0x1f000000000000, // VSX Vector Convert Single-Precision to Double-Precision format XX2-form (xvcvspdp XT,XB)
  4331  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4332  	{XVCVSPSXDS, 0xfc0007fc00000000, 0xf000066000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Signed Doubleword format XX2-form (xvcvspsxds XT,XB)
  4333  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4334  	{XVCVSPSXWS, 0xfc0007fc00000000, 0xf000026000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Signed Word format XX2-form (xvcvspsxws XT,XB)
  4335  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4336  	{XVCVSPUXDS, 0xfc0007fc00000000, 0xf000062000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Unsigned Doubleword format XX2-form (xvcvspuxds XT,XB)
  4337  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4338  	{XVCVSPUXWS, 0xfc0007fc00000000, 0xf000022000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Unsigned Word format XX2-form (xvcvspuxws XT,XB)
  4339  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4340  	{XVCVSXDDP, 0xfc0007fc00000000, 0xf00007e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Doubleword to Double-Precision format XX2-form (xvcvsxddp XT,XB)
  4341  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4342  	{XVCVSXDSP, 0xfc0007fc00000000, 0xf00006e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Doubleword to Single-Precision format XX2-form (xvcvsxdsp XT,XB)
  4343  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4344  	{XVCVSXWDP, 0xfc0007fc00000000, 0xf00003e000000000, 0x1f000000000000, // VSX Vector Convert Signed Word to Double-Precision format XX2-form (xvcvsxwdp XT,XB)
  4345  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4346  	{XVCVSXWSP, 0xfc0007fc00000000, 0xf00002e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Word to Single-Precision format XX2-form (xvcvsxwsp XT,XB)
  4347  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4348  	{XVCVUXDDP, 0xfc0007fc00000000, 0xf00007a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Doubleword to Double-Precision format XX2-form (xvcvuxddp XT,XB)
  4349  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4350  	{XVCVUXDSP, 0xfc0007fc00000000, 0xf00006a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Doubleword to Single-Precision format XX2-form (xvcvuxdsp XT,XB)
  4351  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4352  	{XVCVUXWDP, 0xfc0007fc00000000, 0xf00003a000000000, 0x1f000000000000, // VSX Vector Convert Unsigned Word to Double-Precision format XX2-form (xvcvuxwdp XT,XB)
  4353  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4354  	{XVCVUXWSP, 0xfc0007fc00000000, 0xf00002a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Word to Single-Precision format XX2-form (xvcvuxwsp XT,XB)
  4355  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4356  	{XVDIVDP, 0xfc0007f800000000, 0xf00003c000000000, 0x0, // VSX Vector Divide Double-Precision XX3-form (xvdivdp XT,XA,XB)
  4357  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4358  	{XVDIVSP, 0xfc0007f800000000, 0xf00002c000000000, 0x0, // VSX Vector Divide Single-Precision XX3-form (xvdivsp XT,XA,XB)
  4359  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4360  	{XVMADDADP, 0xfc0007f800000000, 0xf000030800000000, 0x0, // VSX Vector Multiply-Add Type-A Double-Precision XX3-form (xvmaddadp XT,XA,XB)
  4361  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4362  	{XVMADDASP, 0xfc0007f800000000, 0xf000020800000000, 0x0, // VSX Vector Multiply-Add Type-A Single-Precision XX3-form (xvmaddasp XT,XA,XB)
  4363  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4364  	{XVMADDMDP, 0xfc0007f800000000, 0xf000034800000000, 0x0, // VSX Vector Multiply-Add Type-M Double-Precision XX3-form (xvmaddmdp XT,XA,XB)
  4365  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4366  	{XVMADDMSP, 0xfc0007f800000000, 0xf000024800000000, 0x0, // VSX Vector Multiply-Add Type-M Single-Precision XX3-form (xvmaddmsp XT,XA,XB)
  4367  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4368  	{XVMAXDP, 0xfc0007f800000000, 0xf000070000000000, 0x0, // VSX Vector Maximum Double-Precision XX3-form (xvmaxdp XT,XA,XB)
  4369  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4370  	{XVMAXSP, 0xfc0007f800000000, 0xf000060000000000, 0x0, // VSX Vector Maximum Single-Precision XX3-form (xvmaxsp XT,XA,XB)
  4371  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4372  	{XVMINDP, 0xfc0007f800000000, 0xf000074000000000, 0x0, // VSX Vector Minimum Double-Precision XX3-form (xvmindp XT,XA,XB)
  4373  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4374  	{XVMINSP, 0xfc0007f800000000, 0xf000064000000000, 0x0, // VSX Vector Minimum Single-Precision XX3-form (xvminsp XT,XA,XB)
  4375  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4376  	{XVMSUBADP, 0xfc0007f800000000, 0xf000038800000000, 0x0, // VSX Vector Multiply-Subtract Type-A Double-Precision XX3-form (xvmsubadp XT,XA,XB)
  4377  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4378  	{XVMSUBASP, 0xfc0007f800000000, 0xf000028800000000, 0x0, // VSX Vector Multiply-Subtract Type-A Single-Precision XX3-form (xvmsubasp XT,XA,XB)
  4379  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4380  	{XVMSUBMDP, 0xfc0007f800000000, 0xf00003c800000000, 0x0, // VSX Vector Multiply-Subtract Type-M Double-Precision XX3-form (xvmsubmdp XT,XA,XB)
  4381  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4382  	{XVMSUBMSP, 0xfc0007f800000000, 0xf00002c800000000, 0x0, // VSX Vector Multiply-Subtract Type-M Single-Precision XX3-form (xvmsubmsp XT,XA,XB)
  4383  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4384  	{XVMULDP, 0xfc0007f800000000, 0xf000038000000000, 0x0, // VSX Vector Multiply Double-Precision XX3-form (xvmuldp XT,XA,XB)
  4385  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4386  	{XVMULSP, 0xfc0007f800000000, 0xf000028000000000, 0x0, // VSX Vector Multiply Single-Precision XX3-form (xvmulsp XT,XA,XB)
  4387  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4388  	{XVNABSDP, 0xfc0007fc00000000, 0xf00007a400000000, 0x1f000000000000, // VSX Vector Negative Absolute Double-Precision XX2-form (xvnabsdp XT,XB)
  4389  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4390  	{XVNABSSP, 0xfc0007fc00000000, 0xf00006a400000000, 0x1f000000000000, // VSX Vector Negative Absolute Single-Precision XX2-form (xvnabssp XT,XB)
  4391  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4392  	{XVNEGDP, 0xfc0007fc00000000, 0xf00007e400000000, 0x1f000000000000, // VSX Vector Negate Double-Precision XX2-form (xvnegdp XT,XB)
  4393  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4394  	{XVNEGSP, 0xfc0007fc00000000, 0xf00006e400000000, 0x1f000000000000, // VSX Vector Negate Single-Precision XX2-form (xvnegsp XT,XB)
  4395  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4396  	{XVNMADDADP, 0xfc0007f800000000, 0xf000070800000000, 0x0, // VSX Vector Negative Multiply-Add Type-A Double-Precision XX3-form (xvnmaddadp XT,XA,XB)
  4397  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4398  	{XVNMADDASP, 0xfc0007f800000000, 0xf000060800000000, 0x0, // VSX Vector Negative Multiply-Add Type-A Single-Precision XX3-form (xvnmaddasp XT,XA,XB)
  4399  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4400  	{XVNMADDMDP, 0xfc0007f800000000, 0xf000074800000000, 0x0, // VSX Vector Negative Multiply-Add Type-M Double-Precision XX3-form (xvnmaddmdp XT,XA,XB)
  4401  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4402  	{XVNMADDMSP, 0xfc0007f800000000, 0xf000064800000000, 0x0, // VSX Vector Negative Multiply-Add Type-M Single-Precision XX3-form (xvnmaddmsp XT,XA,XB)
  4403  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4404  	{XVNMSUBADP, 0xfc0007f800000000, 0xf000078800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-A Double-Precision XX3-form (xvnmsubadp XT,XA,XB)
  4405  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4406  	{XVNMSUBASP, 0xfc0007f800000000, 0xf000068800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-A Single-Precision XX3-form (xvnmsubasp XT,XA,XB)
  4407  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4408  	{XVNMSUBMDP, 0xfc0007f800000000, 0xf00007c800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-M Double-Precision XX3-form (xvnmsubmdp XT,XA,XB)
  4409  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4410  	{XVNMSUBMSP, 0xfc0007f800000000, 0xf00006c800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-M Single-Precision XX3-form (xvnmsubmsp XT,XA,XB)
  4411  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4412  	{XVRDPI, 0xfc0007fc00000000, 0xf000032400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form (xvrdpi XT,XB)
  4413  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4414  	{XVRDPIC, 0xfc0007fc00000000, 0xf00003ac00000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form (xvrdpic XT,XB)
  4415  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4416  	{XVRDPIM, 0xfc0007fc00000000, 0xf00003e400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form (xvrdpim XT,XB)
  4417  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4418  	{XVRDPIP, 0xfc0007fc00000000, 0xf00003a400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form (xvrdpip XT,XB)
  4419  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4420  	{XVRDPIZ, 0xfc0007fc00000000, 0xf000036400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form (xvrdpiz XT,XB)
  4421  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4422  	{XVREDP, 0xfc0007fc00000000, 0xf000036800000000, 0x1f000000000000, // VSX Vector Reciprocal Estimate Double-Precision XX2-form (xvredp XT,XB)
  4423  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4424  	{XVRESP, 0xfc0007fc00000000, 0xf000026800000000, 0x1f000000000000, // VSX Vector Reciprocal Estimate Single-Precision XX2-form (xvresp XT,XB)
  4425  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4426  	{XVRSPI, 0xfc0007fc00000000, 0xf000022400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form (xvrspi XT,XB)
  4427  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4428  	{XVRSPIC, 0xfc0007fc00000000, 0xf00002ac00000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form (xvrspic XT,XB)
  4429  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4430  	{XVRSPIM, 0xfc0007fc00000000, 0xf00002e400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form (xvrspim XT,XB)
  4431  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4432  	{XVRSPIP, 0xfc0007fc00000000, 0xf00002a400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form (xvrspip XT,XB)
  4433  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4434  	{XVRSPIZ, 0xfc0007fc00000000, 0xf000026400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form (xvrspiz XT,XB)
  4435  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4436  	{XVRSQRTEDP, 0xfc0007fc00000000, 0xf000032800000000, 0x1f000000000000, // VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form (xvrsqrtedp XT,XB)
  4437  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4438  	{XVRSQRTESP, 0xfc0007fc00000000, 0xf000022800000000, 0x1f000000000000, // VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form (xvrsqrtesp XT,XB)
  4439  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4440  	{XVSQRTDP, 0xfc0007fc00000000, 0xf000032c00000000, 0x1f000000000000, // VSX Vector Square Root Double-Precision XX2-form (xvsqrtdp XT,XB)
  4441  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4442  	{XVSQRTSP, 0xfc0007fc00000000, 0xf000022c00000000, 0x1f000000000000, // VSX Vector Square Root Single-Precision XX2-form (xvsqrtsp XT,XB)
  4443  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
  4444  	{XVSUBDP, 0xfc0007f800000000, 0xf000034000000000, 0x0, // VSX Vector Subtract Double-Precision XX3-form (xvsubdp XT,XA,XB)
  4445  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4446  	{XVSUBSP, 0xfc0007f800000000, 0xf000024000000000, 0x0, // VSX Vector Subtract Single-Precision XX3-form (xvsubsp XT,XA,XB)
  4447  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4448  	{XVTDIVDP, 0xfc0007f800000000, 0xf00003e800000000, 0x60000100000000, // VSX Vector Test for software Divide Double-Precision XX3-form (xvtdivdp BF,XA,XB)
  4449  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4450  	{XVTDIVSP, 0xfc0007f800000000, 0xf00002e800000000, 0x60000100000000, // VSX Vector Test for software Divide Single-Precision XX3-form (xvtdivsp BF,XA,XB)
  4451  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4452  	{XVTSQRTDP, 0xfc0007fc00000000, 0xf00003a800000000, 0x7f000100000000, // VSX Vector Test for software Square Root Double-Precision XX2-form (xvtsqrtdp BF,XB)
  4453  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
  4454  	{XVTSQRTSP, 0xfc0007fc00000000, 0xf00002a800000000, 0x7f000100000000, // VSX Vector Test for software Square Root Single-Precision XX2-form (xvtsqrtsp BF,XB)
  4455  		[6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
  4456  	{XXLAND, 0xfc0007f800000000, 0xf000041000000000, 0x0, // VSX Vector Logical AND XX3-form (xxland XT,XA,XB)
  4457  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4458  	{XXLANDC, 0xfc0007f800000000, 0xf000045000000000, 0x0, // VSX Vector Logical AND with Complement XX3-form (xxlandc XT,XA,XB)
  4459  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4460  	{XXLNOR, 0xfc0007f800000000, 0xf000051000000000, 0x0, // VSX Vector Logical NOR XX3-form (xxlnor XT,XA,XB)
  4461  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4462  	{XXLOR, 0xfc0007f800000000, 0xf000049000000000, 0x0, // VSX Vector Logical OR XX3-form (xxlor XT,XA,XB)
  4463  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4464  	{XXLXOR, 0xfc0007f800000000, 0xf00004d000000000, 0x0, // VSX Vector Logical XOR XX3-form (xxlxor XT,XA,XB)
  4465  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4466  	{XXMRGHW, 0xfc0007f800000000, 0xf000009000000000, 0x0, // VSX Vector Merge High Word XX3-form (xxmrghw XT,XA,XB)
  4467  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4468  	{XXMRGLW, 0xfc0007f800000000, 0xf000019000000000, 0x0, // VSX Vector Merge Low Word XX3-form (xxmrglw XT,XA,XB)
  4469  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
  4470  	{XXPERMDI, 0xfc0004f800000000, 0xf000005000000000, 0x0, // VSX Vector Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM)
  4471  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
  4472  	{XXSEL, 0xfc00003000000000, 0xf000003000000000, 0x0, // VSX Vector Select XX4-form (xxsel XT,XA,XB,XC)
  4473  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}},
  4474  	{XXSLDWI, 0xfc0004f800000000, 0xf000001000000000, 0x0, // VSX Vector Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW)
  4475  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
  4476  	{XXSPLTW, 0xfc0007fc00000000, 0xf000029000000000, 0x1c000000000000, // VSX Vector Splat Word XX2-form (xxspltw XT,XB,UIM)
  4477  		[6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}},
  4478  	{CMPB, 0xfc0007fe00000000, 0x7c0003f800000000, 0x100000000, // Compare Bytes X-form (cmpb RA,RS,RB)
  4479  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  4480  	{DADD, 0xfc0007ff00000000, 0xec00000400000000, 0x0, // DFP Add X-form (dadd FRT,FRA,FRB)
  4481  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4482  	{DADDCC, 0xfc0007ff00000000, 0xec00000500000000, 0x0, // DFP Add X-form (dadd. FRT,FRA,FRB)
  4483  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4484  	{DADDQ, 0xfc0007ff00000000, 0xfc00000400000000, 0x0, // DFP Add Quad X-form (daddq FRTp,FRAp,FRBp)
  4485  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4486  	{DADDQCC, 0xfc0007ff00000000, 0xfc00000500000000, 0x0, // DFP Add Quad X-form (daddq. FRTp,FRAp,FRBp)
  4487  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4488  	{DCFFIXQ, 0xfc0007ff00000000, 0xfc00064400000000, 0x1f000000000000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB)
  4489  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4490  	{DCFFIXQCC, 0xfc0007ff00000000, 0xfc00064500000000, 0x1f000000000000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB)
  4491  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4492  	{DCMPO, 0xfc0007fe00000000, 0xec00010400000000, 0x60000100000000, // DFP Compare Ordered X-form (dcmpo BF,FRA,FRB)
  4493  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4494  	{DCMPOQ, 0xfc0007fe00000000, 0xfc00010400000000, 0x60000100000000, // DFP Compare Ordered Quad X-form (dcmpoq BF,FRAp,FRBp)
  4495  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4496  	{DCMPU, 0xfc0007fe00000000, 0xec00050400000000, 0x60000100000000, // DFP Compare Unordered X-form (dcmpu BF,FRA,FRB)
  4497  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4498  	{DCMPUQ, 0xfc0007fe00000000, 0xfc00050400000000, 0x60000100000000, // DFP Compare Unordered Quad X-form (dcmpuq BF,FRAp,FRBp)
  4499  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4500  	{DCTDP, 0xfc0007ff00000000, 0xec00020400000000, 0x1f000000000000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB)
  4501  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4502  	{DCTDPCC, 0xfc0007ff00000000, 0xec00020500000000, 0x1f000000000000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB)
  4503  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4504  	{DCTFIX, 0xfc0007ff00000000, 0xec00024400000000, 0x1f000000000000, // DFP Convert To Fixed X-form (dctfix FRT,FRB)
  4505  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4506  	{DCTFIXCC, 0xfc0007ff00000000, 0xec00024500000000, 0x1f000000000000, // DFP Convert To Fixed X-form (dctfix. FRT,FRB)
  4507  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4508  	{DCTFIXQ, 0xfc0007ff00000000, 0xfc00024400000000, 0x1f000000000000, // DFP Convert To Fixed Quad X-form (dctfixq FRT,FRBp)
  4509  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4510  	{DCTFIXQCC, 0xfc0007ff00000000, 0xfc00024500000000, 0x1f000000000000, // DFP Convert To Fixed Quad X-form (dctfixq. FRT,FRBp)
  4511  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4512  	{DCTQPQ, 0xfc0007ff00000000, 0xfc00020400000000, 0x1f000000000000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB)
  4513  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4514  	{DCTQPQCC, 0xfc0007ff00000000, 0xfc00020500000000, 0x1f000000000000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB)
  4515  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4516  	{DDEDPD, 0xfc0007ff00000000, 0xec00028400000000, 0x7000000000000, // DFP Decode DPD To BCD X-form (ddedpd SP,FRT,FRB)
  4517  		[6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
  4518  	{DDEDPDCC, 0xfc0007ff00000000, 0xec00028500000000, 0x7000000000000, // DFP Decode DPD To BCD X-form (ddedpd. SP,FRT,FRB)
  4519  		[6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
  4520  	{DDEDPDQ, 0xfc0007ff00000000, 0xfc00028400000000, 0x7000000000000, // DFP Decode DPD To BCD Quad X-form (ddedpdq SP,FRTp,FRBp)
  4521  		[6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
  4522  	{DDEDPDQCC, 0xfc0007ff00000000, 0xfc00028500000000, 0x7000000000000, // DFP Decode DPD To BCD Quad X-form (ddedpdq. SP,FRTp,FRBp)
  4523  		[6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
  4524  	{DDIV, 0xfc0007ff00000000, 0xec00044400000000, 0x0, // DFP Divide X-form (ddiv FRT,FRA,FRB)
  4525  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4526  	{DDIVCC, 0xfc0007ff00000000, 0xec00044500000000, 0x0, // DFP Divide X-form (ddiv. FRT,FRA,FRB)
  4527  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4528  	{DDIVQ, 0xfc0007ff00000000, 0xfc00044400000000, 0x0, // DFP Divide Quad X-form (ddivq FRTp,FRAp,FRBp)
  4529  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4530  	{DDIVQCC, 0xfc0007ff00000000, 0xfc00044500000000, 0x0, // DFP Divide Quad X-form (ddivq. FRTp,FRAp,FRBp)
  4531  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4532  	{DENBCD, 0xfc0007ff00000000, 0xec00068400000000, 0xf000000000000, // DFP Encode BCD To DPD X-form (denbcd S,FRT,FRB)
  4533  		[6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
  4534  	{DENBCDCC, 0xfc0007ff00000000, 0xec00068500000000, 0xf000000000000, // DFP Encode BCD To DPD X-form (denbcd. S,FRT,FRB)
  4535  		[6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
  4536  	{DENBCDQ, 0xfc0007ff00000000, 0xfc00068400000000, 0xf000000000000, // DFP Encode BCD To DPD Quad X-form (denbcdq S,FRTp,FRBp)
  4537  		[6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
  4538  	{DENBCDQCC, 0xfc0007ff00000000, 0xfc00068500000000, 0xf000000000000, // DFP Encode BCD To DPD Quad X-form (denbcdq. S,FRTp,FRBp)
  4539  		[6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
  4540  	{DIEX, 0xfc0007ff00000000, 0xec0006c400000000, 0x0, // DFP Insert Biased Exponent X-form (diex FRT,FRA,FRB)
  4541  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4542  	{DIEXCC, 0xfc0007ff00000000, 0xec0006c500000000, 0x0, // DFP Insert Biased Exponent X-form (diex. FRT,FRA,FRB)
  4543  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4544  	{DIEXQCC, 0xfc0007ff00000000, 0xfc0006c500000000, 0x0, // DFP Insert Biased Exponent Quad X-form (diexq. FRTp,FRA,FRBp)
  4545  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4546  	{DIEXQ, 0xfc0007fe00000000, 0xfc0006c400000000, 0x0, // DFP Insert Biased Exponent Quad X-form (diexq FRTp,FRA,FRBp)
  4547  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4548  	{DMUL, 0xfc0007ff00000000, 0xec00004400000000, 0x0, // DFP Multiply X-form (dmul FRT,FRA,FRB)
  4549  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4550  	{DMULCC, 0xfc0007ff00000000, 0xec00004500000000, 0x0, // DFP Multiply X-form (dmul. FRT,FRA,FRB)
  4551  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4552  	{DMULQ, 0xfc0007ff00000000, 0xfc00004400000000, 0x0, // DFP Multiply Quad X-form (dmulq FRTp,FRAp,FRBp)
  4553  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4554  	{DMULQCC, 0xfc0007ff00000000, 0xfc00004500000000, 0x0, // DFP Multiply Quad X-form (dmulq. FRTp,FRAp,FRBp)
  4555  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4556  	{DQUA, 0xfc0001ff00000000, 0xec00000600000000, 0x0, // DFP Quantize Z23-form (dqua FRT,FRA,FRB,RMC)
  4557  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4558  	{DQUACC, 0xfc0001ff00000000, 0xec00000700000000, 0x0, // DFP Quantize Z23-form (dqua. FRT,FRA,FRB,RMC)
  4559  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4560  	{DQUAI, 0xfc0001ff00000000, 0xec00008600000000, 0x0, // DFP Quantize Immediate Z23-form (dquai TE,FRT,FRB,RMC)
  4561  		[6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4562  	{DQUAICC, 0xfc0001ff00000000, 0xec00008700000000, 0x0, // DFP Quantize Immediate Z23-form (dquai. TE,FRT,FRB,RMC)
  4563  		[6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4564  	{DQUAIQ, 0xfc0001ff00000000, 0xfc00008600000000, 0x0, // DFP Quantize Immediate Quad Z23-form (dquaiq TE,FRTp,FRBp,RMC)
  4565  		[6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4566  	{DQUAIQCC, 0xfc0001ff00000000, 0xfc00008700000000, 0x0, // DFP Quantize Immediate Quad Z23-form (dquaiq. TE,FRTp,FRBp,RMC)
  4567  		[6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4568  	{DQUAQ, 0xfc0001ff00000000, 0xfc00000600000000, 0x0, // DFP Quantize Quad Z23-form (dquaq FRTp,FRAp,FRBp,RMC)
  4569  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4570  	{DQUAQCC, 0xfc0001ff00000000, 0xfc00000700000000, 0x0, // DFP Quantize Quad Z23-form (dquaq. FRTp,FRAp,FRBp,RMC)
  4571  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4572  	{DRDPQ, 0xfc0007ff00000000, 0xfc00060400000000, 0x1f000000000000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp)
  4573  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4574  	{DRDPQCC, 0xfc0007ff00000000, 0xfc00060500000000, 0x1f000000000000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp)
  4575  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4576  	{DRINTN, 0xfc0001ff00000000, 0xec0001c600000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Z23-form (drintn R,FRT,FRB,RMC)
  4577  		[6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4578  	{DRINTNCC, 0xfc0001ff00000000, 0xec0001c700000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Z23-form (drintn. R,FRT,FRB,RMC)
  4579  		[6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4580  	{DRINTNQ, 0xfc0001ff00000000, 0xfc0001c600000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Quad Z23-form (drintnq R,FRTp,FRBp,RMC)
  4581  		[6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4582  	{DRINTNQCC, 0xfc0001ff00000000, 0xfc0001c700000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Quad Z23-form (drintnq. R,FRTp,FRBp,RMC)
  4583  		[6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4584  	{DRINTX, 0xfc0001ff00000000, 0xec0000c600000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Z23-form (drintx R,FRT,FRB,RMC)
  4585  		[6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4586  	{DRINTXCC, 0xfc0001ff00000000, 0xec0000c700000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Z23-form (drintx. R,FRT,FRB,RMC)
  4587  		[6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4588  	{DRINTXQ, 0xfc0001ff00000000, 0xfc0000c600000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Quad Z23-form (drintxq R,FRTp,FRBp,RMC)
  4589  		[6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4590  	{DRINTXQCC, 0xfc0001ff00000000, 0xfc0000c700000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Quad Z23-form (drintxq. R,FRTp,FRBp,RMC)
  4591  		[6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4592  	{DRRND, 0xfc0001ff00000000, 0xec00004600000000, 0x0, // DFP Reround Z23-form (drrnd FRT,FRA,FRB,RMC)
  4593  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4594  	{DRRNDCC, 0xfc0001ff00000000, 0xec00004700000000, 0x0, // DFP Reround Z23-form (drrnd. FRT,FRA,FRB,RMC)
  4595  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4596  	{DRRNDQ, 0xfc0001ff00000000, 0xfc00004600000000, 0x0, // DFP Reround Quad Z23-form (drrndq FRTp,FRA,FRBp,RMC)
  4597  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4598  	{DRRNDQCC, 0xfc0001ff00000000, 0xfc00004700000000, 0x0, // DFP Reround Quad Z23-form (drrndq. FRTp,FRA,FRBp,RMC)
  4599  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
  4600  	{DRSP, 0xfc0007ff00000000, 0xec00060400000000, 0x1f000000000000, // DFP Round To DFP Short X-form (drsp FRT,FRB)
  4601  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4602  	{DRSPCC, 0xfc0007ff00000000, 0xec00060500000000, 0x1f000000000000, // DFP Round To DFP Short X-form (drsp. FRT,FRB)
  4603  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4604  	{DSCLI, 0xfc0003ff00000000, 0xec00008400000000, 0x0, // DFP Shift Significand Left Immediate Z22-form (dscli FRT,FRA,SH)
  4605  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4606  	{DSCLICC, 0xfc0003ff00000000, 0xec00008500000000, 0x0, // DFP Shift Significand Left Immediate Z22-form (dscli. FRT,FRA,SH)
  4607  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4608  	{DSCLIQ, 0xfc0003ff00000000, 0xfc00008400000000, 0x0, // DFP Shift Significand Left Immediate Quad Z22-form (dscliq FRTp,FRAp,SH)
  4609  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4610  	{DSCLIQCC, 0xfc0003ff00000000, 0xfc00008500000000, 0x0, // DFP Shift Significand Left Immediate Quad Z22-form (dscliq. FRTp,FRAp,SH)
  4611  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4612  	{DSCRI, 0xfc0003ff00000000, 0xec0000c400000000, 0x0, // DFP Shift Significand Right Immediate Z22-form (dscri FRT,FRA,SH)
  4613  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4614  	{DSCRICC, 0xfc0003ff00000000, 0xec0000c500000000, 0x0, // DFP Shift Significand Right Immediate Z22-form (dscri. FRT,FRA,SH)
  4615  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4616  	{DSCRIQ, 0xfc0003ff00000000, 0xfc0000c400000000, 0x0, // DFP Shift Significand Right Immediate Quad Z22-form (dscriq FRTp,FRAp,SH)
  4617  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4618  	{DSCRIQCC, 0xfc0003ff00000000, 0xfc0000c500000000, 0x0, // DFP Shift Significand Right Immediate Quad Z22-form (dscriq. FRTp,FRAp,SH)
  4619  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4620  	{DSUB, 0xfc0007ff00000000, 0xec00040400000000, 0x0, // DFP Subtract X-form (dsub FRT,FRA,FRB)
  4621  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4622  	{DSUBCC, 0xfc0007ff00000000, 0xec00040500000000, 0x0, // DFP Subtract X-form (dsub. FRT,FRA,FRB)
  4623  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4624  	{DSUBQ, 0xfc0007ff00000000, 0xfc00040400000000, 0x0, // DFP Subtract Quad X-form (dsubq FRTp,FRAp,FRBp)
  4625  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4626  	{DSUBQCC, 0xfc0007ff00000000, 0xfc00040500000000, 0x0, // DFP Subtract Quad X-form (dsubq. FRTp,FRAp,FRBp)
  4627  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4628  	{DTSTDC, 0xfc0003fe00000000, 0xec00018400000000, 0x60000100000000, // DFP Test Data Class Z22-form (dtstdc BF,FRA,DCM)
  4629  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4630  	{DTSTDCQ, 0xfc0003fe00000000, 0xfc00018400000000, 0x60000100000000, // DFP Test Data Class Quad Z22-form (dtstdcq BF,FRAp,DCM)
  4631  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4632  	{DTSTDG, 0xfc0003fe00000000, 0xec0001c400000000, 0x60000100000000, // DFP Test Data Group Z22-form (dtstdg BF,FRA,DGM)
  4633  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4634  	{DTSTDGQ, 0xfc0003fe00000000, 0xfc0001c400000000, 0x60000100000000, // DFP Test Data Group Quad Z22-form (dtstdgq BF,FRAp,DGM)
  4635  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
  4636  	{DTSTEX, 0xfc0007fe00000000, 0xec00014400000000, 0x60000100000000, // DFP Test Exponent X-form (dtstex BF,FRA,FRB)
  4637  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4638  	{DTSTEXQ, 0xfc0007fe00000000, 0xfc00014400000000, 0x60000100000000, // DFP Test Exponent Quad X-form (dtstexq BF,FRAp,FRBp)
  4639  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4640  	{DTSTSF, 0xfc0007fe00000000, 0xec00054400000000, 0x60000100000000, // DFP Test Significance X-form (dtstsf BF,FRA,FRB)
  4641  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4642  	{DTSTSFQ, 0xfc0007fe00000000, 0xfc00054400000000, 0x60000100000000, // DFP Test Significance Quad X-form (dtstsfq BF,FRA,FRBp)
  4643  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  4644  	{DXEX, 0xfc0007ff00000000, 0xec0002c400000000, 0x1f000000000000, // DFP Extract Biased Exponent X-form (dxex FRT,FRB)
  4645  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4646  	{DXEXCC, 0xfc0007ff00000000, 0xec0002c500000000, 0x1f000000000000, // DFP Extract Biased Exponent X-form (dxex. FRT,FRB)
  4647  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4648  	{DXEXQ, 0xfc0007ff00000000, 0xfc0002c400000000, 0x1f000000000000, // DFP Extract Biased Exponent Quad X-form (dxexq FRT,FRBp)
  4649  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4650  	{DXEXQCC, 0xfc0007ff00000000, 0xfc0002c500000000, 0x1f000000000000, // DFP Extract Biased Exponent Quad X-form (dxexq. FRT,FRBp)
  4651  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  4652  	{FCPSGN, 0xfc0007ff00000000, 0xfc00001000000000, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB)
  4653  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4654  	{FCPSGNCC, 0xfc0007ff00000000, 0xfc00001100000000, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB)
  4655  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  4656  	{LBZCIX, 0xfc0007fe00000000, 0x7c0006aa00000000, 0x100000000, // Load Byte & Zero Caching Inhibited Indexed X-form (lbzcix RT,RA,RB)
  4657  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4658  	{LDCIX, 0xfc0007fe00000000, 0x7c0006ea00000000, 0x100000000, // Load Doubleword Caching Inhibited Indexed X-form (ldcix RT,RA,RB)
  4659  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4660  	{LFDP, 0xfc00000300000000, 0xe400000000000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA))
  4661  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  4662  	{LFDPX, 0xfc0007fe00000000, 0x7c00062e00000000, 0x100000000, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB)
  4663  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4664  	{LFIWAX, 0xfc0007fe00000000, 0x7c0006ae00000000, 0x100000000, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB)
  4665  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4666  	{LHZCIX, 0xfc0007fe00000000, 0x7c00066a00000000, 0x100000000, // Load Halfword & Zero Caching Inhibited Indexed X-form (lhzcix RT,RA,RB)
  4667  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4668  	{LWZCIX, 0xfc0007fe00000000, 0x7c00062a00000000, 0x100000000, // Load Word & Zero Caching Inhibited Indexed X-form (lwzcix RT,RA,RB)
  4669  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4670  	{PRTYD, 0xfc0007fe00000000, 0x7c00017400000000, 0xf80100000000, // Parity Doubleword X-form (prtyd RA,RS)
  4671  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  4672  	{PRTYW, 0xfc0007fe00000000, 0x7c00013400000000, 0xf80100000000, // Parity Word X-form (prtyw RA,RS)
  4673  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  4674  	{SLBFEECC, 0xfc0007ff00000000, 0x7c0007a700000000, 0x1f000000000000, // SLB Find Entry ESID X-form (slbfee. RT,RB)
  4675  		[6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
  4676  	{STBCIX, 0xfc0007fe00000000, 0x7c0007aa00000000, 0x100000000, // Store Byte Caching Inhibited Indexed X-form (stbcix RS,RA,RB)
  4677  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4678  	{STDCIX, 0xfc0007fe00000000, 0x7c0007ea00000000, 0x100000000, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB)
  4679  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4680  	{STFDP, 0xfc00000300000000, 0xf400000000000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA))
  4681  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  4682  	{STFDPX, 0xfc0007fe00000000, 0x7c00072e00000000, 0x100000000, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB)
  4683  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4684  	{STHCIX, 0xfc0007fe00000000, 0x7c00076a00000000, 0x100000000, // Store Halfword Caching Inhibited Indexed X-form (sthcix RS,RA,RB)
  4685  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4686  	{STWCIX, 0xfc0007fe00000000, 0x7c00072a00000000, 0x100000000, // Store Word Caching Inhibited Indexed X-form (stwcix RS,RA,RB)
  4687  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4688  	{ISEL, 0xfc00003e00000000, 0x7c00001e00000000, 0x100000000, // Integer Select A-form (isel RT,RA,RB,BC)
  4689  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}},
  4690  	{LVEBX, 0xfc0007fe00000000, 0x7c00000e00000000, 0x100000000, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB)
  4691  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4692  	{LVEHX, 0xfc0007fe00000000, 0x7c00004e00000000, 0x100000000, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB)
  4693  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4694  	{LVEWX, 0xfc0007fe00000000, 0x7c00008e00000000, 0x100000000, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB)
  4695  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4696  	{LVSL, 0xfc0007fe00000000, 0x7c00000c00000000, 0x100000000, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB)
  4697  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4698  	{LVSR, 0xfc0007fe00000000, 0x7c00004c00000000, 0x100000000, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB)
  4699  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4700  	{LVX, 0xfc0007fe00000000, 0x7c0000ce00000000, 0x100000000, // Load Vector Indexed X-form (lvx VRT,RA,RB)
  4701  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4702  	{LVXL, 0xfc0007fe00000000, 0x7c0002ce00000000, 0x100000000, // Load Vector Indexed Last X-form (lvxl VRT,RA,RB)
  4703  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4704  	{MFVSCR, 0xfc0007ff00000000, 0x1000060400000000, 0x1ff80000000000, // Move From Vector Status and Control Register VX-form (mfvscr VRT)
  4705  		[6]*argField{ap_VecReg_6_10}},
  4706  	{MTVSCR, 0xfc0007ff00000000, 0x1000064400000000, 0x3ff000000000000, // Move To Vector Status and Control Register VX-form (mtvscr VRB)
  4707  		[6]*argField{ap_VecReg_16_20}},
  4708  	{STVEBX, 0xfc0007fe00000000, 0x7c00010e00000000, 0x100000000, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB)
  4709  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4710  	{STVEHX, 0xfc0007fe00000000, 0x7c00014e00000000, 0x100000000, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB)
  4711  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4712  	{STVEWX, 0xfc0007fe00000000, 0x7c00018e00000000, 0x100000000, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB)
  4713  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4714  	{STVX, 0xfc0007fe00000000, 0x7c0001ce00000000, 0x100000000, // Store Vector Indexed X-form (stvx VRS,RA,RB)
  4715  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4716  	{STVXL, 0xfc0007fe00000000, 0x7c0003ce00000000, 0x100000000, // Store Vector Indexed Last X-form (stvxl VRS,RA,RB)
  4717  		[6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  4718  	{TLBIEL, 0xfc0007fe00000000, 0x7c00022400000000, 0x10000100000000, // TLB Invalidate Entry Local X-form (tlbiel RB,RS,RIC,PRS,R)
  4719  		[6]*argField{ap_Reg_16_20, ap_Reg_6_10, ap_ImmUnsigned_12_13, ap_ImmUnsigned_14_14, ap_ImmUnsigned_15_15}},
  4720  	{VADDCUW, 0xfc0007ff00000000, 0x1000018000000000, 0x0, // Vector Add & write Carry Unsigned Word VX-form (vaddcuw VRT,VRA,VRB)
  4721  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4722  	{VADDFP, 0xfc0007ff00000000, 0x1000000a00000000, 0x0, // Vector Add Floating-Point VX-form (vaddfp VRT,VRA,VRB)
  4723  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4724  	{VADDSBS, 0xfc0007ff00000000, 0x1000030000000000, 0x0, // Vector Add Signed Byte Saturate VX-form (vaddsbs VRT,VRA,VRB)
  4725  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4726  	{VADDSHS, 0xfc0007ff00000000, 0x1000034000000000, 0x0, // Vector Add Signed Halfword Saturate VX-form (vaddshs VRT,VRA,VRB)
  4727  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4728  	{VADDSWS, 0xfc0007ff00000000, 0x1000038000000000, 0x0, // Vector Add Signed Word Saturate VX-form (vaddsws VRT,VRA,VRB)
  4729  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4730  	{VADDUBM, 0xfc0007ff00000000, 0x1000000000000000, 0x0, // Vector Add Unsigned Byte Modulo VX-form (vaddubm VRT,VRA,VRB)
  4731  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4732  	{VADDUBS, 0xfc0007ff00000000, 0x1000020000000000, 0x0, // Vector Add Unsigned Byte Saturate VX-form (vaddubs VRT,VRA,VRB)
  4733  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4734  	{VADDUHM, 0xfc0007ff00000000, 0x1000004000000000, 0x0, // Vector Add Unsigned Halfword Modulo VX-form (vadduhm VRT,VRA,VRB)
  4735  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4736  	{VADDUHS, 0xfc0007ff00000000, 0x1000024000000000, 0x0, // Vector Add Unsigned Halfword Saturate VX-form (vadduhs VRT,VRA,VRB)
  4737  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4738  	{VADDUWM, 0xfc0007ff00000000, 0x1000008000000000, 0x0, // Vector Add Unsigned Word Modulo VX-form (vadduwm VRT,VRA,VRB)
  4739  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4740  	{VADDUWS, 0xfc0007ff00000000, 0x1000028000000000, 0x0, // Vector Add Unsigned Word Saturate VX-form (vadduws VRT,VRA,VRB)
  4741  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4742  	{VAND, 0xfc0007ff00000000, 0x1000040400000000, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB)
  4743  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4744  	{VANDC, 0xfc0007ff00000000, 0x1000044400000000, 0x0, // Vector Logical AND with Complement VX-form (vandc VRT,VRA,VRB)
  4745  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4746  	{VAVGSB, 0xfc0007ff00000000, 0x1000050200000000, 0x0, // Vector Average Signed Byte VX-form (vavgsb VRT,VRA,VRB)
  4747  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4748  	{VAVGSH, 0xfc0007ff00000000, 0x1000054200000000, 0x0, // Vector Average Signed Halfword VX-form (vavgsh VRT,VRA,VRB)
  4749  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4750  	{VAVGSW, 0xfc0007ff00000000, 0x1000058200000000, 0x0, // Vector Average Signed Word VX-form (vavgsw VRT,VRA,VRB)
  4751  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4752  	{VAVGUB, 0xfc0007ff00000000, 0x1000040200000000, 0x0, // Vector Average Unsigned Byte VX-form (vavgub VRT,VRA,VRB)
  4753  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4754  	{VAVGUH, 0xfc0007ff00000000, 0x1000044200000000, 0x0, // Vector Average Unsigned Halfword VX-form (vavguh VRT,VRA,VRB)
  4755  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4756  	{VAVGUW, 0xfc0007ff00000000, 0x1000048200000000, 0x0, // Vector Average Unsigned Word VX-form (vavguw VRT,VRA,VRB)
  4757  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4758  	{VCFSX, 0xfc0007ff00000000, 0x1000034a00000000, 0x0, // Vector Convert with round to nearest From Signed Word to floating-point format VX-form (vcfsx VRT,VRB,UIM)
  4759  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
  4760  	{VCFUX, 0xfc0007ff00000000, 0x1000030a00000000, 0x0, // Vector Convert with round to nearest From Unsigned Word to floating-point format VX-form (vcfux VRT,VRB,UIM)
  4761  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
  4762  	{VCMPBFP, 0xfc0007ff00000000, 0x100003c600000000, 0x0, // Vector Compare Bounds Floating-Point VC-form (vcmpbfp VRT,VRA,VRB)
  4763  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4764  	{VCMPBFPCC, 0xfc0007ff00000000, 0x100007c600000000, 0x0, // Vector Compare Bounds Floating-Point VC-form (vcmpbfp. VRT,VRA,VRB)
  4765  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4766  	{VCMPEQFP, 0xfc0007ff00000000, 0x100000c600000000, 0x0, // Vector Compare Equal Floating-Point VC-form (vcmpeqfp VRT,VRA,VRB)
  4767  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4768  	{VCMPEQFPCC, 0xfc0007ff00000000, 0x100004c600000000, 0x0, // Vector Compare Equal Floating-Point VC-form (vcmpeqfp. VRT,VRA,VRB)
  4769  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4770  	{VCMPEQUB, 0xfc0007ff00000000, 0x1000000600000000, 0x0, // Vector Compare Equal Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB)
  4771  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4772  	{VCMPEQUBCC, 0xfc0007ff00000000, 0x1000040600000000, 0x0, // Vector Compare Equal Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB)
  4773  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4774  	{VCMPEQUH, 0xfc0007ff00000000, 0x1000004600000000, 0x0, // Vector Compare Equal Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB)
  4775  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4776  	{VCMPEQUHCC, 0xfc0007ff00000000, 0x1000044600000000, 0x0, // Vector Compare Equal Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB)
  4777  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4778  	{VCMPEQUW, 0xfc0007ff00000000, 0x1000008600000000, 0x0, // Vector Compare Equal Unsigned Word VC-form (vcmpequw VRT,VRA,VRB)
  4779  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4780  	{VCMPEQUWCC, 0xfc0007ff00000000, 0x1000048600000000, 0x0, // Vector Compare Equal Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB)
  4781  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4782  	{VCMPGEFP, 0xfc0007ff00000000, 0x100001c600000000, 0x0, // Vector Compare Greater Than or Equal Floating-Point VC-form (vcmpgefp VRT,VRA,VRB)
  4783  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4784  	{VCMPGEFPCC, 0xfc0007ff00000000, 0x100005c600000000, 0x0, // Vector Compare Greater Than or Equal Floating-Point VC-form (vcmpgefp. VRT,VRA,VRB)
  4785  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4786  	{VCMPGTFP, 0xfc0007ff00000000, 0x100002c600000000, 0x0, // Vector Compare Greater Than Floating-Point VC-form (vcmpgtfp VRT,VRA,VRB)
  4787  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4788  	{VCMPGTFPCC, 0xfc0007ff00000000, 0x100006c600000000, 0x0, // Vector Compare Greater Than Floating-Point VC-form (vcmpgtfp. VRT,VRA,VRB)
  4789  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4790  	{VCMPGTSB, 0xfc0007ff00000000, 0x1000030600000000, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB)
  4791  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4792  	{VCMPGTSBCC, 0xfc0007ff00000000, 0x1000070600000000, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB)
  4793  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4794  	{VCMPGTSH, 0xfc0007ff00000000, 0x1000034600000000, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB)
  4795  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4796  	{VCMPGTSHCC, 0xfc0007ff00000000, 0x1000074600000000, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB)
  4797  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4798  	{VCMPGTSW, 0xfc0007ff00000000, 0x1000038600000000, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB)
  4799  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4800  	{VCMPGTSWCC, 0xfc0007ff00000000, 0x1000078600000000, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB)
  4801  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4802  	{VCMPGTUB, 0xfc0007ff00000000, 0x1000020600000000, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB)
  4803  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4804  	{VCMPGTUBCC, 0xfc0007ff00000000, 0x1000060600000000, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB)
  4805  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4806  	{VCMPGTUH, 0xfc0007ff00000000, 0x1000024600000000, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB)
  4807  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4808  	{VCMPGTUHCC, 0xfc0007ff00000000, 0x1000064600000000, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB)
  4809  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4810  	{VCMPGTUW, 0xfc0007ff00000000, 0x1000028600000000, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB)
  4811  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4812  	{VCMPGTUWCC, 0xfc0007ff00000000, 0x1000068600000000, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB)
  4813  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4814  	{VCTSXS, 0xfc0007ff00000000, 0x100003ca00000000, 0x0, // Vector Convert with round to zero from floating-point To Signed Word format Saturate VX-form (vctsxs VRT,VRB,UIM)
  4815  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
  4816  	{VCTUXS, 0xfc0007ff00000000, 0x1000038a00000000, 0x0, // Vector Convert with round to zero from floating-point To Unsigned Word format Saturate VX-form (vctuxs VRT,VRB,UIM)
  4817  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
  4818  	{VEXPTEFP, 0xfc0007ff00000000, 0x1000018a00000000, 0x1f000000000000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB)
  4819  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4820  	{VLOGEFP, 0xfc0007ff00000000, 0x100001ca00000000, 0x1f000000000000, // Vector Log Base 2 Estimate Floating-Point VX-form (vlogefp VRT,VRB)
  4821  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4822  	{VMADDFP, 0xfc00003f00000000, 0x1000002e00000000, 0x0, // Vector Multiply-Add Floating-Point VA-form (vmaddfp VRT,VRA,VRC,VRB)
  4823  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
  4824  	{VMAXFP, 0xfc0007ff00000000, 0x1000040a00000000, 0x0, // Vector Maximum Floating-Point VX-form (vmaxfp VRT,VRA,VRB)
  4825  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4826  	{VMAXSB, 0xfc0007ff00000000, 0x1000010200000000, 0x0, // Vector Maximum Signed Byte VX-form (vmaxsb VRT,VRA,VRB)
  4827  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4828  	{VMAXSH, 0xfc0007ff00000000, 0x1000014200000000, 0x0, // Vector Maximum Signed Halfword VX-form (vmaxsh VRT,VRA,VRB)
  4829  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4830  	{VMAXSW, 0xfc0007ff00000000, 0x1000018200000000, 0x0, // Vector Maximum Signed Word VX-form (vmaxsw VRT,VRA,VRB)
  4831  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4832  	{VMAXUB, 0xfc0007ff00000000, 0x1000000200000000, 0x0, // Vector Maximum Unsigned Byte VX-form (vmaxub VRT,VRA,VRB)
  4833  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4834  	{VMAXUH, 0xfc0007ff00000000, 0x1000004200000000, 0x0, // Vector Maximum Unsigned Halfword VX-form (vmaxuh VRT,VRA,VRB)
  4835  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4836  	{VMAXUW, 0xfc0007ff00000000, 0x1000008200000000, 0x0, // Vector Maximum Unsigned Word VX-form (vmaxuw VRT,VRA,VRB)
  4837  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4838  	{VMHADDSHS, 0xfc00003f00000000, 0x1000002000000000, 0x0, // Vector Multiply-High-Add Signed Halfword Saturate VA-form (vmhaddshs VRT,VRA,VRB,VRC)
  4839  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4840  	{VMHRADDSHS, 0xfc00003f00000000, 0x1000002100000000, 0x0, // Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form (vmhraddshs VRT,VRA,VRB,VRC)
  4841  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4842  	{VMINFP, 0xfc0007ff00000000, 0x1000044a00000000, 0x0, // Vector Minimum Floating-Point VX-form (vminfp VRT,VRA,VRB)
  4843  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4844  	{VMINSB, 0xfc0007ff00000000, 0x1000030200000000, 0x0, // Vector Minimum Signed Byte VX-form (vminsb VRT,VRA,VRB)
  4845  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4846  	{VMINSH, 0xfc0007ff00000000, 0x1000034200000000, 0x0, // Vector Minimum Signed Halfword VX-form (vminsh VRT,VRA,VRB)
  4847  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4848  	{VMINSW, 0xfc0007ff00000000, 0x1000038200000000, 0x0, // Vector Minimum Signed Word VX-form (vminsw VRT,VRA,VRB)
  4849  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4850  	{VMINUB, 0xfc0007ff00000000, 0x1000020200000000, 0x0, // Vector Minimum Unsigned Byte VX-form (vminub VRT,VRA,VRB)
  4851  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4852  	{VMINUH, 0xfc0007ff00000000, 0x1000024200000000, 0x0, // Vector Minimum Unsigned Halfword VX-form (vminuh VRT,VRA,VRB)
  4853  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4854  	{VMINUW, 0xfc0007ff00000000, 0x1000028200000000, 0x0, // Vector Minimum Unsigned Word VX-form (vminuw VRT,VRA,VRB)
  4855  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4856  	{VMLADDUHM, 0xfc00003f00000000, 0x1000002200000000, 0x0, // Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form (vmladduhm VRT,VRA,VRB,VRC)
  4857  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4858  	{VMRGHB, 0xfc0007ff00000000, 0x1000000c00000000, 0x0, // Vector Merge High Byte VX-form (vmrghb VRT,VRA,VRB)
  4859  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4860  	{VMRGHH, 0xfc0007ff00000000, 0x1000004c00000000, 0x0, // Vector Merge High Halfword VX-form (vmrghh VRT,VRA,VRB)
  4861  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4862  	{VMRGHW, 0xfc0007ff00000000, 0x1000008c00000000, 0x0, // Vector Merge High Word VX-form (vmrghw VRT,VRA,VRB)
  4863  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4864  	{VMRGLB, 0xfc0007ff00000000, 0x1000010c00000000, 0x0, // Vector Merge Low Byte VX-form (vmrglb VRT,VRA,VRB)
  4865  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4866  	{VMRGLH, 0xfc0007ff00000000, 0x1000014c00000000, 0x0, // Vector Merge Low Halfword VX-form (vmrglh VRT,VRA,VRB)
  4867  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4868  	{VMRGLW, 0xfc0007ff00000000, 0x1000018c00000000, 0x0, // Vector Merge Low Word VX-form (vmrglw VRT,VRA,VRB)
  4869  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4870  	{VMSUMMBM, 0xfc00003f00000000, 0x1000002500000000, 0x0, // Vector Multiply-Sum Mixed Byte Modulo VA-form (vmsummbm VRT,VRA,VRB,VRC)
  4871  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4872  	{VMSUMSHM, 0xfc00003f00000000, 0x1000002800000000, 0x0, // Vector Multiply-Sum Signed Halfword Modulo VA-form (vmsumshm VRT,VRA,VRB,VRC)
  4873  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4874  	{VMSUMSHS, 0xfc00003f00000000, 0x1000002900000000, 0x0, // Vector Multiply-Sum Signed Halfword Saturate VA-form (vmsumshs VRT,VRA,VRB,VRC)
  4875  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4876  	{VMSUMUBM, 0xfc00003f00000000, 0x1000002400000000, 0x0, // Vector Multiply-Sum Unsigned Byte Modulo VA-form (vmsumubm VRT,VRA,VRB,VRC)
  4877  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4878  	{VMSUMUHM, 0xfc00003f00000000, 0x1000002600000000, 0x0, // Vector Multiply-Sum Unsigned Halfword Modulo VA-form (vmsumuhm VRT,VRA,VRB,VRC)
  4879  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4880  	{VMSUMUHS, 0xfc00003f00000000, 0x1000002700000000, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC)
  4881  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4882  	{VMULESB, 0xfc0007ff00000000, 0x1000030800000000, 0x0, // Vector Multiply Even Signed Byte VX-form (vmulesb VRT,VRA,VRB)
  4883  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4884  	{VMULESH, 0xfc0007ff00000000, 0x1000034800000000, 0x0, // Vector Multiply Even Signed Halfword VX-form (vmulesh VRT,VRA,VRB)
  4885  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4886  	{VMULEUB, 0xfc0007ff00000000, 0x1000020800000000, 0x0, // Vector Multiply Even Unsigned Byte VX-form (vmuleub VRT,VRA,VRB)
  4887  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4888  	{VMULEUH, 0xfc0007ff00000000, 0x1000024800000000, 0x0, // Vector Multiply Even Unsigned Halfword VX-form (vmuleuh VRT,VRA,VRB)
  4889  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4890  	{VMULOSB, 0xfc0007ff00000000, 0x1000010800000000, 0x0, // Vector Multiply Odd Signed Byte VX-form (vmulosb VRT,VRA,VRB)
  4891  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4892  	{VMULOSH, 0xfc0007ff00000000, 0x1000014800000000, 0x0, // Vector Multiply Odd Signed Halfword VX-form (vmulosh VRT,VRA,VRB)
  4893  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4894  	{VMULOUB, 0xfc0007ff00000000, 0x1000000800000000, 0x0, // Vector Multiply Odd Unsigned Byte VX-form (vmuloub VRT,VRA,VRB)
  4895  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4896  	{VMULOUH, 0xfc0007ff00000000, 0x1000004800000000, 0x0, // Vector Multiply Odd Unsigned Halfword VX-form (vmulouh VRT,VRA,VRB)
  4897  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4898  	{VNMSUBFP, 0xfc00003f00000000, 0x1000002f00000000, 0x0, // Vector Negative Multiply-Subtract Floating-Point VA-form (vnmsubfp VRT,VRA,VRC,VRB)
  4899  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
  4900  	{VNOR, 0xfc0007ff00000000, 0x1000050400000000, 0x0, // Vector Logical NOR VX-form (vnor VRT,VRA,VRB)
  4901  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4902  	{VOR, 0xfc0007ff00000000, 0x1000048400000000, 0x0, // Vector Logical OR VX-form (vor VRT,VRA,VRB)
  4903  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4904  	{VPERM, 0xfc00003f00000000, 0x1000002b00000000, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC)
  4905  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4906  	{VPKPX, 0xfc0007ff00000000, 0x1000030e00000000, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB)
  4907  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4908  	{VPKSHSS, 0xfc0007ff00000000, 0x1000018e00000000, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB)
  4909  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4910  	{VPKSHUS, 0xfc0007ff00000000, 0x1000010e00000000, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB)
  4911  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4912  	{VPKSWSS, 0xfc0007ff00000000, 0x100001ce00000000, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB)
  4913  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4914  	{VPKSWUS, 0xfc0007ff00000000, 0x1000014e00000000, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB)
  4915  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4916  	{VPKUHUM, 0xfc0007ff00000000, 0x1000000e00000000, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB)
  4917  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4918  	{VPKUHUS, 0xfc0007ff00000000, 0x1000008e00000000, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB)
  4919  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4920  	{VPKUWUM, 0xfc0007ff00000000, 0x1000004e00000000, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB)
  4921  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4922  	{VPKUWUS, 0xfc0007ff00000000, 0x100000ce00000000, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB)
  4923  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4924  	{VREFP, 0xfc0007ff00000000, 0x1000010a00000000, 0x1f000000000000, // Vector Reciprocal Estimate Floating-Point VX-form (vrefp VRT,VRB)
  4925  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4926  	{VRFIM, 0xfc0007ff00000000, 0x100002ca00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward -Infinity VX-form (vrfim VRT,VRB)
  4927  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4928  	{VRFIN, 0xfc0007ff00000000, 0x1000020a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer Nearest VX-form (vrfin VRT,VRB)
  4929  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4930  	{VRFIP, 0xfc0007ff00000000, 0x1000028a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward +Infinity VX-form (vrfip VRT,VRB)
  4931  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4932  	{VRFIZ, 0xfc0007ff00000000, 0x1000024a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward Zero VX-form (vrfiz VRT,VRB)
  4933  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4934  	{VRLB, 0xfc0007ff00000000, 0x1000000400000000, 0x0, // Vector Rotate Left Byte VX-form (vrlb VRT,VRA,VRB)
  4935  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4936  	{VRLH, 0xfc0007ff00000000, 0x1000004400000000, 0x0, // Vector Rotate Left Halfword VX-form (vrlh VRT,VRA,VRB)
  4937  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4938  	{VRLW, 0xfc0007ff00000000, 0x1000008400000000, 0x0, // Vector Rotate Left Word VX-form (vrlw VRT,VRA,VRB)
  4939  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4940  	{VRSQRTEFP, 0xfc0007ff00000000, 0x1000014a00000000, 0x1f000000000000, // Vector Reciprocal Square Root Estimate Floating-Point VX-form (vrsqrtefp VRT,VRB)
  4941  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  4942  	{VSEL, 0xfc00003f00000000, 0x1000002a00000000, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC)
  4943  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
  4944  	{VSL, 0xfc0007ff00000000, 0x100001c400000000, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB)
  4945  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4946  	{VSLB, 0xfc0007ff00000000, 0x1000010400000000, 0x0, // Vector Shift Left Byte VX-form (vslb VRT,VRA,VRB)
  4947  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4948  	{VSLDOI, 0xfc00003f00000000, 0x1000002c00000000, 0x40000000000, // Vector Shift Left Double by Octet Immediate VA-form (vsldoi VRT,VRA,VRB,SHB)
  4949  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}},
  4950  	{VSLH, 0xfc0007ff00000000, 0x1000014400000000, 0x0, // Vector Shift Left Halfword VX-form (vslh VRT,VRA,VRB)
  4951  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4952  	{VSLO, 0xfc0007ff00000000, 0x1000040c00000000, 0x0, // Vector Shift Left by Octet VX-form (vslo VRT,VRA,VRB)
  4953  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4954  	{VSLW, 0xfc0007ff00000000, 0x1000018400000000, 0x0, // Vector Shift Left Word VX-form (vslw VRT,VRA,VRB)
  4955  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4956  	{VSPLTB, 0xfc0007ff00000000, 0x1000020c00000000, 0x10000000000000, // Vector Splat Byte VX-form (vspltb VRT,VRB,UIM)
  4957  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
  4958  	{VSPLTH, 0xfc0007ff00000000, 0x1000024c00000000, 0x18000000000000, // Vector Splat Halfword VX-form (vsplth VRT,VRB,UIM)
  4959  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}},
  4960  	{VSPLTISB, 0xfc0007ff00000000, 0x1000030c00000000, 0xf80000000000, // Vector Splat Immediate Signed Byte VX-form (vspltisb VRT,SIM)
  4961  		[6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
  4962  	{VSPLTISH, 0xfc0007ff00000000, 0x1000034c00000000, 0xf80000000000, // Vector Splat Immediate Signed Halfword VX-form (vspltish VRT,SIM)
  4963  		[6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
  4964  	{VSPLTISW, 0xfc0007ff00000000, 0x1000038c00000000, 0xf80000000000, // Vector Splat Immediate Signed Word VX-form (vspltisw VRT,SIM)
  4965  		[6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
  4966  	{VSPLTW, 0xfc0007ff00000000, 0x1000028c00000000, 0x1c000000000000, // Vector Splat Word VX-form (vspltw VRT,VRB,UIM)
  4967  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}},
  4968  	{VSR, 0xfc0007ff00000000, 0x100002c400000000, 0x0, // Vector Shift Right VX-form (vsr VRT,VRA,VRB)
  4969  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4970  	{VSRAB, 0xfc0007ff00000000, 0x1000030400000000, 0x0, // Vector Shift Right Algebraic Byte VX-form (vsrab VRT,VRA,VRB)
  4971  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4972  	{VSRAH, 0xfc0007ff00000000, 0x1000034400000000, 0x0, // Vector Shift Right Algebraic Halfword VX-form (vsrah VRT,VRA,VRB)
  4973  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4974  	{VSRAW, 0xfc0007ff00000000, 0x1000038400000000, 0x0, // Vector Shift Right Algebraic Word VX-form (vsraw VRT,VRA,VRB)
  4975  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4976  	{VSRB, 0xfc0007ff00000000, 0x1000020400000000, 0x0, // Vector Shift Right Byte VX-form (vsrb VRT,VRA,VRB)
  4977  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4978  	{VSRH, 0xfc0007ff00000000, 0x1000024400000000, 0x0, // Vector Shift Right Halfword VX-form (vsrh VRT,VRA,VRB)
  4979  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4980  	{VSRO, 0xfc0007ff00000000, 0x1000044c00000000, 0x0, // Vector Shift Right by Octet VX-form (vsro VRT,VRA,VRB)
  4981  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4982  	{VSRW, 0xfc0007ff00000000, 0x1000028400000000, 0x0, // Vector Shift Right Word VX-form (vsrw VRT,VRA,VRB)
  4983  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4984  	{VSUBCUW, 0xfc0007ff00000000, 0x1000058000000000, 0x0, // Vector Subtract & Write Carry-out Unsigned Word VX-form (vsubcuw VRT,VRA,VRB)
  4985  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4986  	{VSUBFP, 0xfc0007ff00000000, 0x1000004a00000000, 0x0, // Vector Subtract Floating-Point VX-form (vsubfp VRT,VRA,VRB)
  4987  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4988  	{VSUBSBS, 0xfc0007ff00000000, 0x1000070000000000, 0x0, // Vector Subtract Signed Byte Saturate VX-form (vsubsbs VRT,VRA,VRB)
  4989  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4990  	{VSUBSHS, 0xfc0007ff00000000, 0x1000074000000000, 0x0, // Vector Subtract Signed Halfword Saturate VX-form (vsubshs VRT,VRA,VRB)
  4991  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4992  	{VSUBSWS, 0xfc0007ff00000000, 0x1000078000000000, 0x0, // Vector Subtract Signed Word Saturate VX-form (vsubsws VRT,VRA,VRB)
  4993  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4994  	{VSUBUBM, 0xfc0007ff00000000, 0x1000040000000000, 0x0, // Vector Subtract Unsigned Byte Modulo VX-form (vsububm VRT,VRA,VRB)
  4995  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4996  	{VSUBUBS, 0xfc0007ff00000000, 0x1000060000000000, 0x0, // Vector Subtract Unsigned Byte Saturate VX-form (vsububs VRT,VRA,VRB)
  4997  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  4998  	{VSUBUHM, 0xfc0007ff00000000, 0x1000044000000000, 0x0, // Vector Subtract Unsigned Halfword Modulo VX-form (vsubuhm VRT,VRA,VRB)
  4999  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5000  	{VSUBUHS, 0xfc0007ff00000000, 0x1000064000000000, 0x0, // Vector Subtract Unsigned Halfword Saturate VX-form (vsubuhs VRT,VRA,VRB)
  5001  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5002  	{VSUBUWM, 0xfc0007ff00000000, 0x1000048000000000, 0x0, // Vector Subtract Unsigned Word Modulo VX-form (vsubuwm VRT,VRA,VRB)
  5003  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5004  	{VSUBUWS, 0xfc0007ff00000000, 0x1000068000000000, 0x0, // Vector Subtract Unsigned Word Saturate VX-form (vsubuws VRT,VRA,VRB)
  5005  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5006  	{VSUM2SWS, 0xfc0007ff00000000, 0x1000068800000000, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB)
  5007  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5008  	{VSUM4SBS, 0xfc0007ff00000000, 0x1000070800000000, 0x0, // Vector Sum across Quarter Signed Byte Saturate VX-form (vsum4sbs VRT,VRA,VRB)
  5009  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5010  	{VSUM4SHS, 0xfc0007ff00000000, 0x1000064800000000, 0x0, // Vector Sum across Quarter Signed Halfword Saturate VX-form (vsum4shs VRT,VRA,VRB)
  5011  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5012  	{VSUM4UBS, 0xfc0007ff00000000, 0x1000060800000000, 0x0, // Vector Sum across Quarter Unsigned Byte Saturate VX-form (vsum4ubs VRT,VRA,VRB)
  5013  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5014  	{VSUMSWS, 0xfc0007ff00000000, 0x1000078800000000, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB)
  5015  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5016  	{VUPKHPX, 0xfc0007ff00000000, 0x1000034e00000000, 0x1f000000000000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB)
  5017  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  5018  	{VUPKHSB, 0xfc0007ff00000000, 0x1000020e00000000, 0x1f000000000000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB)
  5019  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  5020  	{VUPKHSH, 0xfc0007ff00000000, 0x1000024e00000000, 0x1f000000000000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB)
  5021  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  5022  	{VUPKLPX, 0xfc0007ff00000000, 0x100003ce00000000, 0x1f000000000000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB)
  5023  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  5024  	{VUPKLSB, 0xfc0007ff00000000, 0x1000028e00000000, 0x1f000000000000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB)
  5025  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  5026  	{VUPKLSH, 0xfc0007ff00000000, 0x100002ce00000000, 0x1f000000000000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB)
  5027  		[6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
  5028  	{VXOR, 0xfc0007ff00000000, 0x100004c400000000, 0x0, // Vector Logical XOR VX-form (vxor VRT,VRA,VRB)
  5029  		[6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
  5030  	{FRE, 0xfc00003f00000000, 0xfc00003000000000, 0x1f07c000000000, // Floating Reciprocal Estimate A-form (fre FRT,FRB)
  5031  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5032  	{FRECC, 0xfc00003f00000000, 0xfc00003100000000, 0x1f07c000000000, // Floating Reciprocal Estimate A-form (fre. FRT,FRB)
  5033  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5034  	{FRIM, 0xfc0007ff00000000, 0xfc0003d000000000, 0x1f000000000000, // Floating Round to Integer Minus X-form (frim FRT,FRB)
  5035  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5036  	{FRIMCC, 0xfc0007ff00000000, 0xfc0003d100000000, 0x1f000000000000, // Floating Round to Integer Minus X-form (frim. FRT,FRB)
  5037  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5038  	{FRIN, 0xfc0007ff00000000, 0xfc00031000000000, 0x1f000000000000, // Floating Round to Integer Nearest X-form (frin FRT,FRB)
  5039  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5040  	{FRINCC, 0xfc0007ff00000000, 0xfc00031100000000, 0x1f000000000000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB)
  5041  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5042  	{FRIP, 0xfc0007ff00000000, 0xfc00039000000000, 0x1f000000000000, // Floating Round to Integer Plus X-form (frip FRT,FRB)
  5043  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5044  	{FRIPCC, 0xfc0007ff00000000, 0xfc00039100000000, 0x1f000000000000, // Floating Round to Integer Plus X-form (frip. FRT,FRB)
  5045  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5046  	{FRIZ, 0xfc0007ff00000000, 0xfc00035000000000, 0x1f000000000000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB)
  5047  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5048  	{FRIZCC, 0xfc0007ff00000000, 0xfc00035100000000, 0x1f000000000000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB)
  5049  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5050  	{FRSQRTES, 0xfc00003f00000000, 0xec00003400000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate Single A-form (frsqrtes FRT,FRB)
  5051  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5052  	{FRSQRTESCC, 0xfc00003f00000000, 0xec00003500000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate Single A-form (frsqrtes. FRT,FRB)
  5053  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5054  	{HRFID, 0xfc0007fe00000000, 0x4c00022400000000, 0x3fff80100000000, // Return From Interrupt Doubleword Hypervisor XL-form (hrfid)
  5055  		[6]*argField{}},
  5056  	{POPCNTB, 0xfc0007fe00000000, 0x7c0000f400000000, 0xf80100000000, // Population Count Bytes X-form (popcntb RA, RS)
  5057  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5058  	{MFOCRF, 0xfc1007fe00000000, 0x7c10002600000000, 0x80100000000, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM)
  5059  		[6]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}},
  5060  	{MTOCRF, 0xfc1007fe00000000, 0x7c10012000000000, 0x80100000000, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS)
  5061  		[6]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
  5062  	{SLBMFEE, 0xfc0007fe00000000, 0x7c00072600000000, 0x1e000100000000, // SLB Move From Entry ESID X-form (slbmfee RT,RB)
  5063  		[6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
  5064  	{SLBMFEV, 0xfc0007fe00000000, 0x7c0006a600000000, 0x1e000100000000, // SLB Move From Entry VSID X-form (slbmfev RT,RB)
  5065  		[6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
  5066  	{SLBMTE, 0xfc0007fe00000000, 0x7c00032400000000, 0x1f000100000000, // SLB Move To Entry X-form (slbmte RS,RB)
  5067  		[6]*argField{ap_Reg_6_10, ap_Reg_16_20}},
  5068  	{RFSCV, 0xfc0007fe00000000, 0x4c0000a400000000, 0x3fff80100000000, // Return From System Call Vectored XL-form (rfscv)
  5069  		[6]*argField{}},
  5070  	{SCV, 0xfc00000300000000, 0x4400000100000000, 0x3fff01c00000000, // System Call Vectored SC-form (scv LEV)
  5071  		[6]*argField{ap_ImmUnsigned_20_26}},
  5072  	{LQ, 0xfc00000000000000, 0xe000000000000000, 0xf00000000, // Load Quadword DQ-form (lq RTp,DQ(RA))
  5073  		[6]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
  5074  	{STQ, 0xfc00000300000000, 0xf800000200000000, 0x0, // Store Quadword DS-form (stq RSp,DS(RA))
  5075  		[6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  5076  	{CNTLZD, 0xfc0007ff00000000, 0x7c00007400000000, 0xf80000000000, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS)
  5077  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5078  	{CNTLZDCC, 0xfc0007ff00000000, 0x7c00007500000000, 0xf80000000000, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS)
  5079  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5080  	{DCBF, 0xfc0007fe00000000, 0x7c0000ac00000000, 0x300000100000000, // Data Cache Block Flush X-form (dcbf RA,RB,L)
  5081  		[6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_8_10}},
  5082  	{DCBST, 0xfc0007fe00000000, 0x7c00006c00000000, 0x3e0000100000000, // Data Cache Block Store X-form (dcbst RA,RB)
  5083  		[6]*argField{ap_Reg_11_15, ap_Reg_16_20}},
  5084  	{DCBT, 0xfc0007fe00000000, 0x7c00022c00000000, 0x100000000, // Data Cache Block Touch X-form (dcbt RA,RB,TH)
  5085  		[6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
  5086  	{DCBTST, 0xfc0007fe00000000, 0x7c0001ec00000000, 0x100000000, // Data Cache Block Touch for Store X-form (dcbtst RA,RB,TH)
  5087  		[6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
  5088  	{DIVD, 0xfc0007ff00000000, 0x7c0003d200000000, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB)
  5089  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5090  	{DIVDCC, 0xfc0007ff00000000, 0x7c0003d300000000, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB)
  5091  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5092  	{DIVDO, 0xfc0007ff00000000, 0x7c0007d200000000, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB)
  5093  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5094  	{DIVDOCC, 0xfc0007ff00000000, 0x7c0007d300000000, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB)
  5095  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5096  	{DIVDU, 0xfc0007ff00000000, 0x7c00039200000000, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB)
  5097  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5098  	{DIVDUCC, 0xfc0007ff00000000, 0x7c00039300000000, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB)
  5099  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5100  	{DIVDUO, 0xfc0007ff00000000, 0x7c00079200000000, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB)
  5101  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5102  	{DIVDUOCC, 0xfc0007ff00000000, 0x7c00079300000000, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB)
  5103  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5104  	{DIVW, 0xfc0007ff00000000, 0x7c0003d600000000, 0x0, // Divide Word XO-form (divw RT,RA,RB)
  5105  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5106  	{DIVWCC, 0xfc0007ff00000000, 0x7c0003d700000000, 0x0, // Divide Word XO-form (divw. RT,RA,RB)
  5107  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5108  	{DIVWO, 0xfc0007ff00000000, 0x7c0007d600000000, 0x0, // Divide Word XO-form (divwo RT,RA,RB)
  5109  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5110  	{DIVWOCC, 0xfc0007ff00000000, 0x7c0007d700000000, 0x0, // Divide Word XO-form (divwo. RT,RA,RB)
  5111  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5112  	{DIVWU, 0xfc0007ff00000000, 0x7c00039600000000, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB)
  5113  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5114  	{DIVWUCC, 0xfc0007ff00000000, 0x7c00039700000000, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB)
  5115  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5116  	{DIVWUO, 0xfc0007ff00000000, 0x7c00079600000000, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB)
  5117  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5118  	{DIVWUOCC, 0xfc0007ff00000000, 0x7c00079700000000, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB)
  5119  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5120  	{EIEIO, 0xfc0007fe00000000, 0x7c0006ac00000000, 0x3fff80100000000, // Enforce In-order Execution of I/O X-form (eieio)
  5121  		[6]*argField{}},
  5122  	{EXTSB, 0xfc0007ff00000000, 0x7c00077400000000, 0xf80000000000, // Extend Sign Byte X-form (extsb RA,RS)
  5123  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5124  	{EXTSBCC, 0xfc0007ff00000000, 0x7c00077500000000, 0xf80000000000, // Extend Sign Byte X-form (extsb. RA,RS)
  5125  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5126  	{EXTSW, 0xfc0007ff00000000, 0x7c0007b400000000, 0xf80000000000, // Extend Sign Word X-form (extsw RA,RS)
  5127  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5128  	{EXTSWCC, 0xfc0007ff00000000, 0x7c0007b500000000, 0xf80000000000, // Extend Sign Word X-form (extsw. RA,RS)
  5129  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5130  	{FADDS, 0xfc00003f00000000, 0xec00002a00000000, 0x7c000000000, // Floating Add Single A-form (fadds FRT,FRA,FRB)
  5131  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5132  	{FADDSCC, 0xfc00003f00000000, 0xec00002b00000000, 0x7c000000000, // Floating Add Single A-form (fadds. FRT,FRA,FRB)
  5133  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5134  	{FCFID, 0xfc0007ff00000000, 0xfc00069c00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Double-Precision format X-form (fcfid FRT,FRB)
  5135  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5136  	{FCFIDCC, 0xfc0007ff00000000, 0xfc00069d00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Double-Precision format X-form (fcfid. FRT,FRB)
  5137  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5138  	{FCTID, 0xfc0007ff00000000, 0xfc00065c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Doubleword format X-form (fctid FRT,FRB)
  5139  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5140  	{FCTIDCC, 0xfc0007ff00000000, 0xfc00065d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Doubleword format X-form (fctid. FRT,FRB)
  5141  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5142  	{FCTIDZ, 0xfc0007ff00000000, 0xfc00065e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Doubleword format X-form (fctidz FRT,FRB)
  5143  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5144  	{FCTIDZCC, 0xfc0007ff00000000, 0xfc00065f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Doubleword format X-form (fctidz. FRT,FRB)
  5145  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5146  	{FDIVS, 0xfc00003f00000000, 0xec00002400000000, 0x7c000000000, // Floating Divide Single A-form (fdivs FRT,FRA,FRB)
  5147  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5148  	{FDIVSCC, 0xfc00003f00000000, 0xec00002500000000, 0x7c000000000, // Floating Divide Single A-form (fdivs. FRT,FRA,FRB)
  5149  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5150  	{FMADDS, 0xfc00003f00000000, 0xec00003a00000000, 0x0, // Floating Multiply-Add Single A-form (fmadds FRT,FRA,FRC,FRB)
  5151  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5152  	{FMADDSCC, 0xfc00003f00000000, 0xec00003b00000000, 0x0, // Floating Multiply-Add Single A-form (fmadds. FRT,FRA,FRC,FRB)
  5153  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5154  	{FMSUBS, 0xfc00003f00000000, 0xec00003800000000, 0x0, // Floating Multiply-Subtract Single A-form (fmsubs FRT,FRA,FRC,FRB)
  5155  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5156  	{FMSUBSCC, 0xfc00003f00000000, 0xec00003900000000, 0x0, // Floating Multiply-Subtract Single A-form (fmsubs. FRT,FRA,FRC,FRB)
  5157  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5158  	{FMULS, 0xfc00003f00000000, 0xec00003200000000, 0xf80000000000, // Floating Multiply Single A-form (fmuls FRT,FRA,FRC)
  5159  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
  5160  	{FMULSCC, 0xfc00003f00000000, 0xec00003300000000, 0xf80000000000, // Floating Multiply Single A-form (fmuls. FRT,FRA,FRC)
  5161  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
  5162  	{FNMADDS, 0xfc00003f00000000, 0xec00003e00000000, 0x0, // Floating Negative Multiply-Add Single A-form (fnmadds FRT,FRA,FRC,FRB)
  5163  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5164  	{FNMADDSCC, 0xfc00003f00000000, 0xec00003f00000000, 0x0, // Floating Negative Multiply-Add Single A-form (fnmadds. FRT,FRA,FRC,FRB)
  5165  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5166  	{FNMSUBS, 0xfc00003f00000000, 0xec00003c00000000, 0x0, // Floating Negative Multiply-Subtract Single A-form (fnmsubs FRT,FRA,FRC,FRB)
  5167  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5168  	{FNMSUBSCC, 0xfc00003f00000000, 0xec00003d00000000, 0x0, // Floating Negative Multiply-Subtract Single A-form (fnmsubs. FRT,FRA,FRC,FRB)
  5169  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5170  	{FRES, 0xfc00003f00000000, 0xec00003000000000, 0x1f07c000000000, // Floating Reciprocal Estimate Single A-form (fres FRT,FRB)
  5171  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5172  	{FRESCC, 0xfc00003f00000000, 0xec00003100000000, 0x1f07c000000000, // Floating Reciprocal Estimate Single A-form (fres. FRT,FRB)
  5173  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5174  	{FRSQRTE, 0xfc00003f00000000, 0xfc00003400000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate A-form (frsqrte FRT,FRB)
  5175  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5176  	{FRSQRTECC, 0xfc00003f00000000, 0xfc00003500000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate A-form (frsqrte. FRT,FRB)
  5177  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5178  	{FSEL, 0xfc00003f00000000, 0xfc00002e00000000, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB)
  5179  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5180  	{FSELCC, 0xfc00003f00000000, 0xfc00002f00000000, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB)
  5181  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5182  	{FSQRTS, 0xfc00003f00000000, 0xec00002c00000000, 0x1f07c000000000, // Floating Square Root Single A-form (fsqrts FRT,FRB)
  5183  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5184  	{FSQRTSCC, 0xfc00003f00000000, 0xec00002d00000000, 0x1f07c000000000, // Floating Square Root Single A-form (fsqrts. FRT,FRB)
  5185  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5186  	{FSUBS, 0xfc00003f00000000, 0xec00002800000000, 0x7c000000000, // Floating Subtract Single A-form (fsubs FRT,FRA,FRB)
  5187  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5188  	{FSUBSCC, 0xfc00003f00000000, 0xec00002900000000, 0x7c000000000, // Floating Subtract Single A-form (fsubs. FRT,FRA,FRB)
  5189  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5190  	{ICBI, 0xfc0007fe00000000, 0x7c0007ac00000000, 0x3e0000100000000, // Instruction Cache Block Invalidate X-form (icbi RA,RB)
  5191  		[6]*argField{ap_Reg_11_15, ap_Reg_16_20}},
  5192  	{LD, 0xfc00000300000000, 0xe800000000000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA))
  5193  		[6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  5194  	{LDARX, 0xfc0007fe00000000, 0x7c0000a800000000, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH)
  5195  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
  5196  	{LDU, 0xfc00000300000000, 0xe800000100000000, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA))
  5197  		[6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  5198  	{LDUX, 0xfc0007fe00000000, 0x7c00006a00000000, 0x100000000, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB)
  5199  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5200  	{LDX, 0xfc0007fe00000000, 0x7c00002a00000000, 0x100000000, // Load Doubleword Indexed X-form (ldx RT,RA,RB)
  5201  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5202  	{LWA, 0xfc00000300000000, 0xe800000200000000, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA))
  5203  		[6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  5204  	{LWARX, 0xfc0007fe00000000, 0x7c00002800000000, 0x0, // Load Word & Reserve Indexed X-form (lwarx RT,RA,RB,EH)
  5205  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
  5206  	{LWAUX, 0xfc0007fe00000000, 0x7c0002ea00000000, 0x100000000, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB)
  5207  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5208  	{LWAX, 0xfc0007fe00000000, 0x7c0002aa00000000, 0x100000000, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB)
  5209  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5210  	{MFTB, 0xfc0007fe00000000, 0x7c0002e600000000, 0x100000000, // Move From Time Base XFX-form (mftb RT,TBR)
  5211  		[6]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
  5212  	{MTMSRD, 0xfc0007fe00000000, 0x7c00016400000000, 0x1ef80100000000, // Move To MSR Doubleword X-form (mtmsrd RS,L)
  5213  		[6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
  5214  	{MULHD, 0xfc0003ff00000000, 0x7c00009200000000, 0x40000000000, // Multiply High Doubleword XO-form (mulhd RT,RA,RB)
  5215  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5216  	{MULHDCC, 0xfc0003ff00000000, 0x7c00009300000000, 0x40000000000, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB)
  5217  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5218  	{MULHDU, 0xfc0003ff00000000, 0x7c00001200000000, 0x40000000000, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB)
  5219  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5220  	{MULHDUCC, 0xfc0003ff00000000, 0x7c00001300000000, 0x40000000000, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB)
  5221  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5222  	{MULHW, 0xfc0003ff00000000, 0x7c00009600000000, 0x40000000000, // Multiply High Word XO-form (mulhw RT,RA,RB)
  5223  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5224  	{MULHWCC, 0xfc0003ff00000000, 0x7c00009700000000, 0x40000000000, // Multiply High Word XO-form (mulhw. RT,RA,RB)
  5225  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5226  	{MULHWU, 0xfc0003ff00000000, 0x7c00001600000000, 0x40000000000, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB)
  5227  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5228  	{MULHWUCC, 0xfc0003ff00000000, 0x7c00001700000000, 0x40000000000, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB)
  5229  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5230  	{MULLD, 0xfc0007ff00000000, 0x7c0001d200000000, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB)
  5231  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5232  	{MULLDCC, 0xfc0007ff00000000, 0x7c0001d300000000, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB)
  5233  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5234  	{MULLDO, 0xfc0007ff00000000, 0x7c0005d200000000, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB)
  5235  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5236  	{MULLDOCC, 0xfc0007ff00000000, 0x7c0005d300000000, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB)
  5237  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5238  	{RFID, 0xfc0007fe00000000, 0x4c00002400000000, 0x3fff80100000000, // Return from Interrupt Doubleword XL-form (rfid)
  5239  		[6]*argField{}},
  5240  	{RLDCL, 0xfc00001f00000000, 0x7800001000000000, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB)
  5241  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
  5242  	{RLDCLCC, 0xfc00001f00000000, 0x7800001100000000, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB)
  5243  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
  5244  	{RLDCR, 0xfc00001f00000000, 0x7800001200000000, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME)
  5245  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
  5246  	{RLDCRCC, 0xfc00001f00000000, 0x7800001300000000, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME)
  5247  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
  5248  	{RLDIC, 0xfc00001d00000000, 0x7800000800000000, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB)
  5249  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
  5250  	{RLDICCC, 0xfc00001d00000000, 0x7800000900000000, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB)
  5251  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
  5252  	{RLDICL, 0xfc00001d00000000, 0x7800000000000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB)
  5253  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
  5254  	{RLDICLCC, 0xfc00001d00000000, 0x7800000100000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB)
  5255  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
  5256  	{RLDICR, 0xfc00001d00000000, 0x7800000400000000, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME)
  5257  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
  5258  	{RLDICRCC, 0xfc00001d00000000, 0x7800000500000000, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME)
  5259  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
  5260  	{RLDIMI, 0xfc00001d00000000, 0x7800000c00000000, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB)
  5261  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
  5262  	{RLDIMICC, 0xfc00001d00000000, 0x7800000d00000000, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB)
  5263  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
  5264  	{SC, 0xfc00000200000000, 0x4400000200000000, 0x3fff01d00000000, // System Call SC-form (sc LEV)
  5265  		[6]*argField{ap_ImmUnsigned_20_26}},
  5266  	{SLBIA, 0xfc0007fe00000000, 0x7c0003e400000000, 0x31ff80100000000, // SLB Invalidate All X-form (slbia IH)
  5267  		[6]*argField{ap_ImmUnsigned_8_10}},
  5268  	{SLBIE, 0xfc0007fe00000000, 0x7c00036400000000, 0x3ff000100000000, // SLB Invalidate Entry X-form (slbie RB)
  5269  		[6]*argField{ap_Reg_16_20}},
  5270  	{SLD, 0xfc0007ff00000000, 0x7c00003600000000, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB)
  5271  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5272  	{SLDCC, 0xfc0007ff00000000, 0x7c00003700000000, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB)
  5273  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5274  	{SRAD, 0xfc0007ff00000000, 0x7c00063400000000, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB)
  5275  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5276  	{SRADCC, 0xfc0007ff00000000, 0x7c00063500000000, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB)
  5277  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5278  	{SRADI, 0xfc0007fd00000000, 0x7c00067400000000, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH)
  5279  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
  5280  	{SRADICC, 0xfc0007fd00000000, 0x7c00067500000000, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH)
  5281  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
  5282  	{SRD, 0xfc0007ff00000000, 0x7c00043600000000, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB)
  5283  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5284  	{SRDCC, 0xfc0007ff00000000, 0x7c00043700000000, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB)
  5285  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5286  	{STD, 0xfc00000300000000, 0xf800000000000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA))
  5287  		[6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  5288  	{STDCXCC, 0xfc0007ff00000000, 0x7c0001ad00000000, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB)
  5289  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5290  	{STDU, 0xfc00000300000000, 0xf800000100000000, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA))
  5291  		[6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
  5292  	{STDUX, 0xfc0007fe00000000, 0x7c00016a00000000, 0x100000000, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB)
  5293  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5294  	{STDX, 0xfc0007fe00000000, 0x7c00012a00000000, 0x100000000, // Store Doubleword Indexed X-form (stdx RS,RA,RB)
  5295  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5296  	{STFIWX, 0xfc0007fe00000000, 0x7c0007ae00000000, 0x100000000, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB)
  5297  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5298  	{STWCXCC, 0xfc0007ff00000000, 0x7c00012d00000000, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB)
  5299  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5300  	{SUBF, 0xfc0007ff00000000, 0x7c00005000000000, 0x0, // Subtract From XO-form (subf RT,RA,RB)
  5301  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5302  	{SUBFCC, 0xfc0007ff00000000, 0x7c00005100000000, 0x0, // Subtract From XO-form (subf. RT,RA,RB)
  5303  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5304  	{SUBFO, 0xfc0007ff00000000, 0x7c00045000000000, 0x0, // Subtract From XO-form (subfo RT,RA,RB)
  5305  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5306  	{SUBFOCC, 0xfc0007ff00000000, 0x7c00045100000000, 0x0, // Subtract From XO-form (subfo. RT,RA,RB)
  5307  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5308  	{TD, 0xfc0007fe00000000, 0x7c00008800000000, 0x100000000, // Trap Doubleword X-form (td TO,RA,RB)
  5309  		[6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5310  	{TDI, 0xfc00000000000000, 0x800000000000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI)
  5311  		[6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5312  	{TLBSYNC, 0xfc0007fe00000000, 0x7c00046c00000000, 0x3fff80100000000, // TLB Synchronize X-form (tlbsync)
  5313  		[6]*argField{}},
  5314  	{FCTIW, 0xfc0007ff00000000, 0xfc00001c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Word format X-form (fctiw FRT,FRB)
  5315  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5316  	{FCTIWCC, 0xfc0007ff00000000, 0xfc00001d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Word format X-form (fctiw. FRT,FRB)
  5317  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5318  	{FCTIWZ, 0xfc0007ff00000000, 0xfc00001e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Word fomat X-form (fctiwz FRT,FRB)
  5319  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5320  	{FCTIWZCC, 0xfc0007ff00000000, 0xfc00001f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Word fomat X-form (fctiwz. FRT,FRB)
  5321  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5322  	{FSQRT, 0xfc00003f00000000, 0xfc00002c00000000, 0x1f07c000000000, // Floating Square Root A-form (fsqrt FRT,FRB)
  5323  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5324  	{FSQRTCC, 0xfc00003f00000000, 0xfc00002d00000000, 0x1f07c000000000, // Floating Square Root A-form (fsqrt. FRT,FRB)
  5325  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5326  	{ADD, 0xfc0007ff00000000, 0x7c00021400000000, 0x0, // Add XO-form (add RT,RA,RB)
  5327  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5328  	{ADDCC, 0xfc0007ff00000000, 0x7c00021500000000, 0x0, // Add XO-form (add. RT,RA,RB)
  5329  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5330  	{ADDO, 0xfc0007ff00000000, 0x7c00061400000000, 0x0, // Add XO-form (addo RT,RA,RB)
  5331  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5332  	{ADDOCC, 0xfc0007ff00000000, 0x7c00061500000000, 0x0, // Add XO-form (addo. RT,RA,RB)
  5333  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5334  	{ADDC, 0xfc0007ff00000000, 0x7c00001400000000, 0x0, // Add Carrying XO-form (addc RT,RA,RB)
  5335  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5336  	{ADDCCC, 0xfc0007ff00000000, 0x7c00001500000000, 0x0, // Add Carrying XO-form (addc. RT,RA,RB)
  5337  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5338  	{ADDCO, 0xfc0007ff00000000, 0x7c00041400000000, 0x0, // Add Carrying XO-form (addco RT,RA,RB)
  5339  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5340  	{ADDCOCC, 0xfc0007ff00000000, 0x7c00041500000000, 0x0, // Add Carrying XO-form (addco. RT,RA,RB)
  5341  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5342  	{ADDE, 0xfc0007ff00000000, 0x7c00011400000000, 0x0, // Add Extended XO-form (adde RT,RA,RB)
  5343  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5344  	{ADDECC, 0xfc0007ff00000000, 0x7c00011500000000, 0x0, // Add Extended XO-form (adde. RT,RA,RB)
  5345  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5346  	{ADDEO, 0xfc0007ff00000000, 0x7c00051400000000, 0x0, // Add Extended XO-form (addeo RT,RA,RB)
  5347  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5348  	{ADDEOCC, 0xfc0007ff00000000, 0x7c00051500000000, 0x0, // Add Extended XO-form (addeo. RT,RA,RB)
  5349  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5350  	{LI, 0xfc1f000000000000, 0x3800000000000000, 0x0, // Add Immediate D-form (li RT,SI)
  5351  		[6]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
  5352  	{ADDI, 0xfc00000000000000, 0x3800000000000000, 0x0, // Add Immediate D-form (addi RT,RA,SI)
  5353  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5354  	{ADDIC, 0xfc00000000000000, 0x3000000000000000, 0x0, // Add Immediate Carrying D-form (addic RT,RA,SI)
  5355  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5356  	{ADDICCC, 0xfc00000000000000, 0x3400000000000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI)
  5357  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5358  	{LIS, 0xfc1f000000000000, 0x3c00000000000000, 0x0, // Add Immediate Shifted D-form (lis RT,SI)
  5359  		[6]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
  5360  	{ADDIS, 0xfc00000000000000, 0x3c00000000000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI)
  5361  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5362  	{ADDME, 0xfc0007ff00000000, 0x7c0001d400000000, 0xf80000000000, // Add to Minus One Extended XO-form (addme RT,RA)
  5363  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5364  	{ADDMECC, 0xfc0007ff00000000, 0x7c0001d500000000, 0xf80000000000, // Add to Minus One Extended XO-form (addme. RT,RA)
  5365  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5366  	{ADDMEO, 0xfc0007ff00000000, 0x7c0005d400000000, 0xf80000000000, // Add to Minus One Extended XO-form (addmeo RT,RA)
  5367  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5368  	{ADDMEOCC, 0xfc0007ff00000000, 0x7c0005d500000000, 0xf80000000000, // Add to Minus One Extended XO-form (addmeo. RT,RA)
  5369  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5370  	{ADDZE, 0xfc0007ff00000000, 0x7c00019400000000, 0xf80000000000, // Add to Zero Extended XO-form (addze RT,RA)
  5371  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5372  	{ADDZECC, 0xfc0007ff00000000, 0x7c00019500000000, 0xf80000000000, // Add to Zero Extended XO-form (addze. RT,RA)
  5373  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5374  	{ADDZEO, 0xfc0007ff00000000, 0x7c00059400000000, 0xf80000000000, // Add to Zero Extended XO-form (addzeo RT,RA)
  5375  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5376  	{ADDZEOCC, 0xfc0007ff00000000, 0x7c00059500000000, 0xf80000000000, // Add to Zero Extended XO-form (addzeo. RT,RA)
  5377  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5378  	{AND, 0xfc0007ff00000000, 0x7c00003800000000, 0x0, // AND X-form (and RA,RS,RB)
  5379  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5380  	{ANDCC, 0xfc0007ff00000000, 0x7c00003900000000, 0x0, // AND X-form (and. RA,RS,RB)
  5381  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5382  	{ANDC, 0xfc0007ff00000000, 0x7c00007800000000, 0x0, // AND with Complement X-form (andc RA,RS,RB)
  5383  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5384  	{ANDCCC, 0xfc0007ff00000000, 0x7c00007900000000, 0x0, // AND with Complement X-form (andc. RA,RS,RB)
  5385  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5386  	{ANDICC, 0xfc00000000000000, 0x7000000000000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI)
  5387  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
  5388  	{ANDISCC, 0xfc00000000000000, 0x7400000000000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI)
  5389  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
  5390  	{B, 0xfc00000300000000, 0x4800000000000000, 0x0, // Branch I-form (b target_addr)
  5391  		[6]*argField{ap_PCRel_6_29_shift2}},
  5392  	{BA, 0xfc00000300000000, 0x4800000200000000, 0x0, // Branch I-form (ba target_addr)
  5393  		[6]*argField{ap_Label_6_29_shift2}},
  5394  	{BL, 0xfc00000300000000, 0x4800000100000000, 0x0, // Branch I-form (bl target_addr)
  5395  		[6]*argField{ap_PCRel_6_29_shift2}},
  5396  	{BLA, 0xfc00000300000000, 0x4800000300000000, 0x0, // Branch I-form (bla target_addr)
  5397  		[6]*argField{ap_Label_6_29_shift2}},
  5398  	{BC, 0xfc00000300000000, 0x4000000000000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr)
  5399  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
  5400  	{BCA, 0xfc00000300000000, 0x4000000200000000, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr)
  5401  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
  5402  	{BCL, 0xfc00000300000000, 0x4000000100000000, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr)
  5403  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
  5404  	{BCLA, 0xfc00000300000000, 0x4000000300000000, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr)
  5405  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
  5406  	{BCCTR, 0xfc0007ff00000000, 0x4c00042000000000, 0xe00000000000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH)
  5407  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
  5408  	{BCCTRL, 0xfc0007ff00000000, 0x4c00042100000000, 0xe00000000000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH)
  5409  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
  5410  	{BCLR, 0xfc0007ff00000000, 0x4c00002000000000, 0xe00000000000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH)
  5411  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
  5412  	{BCLRL, 0xfc0007ff00000000, 0x4c00002100000000, 0xe00000000000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH)
  5413  		[6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
  5414  	{CMPW, 0xfc2007fe00000000, 0x7c00000000000000, 0x40000100000000, // Compare X-form (cmpw BF,RA,RB)
  5415  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
  5416  	{CMPD, 0xfc2007fe00000000, 0x7c20000000000000, 0x40000100000000, // Compare X-form (cmpd BF,RA,RB)
  5417  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
  5418  	{CMP, 0xfc0007fe00000000, 0x7c00000000000000, 0x40000100000000, // Compare X-form (cmp BF,L,RA,RB)
  5419  		[6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
  5420  	{CMPWI, 0xfc20000000000000, 0x2c00000000000000, 0x40000000000000, // Compare Immediate D-form (cmpwi BF,RA,SI)
  5421  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5422  	{CMPDI, 0xfc20000000000000, 0x2c20000000000000, 0x40000000000000, // Compare Immediate D-form (cmpdi BF,RA,SI)
  5423  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5424  	{CMPI, 0xfc00000000000000, 0x2c00000000000000, 0x40000000000000, // Compare Immediate D-form (cmpi BF,L,RA,SI)
  5425  		[6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5426  	{CMPLW, 0xfc2007fe00000000, 0x7c00004000000000, 0x40000100000000, // Compare Logical X-form (cmplw BF,RA,RB)
  5427  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
  5428  	{CMPLD, 0xfc2007fe00000000, 0x7c20004000000000, 0x40000100000000, // Compare Logical X-form (cmpld BF,RA,RB)
  5429  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
  5430  	{CMPL, 0xfc0007fe00000000, 0x7c00004000000000, 0x40000100000000, // Compare Logical X-form (cmpl BF,L,RA,RB)
  5431  		[6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
  5432  	{CMPLWI, 0xfc20000000000000, 0x2800000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI)
  5433  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
  5434  	{CMPLDI, 0xfc20000000000000, 0x2820000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI)
  5435  		[6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
  5436  	{CMPLI, 0xfc00000000000000, 0x2800000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmpli BF,L,RA,UI)
  5437  		[6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
  5438  	{CNTLZW, 0xfc0007ff00000000, 0x7c00003400000000, 0xf80000000000, // Count Leading Zeros Word X-form (cntlzw RA,RS)
  5439  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5440  	{CNTLZWCC, 0xfc0007ff00000000, 0x7c00003500000000, 0xf80000000000, // Count Leading Zeros Word X-form (cntlzw. RA,RS)
  5441  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5442  	{CRAND, 0xfc0007fe00000000, 0x4c00020200000000, 0x100000000, // Condition Register AND XL-form (crand BT,BA,BB)
  5443  		[6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
  5444  	{CRANDC, 0xfc0007fe00000000, 0x4c00010200000000, 0x100000000, // Condition Register AND with Complement XL-form (crandc BT,BA,BB)
  5445  		[6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
  5446  	{CREQV, 0xfc0007fe00000000, 0x4c00024200000000, 0x100000000, // Condition Register Equivalent XL-form (creqv BT,BA,BB)
  5447  		[6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
  5448  	{CRNAND, 0xfc0007fe00000000, 0x4c0001c200000000, 0x100000000, // Condition Register NAND XL-form (crnand BT,BA,BB)
  5449  		[6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
  5450  	{CRNOR, 0xfc0007fe00000000, 0x4c00004200000000, 0x100000000, // Condition Register NOR XL-form (crnor BT,BA,BB)
  5451  		[6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
  5452  	{CROR, 0xfc0007fe00000000, 0x4c00038200000000, 0x100000000, // Condition Register OR XL-form (cror BT,BA,BB)
  5453  		[6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
  5454  	{CRORC, 0xfc0007fe00000000, 0x4c00034200000000, 0x100000000, // Condition Register OR with Complement XL-form (crorc BT,BA,BB)
  5455  		[6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
  5456  	{CRXOR, 0xfc0007fe00000000, 0x4c00018200000000, 0x100000000, // Condition Register XOR XL-form (crxor BT,BA,BB)
  5457  		[6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
  5458  	{DCBZ, 0xfc0007fe00000000, 0x7c0007ec00000000, 0x3e0000100000000, // Data Cache Block set to Zero X-form (dcbz RA,RB)
  5459  		[6]*argField{ap_Reg_11_15, ap_Reg_16_20}},
  5460  	{EQV, 0xfc0007ff00000000, 0x7c00023800000000, 0x0, // Equivalent X-form (eqv RA,RS,RB)
  5461  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5462  	{EQVCC, 0xfc0007ff00000000, 0x7c00023900000000, 0x0, // Equivalent X-form (eqv. RA,RS,RB)
  5463  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5464  	{EXTSH, 0xfc0007ff00000000, 0x7c00073400000000, 0xf80000000000, // Extend Sign Halfword X-form (extsh RA,RS)
  5465  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5466  	{EXTSHCC, 0xfc0007ff00000000, 0x7c00073500000000, 0xf80000000000, // Extend Sign Halfword X-form (extsh. RA,RS)
  5467  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10}},
  5468  	{FABS, 0xfc0007ff00000000, 0xfc00021000000000, 0x1f000000000000, // Floating Absolute Value X-form (fabs FRT,FRB)
  5469  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5470  	{FABSCC, 0xfc0007ff00000000, 0xfc00021100000000, 0x1f000000000000, // Floating Absolute Value X-form (fabs. FRT,FRB)
  5471  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5472  	{FADD, 0xfc00003f00000000, 0xfc00002a00000000, 0x7c000000000, // Floating Add A-form (fadd FRT,FRA,FRB)
  5473  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5474  	{FADDCC, 0xfc00003f00000000, 0xfc00002b00000000, 0x7c000000000, // Floating Add A-form (fadd. FRT,FRA,FRB)
  5475  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5476  	{FCMPO, 0xfc0007fe00000000, 0xfc00004000000000, 0x60000100000000, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB)
  5477  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  5478  	{FCMPU, 0xfc0007fe00000000, 0xfc00000000000000, 0x60000100000000, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB)
  5479  		[6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
  5480  	{FDIV, 0xfc00003f00000000, 0xfc00002400000000, 0x7c000000000, // Floating Divide A-form (fdiv FRT,FRA,FRB)
  5481  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5482  	{FDIVCC, 0xfc00003f00000000, 0xfc00002500000000, 0x7c000000000, // Floating Divide A-form (fdiv. FRT,FRA,FRB)
  5483  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5484  	{FMADD, 0xfc00003f00000000, 0xfc00003a00000000, 0x0, // Floating Multiply-Add A-form (fmadd FRT,FRA,FRC,FRB)
  5485  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5486  	{FMADDCC, 0xfc00003f00000000, 0xfc00003b00000000, 0x0, // Floating Multiply-Add A-form (fmadd. FRT,FRA,FRC,FRB)
  5487  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5488  	{FMR, 0xfc0007ff00000000, 0xfc00009000000000, 0x1f000000000000, // Floating Move Register X-form (fmr FRT,FRB)
  5489  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5490  	{FMRCC, 0xfc0007ff00000000, 0xfc00009100000000, 0x1f000000000000, // Floating Move Register X-form (fmr. FRT,FRB)
  5491  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5492  	{FMSUB, 0xfc00003f00000000, 0xfc00003800000000, 0x0, // Floating Multiply-Subtract A-form (fmsub FRT,FRA,FRC,FRB)
  5493  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5494  	{FMSUBCC, 0xfc00003f00000000, 0xfc00003900000000, 0x0, // Floating Multiply-Subtract A-form (fmsub. FRT,FRA,FRC,FRB)
  5495  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5496  	{FMUL, 0xfc00003f00000000, 0xfc00003200000000, 0xf80000000000, // Floating Multiply A-form (fmul FRT,FRA,FRC)
  5497  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
  5498  	{FMULCC, 0xfc00003f00000000, 0xfc00003300000000, 0xf80000000000, // Floating Multiply A-form (fmul. FRT,FRA,FRC)
  5499  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
  5500  	{FNABS, 0xfc0007ff00000000, 0xfc00011000000000, 0x1f000000000000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB)
  5501  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5502  	{FNABSCC, 0xfc0007ff00000000, 0xfc00011100000000, 0x1f000000000000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB)
  5503  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5504  	{FNEG, 0xfc0007ff00000000, 0xfc00005000000000, 0x1f000000000000, // Floating Negate X-form (fneg FRT,FRB)
  5505  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5506  	{FNEGCC, 0xfc0007ff00000000, 0xfc00005100000000, 0x1f000000000000, // Floating Negate X-form (fneg. FRT,FRB)
  5507  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5508  	{FNMADD, 0xfc00003f00000000, 0xfc00003e00000000, 0x0, // Floating Negative Multiply-Add A-form (fnmadd FRT,FRA,FRC,FRB)
  5509  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5510  	{FNMADDCC, 0xfc00003f00000000, 0xfc00003f00000000, 0x0, // Floating Negative Multiply-Add A-form (fnmadd. FRT,FRA,FRC,FRB)
  5511  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5512  	{FNMSUB, 0xfc00003f00000000, 0xfc00003c00000000, 0x0, // Floating Negative Multiply-Subtract A-form (fnmsub FRT,FRA,FRC,FRB)
  5513  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5514  	{FNMSUBCC, 0xfc00003f00000000, 0xfc00003d00000000, 0x0, // Floating Negative Multiply-Subtract A-form (fnmsub. FRT,FRA,FRC,FRB)
  5515  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
  5516  	{FRSP, 0xfc0007ff00000000, 0xfc00001800000000, 0x1f000000000000, // Floating Round to Single-Precision X-form (frsp FRT,FRB)
  5517  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5518  	{FRSPCC, 0xfc0007ff00000000, 0xfc00001900000000, 0x1f000000000000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB)
  5519  		[6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
  5520  	{FSUB, 0xfc00003f00000000, 0xfc00002800000000, 0x7c000000000, // Floating Subtract A-form (fsub FRT,FRA,FRB)
  5521  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5522  	{FSUBCC, 0xfc00003f00000000, 0xfc00002900000000, 0x7c000000000, // Floating Subtract A-form (fsub. FRT,FRA,FRB)
  5523  		[6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
  5524  	{ISYNC, 0xfc0007fe00000000, 0x4c00012c00000000, 0x3fff80100000000, // Instruction Synchronize XL-form (isync)
  5525  		[6]*argField{}},
  5526  	{LBZ, 0xfc00000000000000, 0x8800000000000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA))
  5527  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5528  	{LBZU, 0xfc00000000000000, 0x8c00000000000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA))
  5529  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5530  	{LBZUX, 0xfc0007fe00000000, 0x7c0000ee00000000, 0x100000000, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB)
  5531  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5532  	{LBZX, 0xfc0007fe00000000, 0x7c0000ae00000000, 0x100000000, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB)
  5533  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5534  	{LFD, 0xfc00000000000000, 0xc800000000000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA))
  5535  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5536  	{LFDU, 0xfc00000000000000, 0xcc00000000000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA))
  5537  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5538  	{LFDUX, 0xfc0007fe00000000, 0x7c0004ee00000000, 0x100000000, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB)
  5539  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5540  	{LFDX, 0xfc0007fe00000000, 0x7c0004ae00000000, 0x100000000, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB)
  5541  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5542  	{LFS, 0xfc00000000000000, 0xc000000000000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA))
  5543  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5544  	{LFSU, 0xfc00000000000000, 0xc400000000000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA))
  5545  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5546  	{LFSUX, 0xfc0007fe00000000, 0x7c00046e00000000, 0x100000000, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB)
  5547  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5548  	{LFSX, 0xfc0007fe00000000, 0x7c00042e00000000, 0x100000000, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB)
  5549  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5550  	{LHA, 0xfc00000000000000, 0xa800000000000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA))
  5551  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5552  	{LHAU, 0xfc00000000000000, 0xac00000000000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA))
  5553  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5554  	{LHAUX, 0xfc0007fe00000000, 0x7c0002ee00000000, 0x100000000, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB)
  5555  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5556  	{LHAX, 0xfc0007fe00000000, 0x7c0002ae00000000, 0x100000000, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB)
  5557  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5558  	{LHBRX, 0xfc0007fe00000000, 0x7c00062c00000000, 0x100000000, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB)
  5559  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5560  	{LHZ, 0xfc00000000000000, 0xa000000000000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA))
  5561  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5562  	{LHZU, 0xfc00000000000000, 0xa400000000000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA))
  5563  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5564  	{LHZUX, 0xfc0007fe00000000, 0x7c00026e00000000, 0x100000000, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB)
  5565  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5566  	{LHZX, 0xfc0007fe00000000, 0x7c00022e00000000, 0x100000000, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB)
  5567  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5568  	{LMW, 0xfc00000000000000, 0xb800000000000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA))
  5569  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5570  	{LSWI, 0xfc0007fe00000000, 0x7c0004aa00000000, 0x100000000, // Load String Word Immediate X-form (lswi RT,RA,NB)
  5571  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
  5572  	{LSWX, 0xfc0007fe00000000, 0x7c00042a00000000, 0x100000000, // Load String Word Indexed X-form (lswx RT,RA,RB)
  5573  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5574  	{LWBRX, 0xfc0007fe00000000, 0x7c00042c00000000, 0x100000000, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB)
  5575  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5576  	{LWZ, 0xfc00000000000000, 0x8000000000000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA))
  5577  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5578  	{LWZU, 0xfc00000000000000, 0x8400000000000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA))
  5579  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5580  	{LWZUX, 0xfc0007fe00000000, 0x7c00006e00000000, 0x100000000, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB)
  5581  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5582  	{LWZX, 0xfc0007fe00000000, 0x7c00002e00000000, 0x100000000, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB)
  5583  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5584  	{MCRF, 0xfc0007fe00000000, 0x4c00000000000000, 0x63f80100000000, // Move Condition Register Field XL-form (mcrf BF,BFA)
  5585  		[6]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
  5586  	{MCRFS, 0xfc0007fe00000000, 0xfc00008000000000, 0x63f80100000000, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA)
  5587  		[6]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
  5588  	{MFCR, 0xfc1007fe00000000, 0x7c00002600000000, 0xff80100000000, // Move From Condition Register XFX-form (mfcr RT)
  5589  		[6]*argField{ap_Reg_6_10}},
  5590  	{MFFS, 0xfc1f07ff00000000, 0xfc00048e00000000, 0xf80000000000, // Move From FPSCR X-form (mffs FRT)
  5591  		[6]*argField{ap_FPReg_6_10}},
  5592  	{MFFSCC, 0xfc1f07ff00000000, 0xfc00048f00000000, 0xf80000000000, // Move From FPSCR X-form (mffs. FRT)
  5593  		[6]*argField{ap_FPReg_6_10}},
  5594  	{MFMSR, 0xfc0007fe00000000, 0x7c0000a600000000, 0x1ff80100000000, // Move From MSR X-form (mfmsr RT)
  5595  		[6]*argField{ap_Reg_6_10}},
  5596  	{MFSPR, 0xfc0007fe00000000, 0x7c0002a600000000, 0x100000000, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
  5597  		[6]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
  5598  	{MTCRF, 0xfc1007fe00000000, 0x7c00012000000000, 0x80100000000, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS)
  5599  		[6]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
  5600  	{MTFSB0, 0xfc0007ff00000000, 0xfc00008c00000000, 0x1ff80000000000, // Move To FPSCR Bit 0 X-form (mtfsb0 BT)
  5601  		[6]*argField{ap_ImmUnsigned_6_10}},
  5602  	{MTFSB0CC, 0xfc0007ff00000000, 0xfc00008d00000000, 0x1ff80000000000, // Move To FPSCR Bit 0 X-form (mtfsb0. BT)
  5603  		[6]*argField{ap_ImmUnsigned_6_10}},
  5604  	{MTFSB1, 0xfc0007ff00000000, 0xfc00004c00000000, 0x1ff80000000000, // Move To FPSCR Bit 1 X-form (mtfsb1 BT)
  5605  		[6]*argField{ap_ImmUnsigned_6_10}},
  5606  	{MTFSB1CC, 0xfc0007ff00000000, 0xfc00004d00000000, 0x1ff80000000000, // Move To FPSCR Bit 1 X-form (mtfsb1. BT)
  5607  		[6]*argField{ap_ImmUnsigned_6_10}},
  5608  	{MTFSF, 0xfc0007ff00000000, 0xfc00058e00000000, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W)
  5609  		[6]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
  5610  	{MTFSFCC, 0xfc0007ff00000000, 0xfc00058f00000000, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W)
  5611  		[6]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
  5612  	{MTFSFI, 0xfc0007ff00000000, 0xfc00010c00000000, 0x7e080000000000, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W)
  5613  		[6]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
  5614  	{MTFSFICC, 0xfc0007ff00000000, 0xfc00010d00000000, 0x7e080000000000, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W)
  5615  		[6]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
  5616  	{MTMSR, 0xfc0007fe00000000, 0x7c00012400000000, 0x1ef80100000000, // Move To MSR X-form (mtmsr RS,L)
  5617  		[6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
  5618  	{MTSPR, 0xfc0007fe00000000, 0x7c0003a600000000, 0x100000000, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
  5619  		[6]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
  5620  	{MULLI, 0xfc00000000000000, 0x1c00000000000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI)
  5621  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5622  	{MULLW, 0xfc0007ff00000000, 0x7c0001d600000000, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB)
  5623  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5624  	{MULLWCC, 0xfc0007ff00000000, 0x7c0001d700000000, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB)
  5625  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5626  	{MULLWO, 0xfc0007ff00000000, 0x7c0005d600000000, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB)
  5627  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5628  	{MULLWOCC, 0xfc0007ff00000000, 0x7c0005d700000000, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB)
  5629  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5630  	{NAND, 0xfc0007ff00000000, 0x7c0003b800000000, 0x0, // NAND X-form (nand RA,RS,RB)
  5631  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5632  	{NANDCC, 0xfc0007ff00000000, 0x7c0003b900000000, 0x0, // NAND X-form (nand. RA,RS,RB)
  5633  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5634  	{NEG, 0xfc0007ff00000000, 0x7c0000d000000000, 0xf80000000000, // Negate XO-form (neg RT,RA)
  5635  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5636  	{NEGCC, 0xfc0007ff00000000, 0x7c0000d100000000, 0xf80000000000, // Negate XO-form (neg. RT,RA)
  5637  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5638  	{NEGO, 0xfc0007ff00000000, 0x7c0004d000000000, 0xf80000000000, // Negate XO-form (nego RT,RA)
  5639  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5640  	{NEGOCC, 0xfc0007ff00000000, 0x7c0004d100000000, 0xf80000000000, // Negate XO-form (nego. RT,RA)
  5641  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5642  	{NOR, 0xfc0007ff00000000, 0x7c0000f800000000, 0x0, // NOR X-form (nor RA,RS,RB)
  5643  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5644  	{NORCC, 0xfc0007ff00000000, 0x7c0000f900000000, 0x0, // NOR X-form (nor. RA,RS,RB)
  5645  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5646  	{OR, 0xfc0007ff00000000, 0x7c00037800000000, 0x0, // OR X-form (or RA,RS,RB)
  5647  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5648  	{ORCC, 0xfc0007ff00000000, 0x7c00037900000000, 0x0, // OR X-form (or. RA,RS,RB)
  5649  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5650  	{ORC, 0xfc0007ff00000000, 0x7c00033800000000, 0x0, // OR with Complement X-form (orc RA,RS,RB)
  5651  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5652  	{ORCCC, 0xfc0007ff00000000, 0x7c00033900000000, 0x0, // OR with Complement X-form (orc. RA,RS,RB)
  5653  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5654  	{NOP, 0xffffffff00000000, 0x6000000000000000, 0x0, // OR Immediate D-form (nop)
  5655  		[6]*argField{}},
  5656  	{ORI, 0xfc00000000000000, 0x6000000000000000, 0x0, // OR Immediate D-form (ori RA,RS,UI)
  5657  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
  5658  	{ORIS, 0xfc00000000000000, 0x6400000000000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI)
  5659  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
  5660  	{RLWIMI, 0xfc00000100000000, 0x5000000000000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME)
  5661  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
  5662  	{RLWIMICC, 0xfc00000100000000, 0x5000000100000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME)
  5663  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
  5664  	{RLWINM, 0xfc00000100000000, 0x5400000000000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME)
  5665  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
  5666  	{RLWINMCC, 0xfc00000100000000, 0x5400000100000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME)
  5667  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
  5668  	{RLWNM, 0xfc00000100000000, 0x5c00000000000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME)
  5669  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
  5670  	{RLWNMCC, 0xfc00000100000000, 0x5c00000100000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME)
  5671  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
  5672  	{SLW, 0xfc0007ff00000000, 0x7c00003000000000, 0x0, // Shift Left Word X-form (slw RA,RS,RB)
  5673  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5674  	{SLWCC, 0xfc0007ff00000000, 0x7c00003100000000, 0x0, // Shift Left Word X-form (slw. RA,RS,RB)
  5675  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5676  	{SRAW, 0xfc0007ff00000000, 0x7c00063000000000, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB)
  5677  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5678  	{SRAWCC, 0xfc0007ff00000000, 0x7c00063100000000, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB)
  5679  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5680  	{SRAWI, 0xfc0007ff00000000, 0x7c00067000000000, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH)
  5681  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
  5682  	{SRAWICC, 0xfc0007ff00000000, 0x7c00067100000000, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH)
  5683  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
  5684  	{SRW, 0xfc0007ff00000000, 0x7c00043000000000, 0x0, // Shift Right Word X-form (srw RA,RS,RB)
  5685  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5686  	{SRWCC, 0xfc0007ff00000000, 0x7c00043100000000, 0x0, // Shift Right Word X-form (srw. RA,RS,RB)
  5687  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5688  	{STB, 0xfc00000000000000, 0x9800000000000000, 0x0, // Store Byte D-form (stb RS,D(RA))
  5689  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5690  	{STBU, 0xfc00000000000000, 0x9c00000000000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA))
  5691  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5692  	{STBUX, 0xfc0007fe00000000, 0x7c0001ee00000000, 0x100000000, // Store Byte with Update Indexed X-form (stbux RS,RA,RB)
  5693  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5694  	{STBX, 0xfc0007fe00000000, 0x7c0001ae00000000, 0x100000000, // Store Byte Indexed X-form (stbx RS,RA,RB)
  5695  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5696  	{STFD, 0xfc00000000000000, 0xd800000000000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA))
  5697  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5698  	{STFDU, 0xfc00000000000000, 0xdc00000000000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA))
  5699  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5700  	{STFDUX, 0xfc0007fe00000000, 0x7c0005ee00000000, 0x100000000, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB)
  5701  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5702  	{STFDX, 0xfc0007fe00000000, 0x7c0005ae00000000, 0x100000000, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB)
  5703  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5704  	{STFS, 0xfc00000000000000, 0xd000000000000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA))
  5705  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5706  	{STFSU, 0xfc00000000000000, 0xd400000000000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA))
  5707  		[6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5708  	{STFSUX, 0xfc0007fe00000000, 0x7c00056e00000000, 0x100000000, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB)
  5709  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5710  	{STFSX, 0xfc0007fe00000000, 0x7c00052e00000000, 0x100000000, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB)
  5711  		[6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5712  	{STH, 0xfc00000000000000, 0xb000000000000000, 0x0, // Store Halfword D-form (sth RS,D(RA))
  5713  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5714  	{STHBRX, 0xfc0007fe00000000, 0x7c00072c00000000, 0x100000000, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB)
  5715  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5716  	{STHU, 0xfc00000000000000, 0xb400000000000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA))
  5717  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5718  	{STHUX, 0xfc0007fe00000000, 0x7c00036e00000000, 0x100000000, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB)
  5719  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5720  	{STHX, 0xfc0007fe00000000, 0x7c00032e00000000, 0x100000000, // Store Halfword Indexed X-form (sthx RS,RA,RB)
  5721  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5722  	{STMW, 0xfc00000000000000, 0xbc00000000000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA))
  5723  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5724  	{STSWI, 0xfc0007fe00000000, 0x7c0005aa00000000, 0x100000000, // Store String Word Immediate X-form (stswi RS,RA,NB)
  5725  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
  5726  	{STSWX, 0xfc0007fe00000000, 0x7c00052a00000000, 0x100000000, // Store String Word Indexed X-form (stswx RS,RA,RB)
  5727  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5728  	{STW, 0xfc00000000000000, 0x9000000000000000, 0x0, // Store Word D-form (stw RS,D(RA))
  5729  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5730  	{STWBRX, 0xfc0007fe00000000, 0x7c00052c00000000, 0x100000000, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB)
  5731  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5732  	{STWU, 0xfc00000000000000, 0x9400000000000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA))
  5733  		[6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
  5734  	{STWUX, 0xfc0007fe00000000, 0x7c00016e00000000, 0x100000000, // Store Word with Update Indexed X-form (stwux RS,RA,RB)
  5735  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5736  	{STWX, 0xfc0007fe00000000, 0x7c00012e00000000, 0x100000000, // Store Word Indexed X-form (stwx RS,RA,RB)
  5737  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5738  	{SUBFC, 0xfc0007ff00000000, 0x7c00001000000000, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB)
  5739  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5740  	{SUBFCCC, 0xfc0007ff00000000, 0x7c00001100000000, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB)
  5741  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5742  	{SUBFCO, 0xfc0007ff00000000, 0x7c00041000000000, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB)
  5743  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5744  	{SUBFCOCC, 0xfc0007ff00000000, 0x7c00041100000000, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB)
  5745  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5746  	{SUBFE, 0xfc0007ff00000000, 0x7c00011000000000, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB)
  5747  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5748  	{SUBFECC, 0xfc0007ff00000000, 0x7c00011100000000, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB)
  5749  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5750  	{SUBFEO, 0xfc0007ff00000000, 0x7c00051000000000, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB)
  5751  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5752  	{SUBFEOCC, 0xfc0007ff00000000, 0x7c00051100000000, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB)
  5753  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5754  	{SUBFIC, 0xfc00000000000000, 0x2000000000000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI)
  5755  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5756  	{SUBFME, 0xfc0007ff00000000, 0x7c0001d000000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfme RT,RA)
  5757  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5758  	{SUBFMECC, 0xfc0007ff00000000, 0x7c0001d100000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfme. RT,RA)
  5759  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5760  	{SUBFMEO, 0xfc0007ff00000000, 0x7c0005d000000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfmeo RT,RA)
  5761  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5762  	{SUBFMEOCC, 0xfc0007ff00000000, 0x7c0005d100000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA)
  5763  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5764  	{SUBFZE, 0xfc0007ff00000000, 0x7c00019000000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfze RT,RA)
  5765  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5766  	{SUBFZECC, 0xfc0007ff00000000, 0x7c00019100000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfze. RT,RA)
  5767  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5768  	{SUBFZEO, 0xfc0007ff00000000, 0x7c00059000000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfzeo RT,RA)
  5769  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5770  	{SUBFZEOCC, 0xfc0007ff00000000, 0x7c00059100000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfzeo. RT,RA)
  5771  		[6]*argField{ap_Reg_6_10, ap_Reg_11_15}},
  5772  	{SYNC, 0xfc0007fe00000000, 0x7c0004ac00000000, 0x31cf80100000000, // Synchronize X-form (sync L,SC)
  5773  		[6]*argField{ap_ImmUnsigned_8_10, ap_ImmUnsigned_14_15}},
  5774  	{TLBIE, 0xfc0007fe00000000, 0x7c00026400000000, 0x10000100000000, // TLB Invalidate Entry X-form (tlbie RB,RS,RIC,PRS,R)
  5775  		[6]*argField{ap_Reg_16_20, ap_Reg_6_10, ap_ImmUnsigned_12_13, ap_ImmUnsigned_14_14, ap_ImmUnsigned_15_15}},
  5776  	{TW, 0xfc0007fe00000000, 0x7c00000800000000, 0x100000000, // Trap Word X-form (tw TO,RA,RB)
  5777  		[6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
  5778  	{TWI, 0xfc00000000000000, 0xc00000000000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI)
  5779  		[6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
  5780  	{XOR, 0xfc0007ff00000000, 0x7c00027800000000, 0x0, // XOR X-form (xor RA,RS,RB)
  5781  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5782  	{XORCC, 0xfc0007ff00000000, 0x7c00027900000000, 0x0, // XOR X-form (xor. RA,RS,RB)
  5783  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
  5784  	{XORI, 0xfc00000000000000, 0x6800000000000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI)
  5785  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
  5786  	{XORIS, 0xfc00000000000000, 0x6c00000000000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI)
  5787  		[6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
  5788  }
  5789  

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