1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 (Add(Ptr|64|32|16|8) ...) => (ADDV ...)
6 (Add(32|64)F ...) => (ADD(F|D) ...)
7
8 (Sub(Ptr|64|32|16|8) ...) => (SUBV ...)
9 (Sub(32|64)F ...) => (SUB(F|D) ...)
10
11 (Mul(64|32|16|8) x y) => (Select1 (MULVU x y))
12 (Mul(32|64)F ...) => (MUL(F|D) ...)
13 (Mul64uhilo ...) => (MULVU ...)
14 (Select0 (Mul64uover x y)) => (Select1 <typ.UInt64> (MULVU x y))
15 (Select1 (Mul64uover x y)) => (SGTU <typ.Bool> (Select0 <typ.UInt64> (MULVU x y)) (MOVVconst <typ.UInt64> [0]))
16
17 (Hmul64 x y) => (Select0 (MULV x y))
18 (Hmul64u x y) => (Select0 (MULVU x y))
19 (Hmul32 x y) => (SRAVconst (Select1 <typ.Int64> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32])
20 (Hmul32u x y) => (SRLVconst (Select1 <typ.UInt64> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32])
21
22 (Div64 x y) => (Select1 (DIVV x y))
23 (Div64u x y) => (Select1 (DIVVU x y))
24 (Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
25 (Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
26 (Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
27 (Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
28 (Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
29 (Div8u x y) => (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
30 (Div(32|64)F ...) => (DIV(F|D) ...)
31
32 (Mod64 x y) => (Select0 (DIVV x y))
33 (Mod64u x y) => (Select0 (DIVVU x y))
34 (Mod32 x y) => (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
35 (Mod32u x y) => (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
36 (Mod16 x y) => (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
37 (Mod16u x y) => (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
38 (Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
39 (Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
40
41 (Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c)
42 (Select1 <t> (Add64carry x y c)) =>
43 (OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
44
45 (Select0 <t> (Sub64borrow x y c)) => (SUBV (SUBV <t> x y) c)
46 (Select1 <t> (Sub64borrow x y c)) =>
47 (OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s))
48
49 // math package intrinsics
50 (Abs ...) => (ABSD ...)
51
52 // (x + y) / 2 with x>=y => (x - y) / 2 + y
53 (Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
54
55 (And(64|32|16|8) ...) => (AND ...)
56 (Or(64|32|16|8) ...) => (OR ...)
57 (Xor(64|32|16|8) ...) => (XOR ...)
58
59 // shifts
60 // hardware instruction uses only the low 6 bits of the shift
61 // we compare to 64 to ensure Go semantics for large shifts
62
63 // left shift
64 (Lsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLV x y)
65 (Lsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLV x y)
66 (Lsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLV x y)
67 (Lsh8x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLV x y)
68
69 (Lsh64x64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
70 (Lsh64x32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
71 (Lsh64x16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
72 (Lsh64x8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
73
74 (Lsh32x64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
75 (Lsh32x32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
76 (Lsh32x16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
77 (Lsh32x8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
78
79 (Lsh16x64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
80 (Lsh16x32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
81 (Lsh16x16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
82 (Lsh16x8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
83
84 (Lsh8x64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
85 (Lsh8x32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
86 (Lsh8x16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
87 (Lsh8x8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
88
89 // unsigned right shift
90 (Rsh64Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLV x y)
91 (Rsh32Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLV (ZeroExt32to64 x) y)
92 (Rsh16Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLV (ZeroExt16to64 x) y)
93 (Rsh8Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLV (ZeroExt8to64 x) y)
94
95 (Rsh64Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> x y))
96 (Rsh64Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> x (ZeroExt32to64 y)))
97 (Rsh64Ux16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> x (ZeroExt16to64 y)))
98 (Rsh64Ux8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> x (ZeroExt8to64 y)))
99
100 (Rsh32Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt32to64 x) y))
101 (Rsh32Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt32to64 y)))
102 (Rsh32Ux16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt16to64 y)))
103 (Rsh32Ux8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt8to64 y)))
104
105 (Rsh16Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt16to64 x) y))
106 (Rsh16Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y)))
107 (Rsh16Ux16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y)))
108 (Rsh16Ux8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y)))
109
110 (Rsh8Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt8to64 x) y))
111 (Rsh8Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y)))
112 (Rsh8Ux16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y)))
113 (Rsh8Ux8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y)))
114
115 // signed right shift
116 (Rsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAV x y)
117 (Rsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) y)
118 (Rsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) y)
119 (Rsh8x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) y)
120
121 (Rsh64x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
122 (Rsh64x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
123 (Rsh64x16 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
124 (Rsh64x8 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
125
126 (Rsh32x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
127 (Rsh32x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
128 (Rsh32x16 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
129 (Rsh32x8 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
130
131 (Rsh16x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
132 (Rsh16x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
133 (Rsh16x16 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
134 (Rsh16x8 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
135
136 (Rsh8x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
137 (Rsh8x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
138 (Rsh8x16 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
139 (Rsh8x8 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
140
141 // rotates
142 (RotateLeft8 <t> x (MOVVconst [c])) => (Or8 (Lsh8x64 <t> x (MOVVconst [c&7])) (Rsh8Ux64 <t> x (MOVVconst [-c&7])))
143 (RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15])))
144 (RotateLeft32 <t> x (MOVVconst [c])) => (Or32 (Lsh32x64 <t> x (MOVVconst [c&31])) (Rsh32Ux64 <t> x (MOVVconst [-c&31])))
145 (RotateLeft64 <t> x (MOVVconst [c])) => (Or64 (Lsh64x64 <t> x (MOVVconst [c&63])) (Rsh64Ux64 <t> x (MOVVconst [-c&63])))
146
147 // unary ops
148 (Neg(64|32|16|8) ...) => (NEGV ...)
149 (Neg(32|64)F ...) => (NEG(F|D) ...)
150
151 (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
152
153 (Sqrt ...) => (SQRTD ...)
154 (Sqrt32 ...) => (SQRTF ...)
155
156 // boolean ops -- booleans are represented with 0=false, 1=true
157 (AndB ...) => (AND ...)
158 (OrB ...) => (OR ...)
159 (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
160 (NeqB ...) => (XOR ...)
161 (Not x) => (XORconst [1] x)
162
163 // constants
164 (Const(64|32|16|8) [val]) => (MOVVconst [int64(val)])
165 (Const(32|64)F [val]) => (MOV(F|D)const [float64(val)])
166 (ConstNil) => (MOVVconst [0])
167 (ConstBool [t]) => (MOVVconst [int64(ssa.B2i(t))])
168
169 (Slicemask <t> x) => (SRAVconst (NEGV <t> x) [63])
170
171 // truncations
172 // Because we ignore high parts of registers, truncates are just copies.
173 (Trunc16to8 ...) => (Copy ...)
174 (Trunc32to8 ...) => (Copy ...)
175 (Trunc32to16 ...) => (Copy ...)
176 (Trunc64to8 ...) => (Copy ...)
177 (Trunc64to16 ...) => (Copy ...)
178 (Trunc64to32 ...) => (Copy ...)
179
180 // Zero-/Sign-extensions
181 (ZeroExt8to16 ...) => (MOVBUreg ...)
182 (ZeroExt8to32 ...) => (MOVBUreg ...)
183 (ZeroExt16to32 ...) => (MOVHUreg ...)
184 (ZeroExt8to64 ...) => (MOVBUreg ...)
185 (ZeroExt16to64 ...) => (MOVHUreg ...)
186 (ZeroExt32to64 ...) => (MOVWUreg ...)
187
188 (SignExt8to16 ...) => (MOVBreg ...)
189 (SignExt8to32 ...) => (MOVBreg ...)
190 (SignExt16to32 ...) => (MOVHreg ...)
191 (SignExt8to64 ...) => (MOVBreg ...)
192 (SignExt16to64 ...) => (MOVHreg ...)
193 (SignExt32to64 ...) => (MOVWreg ...)
194
195 // float <=> int conversion
196 (Cvt32to32F ...) => (MOVWF ...)
197 (Cvt32to64F ...) => (MOVWD ...)
198 (Cvt64to32F ...) => (MOVVF ...)
199 (Cvt64to64F ...) => (MOVVD ...)
200 (Cvt32Fto32 ...) => (TRUNCFW ...)
201 (Cvt64Fto32 ...) => (TRUNCDW ...)
202 (Cvt32Fto64 ...) => (TRUNCFV ...)
203 (Cvt64Fto64 ...) => (TRUNCDV ...)
204 (Cvt32Fto64F ...) => (MOVFD ...)
205 (Cvt64Fto32F ...) => (MOVDF ...)
206
207 (CvtBoolToUint8 ...) => (Copy ...)
208
209 (Round(32|64)F ...) => (Copy ...)
210
211 // comparisons
212 (Eq8 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)))
213 (Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y)))
214 (Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)))
215 (Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y))
216 (EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y))
217 (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
218
219 (Neq8 x y) => (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0]))
220 (Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0]))
221 (Neq32 x y) => (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0]))
222 (Neq64 x y) => (SGTU (XOR x y) (MOVVconst [0]))
223 (NeqPtr x y) => (SGTU (XOR x y) (MOVVconst [0]))
224 (Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y))
225
226 (Less8 x y) => (SGT (SignExt8to64 y) (SignExt8to64 x))
227 (Less16 x y) => (SGT (SignExt16to64 y) (SignExt16to64 x))
228 (Less32 x y) => (SGT (SignExt32to64 y) (SignExt32to64 x))
229 (Less64 x y) => (SGT y x)
230 (Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN
231
232 (Less8U x y) => (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x))
233 (Less16U x y) => (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x))
234 (Less32U x y) => (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x))
235 (Less64U x y) => (SGTU y x)
236
237 (Leq8 x y) => (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y)))
238 (Leq16 x y) => (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y)))
239 (Leq32 x y) => (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y)))
240 (Leq64 x y) => (XOR (MOVVconst [1]) (SGT x y))
241 (Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN
242
243 (Leq8U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y)))
244 (Leq16U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y)))
245 (Leq32U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y)))
246 (Leq64U x y) => (XOR (MOVVconst [1]) (SGTU x y))
247
248 (OffPtr [off] ptr:(SP)) && ssa.Is32Bit(off) => (MOVVaddr [int32(off)] ptr)
249 (OffPtr [off] ptr) && ssa.Is32Bit(off) => (ADDVconst [off] ptr)
250 (OffPtr [off] ptr) && !ssa.Is32Bit(off) => (ADDV ptr (MOVVconst <typ.UInt64> [off]))
251
252 (Addr {sym} base) => (MOVVaddr {sym} base)
253 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVVaddr {sym} (SPanchored base mem))
254 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVVaddr {sym} base)
255
256 // loads
257 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
258 (Load <t> ptr mem) && (ssa.Is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
259 (Load <t> ptr mem) && (ssa.Is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
260 (Load <t> ptr mem) && (ssa.Is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
261 (Load <t> ptr mem) && (ssa.Is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
262 (Load <t> ptr mem) && (ssa.Is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
263 (Load <t> ptr mem) && (ssa.Is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
264 (Load <t> ptr mem) && (ssa.Is64BitInt(t) ||ssa.IsPtr(t)) => (MOVVload ptr mem)
265 (Load <t> ptr mem) && ssa.Is32BitFloat(t) => (MOVFload ptr mem)
266 (Load <t> ptr mem) && ssa.Is64BitFloat(t) => (MOVDload ptr mem)
267
268 // stores
269 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
270 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
271 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
272 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
273 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
274 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
275
276 // zeroing
277 (Zero [0] _ mem) => mem
278 (Zero [1] ptr mem) => (MOVBstore ptr (MOVVconst [0]) mem)
279 (Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 =>
280 (MOVHstore ptr (MOVVconst [0]) mem)
281 (Zero [2] ptr mem) =>
282 (MOVBstore [1] ptr (MOVVconst [0])
283 (MOVBstore [0] ptr (MOVVconst [0]) mem))
284 (Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 =>
285 (MOVWstore ptr (MOVVconst [0]) mem)
286 (Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 =>
287 (MOVHstore [2] ptr (MOVVconst [0])
288 (MOVHstore [0] ptr (MOVVconst [0]) mem))
289 (Zero [4] ptr mem) =>
290 (MOVBstore [3] ptr (MOVVconst [0])
291 (MOVBstore [2] ptr (MOVVconst [0])
292 (MOVBstore [1] ptr (MOVVconst [0])
293 (MOVBstore [0] ptr (MOVVconst [0]) mem))))
294 (Zero [8] {t} ptr mem) && t.Alignment()%8 == 0 =>
295 (MOVVstore ptr (MOVVconst [0]) mem)
296 (Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 =>
297 (MOVWstore [4] ptr (MOVVconst [0])
298 (MOVWstore [0] ptr (MOVVconst [0]) mem))
299 (Zero [8] {t} ptr mem) && t.Alignment()%2 == 0 =>
300 (MOVHstore [6] ptr (MOVVconst [0])
301 (MOVHstore [4] ptr (MOVVconst [0])
302 (MOVHstore [2] ptr (MOVVconst [0])
303 (MOVHstore [0] ptr (MOVVconst [0]) mem))))
304
305 (Zero [3] ptr mem) =>
306 (MOVBstore [2] ptr (MOVVconst [0])
307 (MOVBstore [1] ptr (MOVVconst [0])
308 (MOVBstore [0] ptr (MOVVconst [0]) mem)))
309 (Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 =>
310 (MOVHstore [4] ptr (MOVVconst [0])
311 (MOVHstore [2] ptr (MOVVconst [0])
312 (MOVHstore [0] ptr (MOVVconst [0]) mem)))
313 (Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 =>
314 (MOVWstore [8] ptr (MOVVconst [0])
315 (MOVWstore [4] ptr (MOVVconst [0])
316 (MOVWstore [0] ptr (MOVVconst [0]) mem)))
317 (Zero [16] {t} ptr mem) && t.Alignment()%8 == 0 =>
318 (MOVVstore [8] ptr (MOVVconst [0])
319 (MOVVstore [0] ptr (MOVVconst [0]) mem))
320 (Zero [24] {t} ptr mem) && t.Alignment()%8 == 0 =>
321 (MOVVstore [16] ptr (MOVVconst [0])
322 (MOVVstore [8] ptr (MOVVconst [0])
323 (MOVVstore [0] ptr (MOVVconst [0]) mem)))
324
325 // medium zeroing uses a duff device
326 // 8, and 128 are magic constants, see runtime/mkduff.go
327 (Zero [s] {t} ptr mem)
328 && s%8 == 0 && s > 24 && s <= 8*128
329 && t.Alignment()%8 == 0 =>
330 (DUFFZERO [8 * (128 - s/8)] ptr mem)
331
332 // large or unaligned zeroing uses a loop
333 (Zero [s] {t} ptr mem)
334 && s > 8*128 || t.Alignment()%8 != 0 =>
335 (LoweredZero [t.Alignment()]
336 ptr
337 (ADDVconst <ptr.Type> ptr [s-ssa.MoveSize(t.Alignment(), config)])
338 mem)
339
340 // moves
341 (Move [0] _ _ mem) => mem
342 (Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
343 (Move [2] {t} dst src mem) && t.Alignment()%2 == 0 =>
344 (MOVHstore dst (MOVHload src mem) mem)
345 (Move [2] dst src mem) =>
346 (MOVBstore [1] dst (MOVBload [1] src mem)
347 (MOVBstore dst (MOVBload src mem) mem))
348 (Move [4] {t} dst src mem) && t.Alignment()%4 == 0 =>
349 (MOVWstore dst (MOVWload src mem) mem)
350 (Move [4] {t} dst src mem) && t.Alignment()%2 == 0 =>
351 (MOVHstore [2] dst (MOVHload [2] src mem)
352 (MOVHstore dst (MOVHload src mem) mem))
353 (Move [4] dst src mem) =>
354 (MOVBstore [3] dst (MOVBload [3] src mem)
355 (MOVBstore [2] dst (MOVBload [2] src mem)
356 (MOVBstore [1] dst (MOVBload [1] src mem)
357 (MOVBstore dst (MOVBload src mem) mem))))
358 (Move [8] {t} dst src mem) && t.Alignment()%8 == 0 =>
359 (MOVVstore dst (MOVVload src mem) mem)
360 (Move [8] {t} dst src mem) && t.Alignment()%4 == 0 =>
361 (MOVWstore [4] dst (MOVWload [4] src mem)
362 (MOVWstore dst (MOVWload src mem) mem))
363 (Move [8] {t} dst src mem) && t.Alignment()%2 == 0 =>
364 (MOVHstore [6] dst (MOVHload [6] src mem)
365 (MOVHstore [4] dst (MOVHload [4] src mem)
366 (MOVHstore [2] dst (MOVHload [2] src mem)
367 (MOVHstore dst (MOVHload src mem) mem))))
368
369 (Move [3] dst src mem) =>
370 (MOVBstore [2] dst (MOVBload [2] src mem)
371 (MOVBstore [1] dst (MOVBload [1] src mem)
372 (MOVBstore dst (MOVBload src mem) mem)))
373 (Move [6] {t} dst src mem) && t.Alignment()%2 == 0 =>
374 (MOVHstore [4] dst (MOVHload [4] src mem)
375 (MOVHstore [2] dst (MOVHload [2] src mem)
376 (MOVHstore dst (MOVHload src mem) mem)))
377 (Move [12] {t} dst src mem) && t.Alignment()%4 == 0 =>
378 (MOVWstore [8] dst (MOVWload [8] src mem)
379 (MOVWstore [4] dst (MOVWload [4] src mem)
380 (MOVWstore dst (MOVWload src mem) mem)))
381 (Move [16] {t} dst src mem) && t.Alignment()%8 == 0 =>
382 (MOVVstore [8] dst (MOVVload [8] src mem)
383 (MOVVstore dst (MOVVload src mem) mem))
384 (Move [24] {t} dst src mem) && t.Alignment()%8 == 0 =>
385 (MOVVstore [16] dst (MOVVload [16] src mem)
386 (MOVVstore [8] dst (MOVVload [8] src mem)
387 (MOVVstore dst (MOVVload src mem) mem)))
388
389 // float <=> int register moves, with no conversion.
390 // These come up when compiling math.{Float64bits, Float64frombits, Float32bits, Float32frombits}.
391 (MOVVload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) => (MOVVfpgp val)
392 (MOVDload [off] {sym} ptr (MOVVstore [off] {sym} ptr val _)) => (MOVVgpfp val)
393 (MOVWUload [off] {sym} ptr (MOVFstore [off] {sym} ptr val _)) => (ZeroExt32to64 (MOVWfpgp <typ.Float32> val))
394 (MOVFload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (MOVWgpfp val)
395
396 // If the memory load and store operations use the same ptr, they are combined into a direct move operation between registers.
397 (MOV(V|W|H|B)load [off] {sym} ptr (MOV(V|W|H|B)store [off] {sym} ptr x _)) => (MOV(V|W|H|B)reg x)
398 (MOV(W|H|B)Uload [off] {sym} ptr (MOV(W|H|B)store [off] {sym} ptr x _)) => (MOV(W|H|B)Ureg x)
399
400 // Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set.
401 (MOVVstore [off] {sym} ptr (MOVVfpgp val) mem) => (MOVDstore [off] {sym} ptr val mem)
402 (MOVDstore [off] {sym} ptr (MOVVgpfp val) mem) => (MOVVstore [off] {sym} ptr val mem)
403 (MOVWstore [off] {sym} ptr (MOVWfpgp val) mem) => (MOVFstore [off] {sym} ptr val mem)
404 (MOVFstore [off] {sym} ptr (MOVWgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem)
405
406 // medium move uses a duff device
407 (Move [s] {t} dst src mem)
408 && s%8 == 0 && s >= 24 && s <= 8*128 && t.Alignment()%8 == 0
409 && ssa.LogLargeCopyValue(v, s) =>
410 (DUFFCOPY [16 * (128 - s/8)] dst src mem)
411 // 16 and 128 are magic constants. 16 is the number of bytes to encode:
412 // MOVV (R1), R23
413 // ADDV $8, R1
414 // MOVV R23, (R2)
415 // ADDV $8, R2
416 // and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy.
417
418 // large or unaligned move uses a loop
419 (Move [s] {t} dst src mem)
420 && s > 24 && ssa.LogLargeCopyValue(v, s) || t.Alignment()%8 != 0 =>
421 (LoweredMove [t.Alignment()]
422 dst
423 src
424 (ADDVconst <src.Type> src [s-ssa.MoveSize(t.Alignment(), config)])
425 mem)
426
427 // calls
428 (StaticCall ...) => (CALLstatic ...)
429 (ClosureCall ...) => (CALLclosure ...)
430 (InterCall ...) => (CALLinter ...)
431 (TailCall ...) => (CALLtail ...)
432 (TailCallInter ...) => (CALLtailinter ...)
433
434 // atomic intrinsics
435 (AtomicLoad(8|32|64) ...) => (LoweredAtomicLoad(8|32|64) ...)
436 (AtomicLoadPtr ...) => (LoweredAtomicLoad64 ...)
437
438 (AtomicStore(8|32|64) ...) => (LoweredAtomicStore(8|32|64) ...)
439 (AtomicStorePtrNoWB ...) => (LoweredAtomicStore64 ...)
440
441 (AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...)
442
443 (AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
444
445 (AtomicCompareAndSwap32 ptr old new mem) => (LoweredAtomicCas32 ptr (SignExt32to64 old) new mem)
446 (AtomicCompareAndSwap64 ...) => (LoweredAtomicCas64 ...)
447
448 // AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3,uint32(val) << ((ptr & 3) * 8))
449 (AtomicOr8 ptr val mem) && !config.BigEndian =>
450 (LoweredAtomicOr32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
451 (SLLV <typ.UInt32> (ZeroExt8to32 val)
452 (SLLVconst <typ.UInt64> [3]
453 (ANDconst <typ.UInt64> [3] ptr))) mem)
454
455 // AtomicAnd8(ptr,val) => LoweredAtomicAnd32(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
456 (AtomicAnd8 ptr val mem) && !config.BigEndian =>
457 (LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
458 (OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val)
459 (SLLVconst <typ.UInt64> [3]
460 (ANDconst <typ.UInt64> [3] ptr)))
461 (NOR (MOVVconst [0]) <typ.UInt64> (SLLV <typ.UInt64>
462 (MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3]
463 (ANDconst <typ.UInt64> [3] ptr))))) mem)
464
465 // AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
466 (AtomicOr8 ptr val mem) && config.BigEndian =>
467 (LoweredAtomicOr32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
468 (SLLV <typ.UInt32> (ZeroExt8to32 val)
469 (SLLVconst <typ.UInt64> [3]
470 (ANDconst <typ.UInt64> [3]
471 (XORconst <typ.UInt64> [3] ptr)))) mem)
472
473 // AtomicAnd8(ptr,val) => LoweredAtomicAnd32(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8))))
474 (AtomicAnd8 ptr val mem) && config.BigEndian =>
475 (LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
476 (OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val)
477 (SLLVconst <typ.UInt64> [3]
478 (ANDconst <typ.UInt64> [3]
479 (XORconst <typ.UInt64> [3] ptr))))
480 (NOR (MOVVconst [0]) <typ.UInt64> (SLLV <typ.UInt64>
481 (MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3]
482 (ANDconst <typ.UInt64> [3]
483 (XORconst <typ.UInt64> [3] ptr)))))) mem)
484
485 (AtomicAnd32 ...) => (LoweredAtomicAnd32 ...)
486 (AtomicOr32 ...) => (LoweredAtomicOr32 ...)
487
488 // checks
489 (NilCheck ...) => (LoweredNilCheck ...)
490 (IsNonNil ptr) => (SGTU ptr (MOVVconst [0]))
491 (IsInBounds idx len) => (SGTU len idx)
492 (IsSliceInBounds idx len) => (XOR (MOVVconst [1]) (SGTU idx len))
493
494 // pseudo-ops
495 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
496 (GetCallerSP ...) => (LoweredGetCallerSP ...)
497 (GetCallerPC ...) => (LoweredGetCallerPC ...)
498
499 (If cond yes no) => (NE cond yes no)
500
501 (JumpTable idx) => (JUMPTABLE {ssa.MakeJumpTableSym(b)} idx (MOVVaddr <typ.Uintptr> {ssa.MakeJumpTableSym(b)} (SB)))
502
503 // Write barrier.
504 (WB ...) => (LoweredWB ...)
505
506 // Publication barrier as intrinsic
507 (PubBarrier ...) => (LoweredPubBarrier ...)
508
509 (PanicBounds ...) => (LoweredPanicBoundsRR ...)
510 (LoweredPanicBoundsRR [kind] x (MOVVconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {ssa.PanicBoundsC{C:c}} mem)
511 (LoweredPanicBoundsRR [kind] (MOVVconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {ssa.PanicBoundsC{C:c}} y mem)
512 (LoweredPanicBoundsRC [kind] {p} (MOVVconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:c, Cy:p.C}} mem)
513 (LoweredPanicBoundsCR [kind] {p} (MOVVconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:p.C, Cy:c}} mem)
514
515 // Optimizations
516
517 // Absorb boolean tests into block
518 (NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
519 (NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
520 (EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
521 (EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
522 (NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
523 (NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no)
524 (NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no)
525 (NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no)
526 (EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no)
527 (EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no)
528 (EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no)
529 (EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no)
530 (NE (SGTUconst [1] x) yes no) => (EQ x yes no)
531 (EQ (SGTUconst [1] x) yes no) => (NE x yes no)
532 (NE (SGTU x (MOVVconst [0])) yes no) => (NE x yes no)
533 (EQ (SGTU x (MOVVconst [0])) yes no) => (EQ x yes no)
534 (NE (SGTconst [0] x) yes no) => (LTZ x yes no)
535 (EQ (SGTconst [0] x) yes no) => (GEZ x yes no)
536 (NE (SGT x (MOVVconst [0])) yes no) => (GTZ x yes no)
537 (EQ (SGT x (MOVVconst [0])) yes no) => (LEZ x yes no)
538
539 // fold offset into address
540 (ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) && ssa.Is32Bit(off1+int64(off2)) => (MOVVaddr [int32(off1)+int32(off2)] {sym} ptr)
541
542 // fold address into load/store
543 (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
544 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVBload [off1+int32(off2)] {sym} ptr mem)
545 (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
546 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVBUload [off1+int32(off2)] {sym} ptr mem)
547 (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
548 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVHload [off1+int32(off2)] {sym} ptr mem)
549 (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
550 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVHUload [off1+int32(off2)] {sym} ptr mem)
551 (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
552 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVWload [off1+int32(off2)] {sym} ptr mem)
553 (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
554 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVWUload [off1+int32(off2)] {sym} ptr mem)
555 (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
556 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVVload [off1+int32(off2)] {sym} ptr mem)
557 (MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
558 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVFload [off1+int32(off2)] {sym} ptr mem)
559 (MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
560 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVDload [off1+int32(off2)] {sym} ptr mem)
561
562 (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
563 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVBstore [off1+int32(off2)] {sym} ptr val mem)
564 (MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
565 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVHstore [off1+int32(off2)] {sym} ptr val mem)
566 (MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
567 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVWstore [off1+int32(off2)] {sym} ptr val mem)
568 (MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
569 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVVstore [off1+int32(off2)] {sym} ptr val mem)
570 (MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
571 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVFstore [off1+int32(off2)] {sym} ptr val mem)
572 (MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
573 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) => (MOVDstore [off1+int32(off2)] {sym} ptr val mem)
574
575 (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
576 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
577 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
578 (MOVBload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
579 (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
580 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
581 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
582 (MOVBUload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
583 (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
584 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
585 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
586 (MOVHload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
587 (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
588 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
589 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
590 (MOVHUload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
591 (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
592 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
593 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
594 (MOVWload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
595 (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
596 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
597 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
598 (MOVWUload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
599 (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
600 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
601 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
602 (MOVVload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
603 (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
604 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
605 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
606 (MOVFload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
607 (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
608 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
609 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
610 (MOVDload [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr mem)
611
612 (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
613 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
614 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
615 (MOVBstore [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr val mem)
616 (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
617 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
618 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
619 (MOVHstore [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr val mem)
620 (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
621 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
622 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
623 (MOVWstore [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr val mem)
624 (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
625 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
626 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
627 (MOVVstore [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr val mem)
628 (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
629 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
630 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
631 (MOVFstore [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr val mem)
632 (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
633 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
634 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_shared) =>
635 (MOVDstore [off1+int32(off2)] {ssa.MergeSym(sym1,sym2)} ptr val mem)
636
637 // don't extend after proper load
638 (MOVBreg x:(MOVBload _ _)) => (MOVVreg x)
639 (MOVBUreg x:(MOVBUload _ _)) => (MOVVreg x)
640 (MOVHreg x:(MOVBload _ _)) => (MOVVreg x)
641 (MOVHreg x:(MOVBUload _ _)) => (MOVVreg x)
642 (MOVHreg x:(MOVHload _ _)) => (MOVVreg x)
643 (MOVHUreg x:(MOVBUload _ _)) => (MOVVreg x)
644 (MOVHUreg x:(MOVHUload _ _)) => (MOVVreg x)
645 (MOVWreg x:(MOVBload _ _)) => (MOVVreg x)
646 (MOVWreg x:(MOVBUload _ _)) => (MOVVreg x)
647 (MOVWreg x:(MOVHload _ _)) => (MOVVreg x)
648 (MOVWreg x:(MOVHUload _ _)) => (MOVVreg x)
649 (MOVWreg x:(MOVWload _ _)) => (MOVVreg x)
650 (MOVWUreg x:(MOVBUload _ _)) => (MOVVreg x)
651 (MOVWUreg x:(MOVHUload _ _)) => (MOVVreg x)
652 (MOVWUreg x:(MOVWUload _ _)) => (MOVVreg x)
653
654 // fold double extensions
655 (MOVBreg x:(MOVBreg _)) => (MOVVreg x)
656 (MOVBUreg x:(MOVBUreg _)) => (MOVVreg x)
657 (MOVHreg x:(MOVBreg _)) => (MOVVreg x)
658 (MOVHreg x:(MOVBUreg _)) => (MOVVreg x)
659 (MOVHreg x:(MOVHreg _)) => (MOVVreg x)
660 (MOVHUreg x:(MOVBUreg _)) => (MOVVreg x)
661 (MOVHUreg x:(MOVHUreg _)) => (MOVVreg x)
662 (MOVWreg x:(MOVBreg _)) => (MOVVreg x)
663 (MOVWreg x:(MOVBUreg _)) => (MOVVreg x)
664 (MOVWreg x:(MOVHreg _)) => (MOVVreg x)
665 (MOVWreg x:(MOVWreg _)) => (MOVVreg x)
666 (MOVWUreg x:(MOVBUreg _)) => (MOVVreg x)
667 (MOVWUreg x:(MOVHUreg _)) => (MOVVreg x)
668 (MOVWUreg x:(MOVWUreg _)) => (MOVVreg x)
669
670 // don't extend before store
671 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
672 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
673 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
674 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
675 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
676 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
677 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
678 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
679 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
680 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
681 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
682 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
683
684 // if a register move has only 1 use, just use the same register without emitting instruction
685 // MOVVnop doesn't emit instruction, only for ensuring the type.
686 (MOVVreg x) && x.Uses == 1 => (MOVVnop x)
687
688 // TODO: we should be able to get rid of MOVVnop all together.
689 // But for now, this is enough to get rid of lots of them.
690 (MOVVnop (MOVVconst [c])) => (MOVVconst [c])
691
692 // fold constant into arithmetic ops
693 (ADDV x (MOVVconst <t> [c])) && ssa.Is32Bit(c) && !t.IsPtr() => (ADDVconst [c] x)
694 (SUBV x (MOVVconst [c])) && ssa.Is32Bit(c) => (SUBVconst [c] x)
695 (AND x (MOVVconst [c])) && ssa.Is32Bit(c) => (ANDconst [c] x)
696 (OR x (MOVVconst [c])) && ssa.Is32Bit(c) => (ORconst [c] x)
697 (XOR x (MOVVconst [c])) && ssa.Is32Bit(c) => (XORconst [c] x)
698
699 (SLLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
700 (SRLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
701 (SRAV x (MOVVconst [c])) && uint64(c)>=64 => (SRAVconst x [63])
702 (SLLV x (MOVVconst [c])) => (SLLVconst x [c])
703 (SRLV x (MOVVconst [c])) => (SRLVconst x [c])
704 (SRAV x (MOVVconst [c])) => (SRAVconst x [c])
705
706 (SGT (MOVVconst [c]) x) && ssa.Is32Bit(c) => (SGTconst [c] x)
707 (SGTU (MOVVconst [c]) x) && ssa.Is32Bit(c) => (SGTUconst [c] x)
708
709 // mul by constant
710 (Select1 (MULVU x (MOVVconst [-1]))) => (NEGV x)
711 (Select1 (MULVU _ (MOVVconst [0]))) => (MOVVconst [0])
712 (Select1 (MULVU x (MOVVconst [1]))) => x
713 (Select1 (MULVU x (MOVVconst [c]))) && ssa.IsPowerOfTwo(c) => (SLLVconst [ssa.Log64(c)] x)
714
715 // div by constant
716 (Select1 (DIVVU x (MOVVconst [1]))) => x
717 (Select1 (DIVVU x (MOVVconst [c]))) && ssa.IsPowerOfTwo(c) => (SRLVconst [ssa.Log64(c)] x)
718 (Select0 (DIVVU _ (MOVVconst [1]))) => (MOVVconst [0]) // mod
719 (Select0 (DIVVU x (MOVVconst [c]))) && ssa.IsPowerOfTwo(c) => (ANDconst [c-1] x) // mod
720
721 // Absorb conversion between 32 bit and 64 bit if both src and dst are 32 bit.
722 (MOVDF ((ABS|SQRT)D (MOVFD x))) => ((ABS|SQRT)F x)
723
724 // generic simplifications
725 (ADDV x (NEGV y)) => (SUBV x y)
726 (SUBV x (NEGV y)) => (ADDV x y)
727 (SUBV x x) => (MOVVconst [0])
728 (SUBV (MOVVconst [0]) x) => (NEGV x)
729 (AND x x) => x
730 (OR x x) => x
731 (XOR x x) => (MOVVconst [0])
732 (NEGV (SUBV x y)) => (SUBV y x)
733 (NEGV (NEGV x)) => x
734
735 // remove redundant *const ops
736 (ADDVconst [0] x) => x
737 (SUBVconst [0] x) => x
738 (ANDconst [0] _) => (MOVVconst [0])
739 (ANDconst [-1] x) => x
740 (ORconst [0] x) => x
741 (ORconst [-1] _) => (MOVVconst [-1])
742 (XORconst [0] x) => x
743
744 // generic constant folding
745 (ADDVconst [c] (MOVVconst [d])) => (MOVVconst [c+d])
746 (ADDVconst [c] (ADDVconst [d] x)) && ssa.Is32Bit(c+d) => (ADDVconst [c+d] x)
747 (ADDVconst [c] (SUBVconst [d] x)) && ssa.Is32Bit(c-d) => (ADDVconst [c-d] x)
748 (SUBVconst [c] (MOVVconst [d])) => (MOVVconst [d-c])
749 (SUBVconst [c] (SUBVconst [d] x)) && ssa.Is32Bit(-c-d) => (ADDVconst [-c-d] x)
750 (SUBVconst [c] (ADDVconst [d] x)) && ssa.Is32Bit(-c+d) => (ADDVconst [-c+d] x)
751 (SLLVconst [c] (MOVVconst [d])) => (MOVVconst [d<<uint64(c)])
752 (SRLVconst [c] (MOVVconst [d])) => (MOVVconst [int64(uint64(d)>>uint64(c))])
753 (SRAVconst [c] (MOVVconst [d])) => (MOVVconst [d>>uint64(c)])
754 (Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [c*d])
755 (Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [c/d])
756 (Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)/uint64(d))])
757 (Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [c%d]) // mod
758 (Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)%uint64(d))]) // mod
759 (ANDconst [c] (MOVVconst [d])) => (MOVVconst [c&d])
760 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
761 (ORconst [c] (MOVVconst [d])) => (MOVVconst [c|d])
762 (ORconst [c] (ORconst [d] x)) && ssa.Is32Bit(c|d) => (ORconst [c|d] x)
763 (XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d])
764 (XORconst [c] (XORconst [d] x)) && ssa.Is32Bit(c^d) => (XORconst [c^d] x)
765 (NEGV (MOVVconst [c])) => (MOVVconst [-c])
766 (MOVBreg (MOVVconst [c])) => (MOVVconst [int64(int8(c))])
767 (MOVBUreg (MOVVconst [c])) => (MOVVconst [int64(uint8(c))])
768 (MOVHreg (MOVVconst [c])) => (MOVVconst [int64(int16(c))])
769 (MOVHUreg (MOVVconst [c])) => (MOVVconst [int64(uint16(c))])
770 (MOVWreg (MOVVconst [c])) => (MOVVconst [int64(int32(c))])
771 (MOVWUreg (MOVVconst [c])) => (MOVVconst [int64(uint32(c))])
772 (MOVVreg (MOVVconst [c])) => (MOVVconst [c])
773 (LoweredAtomicStore(32|64) ptr (MOVVconst [0]) mem) => (LoweredAtomicStorezero(32|64) ptr mem)
774 (LoweredAtomicAdd32 ptr (MOVVconst [c]) mem) && ssa.Is32Bit(c) => (LoweredAtomicAddconst32 [int32(c)] ptr mem)
775 (LoweredAtomicAdd64 ptr (MOVVconst [c]) mem) && ssa.Is32Bit(c) => (LoweredAtomicAddconst64 [c] ptr mem)
776
777 // constant comparisons
778 (SGTconst [c] (MOVVconst [d])) && c>d => (MOVVconst [1])
779 (SGTconst [c] (MOVVconst [d])) && c<=d => (MOVVconst [0])
780 (SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) => (MOVVconst [1])
781 (SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) => (MOVVconst [0])
782
783 // other known comparisons
784 (SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVVconst [1])
785 (SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVVconst [0])
786 (SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVVconst [1])
787 (SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVVconst [0])
788 (SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) => (MOVVconst [1])
789 (SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVVconst [1])
790 (SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVVconst [0])
791 (SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVVconst [1])
792 (SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVVconst [0])
793 (SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) => (MOVVconst [1])
794 (SGTconst [c] (MOVWUreg _)) && c < 0 => (MOVVconst [0])
795 (SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVVconst [1])
796 (SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) => (MOVVconst [1])
797 (SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
798 (SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
799
800 // absorb constants into branches
801 (EQ (MOVVconst [0]) yes no) => (First yes no)
802 (EQ (MOVVconst [c]) yes no) && c != 0 => (First no yes)
803 (NE (MOVVconst [0]) yes no) => (First no yes)
804 (NE (MOVVconst [c]) yes no) && c != 0 => (First yes no)
805 (LTZ (MOVVconst [c]) yes no) && c < 0 => (First yes no)
806 (LTZ (MOVVconst [c]) yes no) && c >= 0 => (First no yes)
807 (LEZ (MOVVconst [c]) yes no) && c <= 0 => (First yes no)
808 (LEZ (MOVVconst [c]) yes no) && c > 0 => (First no yes)
809 (GTZ (MOVVconst [c]) yes no) && c > 0 => (First yes no)
810 (GTZ (MOVVconst [c]) yes no) && c <= 0 => (First no yes)
811 (GEZ (MOVVconst [c]) yes no) && c >= 0 => (First yes no)
812 (GEZ (MOVVconst [c]) yes no) && c < 0 => (First no yes)
813
814 // SGT/SGTU with known outcomes.
815 (SGT x x) => (MOVVconst [0])
816 (SGTU x x) => (MOVVconst [0])
817
818 // fold readonly sym load
819 (MOVBUload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVVconst [int64(ssa.Read8(sym, int64(off)))])
820 (MOVHUload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVVconst [int64(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
821 (MOVWUload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVVconst [int64(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
822 (MOVVload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVVconst [int64(ssa.Read64(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
823 (MOVBload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVVconst [int64(int8(ssa.Read8(sym, int64(off))))])
824 (MOVHload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVVconst [int64(int16(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
825 (MOVWload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVVconst [int64(int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
826
View as plain text