1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 // GOPPC64 values indicate power8, power9, etc.
6 // That means the code is compiled for that target,
7 // and will not run on earlier targets.
8 //
9 (Add(Ptr|64|32|16|8) ...) => (ADD ...)
10 (Add64F ...) => (FADD ...)
11 (Add32F ...) => (FADDS ...)
12
13 (Sub(Ptr|64|32|16|8) ...) => (SUB ...)
14 (Sub32F ...) => (FSUBS ...)
15 (Sub64F ...) => (FSUB ...)
16
17 (Min(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMINJDP x y)
18 (Max(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMAXJDP x y)
19
20 // Combine 64 bit integer multiply and adds
21 (ADD z l:(MULLD x y)) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD x y z )
22 (ADD z l:(MULLDconst <mt> [x] y)) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD (MOVDconst <mt> [int64(x)]) y z )
23 (ADDconst <at> [z] l:(MULLD x y)) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD x y (MOVDconst <at> [int64(z)]))
24 (ADDconst <at> [z] l:(MULLDconst <mt> [x] y)) && buildcfg.GOPPC64 >= 9 && l.Uses == 1 && clobber(l) => (MADDLD (MOVDconst <mt> [int64(x)]) y (MOVDconst <at> [int64(z)]))
25
26 (Mod16 x y) => (Mod32 (SignExt16to32 x) (SignExt16to32 y))
27 (Mod16u x y) => (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y))
28 (Mod8 x y) => (Mod32 (SignExt8to32 x) (SignExt8to32 y))
29 (Mod8u x y) => (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y))
30 (Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y)
31 (Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y)))
32 (Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y)
33 (Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y)))
34 (Mod32 x y) && buildcfg.GOPPC64 >= 9 => (MODSW x y)
35 (Mod32 x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVW x y)))
36 (Mod32u x y) && buildcfg.GOPPC64 >= 9 => (MODUW x y)
37 (Mod32u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVWU x y)))
38
39 // (x + y) / 2 with x>=y => (x - y) / 2 + y
40 (Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
41
42 (Mul64 ...) => (MULLD ...)
43 (Mul(32|16|8) ...) => (MULLW ...)
44 (Select0 (Mul64uhilo x y)) => (MULHDU x y)
45 (Select1 (Mul64uhilo x y)) => (MULLD x y)
46 (Select0 (Mul64uover x y)) => (MULLD x y)
47 (Select1 (Mul64uover x y)) => (SETBCR [2] (CMPconst [0] (MULHDU <x.Type> x y)))
48
49 (Div64 [false] x y) => (DIVD x y)
50 (Div64u ...) => (DIVDU ...)
51 (Div32 [false] x y) => (DIVW x y)
52 (Div32u ...) => (DIVWU ...)
53 (Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y))
54 (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
55 (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y))
56 (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))
57
58 (Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...)
59
60 (Mul(32|64)F ...) => ((FMULS|FMUL) ...)
61
62 (Div(32|64)F ...) => ((FDIVS|FDIV) ...)
63
64 // Lowering float <=> int
65 (Cvt32to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD (SignExt32to64 x)))
66 (Cvt64to(32|64)F x) => ((FCFIDS|FCFID) (MTVSRD x))
67
68 (Cvt32Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x))
69 (Cvt64Fto(32|64) x) => (MFVSRD (FCTI(W|D)Z x))
70
71 (Cvt32Fto64F ...) => (Copy ...) // Note v will have the wrong type for patterns dependent on Float32/Float64
72 (Cvt64Fto32F ...) => (FRSP ...)
73
74 (CvtBoolToUint8 ...) => (Copy ...)
75
76 (Round(32|64)F ...) => (LoweredRound(32|64)F ...)
77
78 (Sqrt ...) => (FSQRT ...)
79 (Sqrt32 ...) => (FSQRTS ...)
80 (Floor ...) => (FFLOOR ...)
81 (Ceil ...) => (FCEIL ...)
82 (Trunc ...) => (FTRUNC ...)
83 (Round ...) => (FROUND ...)
84 (Copysign x y) => (FCPSGN y x)
85 (Abs ...) => (FABS ...)
86 (FMA ...) => (FMADD ...)
87
88 // Lowering extension
89 // Note: we always extend to 64 bits even though some ops don't need that many result bits.
90 (SignExt8to(16|32|64) ...) => (MOVBreg ...)
91 (SignExt16to(32|64) ...) => (MOVHreg ...)
92 (SignExt32to64 ...) => (MOVWreg ...)
93
94 (ZeroExt8to(16|32|64) ...) => (MOVBZreg ...)
95 (ZeroExt16to(32|64) ...) => (MOVHZreg ...)
96 (ZeroExt32to64 ...) => (MOVWZreg ...)
97
98 (Trunc(16|32|64)to8 <t> x) && t.IsSigned() => (MOVBreg x)
99 (Trunc(16|32|64)to8 x) => (MOVBZreg x)
100 (Trunc(32|64)to16 <t> x) && t.IsSigned() => (MOVHreg x)
101 (Trunc(32|64)to16 x) => (MOVHZreg x)
102 (Trunc64to32 <t> x) && t.IsSigned() => (MOVWreg x)
103 (Trunc64to32 x) => (MOVWZreg x)
104
105 // Lowering constants
106 (Const(64|32|16|8) [val]) => (MOVDconst [int64(val)])
107 (Const(32|64)F ...) => (FMOV(S|D)const ...)
108 (ConstNil) => (MOVDconst [0])
109 (ConstBool [t]) => (MOVDconst [b2i(t)])
110
111 // Carrying addition.
112 (Select0 (Add64carry x y c)) => (Select0 <typ.UInt64> (ADDE x y (Select1 <typ.UInt64> (ADDCconst c [-1]))))
113 (Select1 (Add64carry x y c)) => (ADDZEzero (Select1 <typ.UInt64> (ADDE x y (Select1 <typ.UInt64> (ADDCconst c [-1])))))
114 // Fold initial carry bit if 0.
115 (ADDE x y (Select1 <typ.UInt64> (ADDCconst (MOVDconst [0]) [-1]))) => (ADDC x y)
116 // Fold transfer of CA -> GPR -> CA. Note 2 uses when feeding into a chained Add64carry.
117 (Select1 (ADDCconst n:(ADDZEzero x) [-1])) && n.Uses <= 2 => x
118 (ADDE (MOVDconst [0]) y c) => (ADDZE y c)
119 (ADDC x (MOVDconst [y])) && is16Bit(y) => (ADDCconst [y] x)
120
121 // Borrowing subtraction.
122 (Select0 (Sub64borrow x y c)) => (Select0 <typ.UInt64> (SUBE x y (Select1 <typ.UInt64> (SUBCconst c [0]))))
123 (Select1 (Sub64borrow x y c)) => (NEG (SUBZEzero (Select1 <typ.UInt64> (SUBE x y (Select1 <typ.UInt64> (SUBCconst c [0]))))))
124 // Fold initial borrow bit if 0.
125 (SUBE x y (Select1 <typ.UInt64> (SUBCconst (MOVDconst [0]) [0]))) => (SUBC x y)
126 // Fold transfer of CA -> GPR -> CA. Note 2 uses when feeding into a chained Sub64borrow.
127 (Select1 (SUBCconst n:(NEG (SUBZEzero x)) [0])) && n.Uses <= 2 => x
128
129 // Constant folding
130 (FABS (FMOVDconst [x])) => (FMOVDconst [math.Abs(x)])
131 (FSQRT (FMOVDconst [x])) && x >= 0 => (FMOVDconst [math.Sqrt(x)])
132 (FFLOOR (FMOVDconst [x])) => (FMOVDconst [math.Floor(x)])
133 (FCEIL (FMOVDconst [x])) => (FMOVDconst [math.Ceil(x)])
134 (FTRUNC (FMOVDconst [x])) => (FMOVDconst [math.Trunc(x)])
135
136 // Rotates
137 (RotateLeft8 <t> x (MOVDconst [c])) => (Or8 (Lsh8x64 <t> x (MOVDconst [c&7])) (Rsh8Ux64 <t> x (MOVDconst [-c&7])))
138 (RotateLeft16 <t> x (MOVDconst [c])) => (Or16 (Lsh16x64 <t> x (MOVDconst [c&15])) (Rsh16Ux64 <t> x (MOVDconst [-c&15])))
139 (RotateLeft(32|64) ...) => ((ROTLW|ROTL) ...)
140
141 // Constant rotate generation
142 (ROTLW x (MOVDconst [c])) => (ROTLWconst x [c&31])
143 (ROTL x (MOVDconst [c])) => (ROTLconst x [c&63])
144
145 // uint8: logical ops with constant -> UI immediates (only if truncation needed).
146 (AND <t> x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) => (ANDconst [int64(uint8(m))] x)
147 (OR <t> x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) => (ORconst [int64(uint8(m))] x)
148 (XOR <t> x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 1 && m != int64(uint8(m)) => (XORconst [int64(uint8(m))] x)
149
150 // uint16: logical ops with constant -> UI immediates (only if truncation needed).
151 (AND <t> x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) => (ANDconst [int64(uint16(m))] x)
152 (OR <t> x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) => (ORconst [int64(uint16(m))] x)
153 (XOR <t> x (MOVDconst [m])) && t.IsUnsigned() && t.Size() == 2 && m != int64(uint16(m)) => (XORconst [int64(uint16(m))] x)
154
155 // Combine rotate and mask operations
156 (ANDconst [m] (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x)
157 (AND (MOVDconst [m]) (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x)
158 (ANDconst [m] (ROTLW x r)) && isPPC64WordRotateMask(m) => (RLWNM [encodePPC64RotateMask(0,m,32)] x r)
159 (AND (MOVDconst [m]) (ROTLW x r)) && isPPC64WordRotateMask(m) => (RLWNM [encodePPC64RotateMask(0,m,32)] x r)
160
161 // Note, any rotated word bitmask is still a valid word bitmask.
162 (ROTLWconst [r] (AND (MOVDconst [m]) x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,rotateLeft32(m,r),32)] x)
163 (ROTLWconst [r] (ANDconst [m] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,rotateLeft32(m,r),32)] x)
164
165 (ANDconst [m] (SRWconst x [s])) && mergePPC64RShiftMask(m,s,32) == 0 => (MOVDconst [0])
166 (ANDconst [m] (SRWconst x [s])) && mergePPC64AndSrwi(m,s) != 0 => (RLWINM [mergePPC64AndSrwi(m,s)] x)
167 (ANDconst [m] (SRDconst x [s])) && mergePPC64AndSrdi(m,s) != 0 => (RLWINM [mergePPC64AndSrdi(m,s)] x)
168 (AND (MOVDconst [m]) (SRWconst x [s])) && mergePPC64RShiftMask(m,s,32) == 0 => (MOVDconst [0])
169 (AND (MOVDconst [m]) (SRWconst x [s])) && mergePPC64AndSrwi(m,s) != 0 => (RLWINM [mergePPC64AndSrwi(m,s)] x)
170 (AND (MOVDconst [m]) (SRDconst x [s])) && mergePPC64AndSrdi(m,s) != 0 => (RLWINM [mergePPC64AndSrdi(m,s)] x)
171
172 (SRWconst (ANDconst [m] x) [s]) && mergePPC64RShiftMask(m>>uint(s),s,32) == 0 => (MOVDconst [0])
173 (SRWconst (ANDconst [m] x) [s]) && mergePPC64AndSrwi(m>>uint(s),s) != 0 => (RLWINM [mergePPC64AndSrwi(m>>uint(s),s)] x)
174 (SRWconst (AND (MOVDconst [m]) x) [s]) && mergePPC64RShiftMask(m>>uint(s),s,32) == 0 => (MOVDconst [0])
175 (SRWconst (AND (MOVDconst [m]) x) [s]) && mergePPC64AndSrwi(m>>uint(s),s) != 0 => (RLWINM [mergePPC64AndSrwi(m>>uint(s),s)] x)
176
177 (ANDconst [m] (SLDconst x [s])) && mergePPC64AndSldi(m,s) != 0 => (RLWINM [mergePPC64AndSldi(m,s)] x)
178 (AND (MOVDconst [m]) (SLDconst x [s])) && mergePPC64AndSldi(m,s) != 0 => (RLWINM [mergePPC64AndSldi(m,s)] x)
179
180 // Merge shift right + shift left and clear left (e.g for a table lookup)
181 (CLRLSLDI [c] (SRWconst [s] x)) && mergePPC64ClrlsldiSrw(int64(c),s) != 0 => (RLWINM [mergePPC64ClrlsldiSrw(int64(c),s)] x)
182 (CLRLSLDI [c] (SRDconst [s] x)) && mergePPC64ClrlsldiSrd(int64(c),s) != 0 => (RLWINM [mergePPC64ClrlsldiSrd(int64(c),s)] x)
183 (SLDconst [l] (SRWconst [r] x)) && mergePPC64SldiSrw(l,r) != 0 => (RLWINM [mergePPC64SldiSrw(l,r)] x)
184 // The following reduction shows up frequently too. e.g b[(x>>14)&0xFF]
185 (CLRLSLDI [c] i:(RLWINM [s] x)) && mergePPC64ClrlsldiRlwinm(c,s) != 0 => (RLWINM [mergePPC64ClrlsldiRlwinm(c,s)] x)
186
187 // large constant signed right shift, we leave the sign bit
188 (Rsh64x64 x (MOVDconst [c])) && uint64(c) >= 64 => (SRADconst x [63])
189 (Rsh32x64 x (MOVDconst [c])) && uint64(c) >= 32 => (SRAWconst x [63])
190 (Rsh16x64 x (MOVDconst [c])) && uint64(c) >= 16 => (SRAWconst (SignExt16to32 x) [63])
191 (Rsh8x64 x (MOVDconst [c])) && uint64(c) >= 8 => (SRAWconst (SignExt8to32 x) [63])
192
193 // constant shifts
194 ((Lsh64|Rsh64|Rsh64U)x64 x (MOVDconst [c])) && uint64(c) < 64 => (S(L|RA|R)Dconst x [c])
195 ((Lsh32|Rsh32|Rsh32U)x64 x (MOVDconst [c])) && uint64(c) < 32 => (S(L|RA|R)Wconst x [c])
196 ((Rsh16|Rsh16U)x64 x (MOVDconst [c])) && uint64(c) < 16 => (SR(AW|W)const ((Sign|Zero)Ext16to32 x) [c])
197 (Lsh16x64 x (MOVDconst [c])) && uint64(c) < 16 => (SLWconst x [c])
198 ((Rsh8|Rsh8U)x64 x (MOVDconst [c])) && uint64(c) < 8 => (SR(AW|W)const ((Sign|Zero)Ext8to32 x) [c])
199 (Lsh8x64 x (MOVDconst [c])) && uint64(c) < 8 => (SLWconst x [c])
200
201 // Lower bounded shifts first. No need to check shift value.
202 (Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
203 (Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y)
204 (Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
205 (Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
206 (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
207 (Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)
208 (Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVHZreg x) y)
209 (Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD (MOVBZreg x) y)
210 (Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD x y)
211 (Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y)
212 (Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVHreg x) y)
213 (Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD (MOVBreg x) y)
214
215 // Unbounded shifts. Go shifts saturate to 0 or -1 when shifting beyond the number of
216 // bits in a type, PPC64 shifts do not (see the ISA for details).
217 //
218 // Note, y is always non-negative.
219 //
220 // Note, ISELZ is intentionally not used in lower. Where possible, ISEL is converted to ISELZ in late lower
221 // after all the ISEL folding rules have been exercised.
222
223 ((Rsh64U|Lsh64)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPUconst y [64]))
224 ((Rsh64U|Lsh64)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPWUconst y [64]))
225 ((Rsh64U|Lsh64)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFC0] y)))
226 ((Rsh64U|Lsh64)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0x00C0] y)))
227 (Rsh64x(64|32) <t> x y) => (ISEL [0] (SRAD <t> x y) (SRADconst <t> x [63]) (CMP(U|WU)const y [64]))
228 (Rsh64x16 <t> x y) => (ISEL [2] (SRAD <t> x y) (SRADconst <t> x [63]) (CMPconst [0] (ANDconst [0xFFC0] y)))
229 (Rsh64x8 <t> x y) => (ISEL [2] (SRAD <t> x y) (SRADconst <t> x [63]) (CMPconst [0] (ANDconst [0x00C0] y)))
230
231 ((Rsh32U|Lsh32)x64 <t> x y) => (ISEL [0] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPUconst y [32]))
232 ((Rsh32U|Lsh32)x32 <t> x y) => (ISEL [0] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPWUconst y [32]))
233 ((Rsh32U|Lsh32)x16 <t> x y) => (ISEL [2] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFE0] y)))
234 ((Rsh32U|Lsh32)x8 <t> x y) => (ISEL [2] (S(R|L)W <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0x00E0] y)))
235 (Rsh32x(64|32) <t> x y) => (ISEL [0] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMP(U|WU)const y [32]))
236 (Rsh32x16 <t> x y) => (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (ANDconst [0xFFE0] y)))
237 (Rsh32x8 <t> x y) => (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (ANDconst [0x00E0] y)))
238
239 ((Rsh16U|Lsh16)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPUconst y [16]))
240 ((Rsh16U|Lsh16)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPWUconst y [16]))
241 ((Rsh16U|Lsh16)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFF0] y)))
242 ((Rsh16U|Lsh16)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVHZreg x) y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0x00F0] y)))
243 (Rsh16x(64|32) <t> x y) => (ISEL [0] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (CMP(U|WU)const y [16]))
244 (Rsh16x16 <t> x y) => (ISEL [2] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (CMPconst [0] (ANDconst [0xFFF0] y)))
245 (Rsh16x8 <t> x y) => (ISEL [2] (SRAD <t> (MOVHreg x) y) (SRADconst <t> (MOVHreg x) [15]) (CMPconst [0] (ANDconst [0x00F0] y)))
246
247 ((Rsh8U|Lsh8)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPUconst y [8]))
248 ((Rsh8U|Lsh8)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPWUconst y [8]))
249 ((Rsh8U|Lsh8)x16 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFF8] y)))
250 ((Rsh8U|Lsh8)x8 <t> x y) => (ISEL [2] (S(R|L)D <t> (MOVBZreg x) y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0x00F8] y)))
251 (Rsh8x(64|32) <t> x y) => (ISEL [0] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (CMP(U|WU)const y [8]))
252 (Rsh8x16 <t> x y) => (ISEL [2] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (CMPconst [0] (ANDconst [0xFFF8] y)))
253 (Rsh8x8 <t> x y) => (ISEL [2] (SRAD <t> (MOVBreg x) y) (SRADconst <t> (MOVBreg x) [7]) (CMPconst [0] (ANDconst [0x00F8] y)))
254
255 // Catch bounded shifts in situations like foo<<uint(shift&63) which might not be caught by the prove pass.
256 (CMP(U|WU)const [d] (ANDconst z [c])) && uint64(d) > uint64(c) => (FlagLT)
257
258 (ORN x (MOVDconst [-1])) => x
259
260 (S(RAD|RD|LD) x (MOVDconst [c])) => (S(RAD|RD|LD)const [c&63 | (c>>6&1*63)] x)
261 (S(RAW|RW|LW) x (MOVDconst [c])) => (S(RAW|RW|LW)const [c&31 | (c>>5&1*31)] x)
262
263 (Addr {sym} base) => (MOVDaddr {sym} [0] base)
264 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVDaddr {sym} (SPanchored base mem))
265 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVDaddr {sym} base)
266 (OffPtr [off] ptr) => (ADD (MOVDconst <typ.Int64> [off]) ptr)
267 (MOVDaddr {sym} [n] p:(ADD x y)) && sym == nil && n == 0 => p
268 (MOVDaddr {sym} [n] ptr) && sym == nil && n == 0 && (ptr.Op == OpArgIntReg || ptr.Op == OpPhi) => ptr
269
270 (Ctz(64|32|16|8)NonZero ...) => (Ctz64 ...)
271
272 (Ctz64 x) && buildcfg.GOPPC64 <= 8 => (POPCNTD (ANDN <typ.Int64> (ADDconst <typ.Int64> [-1] x) x))
273 (Ctz32 x) && buildcfg.GOPPC64 <= 8 => (POPCNTW (MOVWZreg (ANDN <typ.Int> (ADDconst <typ.Int> [-1] x) x)))
274 (Ctz16 x) && buildcfg.GOPPC64 <= 8 => (POPCNTW (MOVHZreg (ANDN <typ.Int16> (ADDconst <typ.Int16> [-1] x) x)))
275 (Ctz8 x) && buildcfg.GOPPC64 <= 8 => (POPCNTB (MOVBZreg (ANDN <typ.UInt8> (ADDconst <typ.UInt8> [-1] x) x)))
276
277 (Ctz64 x) && buildcfg.GOPPC64 >= 9 => (CNTTZD x)
278 (Ctz32 x) && buildcfg.GOPPC64 >= 9 => (CNTTZW (MOVWZreg x))
279 (Ctz16 x) && buildcfg.GOPPC64 >= 9 => (CNTTZD (OR <typ.UInt64> x (MOVDconst [1<<16])))
280 (Ctz8 x) && buildcfg.GOPPC64 >= 9 => (CNTTZD (OR <typ.UInt64> x (MOVDconst [1<<8])))
281
282 (BitLen64 x) => (SUBFCconst [64] (CNTLZD <typ.Int> x))
283 (BitLen32 x) => (SUBFCconst [32] (CNTLZW <typ.Int> x))
284 (BitLen(16|8) x) => (BitLen64 (ZeroExt(16|8)to64 x))
285
286 (PopCount64 ...) => (POPCNTD ...)
287 (PopCount(32|16|8) x) => (POPCNT(W|W|B) (MOV(W|H|B)Zreg x))
288
289 (And(64|32|16|8) ...) => (AND ...)
290 (Or(64|32|16|8) ...) => (OR ...)
291 (Xor(64|32|16|8) ...) => (XOR ...)
292
293 (Neg(64|32|16|8) ...) => (NEG ...)
294 (Neg(64|32)F ...) => (FNEG ...)
295
296 (Com(64|32|16|8) x) => (NOR x x)
297
298 // Lowering boolean ops
299 (AndB ...) => (AND ...)
300 (OrB ...) => (OR ...)
301 (Not x) => (XORconst [1] x)
302
303 // Merge logical operations
304 (AND x (NOR y y)) => (ANDN x y)
305 (OR x (NOR y y)) => (ORN x y)
306
307 // Lowering comparisons
308 (EqB x y) => (ANDconst [1] (EQV x y))
309 // Sign extension dependence on operand sign sets up for sign/zero-extension elision later
310 (Eq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (Equal (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
311 (Eq(8|16) x y) => (Equal (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
312 (Eq(32|64|Ptr) x y) => (Equal ((CMPW|CMP|CMP) x y))
313 (Eq(32|64)F x y) => (Equal (FCMPU x y))
314
315 (NeqB ...) => (XOR ...)
316 // Like Eq8 and Eq16, prefer sign extension likely to enable later elision.
317 (Neq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (NotEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
318 (Neq(8|16) x y) => (NotEqual (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
319 (Neq(32|64|Ptr) x y) => (NotEqual ((CMPW|CMP|CMP) x y))
320 (Neq(32|64)F x y) => (NotEqual (FCMPU x y))
321
322 (Less(8|16) x y) => (LessThan (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
323 (Less(32|64) x y) => (LessThan ((CMPW|CMP) x y))
324 (Less(32|64)F x y) => (FLessThan (FCMPU x y))
325
326 (Less(8|16)U x y) => (LessThan (CMPWU (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
327 (Less(32|64)U x y) => (LessThan ((CMPWU|CMPU) x y))
328
329 (Leq(8|16) x y) => (LessEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
330 (Leq(32|64) x y) => (LessEqual ((CMPW|CMP) x y))
331 (Leq(32|64)F x y) => (FLessEqual (FCMPU x y))
332
333 (Leq(8|16)U x y) => (LessEqual (CMPWU (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
334 (Leq(32|64)U x y) => (LessEqual (CMP(WU|U) x y))
335
336 // Absorb pseudo-ops into blocks.
337 (If (Equal cc) yes no) => (EQ cc yes no)
338 (If (NotEqual cc) yes no) => (NE cc yes no)
339 (If (LessThan cc) yes no) => (LT cc yes no)
340 (If (LessEqual cc) yes no) => (LE cc yes no)
341 (If (GreaterThan cc) yes no) => (GT cc yes no)
342 (If (GreaterEqual cc) yes no) => (GE cc yes no)
343 (If (FLessThan cc) yes no) => (FLT cc yes no)
344 (If (FLessEqual cc) yes no) => (FLE cc yes no)
345 (If (FGreaterThan cc) yes no) => (FGT cc yes no)
346 (If (FGreaterEqual cc) yes no) => (FGE cc yes no)
347
348 (If cond yes no) => (NE (CMPconst [0] (ANDconst [1] cond)) yes no)
349
350 // Absorb boolean tests into block
351 (NE (CMPconst [0] (ANDconst [1] ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) cc))) yes no) => ((EQ|NE|LT|LE|GT|GE) cc yes no)
352 (NE (CMPconst [0] (ANDconst [1] ((FLessThan|FLessEqual|FGreaterThan|FGreaterEqual) cc))) yes no) => ((FLT|FLE|FGT|FGE) cc yes no)
353
354 // absorb flag constants into branches
355 (EQ (FlagEQ) yes no) => (First yes no)
356 (EQ (FlagLT) yes no) => (First no yes)
357 (EQ (FlagGT) yes no) => (First no yes)
358
359 (NE (FlagEQ) yes no) => (First no yes)
360 (NE (FlagLT) yes no) => (First yes no)
361 (NE (FlagGT) yes no) => (First yes no)
362
363 (LT (FlagEQ) yes no) => (First no yes)
364 (LT (FlagLT) yes no) => (First yes no)
365 (LT (FlagGT) yes no) => (First no yes)
366
367 (LE (FlagEQ) yes no) => (First yes no)
368 (LE (FlagLT) yes no) => (First yes no)
369 (LE (FlagGT) yes no) => (First no yes)
370
371 (GT (FlagEQ) yes no) => (First no yes)
372 (GT (FlagLT) yes no) => (First no yes)
373 (GT (FlagGT) yes no) => (First yes no)
374
375 (GE (FlagEQ) yes no) => (First yes no)
376 (GE (FlagLT) yes no) => (First no yes)
377 (GE (FlagGT) yes no) => (First yes no)
378
379 // absorb InvertFlags into branches
380 (LT (InvertFlags cmp) yes no) => (GT cmp yes no)
381 (GT (InvertFlags cmp) yes no) => (LT cmp yes no)
382 (LE (InvertFlags cmp) yes no) => (GE cmp yes no)
383 (GE (InvertFlags cmp) yes no) => (LE cmp yes no)
384 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
385 (NE (InvertFlags cmp) yes no) => (NE cmp yes no)
386
387 // constant comparisons
388 (CMPWconst (MOVDconst [x]) [y]) && int32(x)==int32(y) => (FlagEQ)
389 (CMPWconst (MOVDconst [x]) [y]) && int32(x)<int32(y) => (FlagLT)
390 (CMPWconst (MOVDconst [x]) [y]) && int32(x)>int32(y) => (FlagGT)
391
392 (CMPconst (MOVDconst [x]) [y]) && x==y => (FlagEQ)
393 (CMPconst (MOVDconst [x]) [y]) && x<y => (FlagLT)
394 (CMPconst (MOVDconst [x]) [y]) && x>y => (FlagGT)
395
396 (CMPWUconst (MOVDconst [x]) [y]) && int32(x)==int32(y) => (FlagEQ)
397 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)<uint32(y) => (FlagLT)
398 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)>uint32(y) => (FlagGT)
399
400 (CMPUconst (MOVDconst [x]) [y]) && x==y => (FlagEQ)
401 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)<uint64(y) => (FlagLT)
402 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)>uint64(y) => (FlagGT)
403
404 // absorb flag constants into boolean values
405 (Equal (FlagEQ)) => (MOVDconst [1])
406 (Equal (FlagLT)) => (MOVDconst [0])
407 (Equal (FlagGT)) => (MOVDconst [0])
408
409 (NotEqual (FlagEQ)) => (MOVDconst [0])
410 (NotEqual (FlagLT)) => (MOVDconst [1])
411 (NotEqual (FlagGT)) => (MOVDconst [1])
412
413 (LessThan (FlagEQ)) => (MOVDconst [0])
414 (LessThan (FlagLT)) => (MOVDconst [1])
415 (LessThan (FlagGT)) => (MOVDconst [0])
416
417 (LessEqual (FlagEQ)) => (MOVDconst [1])
418 (LessEqual (FlagLT)) => (MOVDconst [1])
419 (LessEqual (FlagGT)) => (MOVDconst [0])
420
421 (GreaterThan (FlagEQ)) => (MOVDconst [0])
422 (GreaterThan (FlagLT)) => (MOVDconst [0])
423 (GreaterThan (FlagGT)) => (MOVDconst [1])
424
425 (GreaterEqual (FlagEQ)) => (MOVDconst [1])
426 (GreaterEqual (FlagLT)) => (MOVDconst [0])
427 (GreaterEqual (FlagGT)) => (MOVDconst [1])
428
429 // absorb InvertFlags into boolean values
430 ((Equal|NotEqual|LessThan|GreaterThan|LessEqual|GreaterEqual) (InvertFlags x)) => ((Equal|NotEqual|GreaterThan|LessThan|GreaterEqual|LessEqual) x)
431
432
433 // Elide compares of bit tests
434 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (ANDCC x y)) yes no)
435 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(OR x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (ORCC x y)) yes no)
436 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(XOR x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (Select1 <types.TypeFlags> (XORCC x y)) yes no)
437
438 (CondSelect x y (SETBC [a] cmp)) => (ISEL [a] x y cmp)
439 (CondSelect x y (SETBCR [a] cmp)) => (ISEL [a+4] x y cmp)
440 // Only lower after bool is lowered. It should always lower. This helps ensure the folding below happens reliably.
441 (CondSelect x y bool) && flagArg(bool) == nil => (ISEL [6] x y (CMPconst [0] (ANDconst [1] bool)))
442 // Fold any CR -> GPR -> CR transfers when applying the above rule.
443 (ISEL [6] x y (CMPconst [0] (ANDconst [1] (SETBC [c] cmp)))) => (ISEL [c] x y cmp)
444 (ISEL [6] x y ((CMP|CMPW)const [0] (SETBC [c] cmp))) => (ISEL [c] x y cmp)
445 (ISEL [6] x y ((CMP|CMPW)const [0] (SETBCR [c] cmp))) => (ISEL [c+4] x y cmp)
446
447 // Lowering loads
448 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
449 (Load <t> ptr mem) && is32BitInt(t) && t.IsSigned() => (MOVWload ptr mem)
450 (Load <t> ptr mem) && is32BitInt(t) && !t.IsSigned() => (MOVWZload ptr mem)
451 (Load <t> ptr mem) && is16BitInt(t) && t.IsSigned() => (MOVHload ptr mem)
452 (Load <t> ptr mem) && is16BitInt(t) && !t.IsSigned() => (MOVHZload ptr mem)
453 (Load <t> ptr mem) && t.IsBoolean() => (MOVBZload ptr mem)
454 (Load <t> ptr mem) && is8BitInt(t) && t.IsSigned() => (MOVBreg (MOVBZload ptr mem)) // PPC has no signed-byte load.
455 (Load <t> ptr mem) && is8BitInt(t) && !t.IsSigned() => (MOVBZload ptr mem)
456
457 (Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
458 (Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
459
460 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
461 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
462 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
463 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
464 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
465 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
466
467 // Using Zero instead of LoweredZero allows the
468 // target address to be folded where possible.
469 (Zero [0] _ mem) => mem
470 (Zero [1] destptr mem) => (MOVBstorezero destptr mem)
471 (Zero [2] destptr mem) =>
472 (MOVHstorezero destptr mem)
473 (Zero [3] destptr mem) =>
474 (MOVBstorezero [2] destptr
475 (MOVHstorezero destptr mem))
476 (Zero [4] destptr mem) =>
477 (MOVWstorezero destptr mem)
478 (Zero [5] destptr mem) =>
479 (MOVBstorezero [4] destptr
480 (MOVWstorezero destptr mem))
481 (Zero [6] destptr mem) =>
482 (MOVHstorezero [4] destptr
483 (MOVWstorezero destptr mem))
484 (Zero [7] destptr mem) =>
485 (MOVBstorezero [6] destptr
486 (MOVHstorezero [4] destptr
487 (MOVWstorezero destptr mem)))
488
489 (Zero [8] {t} destptr mem) => (MOVDstorezero destptr mem)
490 (Zero [12] {t} destptr mem) =>
491 (MOVWstorezero [8] destptr
492 (MOVDstorezero [0] destptr mem))
493 (Zero [16] {t} destptr mem) =>
494 (MOVDstorezero [8] destptr
495 (MOVDstorezero [0] destptr mem))
496 (Zero [24] {t} destptr mem) =>
497 (MOVDstorezero [16] destptr
498 (MOVDstorezero [8] destptr
499 (MOVDstorezero [0] destptr mem)))
500 (Zero [32] {t} destptr mem) =>
501 (MOVDstorezero [24] destptr
502 (MOVDstorezero [16] destptr
503 (MOVDstorezero [8] destptr
504 (MOVDstorezero [0] destptr mem))))
505
506 // Handle cases not handled above
507 // Lowered Short cases do not generate loops, and as a result don't clobber
508 // the address registers or flags.
509 (Zero [s] ptr mem) && buildcfg.GOPPC64 <= 8 && s < 64 => (LoweredZeroShort [s] ptr mem)
510 (Zero [s] ptr mem) && buildcfg.GOPPC64 <= 8 => (LoweredZero [s] ptr mem)
511 (Zero [s] ptr mem) && s < 128 && buildcfg.GOPPC64 >= 9 => (LoweredQuadZeroShort [s] ptr mem)
512 (Zero [s] ptr mem) && buildcfg.GOPPC64 >= 9 => (LoweredQuadZero [s] ptr mem)
513
514 // moves
515 (Move [0] _ _ mem) => mem
516 (Move [1] dst src mem) => (MOVBstore dst (MOVBZload src mem) mem)
517 (Move [2] dst src mem) =>
518 (MOVHstore dst (MOVHZload src mem) mem)
519 (Move [4] dst src mem) =>
520 (MOVWstore dst (MOVWZload src mem) mem)
521 // MOVD for load and store must have offsets that are multiple of 4
522 (Move [8] {t} dst src mem) =>
523 (MOVDstore dst (MOVDload src mem) mem)
524 (Move [3] dst src mem) =>
525 (MOVBstore [2] dst (MOVBZload [2] src mem)
526 (MOVHstore dst (MOVHload src mem) mem))
527 (Move [5] dst src mem) =>
528 (MOVBstore [4] dst (MOVBZload [4] src mem)
529 (MOVWstore dst (MOVWZload src mem) mem))
530 (Move [6] dst src mem) =>
531 (MOVHstore [4] dst (MOVHZload [4] src mem)
532 (MOVWstore dst (MOVWZload src mem) mem))
533 (Move [7] dst src mem) =>
534 (MOVBstore [6] dst (MOVBZload [6] src mem)
535 (MOVHstore [4] dst (MOVHZload [4] src mem)
536 (MOVWstore dst (MOVWZload src mem) mem)))
537
538 // Large move uses a loop. Since the address is computed and the
539 // offset is zero, any alignment can be used.
540 (Move [s] dst src mem) && s > 8 && buildcfg.GOPPC64 <= 8 && logLargeCopy(v, s) =>
541 (LoweredMove [s] dst src mem)
542 (Move [s] dst src mem) && s > 8 && s <= 64 && buildcfg.GOPPC64 >= 9 =>
543 (LoweredQuadMoveShort [s] dst src mem)
544 (Move [s] dst src mem) && s > 8 && buildcfg.GOPPC64 >= 9 && logLargeCopy(v, s) =>
545 (LoweredQuadMove [s] dst src mem)
546
547 // Calls
548 // Lowering calls
549 (StaticCall ...) => (CALLstatic ...)
550 (ClosureCall ...) => (CALLclosure ...)
551 (InterCall ...) => (CALLinter ...)
552 (TailCall ...) => (CALLtail ...)
553 (TailCallInter ...) => (CALLtailinter ...)
554
555 // Miscellaneous
556 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
557 (GetCallerSP ...) => (LoweredGetCallerSP ...)
558 (GetCallerPC ...) => (LoweredGetCallerPC ...)
559 (IsNonNil ptr) => (NotEqual (CMPconst [0] ptr))
560 (IsInBounds idx len) => (LessThan (CMPU idx len))
561 (IsSliceInBounds idx len) => (LessEqual (CMPU idx len))
562 (NilCheck ...) => (LoweredNilCheck ...)
563
564 // Write barrier.
565 (WB ...) => (LoweredWB ...)
566
567 // Publication barrier as intrinsic
568 (PubBarrier ...) => (LoweredPubBarrier ...)
569
570 (PanicBounds ...) => (LoweredPanicBoundsRR ...)
571 (LoweredPanicBoundsRR [kind] x (MOVDconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {PanicBoundsC{C:c}} mem)
572 (LoweredPanicBoundsRR [kind] (MOVDconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:c}} y mem)
573 (LoweredPanicBoundsRC [kind] {p} (MOVDconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:c, Cy:p.C}} mem)
574 (LoweredPanicBoundsCR [kind] {p} (MOVDconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:p.C, Cy:c}} mem)
575
576 // Optimizations
577 // Note that PPC "logical" immediates come in 0:15 and 16:31 unsigned immediate forms,
578 // so ORconst, XORconst easily expand into a pair.
579
580 // Include very-large constants in the const-const case.
581 (AND (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c&d])
582 (OR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c|d])
583 (XOR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c^d])
584 (ORN (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c|^d])
585 (ANDN (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c&^d])
586 (NOR (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [^(c|d)])
587
588 // Discover consts
589 (AND x (MOVDconst [-1])) => x
590 (AND x (MOVDconst [c])) && isU16Bit(c) => (ANDconst [c] x)
591 (XOR x (MOVDconst [c])) && isU32Bit(c) => (XORconst [c] x)
592 (OR x (MOVDconst [c])) && isU32Bit(c) => (ORconst [c] x)
593
594 // Simplify consts
595 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
596 (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x)
597 (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x)
598 (ANDconst [-1] x) => x
599 (ANDconst [0] _) => (MOVDconst [0])
600 (XORconst [0] x) => x
601 (ORconst [-1] _) => (MOVDconst [-1])
602 (ORconst [0] x) => x
603
604 // zero-extend of small and => small and
605 (MOVBZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFF => y
606 (MOVHZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFF => y
607 (MOVWZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFFFFFF => y
608 (MOVWZreg y:(AND (MOVDconst [c]) _)) && uint64(c) <= 0xFFFFFFFF => y
609
610 // sign extend of small-positive and => small-positive-and
611 (MOVBreg y:(ANDconst [c] _)) && uint64(c) <= 0x7F => y
612 (MOVHreg y:(ANDconst [c] _)) && uint64(c) <= 0x7FFF => y
613 (MOVWreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFF => y // 0xFFFF is largest immediate constant, when regarded as 32-bit is > 0
614 (MOVWreg y:(AND (MOVDconst [c]) _)) && uint64(c) <= 0x7FFFFFFF => y
615
616 // small and of zero-extend => either zero-extend or small and
617 (ANDconst [c] y:(MOVBZreg _)) && c&0xFF == 0xFF => y
618 (ANDconst [0xFF] (MOVBreg x)) => (MOVBZreg x)
619 (ANDconst [c] y:(MOVHZreg _)) && c&0xFFFF == 0xFFFF => y
620 (ANDconst [0xFFFF] (MOVHreg x)) => (MOVHZreg x)
621
622 (AND (MOVDconst [c]) y:(MOVWZreg _)) && c&0xFFFFFFFF == 0xFFFFFFFF => y
623 (AND (MOVDconst [0xFFFFFFFF]) y:(MOVWreg x)) => (MOVWZreg x)
624 // normal case
625 (ANDconst [c] (MOVBZreg x)) => (ANDconst [c&0xFF] x)
626 (ANDconst [c] (MOVHZreg x)) => (ANDconst [c&0xFFFF] x)
627 (ANDconst [c] (MOVWZreg x)) => (ANDconst [c&0xFFFFFFFF] x)
628
629 // Eliminate unnecessary sign/zero extend following right shift
630 (MOV(B|H|W)Zreg (SRWconst [c] (MOVBZreg x))) => (SRWconst [c] (MOVBZreg x))
631 (MOV(H|W)Zreg (SRWconst [c] (MOVHZreg x))) => (SRWconst [c] (MOVHZreg x))
632 (MOVWZreg (SRWconst [c] (MOVWZreg x))) => (SRWconst [c] (MOVWZreg x))
633 (MOV(B|H|W)reg (SRAWconst [c] (MOVBreg x))) => (SRAWconst [c] (MOVBreg x))
634 (MOV(H|W)reg (SRAWconst [c] (MOVHreg x))) => (SRAWconst [c] (MOVHreg x))
635 (MOVWreg (SRAWconst [c] (MOVWreg x))) => (SRAWconst [c] (MOVWreg x))
636
637 (MOV(WZ|W)reg (S(R|RA)Wconst [c] x)) && x.Type.Size() <= 32 => (S(R|RA)Wconst [c] x)
638 (MOV(HZ|H)reg (S(R|RA)Wconst [c] x)) && x.Type.Size() <= 16 => (S(R|RA)Wconst [c] x)
639 (MOV(BZ|B)reg (S(R|RA)Wconst [c] x)) && x.Type.Size() == 8 => (S(R|RA)Wconst [c] x)
640
641 // initial right shift will handle sign/zero extend
642 (MOVBZreg (SRDconst [c] x)) && c>=56 => (SRDconst [c] x)
643 (MOVBreg (SRDconst [c] x)) && c>56 => (SRDconst [c] x)
644 (MOVBreg (SRDconst [c] x)) && c==56 => (SRADconst [c] x)
645 (MOVBreg (SRADconst [c] x)) && c>=56 => (SRADconst [c] x)
646 (MOVBZreg (SRWconst [c] x)) && c>=24 => (SRWconst [c] x)
647 (MOVBreg (SRWconst [c] x)) && c>24 => (SRWconst [c] x)
648 (MOVBreg (SRWconst [c] x)) && c==24 => (SRAWconst [c] x)
649 (MOVBreg (SRAWconst [c] x)) && c>=24 => (SRAWconst [c] x)
650
651 (MOVHZreg (SRDconst [c] x)) && c>=48 => (SRDconst [c] x)
652 (MOVHreg (SRDconst [c] x)) && c>48 => (SRDconst [c] x)
653 (MOVHreg (SRDconst [c] x)) && c==48 => (SRADconst [c] x)
654 (MOVHreg (SRADconst [c] x)) && c>=48 => (SRADconst [c] x)
655 (MOVHZreg (SRWconst [c] x)) && c>=16 => (SRWconst [c] x)
656 (MOVHreg (SRWconst [c] x)) && c>16 => (SRWconst [c] x)
657 (MOVHreg (SRAWconst [c] x)) && c>=16 => (SRAWconst [c] x)
658 (MOVHreg (SRWconst [c] x)) && c==16 => (SRAWconst [c] x)
659
660 (MOVWZreg (SRDconst [c] x)) && c>=32 => (SRDconst [c] x)
661 (MOVWreg (SRDconst [c] x)) && c>32 => (SRDconst [c] x)
662 (MOVWreg (SRADconst [c] x)) && c>=32 => (SRADconst [c] x)
663 (MOVWreg (SRDconst [c] x)) && c==32 => (SRADconst [c] x)
664
665 // Various redundant zero/sign extension combinations.
666 (MOVBZreg y:(MOVBZreg _)) => y // repeat
667 (MOVBreg y:(MOVBreg _)) => y // repeat
668 (MOVBreg (MOVBZreg x)) => (MOVBreg x)
669 (MOVBZreg (MOVBreg x)) => (MOVBZreg x)
670
671 // Catch any remaining rotate+shift cases
672 (MOVBZreg (SRWconst x [s])) && mergePPC64AndSrwi(0xFF,s) != 0 => (RLWINM [mergePPC64AndSrwi(0xFF,s)] x)
673 (MOVBZreg (RLWINM [r] y)) && mergePPC64AndRlwinm(0xFF,r) != 0 => (RLWINM [mergePPC64AndRlwinm(0xFF,r)] y)
674 (MOVHZreg (RLWINM [r] y)) && mergePPC64AndRlwinm(0xFFFF,r) != 0 => (RLWINM [mergePPC64AndRlwinm(0xFFFF,r)] y)
675 (MOVWZreg (RLWINM [r] y)) && mergePPC64MovwzregRlwinm(r) != 0 => (RLWINM [mergePPC64MovwzregRlwinm(r)] y)
676 (ANDconst [m] (RLWINM [r] y)) && mergePPC64AndRlwinm(uint32(m),r) != 0 => (RLWINM [mergePPC64AndRlwinm(uint32(m),r)] y)
677 (SLDconst [s] (RLWINM [r] y)) && mergePPC64SldiRlwinm(s,r) != 0 => (RLWINM [mergePPC64SldiRlwinm(s,r)] y)
678 (RLWINM [r] (MOVHZreg u)) && mergePPC64RlwinmAnd(r,0xFFFF) != 0 => (RLWINM [mergePPC64RlwinmAnd(r,0xFFFF)] u)
679 (RLWINM [r] (ANDconst [a] u)) && mergePPC64RlwinmAnd(r,uint32(a)) != 0 => (RLWINM [mergePPC64RlwinmAnd(r,uint32(a))] u)
680 // SLWconst is a special case of RLWNM which always zero-extends the result.
681 (SLWconst [s] (MOVWZreg w)) => (SLWconst [s] w)
682 (MOVWZreg w:(SLWconst u)) => w
683
684 // H - there are more combinations than these
685
686 (MOVHZreg y:(MOV(H|B)Zreg _)) => y // repeat
687 (MOVHZreg y:(MOVHBRload _ _)) => y
688
689 (MOVHreg y:(MOV(H|B)reg _)) => y // repeat
690
691 (MOV(H|HZ)reg y:(MOV(HZ|H)reg x)) => (MOV(H|HZ)reg x)
692
693 // W - there are more combinations than these
694
695 (MOV(WZ|WZ|WZ|W|W|W)reg y:(MOV(WZ|HZ|BZ|W|H|B)reg _)) => y // repeat
696 (MOVWZreg y:(MOV(H|W)BRload _ _)) => y
697
698 (MOV(W|WZ)reg y:(MOV(WZ|W)reg x)) => (MOV(W|WZ)reg x)
699
700 // Truncate then logical then truncate: omit first, lesser or equal truncate
701 (MOVWZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVWZreg ((OR|XOR|AND) <t> x y))
702 (MOVHZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVHZreg ((OR|XOR|AND) <t> x y))
703 (MOVHZreg ((OR|XOR|AND) <t> x (MOVHZreg y))) => (MOVHZreg ((OR|XOR|AND) <t> x y))
704 (MOVBZreg ((OR|XOR|AND) <t> x (MOVWZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
705 (MOVBZreg ((OR|XOR|AND) <t> x (MOVHZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
706 (MOVBZreg ((OR|XOR|AND) <t> x (MOVBZreg y))) => (MOVBZreg ((OR|XOR|AND) <t> x y))
707
708 (MOV(B|H|W)Zreg z:(ANDconst [c] (MOVBZload ptr x))) => z
709 (MOV(B|H|W)Zreg z:(AND y (MOV(B|H|W)Zload ptr x))) => z
710 (MOV(H|W)Zreg z:(ANDconst [c] (MOVHZload ptr x))) => z
711 (MOVWZreg z:(ANDconst [c] (MOVWZload ptr x))) => z
712
713 // Arithmetic constant ops
714
715 (ADD x (MOVDconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDconst [c] x)
716 (ADDconst [c] (ADDconst [d] x)) && is32Bit(c+d) => (ADDconst [c+d] x)
717 (ADDconst [0] x) => x
718 (SUB x (MOVDconst [c])) && is32Bit(-c) => (ADDconst [-c] x)
719
720 (ADDconst [c] (MOVDaddr [d] {sym} x)) && is32Bit(c+int64(d)) => (MOVDaddr [int32(c+int64(d))] {sym} x)
721 (ADDconst [c] x:(SP)) && is32Bit(c) => (MOVDaddr [int32(c)] x) // so it is rematerializeable
722
723 (MULL(W|D) x (MOVDconst [c])) && is16Bit(c) => (MULL(W|D)const [int32(c)] x)
724
725 // Subtract from (with carry, but ignored) constant.
726 // Note, these clobber the carry bit.
727 (SUB (MOVDconst [c]) x) && is32Bit(c) => (SUBFCconst [c] x)
728 (SUBFCconst [c] (NEG x)) => (ADDconst [c] x)
729 (SUBFCconst [c] (SUBFCconst [d] x)) && is32Bit(c-d) => (ADDconst [c-d] x)
730 (SUBFCconst [0] x) => (NEG x)
731 (ADDconst [c] (SUBFCconst [d] x)) && is32Bit(c+d) => (SUBFCconst [c+d] x)
732 (NEG (ADDconst [c] x)) && is32Bit(-c) => (SUBFCconst [-c] x)
733 (NEG (SUBFCconst [c] x)) && is32Bit(-c) => (ADDconst [-c] x)
734 (NEG (SUB x y)) => (SUB y x)
735 (NEG (NEG x)) => x
736
737 // Use register moves instead of stores and loads to move int<=>float values
738 // Common with math Float64bits, Float64frombits
739 (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) => (MFVSRD x)
740 (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) => (MTVSRD x)
741
742 (FMOVDstore [off] {sym} ptr (MTVSRD x) mem) => (MOVDstore [off] {sym} ptr x mem)
743 (MOVDstore [off] {sym} ptr (MFVSRD x) mem) => (FMOVDstore [off] {sym} ptr x mem)
744
745 (MTVSRD (MOVDconst [c])) && !math.IsNaN(math.Float64frombits(uint64(c))) => (FMOVDconst [math.Float64frombits(uint64(c))])
746 (MFVSRD (FMOVDconst [c])) => (MOVDconst [int64(math.Float64bits(c))])
747
748 (MTVSRD x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (FMOVDload [off] {sym} ptr mem)
749 (MFVSRD x:(FMOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVDload [off] {sym} ptr mem)
750
751 // Rules for MOV* or FMOV* ops determine when indexed (MOV*loadidx or MOV*storeidx)
752 // or non-indexed (MOV*load or MOV*store) should be used. Indexed instructions
753 // require an extra instruction and register to load the index so non-indexed is preferred.
754 // Indexed ops generate indexed load or store instructions for all GOPPC64 values.
755 // Non-indexed ops generate DS-form loads and stores when the offset fits in 16 bits,
756 // and on power8 and power9, a multiple of 4 is required for MOVW and MOVD ops.
757 // On power10, prefixed loads and stores can be used for offsets > 16 bits and <= 32 bits.
758 // and support for PC relative addressing must be available if relocation is needed.
759 // On power10, the assembler will determine when to use DS-form or prefixed
760 // instructions for non-indexed ops depending on the value of the offset.
761 //
762 // Fold offsets for stores.
763 (MOV(D|W|H|B)store [off1] {sym} (ADDconst [off2] x) val mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (MOV(D|W|H|B)store [off1+int32(off2)] {sym} x val mem)
764
765 (FMOV(S|D)store [off1] {sym} (ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (FMOV(S|D)store [off1+int32(off2)] {sym} ptr val mem)
766
767 // Fold address into load/store.
768 // If power10 with PCRel is not available, then
769 // the assembler needs to generate several instructions and use
770 // temp register for accessing global, and each time it will reload
771 // the temp register. So don't fold address of global in that case if there is more than
772 // one use.
773 (MOV(B|H|W|D)store [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
774 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
775 (MOV(B|H|W|D)store [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
776
777 (FMOV(S|D)store [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
778 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
779 (FMOV(S|D)store [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
780
781 (MOV(B|H|W)Zload [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
782 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
783 (MOV(B|H|W)Zload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
784 (MOV(H|W|D)load [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
785 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
786 (MOV(H|W|D)load [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
787 (FMOV(S|D)load [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
788 && ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
789 (FMOV(S|D)load [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
790
791 // Fold offsets for loads.
792 (FMOV(S|D)load [off1] {sym} (ADDconst [off2] ptr) mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (FMOV(S|D)load [off1+int32(off2)] {sym} ptr mem)
793
794 (MOV(D|W|WZ|H|HZ|BZ)load [off1] {sym} (ADDconst [off2] x) mem) && (is16Bit(int64(off1)+off2) || (supportsPPC64PCRel() && is32Bit(int64(off1)+off2))) => (MOV(D|W|WZ|H|HZ|BZ)load [off1+int32(off2)] {sym} x mem)
795
796 // Determine load + addressing that can be done as a register indexed load
797 (MOV(D|W|WZ|H|HZ|BZ)load [0] {sym} p:(ADD ptr idx) mem) && sym == nil && p.Uses == 1 => (MOV(D|W|WZ|H|HZ|BZ)loadidx ptr idx mem)
798
799 // See comments above concerning selection of indexed vs. non-indexed ops.
800 // These cases don't have relocation.
801 (MOV(D|W)loadidx ptr (MOVDconst [c]) mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(D|W)load [int32(c)] ptr mem)
802 (MOV(WZ|H|HZ|BZ)loadidx ptr (MOVDconst [c]) mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(WZ|H|HZ|BZ)load [int32(c)] ptr mem)
803 (MOV(D|W)loadidx (MOVDconst [c]) ptr mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(D|W)load [int32(c)] ptr mem)
804 (MOV(WZ|H|HZ|BZ)loadidx (MOVDconst [c]) ptr mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(WZ|H|HZ|BZ)load [int32(c)] ptr mem)
805
806 // Store of zero => storezero
807 (MOV(D|W|H|B)store [off] {sym} ptr (MOVDconst [0]) mem) => (MOV(D|W|H|B)storezero [off] {sym} ptr mem)
808
809 // Fold offsets for storezero
810 (MOV(D|W|H|B)storezero [off1] {sym} (ADDconst [off2] x) mem) && ((supportsPPC64PCRel() && is32Bit(int64(off1)+off2)) || (is16Bit(int64(off1)+off2))) =>
811 (MOV(D|W|H|B)storezero [off1+int32(off2)] {sym} x mem)
812
813 // Stores with addressing that can be done as indexed stores
814 (MOV(D|W|H|B)store [0] {sym} p:(ADD ptr idx) val mem) && sym == nil && p.Uses == 1 => (MOV(D|W|H|B)storeidx ptr idx val mem)
815
816 (MOVDstoreidx ptr (MOVDconst [c]) val mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOVDstore [int32(c)] ptr val mem)
817 (MOV(W|H|B)storeidx ptr (MOVDconst [c]) val mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(W|H|B)store [int32(c)] ptr val mem)
818 (MOVDstoreidx (MOVDconst [c]) ptr val mem) && ((is16Bit(c) && c%4 == 0) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOVDstore [int32(c)] ptr val mem)
819 (MOV(W|H|B)storeidx (MOVDconst [c]) ptr val mem) && (is16Bit(c) || (buildcfg.GOPPC64 >= 10 && is32Bit(c))) => (MOV(W|H|B)store [int32(c)] ptr val mem)
820
821 // Fold symbols into storezero
822 (MOV(D|W|H|B)storezero [off1] {sym1} p:(MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2)
823 && ((is16Bit(int64(off1+off2)) && (x.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
824 (MOV(D|W|H|B)storezero [off1+off2] {mergeSym(sym1,sym2)} x mem)
825
826 // atomic intrinsics
827 (AtomicLoad(8|32|64|Ptr) ptr mem) => (LoweredAtomicLoad(8|32|64|Ptr) [1] ptr mem)
828 (AtomicLoadAcq(32|64) ptr mem) => (LoweredAtomicLoad(32|64) [0] ptr mem)
829
830 (AtomicStore(8|32|64) ptr val mem) => (LoweredAtomicStore(8|32|64) [1] ptr val mem)
831 (AtomicStoreRel(32|64) ptr val mem) => (LoweredAtomicStore(32|64) [0] ptr val mem)
832
833 (AtomicExchange(8|32|64) ...) => (LoweredAtomicExchange(8|32|64) ...)
834
835 (AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
836
837 (AtomicCompareAndSwap(32|64) ptr old new_ mem) => (LoweredAtomicCas(32|64) [1] ptr old new_ mem)
838 (AtomicCompareAndSwapRel32 ptr old new_ mem) => (LoweredAtomicCas32 [0] ptr old new_ mem)
839
840 (AtomicAnd(8|32) ...) => (LoweredAtomicAnd(8|32) ...)
841 (AtomicOr(8|32) ...) => (LoweredAtomicOr(8|32) ...)
842
843 (Slicemask <t> x) => (SRADconst (NEG <t> x) [63])
844 (ANDconst [1] z:(SRADconst [63] x)) && z.Uses == 1 => (SRDconst [63] x)
845
846 // Note that MOV??reg returns a 64-bit int, x is not necessarily that wide
847 // This may interact with other patterns in the future. (Compare with arm64)
848 (MOV(B|H|W)Zreg x:(MOVBZload _ _)) => x
849 (MOV(B|H|W)Zreg x:(MOVBZloadidx _ _ _)) => x
850 (MOV(H|W)Zreg x:(MOVHZload _ _)) => x
851 (MOV(H|W)Zreg x:(MOVHZloadidx _ _ _)) => x
852 (MOV(H|W)reg x:(MOVHload _ _)) => x
853 (MOV(H|W)reg x:(MOVHloadidx _ _ _)) => x
854 (MOV(WZ|W)reg x:(MOV(WZ|W)load _ _)) => x
855 (MOV(WZ|W)reg x:(MOV(WZ|W)loadidx _ _ _)) => x
856 (MOV(B|W)Zreg x:(Select0 (LoweredAtomicLoad(8|32) _ _))) => x
857
858 // don't extend if argument is already extended
859 (MOVBreg x:(Arg <t>)) && is8BitInt(t) && t.IsSigned() => x
860 (MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !t.IsSigned() => x
861 (MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && t.IsSigned() => x
862 (MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !t.IsSigned() => x
863 (MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && t.IsSigned() => x
864 (MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !t.IsSigned() => x
865
866 (MOVBZreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))])
867 (MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))])
868 (MOVHZreg (MOVDconst [c])) => (MOVDconst [int64(uint16(c))])
869 (MOVHreg (MOVDconst [c])) => (MOVDconst [int64(int16(c))])
870 (MOVWreg (MOVDconst [c])) => (MOVDconst [int64(int32(c))])
871 (MOVWZreg (MOVDconst [c])) => (MOVDconst [int64(uint32(c))])
872
873 // Implement clrsldi and clrslwi extended mnemonics as described in
874 // ISA 3.0 section C.8. AuxInt field contains values needed for
875 // the instructions, packed together since there is only one available.
876 (SLDconst [c] z:(MOVBZreg x)) && c < 8 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,56,63,64)] x)
877 (SLDconst [c] z:(MOVHZreg x)) && c < 16 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,48,63,64)] x)
878 (SLDconst [c] z:(MOVWZreg x)) && c < 32 && z.Uses == 1 => (CLRLSLDI [newPPC64ShiftAuxInt(c,32,63,64)] x)
879
880 (SLDconst [c] z:(ANDconst [d] x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c <= (64-getPPC64ShiftMaskLength(d)) => (CLRLSLDI [newPPC64ShiftAuxInt(c,64-getPPC64ShiftMaskLength(d),63,64)] x)
881 (SLDconst [c] z:(AND (MOVDconst [d]) x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(64-getPPC64ShiftMaskLength(d)) => (CLRLSLDI [newPPC64ShiftAuxInt(c,64-getPPC64ShiftMaskLength(d),63,64)] x)
882 // (x + x) << c → x << (c+1)
883 (SLDconst [c] (ADD x x)) && c < 63 => (SLDconst [c+1] x)
884 (SLWconst [c] z:(MOVBZreg x)) && z.Uses == 1 && c < 8 => (CLRLSLWI [newPPC64ShiftAuxInt(c,24,31,32)] x)
885 (SLWconst [c] z:(MOVHZreg x)) && z.Uses == 1 && c < 16 => (CLRLSLWI [newPPC64ShiftAuxInt(c,16,31,32)] x)
886 (SLWconst [c] z:(ANDconst [d] x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d)) => (CLRLSLWI [newPPC64ShiftAuxInt(c,32-getPPC64ShiftMaskLength(d),31,32)] x)
887 (SLWconst [c] z:(AND (MOVDconst [d]) x)) && z.Uses == 1 && isPPC64ValidShiftMask(d) && c<=(32-getPPC64ShiftMaskLength(d)) => (CLRLSLWI [newPPC64ShiftAuxInt(c,32-getPPC64ShiftMaskLength(d),31,32)] x)
888 // (x + x) << c → x << (c+1)
889 (SLWconst [c] (ADD x x)) && c < 31 => (SLWconst [c+1] x)
890 // special case for power9
891 (SL(W|D)const [c] z:(MOVWreg x)) && c < 32 && buildcfg.GOPPC64 >= 9 => (EXTSWSLconst [c] x)
892
893 // Lose widening ops fed to stores
894 (MOVBstore [off] {sym} ptr (MOV(B|BZ|H|HZ|W|WZ)reg x) mem) => (MOVBstore [off] {sym} ptr x mem)
895 (MOVHstore [off] {sym} ptr (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHstore [off] {sym} ptr x mem)
896 (MOVWstore [off] {sym} ptr (MOV(W|WZ)reg x) mem) => (MOVWstore [off] {sym} ptr x mem)
897 (MOVBstore [off] {sym} ptr (SRWconst (MOV(H|HZ)reg x) [c]) mem) && c <= 8 => (MOVBstore [off] {sym} ptr (SRWconst <typ.UInt32> x [c]) mem)
898 (MOVBstore [off] {sym} ptr (SRWconst (MOV(W|WZ)reg x) [c]) mem) && c <= 24 => (MOVBstore [off] {sym} ptr (SRWconst <typ.UInt32> x [c]) mem)
899 (MOVBstoreidx ptr idx (MOV(B|BZ|H|HZ|W|WZ)reg x) mem) => (MOVBstoreidx ptr idx x mem)
900 (MOVHstoreidx ptr idx (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHstoreidx ptr idx x mem)
901 (MOVWstoreidx ptr idx (MOV(W|WZ)reg x) mem) => (MOVWstoreidx ptr idx x mem)
902 (MOVBstoreidx ptr idx (SRWconst (MOV(H|HZ)reg x) [c]) mem) && c <= 8 => (MOVBstoreidx ptr idx (SRWconst <typ.UInt32> x [c]) mem)
903 (MOVBstoreidx ptr idx (SRWconst (MOV(W|WZ)reg x) [c]) mem) && c <= 24 => (MOVBstoreidx ptr idx (SRWconst <typ.UInt32> x [c]) mem)
904 (MOVHBRstore ptr (MOV(H|HZ|W|WZ)reg x) mem) => (MOVHBRstore ptr x mem)
905 (MOVWBRstore ptr (MOV(W|WZ)reg x) mem) => (MOVWBRstore ptr x mem)
906
907 // Lose W-widening ops fed to compare-W
908 (CMP(W|WU) x (MOV(W|WZ)reg y)) => (CMP(W|WU) x y)
909 (CMP(W|WU) (MOV(W|WZ)reg x) y) => (CMP(W|WU) x y)
910
911 (CMP x (MOVDconst [c])) && is16Bit(c) => (CMPconst x [c])
912 (CMP (MOVDconst [c]) y) && is16Bit(c) => (InvertFlags (CMPconst y [c]))
913 (CMPW x (MOVDconst [c])) && is16Bit(c) => (CMPWconst x [int32(c)])
914 (CMPW (MOVDconst [c]) y) && is16Bit(c) => (InvertFlags (CMPWconst y [int32(c)]))
915
916 (CMPU x (MOVDconst [c])) && isU16Bit(c) => (CMPUconst x [c])
917 (CMPU (MOVDconst [c]) y) && isU16Bit(c) => (InvertFlags (CMPUconst y [c]))
918 (CMPWU x (MOVDconst [c])) && isU16Bit(c) => (CMPWUconst x [int32(c)])
919 (CMPWU (MOVDconst [c]) y) && isU16Bit(c) => (InvertFlags (CMPWUconst y [int32(c)]))
920
921 // Canonicalize the order of arguments to comparisons - helps with CSE.
922 ((CMP|CMPW|CMPU|CMPWU) x y) && canonLessThan(x,y) => (InvertFlags ((CMP|CMPW|CMPU|CMPWU) y x))
923
924 // n is always a zero-extended uint16 value, so n & z is always a non-negative 32 or 64 bit value.
925 // Rewrite to a cmp int64(0) to lower into ANDCCconst in the latelower pass.
926 (CMP(W|U|WU)const [0] a:(ANDconst [n] z)) => (CMPconst [0] a)
927
928 // SETBC auxInt values 0=LT 1=GT 2=EQ Crbit==1 ? 1 : 0
929 // SETBCR auxInt values 0=LT 1=GT 2=EQ Crbit==1 ? 0 : 1
930 (Equal cmp) => (SETBC [2] cmp)
931 (NotEqual cmp) => (SETBCR [2] cmp)
932 (LessThan cmp) => (SETBC [0] cmp)
933 (FLessThan cmp) => (SETBC [0] cmp)
934 (FLessEqual cmp) => (OR (SETBC [2] cmp) (SETBC [0] cmp))
935 (GreaterEqual cmp) => (SETBCR [0] cmp)
936 (GreaterThan cmp) => (SETBC [1] cmp)
937 (FGreaterEqual cmp) => (OR (SETBC [2] cmp) (SETBC [1] cmp))
938 (FGreaterThan cmp) => (SETBC [1] cmp)
939 (LessEqual cmp) => (SETBCR [1] cmp)
940
941 (SETBC [0] (FlagLT)) => (MOVDconst [1])
942 (SETBC [0] (Flag(GT|EQ))) => (MOVDconst [0])
943 (SETBC [1] (FlagGT)) => (MOVDconst [1])
944 (SETBC [1] (Flag(LT|EQ))) => (MOVDconst [0])
945 (SETBC [2] (FlagEQ)) => (MOVDconst [1])
946 (SETBC [2] (Flag(LT|GT))) => (MOVDconst [0])
947
948 (SETBCR [0] (FlagLT)) => (MOVDconst [0])
949 (SETBCR [0] (Flag(GT|EQ))) => (MOVDconst [1])
950 (SETBCR [1] (FlagGT)) => (MOVDconst [0])
951 (SETBCR [1] (Flag(LT|EQ))) => (MOVDconst [1])
952 (SETBCR [2] (FlagEQ)) => (MOVDconst [0])
953 (SETBCR [2] (Flag(LT|GT))) => (MOVDconst [1])
954
955 (SETBC [0] (InvertFlags bool)) => (SETBC [1] bool)
956 (SETBC [1] (InvertFlags bool)) => (SETBC [0] bool)
957 (SETBC [2] (InvertFlags bool)) => (SETBC [2] bool)
958
959 (SETBCR [0] (InvertFlags bool)) => (SETBCR [1] bool)
960 (SETBCR [1] (InvertFlags bool)) => (SETBCR [0] bool)
961 (SETBCR [2] (InvertFlags bool)) => (SETBCR [2] bool)
962
963 // ISEL auxInt values 0=LT 1=GT 2=EQ arg2 ? arg0 : arg1
964 // ISEL auxInt values 4=GE 5=LE 6=NE !arg2 ? arg1 : arg0
965
966 (ISEL [2] x _ (FlagEQ)) => x
967 (ISEL [2] _ y (Flag(LT|GT))) => y
968
969 (ISEL [6] _ y (FlagEQ)) => y
970 (ISEL [6] x _ (Flag(LT|GT))) => x
971
972 (ISEL [0] _ y (Flag(EQ|GT))) => y
973 (ISEL [0] x _ (FlagLT)) => x
974
975 (ISEL [5] _ x (Flag(EQ|LT))) => x
976 (ISEL [5] y _ (FlagGT)) => y
977
978 (ISEL [1] _ y (Flag(EQ|LT))) => y
979 (ISEL [1] x _ (FlagGT)) => x
980
981 (ISEL [4] x _ (Flag(EQ|GT))) => x
982 (ISEL [4] _ y (FlagLT)) => y
983
984 (SETBC [n] (InvertFlags bool)) => (SETBCR [n] bool)
985 (SETBCR [n] (InvertFlags bool)) => (SETBC [n] bool)
986
987 (ISEL [n] x y (InvertFlags bool)) && n%4 == 0 => (ISEL [n+1] x y bool)
988 (ISEL [n] x y (InvertFlags bool)) && n%4 == 1 => (ISEL [n-1] x y bool)
989 (ISEL [n] x y (InvertFlags bool)) && n%4 == 2 => (ISEL [n] x y bool)
990 (XORconst [1] (SETBCR [n] cmp)) => (SETBC [n] cmp)
991 (XORconst [1] (SETBC [n] cmp)) => (SETBCR [n] cmp)
992
993 (SETBC [2] (CMPconst [0] a:(ANDconst [1] _))) => (XORconst [1] a)
994 (SETBCR [2] (CMPconst [0] a:(ANDconst [1] _))) => a
995
996 // Only CMPconst for these in case AND|OR|XOR result is > 32 bits
997 (SETBC [2] (CMPconst [0] a:(AND y z))) && a.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (ANDCC y z )))
998 (SETBCR [2] (CMPconst [0] a:(AND y z))) && a.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (ANDCC y z )))
999
1000 (SETBC [2] (CMPconst [0] o:(OR y z))) && o.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (ORCC y z )))
1001 (SETBCR [2] (CMPconst [0] o:(OR y z))) && o.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (ORCC y z )))
1002
1003 (SETBC [2] (CMPconst [0] a:(XOR y z))) && a.Uses == 1 => (SETBC [2] (Select1 <types.TypeFlags> (XORCC y z )))
1004 (SETBCR [2] (CMPconst [0] a:(XOR y z))) && a.Uses == 1 => (SETBCR [2] (Select1 <types.TypeFlags> (XORCC y z )))
1005
1006 // A particular pattern seen in cgo code:
1007 (AND (MOVDconst [c]) x:(MOVBZload _ _)) => (ANDconst [c&0xFF] x)
1008
1009 // floating point negative abs
1010 (FNEG (F(ABS|NABS) x)) => (F(NABS|ABS) x)
1011
1012 // floating-point fused multiply-add/sub
1013 (F(ADD|SUB) (FMUL x y) z) && x.Block.Func.useFMA(v) => (FM(ADD|SUB) x y z)
1014 (F(ADDS|SUBS) (FMULS x y) z) && x.Block.Func.useFMA(v) => (FM(ADDS|SUBS) x y z)
1015
1016 // Arch-specific inlining for small or disjoint runtime.memmove
1017 (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem)))))
1018 && sz >= 0
1019 && isSameCall(sym, "runtime.memmove")
1020 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
1021 && isInlinableMemmove(dst, src, sz, config)
1022 && clobber(s1, s2, s3, call)
1023 => (Move [sz] dst src mem)
1024
1025 // Match post-lowering calls, register version.
1026 (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem))
1027 && sz >= 0
1028 && isSameCall(sym, "runtime.memmove")
1029 && call.Uses == 1
1030 && isInlinableMemmove(dst, src, sz, config)
1031 && clobber(call)
1032 => (Move [sz] dst src mem)
1033
1034 // Prefetch instructions (TH specified using aux field)
1035 // For DCBT Ra,Rb,TH, A value of TH indicates:
1036 // 0, hint this cache line will be used soon. (PrefetchCache)
1037 // 16, hint this cache line will not be used for long. (PrefetchCacheStreamed)
1038 // See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/
1039 (PrefetchCache ptr mem) => (DCBT ptr mem [0])
1040 (PrefetchCacheStreamed ptr mem) => (DCBT ptr mem [16])
1041
1042 // Use byte reverse instructions on Power10
1043 (Bswap(16|32|64) x) && buildcfg.GOPPC64>=10 => (BR(H|W|D) x)
1044
1045 // Fold bit reversal into loads.
1046 (BR(W|H) x:(MOV(W|H)Zload [off] {sym} ptr mem)) && x.Uses == 1 => @x.Block (MOV(W|H)BRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1047 (BR(W|H) x:(MOV(W|H)Zloadidx ptr idx mem)) && x.Uses == 1 => @x.Block (MOV(W|H)BRloadidx ptr idx mem)
1048 (BRD x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 => @x.Block (MOVDBRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1049 (BRD x:(MOVDloadidx ptr idx mem)) && x.Uses == 1 => @x.Block (MOVDBRloadidx ptr idx mem)
1050
1051 // Fold bit reversal into stores.
1052 (MOV(D|W|H)store [off] {sym} ptr r:(BR(D|W|H) val) mem) && r.Uses == 1 => (MOV(D|W|H)BRstore (MOVDaddr <ptr.Type> [off] {sym} ptr) val mem)
1053 (MOV(D|W|H)storeidx ptr idx r:(BR(D|W|H) val) mem) && r.Uses == 1 => (MOV(D|W|H)BRstoreidx ptr idx val mem)
1054
1055 // GOPPC64<10 rules.
1056 // These Bswap operations should only be introduced by the memcombine pass in places where they can be folded into loads or stores.
1057 (Bswap(32|16) x:(MOV(W|H)Zload [off] {sym} ptr mem)) => @x.Block (MOV(W|H)BRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1058 (Bswap(32|16) x:(MOV(W|H)Zloadidx ptr idx mem)) => @x.Block (MOV(W|H)BRloadidx ptr idx mem)
1059 (Bswap64 x:(MOVDload [off] {sym} ptr mem)) => @x.Block (MOVDBRload (MOVDaddr <ptr.Type> [off] {sym} ptr) mem)
1060 (Bswap64 x:(MOVDloadidx ptr idx mem)) => @x.Block (MOVDBRloadidx ptr idx mem)
1061 (MOV(D|W|H)store [off] {sym} ptr (Bswap(64|32|16) val) mem) => (MOV(D|W|H)BRstore (MOVDaddr <ptr.Type> [off] {sym} ptr) val mem)
1062 (MOV(D|W|H)storeidx ptr idx (Bswap(64|32|16) val) mem) => (MOV(D|W|H)BRstoreidx ptr idx val mem)
1063
View as plain text