1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 // Lowering arithmetic
6 (Add(Ptr|64|32|16|8) ...) => (ADD ...)
7 (Add(64|32)F ...) => (FADD(D|S) ...)
8
9 (Sub(Ptr|64|32|16|8) ...) => (SUB ...)
10 (Sub(64|32)F ...) => (FSUB(D|S) ...)
11
12 (Mul64 ...) => (MUL ...)
13 (Mul64uhilo ...) => (LoweredMuluhilo ...)
14 (Mul64uover ...) => (LoweredMuluover ...)
15 (Mul(32|16|8) ...) => (MULW ...)
16 (Mul(64|32)F ...) => (FMUL(D|S) ...)
17
18 (Div(64|32)F ...) => (FDIV(D|S) ...)
19
20 (Div64 x y [false]) => (DIV x y)
21 (Div64u ...) => (DIVU ...)
22 (Div32 x y [false]) => (DIVW x y)
23 (Div32u ...) => (DIVUW ...)
24 (Div16 x y [false]) => (DIVW (SignExt16to32 x) (SignExt16to32 y))
25 (Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y))
26 (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y))
27 (Div8u x y) => (DIVUW (ZeroExt8to32 x) (ZeroExt8to32 y))
28
29 (Hmul64 ...) => (MULH ...)
30 (Hmul64u ...) => (MULHU ...)
31 (Hmul32 x y) => (SRAI [32] (MUL (SignExt32to64 x) (SignExt32to64 y)))
32 (Hmul32u x y) => (SRLI [32] (MUL (ZeroExt32to64 x) (ZeroExt32to64 y)))
33
34 (Select0 (Add64carry x y c)) => (ADD (ADD <typ.UInt64> x y) c)
35 (Select1 (Add64carry x y c)) =>
36 (OR (SLTU <typ.UInt64> s:(ADD <typ.UInt64> x y) x) (SLTU <typ.UInt64> (ADD <typ.UInt64> s c) s))
37
38 (Select0 (Sub64borrow x y c)) => (SUB (SUB <typ.UInt64> x y) c)
39 (Select1 (Sub64borrow x y c)) =>
40 (OR (SLTU <typ.UInt64> x s:(SUB <typ.UInt64> x y)) (SLTU <typ.UInt64> s (SUB <typ.UInt64> s c)))
41
42 (JumpTable idx) => (JUMPTABLE {ssa.MakeJumpTableSym(b)} idx (MOVaddr <typ.Uintptr> {ssa.MakeJumpTableSym(b)} (SB)))
43
44 // (x + y) / 2 => (x / 2) + (y / 2) + (x & y & 1)
45 (Avg64u <t> x y) => (ADD (ADD <t> (SRLI <t> [1] x) (SRLI <t> [1] y)) (ANDI <t> [1] (AND <t> x y)))
46
47 (Mod64 x y [false]) => (REM x y)
48 (Mod64u ...) => (REMU ...)
49 (Mod32 x y [false]) => (REMW x y)
50 (Mod32u ...) => (REMUW ...)
51 (Mod16 x y [false]) => (REMW (SignExt16to32 x) (SignExt16to32 y))
52 (Mod16u x y) => (REMUW (ZeroExt16to32 x) (ZeroExt16to32 y))
53 (Mod8 x y) => (REMW (SignExt8to32 x) (SignExt8to32 y))
54 (Mod8u x y) => (REMUW (ZeroExt8to32 x) (ZeroExt8to32 y))
55
56 (And(64|32|16|8) ...) => (AND ...)
57 (Or(64|32|16|8) ...) => (OR ...)
58 (Xor(64|32|16|8) ...) => (XOR ...)
59
60 (Neg(64|32|16|8) ...) => (NEG ...)
61 (Neg(64|32)F ...) => (FNEG(D|S) ...)
62
63 (Com(64|32|16|8) ...) => (NOT ...)
64
65 (Sqrt ...) => (FSQRTD ...)
66 (Sqrt32 ...) => (FSQRTS ...)
67
68 (Copysign ...) => (FSGNJD ...)
69
70 (Abs ...) => (FABSD ...)
71
72 (FMA ...) => (FMADDD ...)
73
74 (Min(64|32)F ...) => (LoweredFMIN(D|S) ...)
75 (Max(64|32)F ...) => (LoweredFMAX(D|S) ...)
76
77 // Sign and zero extension.
78
79 (SignExt8to16 ...) => (MOVBreg ...)
80 (SignExt8to32 ...) => (MOVBreg ...)
81 (SignExt8to64 ...) => (MOVBreg ...)
82 (SignExt16to32 ...) => (MOVHreg ...)
83 (SignExt16to64 ...) => (MOVHreg ...)
84 (SignExt32to64 ...) => (MOVWreg ...)
85
86 (ZeroExt8to16 ...) => (MOVBUreg ...)
87 (ZeroExt8to32 ...) => (MOVBUreg ...)
88 (ZeroExt8to64 ...) => (MOVBUreg ...)
89 (ZeroExt16to32 ...) => (MOVHUreg ...)
90 (ZeroExt16to64 ...) => (MOVHUreg ...)
91 (ZeroExt32to64 ...) => (MOVWUreg ...)
92
93 (Cvt32to32F ...) => (FCVTSW ...)
94 (Cvt32to64F ...) => (FCVTDW ...)
95 (Cvt64to32F ...) => (FCVTSL ...)
96 (Cvt64to64F ...) => (FCVTDL ...)
97
98 (Cvt32Fto32 ...) => (FCVTWS ...)
99 (Cvt32Fto64 ...) => (FCVTLS ...)
100 (Cvt64Fto32 ...) => (FCVTWD ...)
101 (Cvt64Fto64 ...) => (FCVTLD ...)
102
103 (Cvt32Fto64F ...) => (FCVTDS ...)
104 (Cvt64Fto32F ...) => (FCVTSD ...)
105
106 (CvtBoolToUint8 ...) => (Copy ...)
107
108 (Round(32|64)F ...) => (LoweredRound(32|64)F ...)
109
110 (Slicemask <t> x) => (SRAI [63] (NEG <t> x))
111
112 // Truncations
113 // We ignore the unused high parts of registers, so truncates are just copies.
114 (Trunc16to8 ...) => (Copy ...)
115 (Trunc32to8 ...) => (Copy ...)
116 (Trunc32to16 ...) => (Copy ...)
117 (Trunc64to8 ...) => (Copy ...)
118 (Trunc64to16 ...) => (Copy ...)
119 (Trunc64to32 ...) => (Copy ...)
120
121 // Shifts
122
123 // SLL only considers the bottom 6 bits of y, similarly SLLW only considers the
124 // bottom 5 bits of y. Ensure that the result is always zero if the shift exceeds
125 // the maximum value.
126 //
127 // Breaking down the operation:
128 //
129 // (SLL x y) generates x << (y & 63).
130 //
131 // If y < 64, this is the value we want. Otherwise, we want zero.
132 //
133 // So, we AND with -1 * uint64(y < 64), which is 0xfffff... if y < 64 and 0 otherwise.
134 (Lsh8x8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg8 <t> (SLTIU <t> [64] (ZeroExt8to64 y))))
135 (Lsh8x16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg8 <t> (SLTIU <t> [64] (ZeroExt16to64 y))))
136 (Lsh8x32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg8 <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
137 (Lsh8x64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg8 <t> (SLTIU <t> [64] y)))
138 (Lsh16x8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt8to64 y))))
139 (Lsh16x16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt16to64 y))))
140 (Lsh16x32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
141 (Lsh16x64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg16 <t> (SLTIU <t> [64] y)))
142 (Lsh32x8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLLW <t> x y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt8to64 y))))
143 (Lsh32x16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLLW <t> x y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt16to64 y))))
144 (Lsh32x32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLLW <t> x y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt32to64 y))))
145 (Lsh32x64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLLW <t> x y) (Neg32 <t> (SLTIU <t> [32] y)))
146 (Lsh64x8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg64 <t> (SLTIU <t> [64] (ZeroExt8to64 y))))
147 (Lsh64x16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg64 <t> (SLTIU <t> [64] (ZeroExt16to64 y))))
148 (Lsh64x32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg64 <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
149 (Lsh64x64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SLL <t> x y) (Neg64 <t> (SLTIU <t> [64] y)))
150
151 (Lsh8x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLL x y)
152 (Lsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLL x y)
153 (Lsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLLW x y)
154 (Lsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SLL x y)
155
156 // SRL only considers the bottom 6 bits of y, similarly SRLW only considers the
157 // bottom 5 bits of y. Ensure that the result is always zero if the shift exceeds
158 // the maximum value. See Lsh above for a detailed description.
159 (Rsh8Ux8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> (ZeroExt8to64 x) y) (Neg8 <t> (SLTIU <t> [64] (ZeroExt8to64 y))))
160 (Rsh8Ux16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> (ZeroExt8to64 x) y) (Neg8 <t> (SLTIU <t> [64] (ZeroExt16to64 y))))
161 (Rsh8Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> (ZeroExt8to64 x) y) (Neg8 <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
162 (Rsh8Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> (ZeroExt8to64 x) y) (Neg8 <t> (SLTIU <t> [64] y)))
163 (Rsh16Ux8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> (ZeroExt16to64 x) y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt8to64 y))))
164 (Rsh16Ux16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> (ZeroExt16to64 x) y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt16to64 y))))
165 (Rsh16Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> (ZeroExt16to64 x) y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
166 (Rsh16Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> (ZeroExt16to64 x) y) (Neg16 <t> (SLTIU <t> [64] y)))
167 (Rsh32Ux8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRLW <t> x y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt8to64 y))))
168 (Rsh32Ux16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRLW <t> x y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt16to64 y))))
169 (Rsh32Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRLW <t> x y) (Neg32 <t> (SLTIU <t> [32] (ZeroExt32to64 y))))
170 (Rsh32Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRLW <t> x y) (Neg32 <t> (SLTIU <t> [32] y)))
171 (Rsh64Ux8 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> x y) (Neg64 <t> (SLTIU <t> [64] (ZeroExt8to64 y))))
172 (Rsh64Ux16 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> x y) (Neg64 <t> (SLTIU <t> [64] (ZeroExt16to64 y))))
173 (Rsh64Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> x y) (Neg64 <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
174 (Rsh64Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (AND (SRL <t> x y) (Neg64 <t> (SLTIU <t> [64] y)))
175
176 (Rsh8Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRL (ZeroExt8to64 x) y)
177 (Rsh16Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRL (ZeroExt16to64 x) y)
178 (Rsh32Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRLW x y)
179 (Rsh64Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRL x y)
180
181 // SRA only considers the bottom 6 bits of y, similarly SRAW only considers the
182 // bottom 5 bits. If y is greater than the maximum value (either 63 or 31
183 // depending on the instruction), the result of the shift should be either 0
184 // or -1 based on the sign bit of x.
185 //
186 // We implement this by performing the max shift (-1) if y > the maximum value.
187 //
188 // We OR (uint64(y < 64) - 1) into y before passing it to SRA. This leaves
189 // us with -1 (0xffff...) if y >= 64. Similarly, we OR (uint64(y < 32) - 1) into y
190 // before passing it to SRAW.
191 //
192 // We don't need to sign-extend the OR result, as it will be at minimum 8 bits,
193 // more than the 5 or 6 bits SRAW and SRA care about.
194 (Rsh8x8 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> (SignExt8to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt8to64 y)))))
195 (Rsh8x16 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> (SignExt8to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt16to64 y)))))
196 (Rsh8x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> (SignExt8to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt32to64 y)))))
197 (Rsh8x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> (SignExt8to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] y))))
198 (Rsh16x8 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> (SignExt16to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt8to64 y)))))
199 (Rsh16x16 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> (SignExt16to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt16to64 y)))))
200 (Rsh16x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> (SignExt16to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt32to64 y)))))
201 (Rsh16x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> (SignExt16to64 x) (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] y))))
202 (Rsh32x8 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAW <t> x (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] (ZeroExt8to64 y)))))
203 (Rsh32x16 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAW <t> x (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] (ZeroExt16to64 y)))))
204 (Rsh32x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAW <t> x (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] (ZeroExt32to64 y)))))
205 (Rsh32x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRAW <t> x (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] y))))
206 (Rsh64x8 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> x (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt8to64 y)))))
207 (Rsh64x16 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> x (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt16to64 y)))))
208 (Rsh64x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> x (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] (ZeroExt32to64 y)))))
209 (Rsh64x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA <t> x (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [64] y))))
210
211 (Rsh8x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRA (SignExt8to64 x) y)
212 (Rsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRA (SignExt16to64 x) y)
213 (Rsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRAW x y)
214 (Rsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SRA x y)
215
216 // Rotates.
217 (RotateLeft8 <t> x y) => (OR (SLL <t> x (ANDI [7] <y.Type> y)) (SRL <t> (ZeroExt8to64 x) (ANDI [7] <y.Type> (NEG <y.Type> y))))
218 (RotateLeft16 <t> x y) => (OR (SLL <t> x (ANDI [15] <y.Type> y)) (SRL <t> (ZeroExt16to64 x) (ANDI [15] <y.Type> (NEG <y.Type> y))))
219 (RotateLeft32 ...) => (ROLW ...)
220 (RotateLeft64 ...) => (ROL ...)
221
222 // Count trailing zeros (note that these will only be emitted for rva22u64 and above).
223 (Ctz(64|32|16|8)NonZero ...) => (Ctz64 ...)
224 (Ctz64 ...) => (CTZ ...)
225 (Ctz32 ...) => (CTZW ...)
226 (Ctz16 x) => (CTZW (ORI <typ.UInt32> [1<<16] x))
227 (Ctz8 x) => (CTZW (ORI <typ.UInt32> [1<<8] x))
228
229 // Bit length (note that these will only be emitted for rva22u64 and above).
230 (BitLen64 <t> x) => (SUB (MOVDconst [64]) (CLZ <t> x))
231 (BitLen32 <t> x) => (SUB (MOVDconst [32]) (CLZW <t> x))
232 (BitLen16 x) => (BitLen64 (ZeroExt16to64 x))
233 (BitLen8 x) => (BitLen64 (ZeroExt8to64 x))
234
235 // Byte swap (note that these will only be emitted for rva22u64 and above).
236 (Bswap64 ...) => (REV8 ...)
237 (Bswap32 <t> x) => (SRLI [32] (REV8 <t> x))
238 (Bswap16 <t> x) => (SRLI [48] (REV8 <t> x))
239
240 // Population count (note that these will be emitted with guards for rva20u64).
241 (PopCount64 ...) => (CPOP ...)
242 (PopCount32 ...) => (CPOPW ...)
243 (PopCount16 x) => (CPOP (ZeroExt16to64 x))
244 (PopCount8 x) => (CPOP (ZeroExt8to64 x))
245
246 (Less64 ...) => (SLT ...)
247 (Less32 x y) => (SLT (SignExt32to64 x) (SignExt32to64 y))
248 (Less16 x y) => (SLT (SignExt16to64 x) (SignExt16to64 y))
249 (Less8 x y) => (SLT (SignExt8to64 x) (SignExt8to64 y))
250 (Less64U ...) => (SLTU ...)
251 (Less32U x y) => (SLTU (ZeroExt32to64 x) (ZeroExt32to64 y))
252 (Less16U x y) => (SLTU (ZeroExt16to64 x) (ZeroExt16to64 y))
253 (Less8U x y) => (SLTU (ZeroExt8to64 x) (ZeroExt8to64 y))
254 (Less(64|32)F ...) => (FLT(D|S) ...)
255
256 // Convert x <= y to !(y > x).
257 (Leq(64|32|16|8) x y) => (Not (Less(64|32|16|8) y x))
258 (Leq(64|32|16|8)U x y) => (Not (Less(64|32|16|8)U y x))
259 (Leq(64|32)F ...) => (FLE(D|S) ...)
260
261 (EqPtr x y) => (SEQZ (SUB <typ.Uintptr> x y))
262 (Eq64 x y) => (SEQZ (SUB <x.Type> x y))
263 (Eq32 x y) && x.Type.IsSigned() => (SEQZ (SUB <x.Type> (SignExt32to64 x) (SignExt32to64 y)))
264 (Eq32 x y) && !x.Type.IsSigned() => (SEQZ (SUB <x.Type> (ZeroExt32to64 x) (ZeroExt32to64 y)))
265 (Eq16 x y) => (SEQZ (SUB <x.Type> (ZeroExt16to64 x) (ZeroExt16to64 y)))
266 (Eq8 x y) => (SEQZ (SUB <x.Type> (ZeroExt8to64 x) (ZeroExt8to64 y)))
267 (Eq(64|32)F ...) => (FEQ(D|S) ...)
268
269 (NeqPtr x y) => (Not (EqPtr x y))
270 (Neq64 x y) => (Not (Eq64 x y))
271 (Neq32 x y) => (Not (Eq32 x y))
272 (Neq16 x y) => (Not (Eq16 x y))
273 (Neq8 x y) => (Not (Eq8 x y))
274 (Neq(64|32)F ...) => (FNE(D|S) ...)
275
276 // Loads
277 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
278 (Load <t> ptr mem) && ( ssa.Is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
279 (Load <t> ptr mem) && ( ssa.Is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
280 (Load <t> ptr mem) && (ssa.Is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
281 (Load <t> ptr mem) && (ssa.Is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
282 (Load <t> ptr mem) && (ssa.Is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
283 (Load <t> ptr mem) && (ssa.Is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
284 (Load <t> ptr mem) && (ssa.Is64BitInt(t) ||ssa.IsPtr(t)) => (MOVDload ptr mem)
285 (Load <t> ptr mem) && ssa.Is32BitFloat(t) => (FMOVWload ptr mem)
286 (Load <t> ptr mem) && ssa.Is64BitFloat(t) => (FMOVDload ptr mem)
287
288 // Stores
289 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
290 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
291 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
292 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
293 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVWstore ptr val mem)
294 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
295
296 // We need to fold MOVaddr into the LD/MOVDstore ops so that the live variable analysis
297 // knows what variables are being read/written by the ops.
298 (MOV(B|BU|H|HU|W|WU|D)load [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) &&
299 ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) &&
300 (base.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
301 (MOV(B|BU|H|HU|W|WU|D)load [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
302
303 (FMOV(W|D)load [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) &&
304 ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) &&
305 (base.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
306 (FMOV(W|D)load [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
307
308 (MOV(B|H|W|D)store [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) &&
309 ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) &&
310 (base.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
311 (MOV(B|H|W|D)store [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
312
313 (MOV(B|H|W|D)storezero [off1] {sym1} (MOVaddr [off2] {sym2} base) mem) &&
314 ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2)) &&
315 (base.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
316 (MOV(B|H|W|D)storezero [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
317
318 (FMOV(W|D)store [off1] {sym1} (MOVaddr [off2] {sym2} base) val mem) &&
319 ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) &&
320 (base.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
321 (FMOV(W|D)store [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
322
323 (MOV(B|BU|H|HU|W|WU|D)load [off1] {sym} (ADDI [off2] base) mem) && ssa.Is32Bit(int64(off1)+off2) =>
324 (MOV(B|BU|H|HU|W|WU|D)load [off1+int32(off2)] {sym} base mem)
325
326 (FMOV(W|D)load [off1] {sym} (ADDI [off2] base) mem) && ssa.Is32Bit(int64(off1)+off2) =>
327 (FMOV(W|D)load [off1+int32(off2)] {sym} base mem)
328
329 (MOV(B|H|W|D)store [off1] {sym} (ADDI [off2] base) val mem) && ssa.Is32Bit(int64(off1)+off2) =>
330 (MOV(B|H|W|D)store [off1+int32(off2)] {sym} base val mem)
331
332 (MOV(B|H|W|D)storezero [off1] {sym} (ADDI [off2] base) mem) && ssa.Is32Bit(int64(off1)+off2) =>
333 (MOV(B|H|W|D)storezero [off1+int32(off2)] {sym} base mem)
334
335 (FMOV(W|D)store [off1] {sym} (ADDI [off2] base) val mem) && ssa.Is32Bit(int64(off1)+off2) =>
336 (FMOV(W|D)store [off1+int32(off2)] {sym} base val mem)
337
338 // Similarly, fold ADDI into MOVaddr to avoid confusing live variable analysis
339 // with OffPtr -> ADDI.
340 (ADDI [c] (MOVaddr [d] {s} x)) && ssa.Is32Bit(c+int64(d)) => (MOVaddr [int32(c)+d] {s} x)
341
342 // Small zeroing
343 (Zero [0] _ mem) => mem
344 (Zero [1] ptr mem) => (MOVBstore ptr (MOVDconst [0]) mem)
345 (Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 =>
346 (MOVHstore ptr (MOVDconst [0]) mem)
347 (Zero [2] ptr mem) =>
348 (MOVBstore [1] ptr (MOVDconst [0])
349 (MOVBstore ptr (MOVDconst [0]) mem))
350 (Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 =>
351 (MOVWstore ptr (MOVDconst [0]) mem)
352 (Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 =>
353 (MOVHstore [2] ptr (MOVDconst [0])
354 (MOVHstore ptr (MOVDconst [0]) mem))
355 (Zero [4] ptr mem) =>
356 (MOVBstore [3] ptr (MOVDconst [0])
357 (MOVBstore [2] ptr (MOVDconst [0])
358 (MOVBstore [1] ptr (MOVDconst [0])
359 (MOVBstore ptr (MOVDconst [0]) mem))))
360 (Zero [8] {t} ptr mem) && t.Alignment()%8 == 0 =>
361 (MOVDstore ptr (MOVDconst [0]) mem)
362 (Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 =>
363 (MOVWstore [4] ptr (MOVDconst [0])
364 (MOVWstore ptr (MOVDconst [0]) mem))
365 (Zero [8] {t} ptr mem) && t.Alignment()%2 == 0 =>
366 (MOVHstore [6] ptr (MOVDconst [0])
367 (MOVHstore [4] ptr (MOVDconst [0])
368 (MOVHstore [2] ptr (MOVDconst [0])
369 (MOVHstore ptr (MOVDconst [0]) mem))))
370
371 (Zero [3] ptr mem) =>
372 (MOVBstore [2] ptr (MOVDconst [0])
373 (MOVBstore [1] ptr (MOVDconst [0])
374 (MOVBstore ptr (MOVDconst [0]) mem)))
375 (Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 =>
376 (MOVHstore [4] ptr (MOVDconst [0])
377 (MOVHstore [2] ptr (MOVDconst [0])
378 (MOVHstore ptr (MOVDconst [0]) mem)))
379
380 // Unroll zeroing in medium size (at most 192 bytes i.e. 3 cachelines)
381 (Zero [s] {t} ptr mem) && s <= 24*ssa.MoveSize(t.Alignment(), config) =>
382 (LoweredZero [s] {t.Alignment()} ptr mem)
383
384 // Generic zeroing uses a loop
385 (Zero [s] {t} ptr mem) && s > 24*ssa.MoveSize(t.Alignment(), config) =>
386 (LoweredZeroLoop [s] {t.Alignment()} ptr mem)
387
388 // Checks
389 (IsNonNil ...) => (SNEZ ...)
390 (IsInBounds ...) => (Less64U ...)
391 (IsSliceInBounds ...) => (Leq64U ...)
392
393 // Trivial lowering
394 (NilCheck ...) => (LoweredNilCheck ...)
395 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
396 (GetCallerSP ...) => (LoweredGetCallerSP ...)
397 (GetCallerPC ...) => (LoweredGetCallerPC ...)
398
399 // Write barrier.
400 (WB ...) => (LoweredWB ...)
401
402 // Publication barrier as intrinsic
403 (PubBarrier ...) => (LoweredPubBarrier ...)
404
405 (PanicBounds ...) => (LoweredPanicBoundsRR ...)
406 (LoweredPanicBoundsRR [kind] x (MOVDconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {ssa.PanicBoundsC{C:c}} mem)
407 (LoweredPanicBoundsRR [kind] (MOVDconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {ssa.PanicBoundsC{C:c}} y mem)
408 (LoweredPanicBoundsRC [kind] {p} (MOVDconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:c, Cy:p.C}} mem)
409 (LoweredPanicBoundsCR [kind] {p} (MOVDconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:p.C, Cy:c}} mem)
410
411 // Small moves
412 (Move [0] _ _ mem) => mem
413 (Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
414 (Move [2] {t} dst src mem) && t.Alignment()%2 == 0 =>
415 (MOVHstore dst (MOVHload src mem) mem)
416 (Move [2] dst src mem) =>
417 (MOVBstore [1] dst (MOVBload [1] src mem)
418 (MOVBstore dst (MOVBload src mem) mem))
419 (Move [4] {t} dst src mem) && t.Alignment()%4 == 0 =>
420 (MOVWstore dst (MOVWload src mem) mem)
421 (Move [4] {t} dst src mem) && t.Alignment()%2 == 0 =>
422 (MOVHstore [2] dst (MOVHload [2] src mem)
423 (MOVHstore dst (MOVHload src mem) mem))
424 (Move [4] dst src mem) =>
425 (MOVBstore [3] dst (MOVBload [3] src mem)
426 (MOVBstore [2] dst (MOVBload [2] src mem)
427 (MOVBstore [1] dst (MOVBload [1] src mem)
428 (MOVBstore dst (MOVBload src mem) mem))))
429 (Move [8] {t} dst src mem) && t.Alignment()%8 == 0 =>
430 (MOVDstore dst (MOVDload src mem) mem)
431 (Move [8] {t} dst src mem) && t.Alignment()%4 == 0 =>
432 (MOVWstore [4] dst (MOVWload [4] src mem)
433 (MOVWstore dst (MOVWload src mem) mem))
434 (Move [8] {t} dst src mem) && t.Alignment()%2 == 0 =>
435 (MOVHstore [6] dst (MOVHload [6] src mem)
436 (MOVHstore [4] dst (MOVHload [4] src mem)
437 (MOVHstore [2] dst (MOVHload [2] src mem)
438 (MOVHstore dst (MOVHload src mem) mem))))
439
440 (Move [3] dst src mem) =>
441 (MOVBstore [2] dst (MOVBload [2] src mem)
442 (MOVBstore [1] dst (MOVBload [1] src mem)
443 (MOVBstore dst (MOVBload src mem) mem)))
444 (Move [6] {t} dst src mem) && t.Alignment()%2 == 0 =>
445 (MOVHstore [4] dst (MOVHload [4] src mem)
446 (MOVHstore [2] dst (MOVHload [2] src mem)
447 (MOVHstore dst (MOVHload src mem) mem)))
448
449 // Generic move
450 (Move [s] {t} dst src mem) && s > 0 && s <= 3*8*ssa.MoveSize(t.Alignment(), config)
451 && ssa.LogLargeCopyValue(v, s) =>
452 (LoweredMove [s] {t.Alignment()} dst src mem)
453
454 // Generic move uses a loop
455 (Move [s] {t} dst src mem) && s > 3*8*ssa.MoveSize(t.Alignment(), config)
456 && ssa.LogLargeCopyValue(v, s) =>
457 (LoweredMoveLoop [s] {t.Alignment()} dst src mem)
458
459 // Boolean ops; 0=false, 1=true
460 (AndB ...) => (AND ...)
461 (OrB ...) => (OR ...)
462 (EqB x y) => (SEQZ (SUB <typ.Bool> x y))
463 (NeqB x y) => (SNEZ (SUB <typ.Bool> x y))
464 (Not ...) => (SEQZ ...)
465
466 // Lowering pointer arithmetic
467 // TODO: Special handling for SP offsets, like ARM
468 (OffPtr [off] ptr:(SP)) && ssa.Is32Bit(off) => (MOVaddr [int32(off)] ptr)
469 (OffPtr [off] ptr) && ssa.Is32Bit(off) => (ADDI [off] ptr)
470 (OffPtr [off] ptr) => (ADD (MOVDconst [off]) ptr)
471
472 (Const(64|32|16|8) [val]) => (MOVDconst [int64(val)])
473 (Const(64|32)F ...) => (FMOV(D|F)const ...)
474 (ConstNil) => (MOVDconst [0])
475 (ConstBool [val]) => (MOVDconst [int64(ssa.B2i(val))])
476
477 (Addr {sym} base) => (MOVaddr {sym} [0] base)
478 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVaddr {sym} (SPanchored base mem))
479 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVaddr {sym} base)
480
481 // Calls
482 (StaticCall ...) => (CALLstatic ...)
483 (ClosureCall ...) => (CALLclosure ...)
484 (InterCall ...) => (CALLinter ...)
485 (TailCall ...) => (CALLtail ...)
486 (TailCallInter ...) => (CALLtailinter ...)
487
488 // Atomic Intrinsics
489 (AtomicLoad(Ptr|64|32|8) ...) => (LoweredAtomicLoad(64|64|32|8) ...)
490 (AtomicStore(PtrNoWB|64|32|8) ...) => (LoweredAtomicStore(64|64|32|8) ...)
491 (AtomicAdd(64|32) ...) => (LoweredAtomicAdd(64|32) ...)
492
493 // AtomicAnd8(ptr,val) => LoweredAtomicAnd32(ptr&^3, ^((uint8(val) ^ 0xff) << ((ptr & 3) * 8)))
494 (AtomicAnd8 ptr val mem) =>
495 (LoweredAtomicAnd32 (ANDI <typ.Uintptr> [^3] ptr)
496 (NOT <typ.UInt32> (SLL <typ.UInt32> (XORI <typ.UInt32> [0xff] (ZeroExt8to32 val))
497 (SLLI <typ.UInt64> [3] (ANDI <typ.UInt64> [3] ptr)))) mem)
498
499 (AtomicAnd32 ...) => (LoweredAtomicAnd32 ...)
500
501 (AtomicAnd32value ...) => (LoweredAtomicAnd32value ...)
502 (AtomicAnd64value ...) => (LoweredAtomicAnd64value ...)
503 (AtomicOr32value ...) => (LoweredAtomicOr32value ...)
504 (AtomicOr64value ...) => (LoweredAtomicOr64value ...)
505
506 (AtomicCompareAndSwap32 ptr old new mem) => (LoweredAtomicCas32 ptr (SignExt32to64 old) new mem)
507 (AtomicCompareAndSwap64 ...) => (LoweredAtomicCas64 ...)
508
509 (AtomicExchange(64|32) ...) => (LoweredAtomicExchange(64|32) ...)
510
511 // AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3, uint32(val)<<((ptr&3)*8))
512 (AtomicOr8 ptr val mem) =>
513 (LoweredAtomicOr32 (ANDI <typ.Uintptr> [^3] ptr)
514 (SLL <typ.UInt32> (ZeroExt8to32 val)
515 (SLLI <typ.UInt64> [3] (ANDI <typ.UInt64> [3] ptr))) mem)
516
517 (AtomicOr32 ...) => (LoweredAtomicOr32 ...)
518
519 // Conditional branches
520 (If cond yes no) => (BNEZ (MOVBUreg <typ.UInt64> cond) yes no)
521
522 // Optimizations
523
524 // Absorb SEQZ/SNEZ into branch.
525 (BEQZ (SEQZ x) yes no) => (BNEZ x yes no)
526 (BEQZ (SNEZ x) yes no) => (BEQZ x yes no)
527 (BNEZ (SEQZ x) yes no) => (BEQZ x yes no)
528 (BNEZ (SNEZ x) yes no) => (BNEZ x yes no)
529
530 // Remove redundant NEG from BEQZ/BNEZ.
531 (BEQZ (NEG x) yes no) => (BEQZ x yes no)
532 (BNEZ (NEG x) yes no) => (BNEZ x yes no)
533
534 // Negate comparison with FNES/FNED.
535 (BEQZ (FNES <t> x y) yes no) => (BNEZ (FEQS <t> x y) yes no)
536 (BNEZ (FNES <t> x y) yes no) => (BEQZ (FEQS <t> x y) yes no)
537 (BEQZ (FNED <t> x y) yes no) => (BNEZ (FEQD <t> x y) yes no)
538 (BNEZ (FNED <t> x y) yes no) => (BEQZ (FEQD <t> x y) yes no)
539
540 // Convert BEQZ/BNEZ into more optimal branch conditions.
541 (BEQZ (SUB x y) yes no) => (BEQ x y yes no)
542 (BNEZ (SUB x y) yes no) => (BNE x y yes no)
543 (BEQZ (SLT x y) yes no) => (BGE x y yes no)
544 (BNEZ (SLT x y) yes no) => (BLT x y yes no)
545 (BEQZ (SLTU x y) yes no) => (BGEU x y yes no)
546 (BNEZ (SLTU x y) yes no) => (BLTU x y yes no)
547 (BEQZ (SLTI [x] y) yes no) => (BGE y (MOVDconst [x]) yes no)
548 (BNEZ (SLTI [x] y) yes no) => (BLT y (MOVDconst [x]) yes no)
549 (BEQZ (SLTIU [x] y) yes no) => (BGEU y (MOVDconst [x]) yes no)
550 (BNEZ (SLTIU [x] y) yes no) => (BLTU y (MOVDconst [x]) yes no)
551
552 // Convert branch with zero to more optimal branch zero.
553 (BEQ (MOVDconst [0]) cond yes no) => (BEQZ cond yes no)
554 (BEQ cond (MOVDconst [0]) yes no) => (BEQZ cond yes no)
555 (BNE (MOVDconst [0]) cond yes no) => (BNEZ cond yes no)
556 (BNE cond (MOVDconst [0]) yes no) => (BNEZ cond yes no)
557 (BLT (MOVDconst [0]) cond yes no) => (BGTZ cond yes no)
558 (BLT cond (MOVDconst [0]) yes no) => (BLTZ cond yes no)
559 (BLTU (MOVDconst [0]) cond yes no) => (BNEZ cond yes no)
560 (BGE (MOVDconst [0]) cond yes no) => (BLEZ cond yes no)
561 (BGE cond (MOVDconst [0]) yes no) => (BGEZ cond yes no)
562 (BGEU (MOVDconst [0]) cond yes no) => (BEQZ cond yes no)
563
564 // Remove redundant NEG from SEQZ/SNEZ.
565 (SEQZ (NEG x)) => (SEQZ x)
566 (SNEZ (NEG x)) => (SNEZ x)
567
568 // Remove redundant SEQZ/SNEZ.
569 (SEQZ (SEQZ x)) => (SNEZ x)
570 (SEQZ (SNEZ x)) => (SEQZ x)
571 (SNEZ (SEQZ x)) => (SEQZ x)
572 (SNEZ (SNEZ x)) => (SNEZ x)
573
574 // Remove redundant SNEZ from bit test.
575 (SNEZ x:(ANDI [1] _)) => x
576
577 // Store zero.
578 (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem)
579 (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem)
580 (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem)
581 (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVDstorezero [off] {sym} ptr mem)
582
583 // Boolean ops are already extended.
584 (MOVBUreg x:((FLES|FLTS|FEQS|FNES) _ _)) => x
585 (MOVBUreg x:((FLED|FLTD|FEQD|FNED) _ _)) => x
586 (MOVBUreg x:((SEQZ|SNEZ) _)) => x
587 (MOVBUreg x:((SLT|SLTU) _ _)) => x
588
589 // Avoid extending when already sufficiently masked.
590 (MOVBreg x:(ANDI [c] y)) && c >= 0 && int64(int8(c)) == c => x
591 (MOVHreg x:(ANDI [c] y)) && c >= 0 && int64(int16(c)) == c => x
592 (MOVWreg x:(ANDI [c] y)) && c >= 0 && int64(int32(c)) == c => x
593 (MOVBUreg x:(ANDI [c] y)) && c >= 0 && int64(uint8(c)) == c => x
594 (MOVHUreg x:(ANDI [c] y)) && c >= 0 && int64(uint16(c)) == c => x
595 (MOVWUreg x:(ANDI [c] y)) && c >= 0 && int64(uint32(c)) == c => x
596
597 // Combine masking and zero extension.
598 (MOVBUreg (ANDI [c] x)) && c < 0 => (ANDI [int64(uint8(c))] x)
599 (MOVHUreg (ANDI [c] x)) && c < 0 => (ANDI [int64(uint16(c))] x)
600 (MOVWUreg (ANDI [c] x)) && c < 0 => (AND (MOVDconst [int64(uint32(c))]) x)
601
602 // Combine negation and sign extension.
603 (MOVWreg (NEG x)) => (NEGW x)
604
605 // Avoid extending when already sufficiently shifted.
606 (MOVBUreg x:(SRLI [c] y)) && c >= 56 => x
607 (MOVHUreg x:(SRLI [c] y)) && c >= 48 => x
608 (MOVWUreg x:(SRLI [c] y)) && c >= 32 => x
609 (MOVBUreg x:(SRLIW [c] y)) && c >= 24 => x
610 (MOVHUreg x:(SRLIW [c] y)) && c >= 16 => x
611 (MOVWUreg x:(SRLIW [c] y)) => x
612
613 // Avoid sign/zero extension for consts.
614 (MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))])
615 (MOVHreg (MOVDconst [c])) => (MOVDconst [int64(int16(c))])
616 (MOVWreg (MOVDconst [c])) => (MOVDconst [int64(int32(c))])
617 (MOVBUreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))])
618 (MOVHUreg (MOVDconst [c])) => (MOVDconst [int64(uint16(c))])
619 (MOVWUreg (MOVDconst [c])) => (MOVDconst [int64(uint32(c))])
620
621 // Avoid sign/zero extension after properly typed load.
622 (MOVBreg x:(MOVBload _ _)) => (MOVDreg x)
623 (MOVHreg x:(MOVBload _ _)) => (MOVDreg x)
624 (MOVHreg x:(MOVBUload _ _)) => (MOVDreg x)
625 (MOVHreg x:(MOVHload _ _)) => (MOVDreg x)
626 (MOVWreg x:(MOVBload _ _)) => (MOVDreg x)
627 (MOVWreg x:(MOVBUload _ _)) => (MOVDreg x)
628 (MOVWreg x:(MOVHload _ _)) => (MOVDreg x)
629 (MOVWreg x:(MOVHUload _ _)) => (MOVDreg x)
630 (MOVWreg x:(MOVWload _ _)) => (MOVDreg x)
631 (MOVBUreg x:(MOVBUload _ _)) => (MOVDreg x)
632 (MOVHUreg x:(MOVBUload _ _)) => (MOVDreg x)
633 (MOVHUreg x:(MOVHUload _ _)) => (MOVDreg x)
634 (MOVWUreg x:(MOVBUload _ _)) => (MOVDreg x)
635 (MOVWUreg x:(MOVHUload _ _)) => (MOVDreg x)
636 (MOVWUreg x:(MOVWUload _ _)) => (MOVDreg x)
637
638 // Avoid zero extension after properly typed atomic operation.
639 (MOVBUreg x:(Select0 (LoweredAtomicLoad8 _ _))) => (MOVDreg x)
640 (MOVBUreg x:(Select0 (LoweredAtomicCas32 _ _ _ _))) => (MOVDreg x)
641 (MOVBUreg x:(Select0 (LoweredAtomicCas64 _ _ _ _))) => (MOVDreg x)
642
643 // Avoid sign extension after word arithmetic.
644 // Careful to not omit the sign extension in cases where regalloc
645 // might restore without it, see issue 80577.
646 (MOVWreg x:(ADDIW _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
647 (MOVWreg x:(SUBW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
648 (MOVWreg x:(NEGW _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
649 (MOVWreg x:(MULW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
650 (MOVWreg x:(DIVW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
651 (MOVWreg x:(DIVUW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
652 (MOVWreg x:(REMW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
653 (MOVWreg x:(REMUW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
654 (MOVWreg x:(ROLW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
655 (MOVWreg x:(RORW _ _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
656 (MOVWreg x:(RORIW _)) && (x.Type.Size() == 8 || (x.Type.Size() == 4 && x.Type.IsSigned())) => (MOVDreg x)
657
658 // Fold double extensions.
659 (MOVBreg x:(MOVBreg _)) => (MOVDreg x)
660 (MOVHreg x:(MOVBreg _)) => (MOVDreg x)
661 (MOVHreg x:(MOVBUreg _)) => (MOVDreg x)
662 (MOVHreg x:(MOVHreg _)) => (MOVDreg x)
663 (MOVWreg x:(MOVBreg _)) => (MOVDreg x)
664 (MOVWreg x:(MOVBUreg _)) => (MOVDreg x)
665 (MOVWreg x:(MOVHreg _)) => (MOVDreg x)
666 (MOVWreg x:(MOVWreg _)) => (MOVDreg x)
667 (MOVBUreg x:(MOVBUreg _)) => (MOVDreg x)
668 (MOVHUreg x:(MOVBUreg _)) => (MOVDreg x)
669 (MOVHUreg x:(MOVHUreg _)) => (MOVDreg x)
670 (MOVWUreg x:(MOVBUreg _)) => (MOVDreg x)
671 (MOVWUreg x:(MOVHUreg _)) => (MOVDreg x)
672 (MOVWUreg x:(MOVWUreg _)) => (MOVDreg x)
673
674 // Do not extend before store.
675 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
676 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
677 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
678 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
679 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
680 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
681 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
682 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
683 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
684 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
685 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
686 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
687
688 // Replace extend after load with alternate load where possible.
689 (MOVBreg <t> x:(MOVBUload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <t> [off] {sym} ptr mem)
690 (MOVHreg <t> x:(MOVHUload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVHload <t> [off] {sym} ptr mem)
691 (MOVWreg <t> x:(MOVWUload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWload <t> [off] {sym} ptr mem)
692 (MOVBUreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBUload <t> [off] {sym} ptr mem)
693 (MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVHUload <t> [off] {sym} ptr mem)
694 (MOVWUreg <t> x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWUload <t> [off] {sym} ptr mem)
695
696 // Replace load from same location as preceding store with copy.
697 (MOV(D|W|H|B)load [off] {sym} ptr1 (MOV(D|W|H|B)store [off] {sym} ptr2 x _)) && ssa.IsSamePtr(ptr1, ptr2) => (MOV(D|W|H|B)reg x)
698 (MOV(W|H|B)Uload [off] {sym} ptr1 (MOV(W|H|B)store [off] {sym} ptr2 x _)) && ssa.IsSamePtr(ptr1, ptr2) => (MOV(W|H|B)Ureg x)
699 (MOVDload [off] {sym} ptr1 (FMOVDstore [off] {sym} ptr2 x _)) && ssa.IsSamePtr(ptr1, ptr2) => (FMVXD x)
700 (FMOVDload [off] {sym} ptr1 (MOVDstore [off] {sym} ptr2 x _)) && ssa.IsSamePtr(ptr1, ptr2) => (FMVDX x)
701 (MOVWload [off] {sym} ptr1 (FMOVWstore [off] {sym} ptr2 x _)) && ssa.IsSamePtr(ptr1, ptr2) => (FMVXS x)
702 (MOVWUload [off] {sym} ptr1 (FMOVWstore [off] {sym} ptr2 x _)) && ssa.IsSamePtr(ptr1, ptr2) => (MOVWUreg (FMVXS x))
703 (FMOVWload [off] {sym} ptr1 (MOVWstore [off] {sym} ptr2 x _)) && ssa.IsSamePtr(ptr1, ptr2) => (FMVSX x)
704
705 // A register move with a single use just reuses its argument's register, so
706 // use the argument directly instead of emitting a move. The value type is not
707 // needed after lowering.
708 (MOVDreg x) && x.Uses == 1 => x
709
710 // Avoid unnecessary zero and sign extension when right shifting.
711 (SRAI [x] (MOVWreg y)) && x >= 0 && x <= 31 => (SRAIW [x] y)
712 (SRLI [x] (MOVWUreg y)) && x >= 0 && x <= 31 => (SRLIW [x] y)
713
714 // Replace right shifts that exceed size of signed type.
715 (SRAI <t> [x] (MOVBreg y)) && x >= 8 => (SRAI [63] (SLLI <t> [56] y))
716 (SRAI <t> [x] (MOVHreg y)) && x >= 16 => (SRAI [63] (SLLI <t> [48] y))
717 (SRAI [x] (MOVWreg y)) && x >= 32 => (SRAIW [31] y)
718
719 // Eliminate right shifts that exceed size of unsigned type.
720 (SRLI [x] (MOVBUreg y)) && x >= 8 => (MOVDconst [0])
721 (SRLI [x] (MOVHUreg y)) && x >= 16 => (MOVDconst [0])
722 (SRLI [x] (MOVWUreg y)) && x >= 32 => (MOVDconst [0])
723
724 // Remove unnecessary masking with shifts.
725 (SLL x (ANDI [63] y)) => (SLL x y)
726 (SRL x (ANDI [63] y)) => (SRL x y)
727 (SRA x (ANDI [63] y)) => (SRA x y)
728 (SLLW x (ANDI [31] y)) => (SLLW x y)
729 (SRLW x (ANDI [31] y)) => (SRLW x y)
730 (SRAW x (ANDI [31] y)) => (SRAW x y)
731
732 // Fold constant into immediate instructions where possible.
733 (ADD (MOVDconst <t> [val]) x) && ssa.Is32Bit(val) && !t.IsPtr() => (ADDI [val] x)
734 (AND (MOVDconst [val]) x) && ssa.Is32Bit(val) => (ANDI [val] x)
735 (OR (MOVDconst [val]) x) && ssa.Is32Bit(val) => (ORI [val] x)
736 (XOR (MOVDconst [val]) x) && ssa.Is32Bit(val) => (XORI [val] x)
737 (ROL x (MOVDconst [val])) => (RORI [-val&63] x)
738 (ROLW x (MOVDconst [val])) => (RORIW [-val&31] x)
739 (ROR x (MOVDconst [val])) => (RORI [val&63] x)
740 (RORW x (MOVDconst [val])) => (RORIW [val&31] x)
741 (SLL x (MOVDconst [val])) => (SLLI [val&63] x)
742 (SLLW x (MOVDconst [val])) => (SLLIW [val&31] x)
743 (SRL x (MOVDconst [val])) => (SRLI [val&63] x)
744 (SRLW x (MOVDconst [val])) => (SRLIW [val&31] x)
745 (SRA x (MOVDconst [val])) => (SRAI [val&63] x)
746 (SRAW x (MOVDconst [val])) => (SRAIW [val&31] x)
747 (SLT x (MOVDconst [val])) && ssa.Is12Bit(val) => (SLTI [val] x)
748 (SLTU x (MOVDconst [val])) && ssa.Is12Bit(val) => (SLTIU [val] x)
749
750 // Replace negated left rotation with right rotation.
751 (ROL x (NEG y)) => (ROR x y)
752 (ROLW x (NEG y)) => (RORW x y)
753
754 // generic simplifications
755 (ADD x (NEG y)) => (SUB x y)
756 (SUB x (NEG y)) => (ADD x y)
757 (SUB x x) => (MOVDconst [0])
758 (AND x x) => x
759 (OR x x) => x
760 (ORN x x) => (MOVDconst [-1])
761 (XOR x x) => (MOVDconst [0])
762
763 // Convert const subtraction into ADDI with negative immediate, where possible.
764 (SUB x (MOVDconst [val])) && ssa.Is32Bit(-val) => (ADDI [-val] x)
765 (SUB <t> (MOVDconst [val]) y) && ssa.Is32Bit(-val) => (NEG (ADDI <t> [-val] y))
766
767 // Subtraction of zero.
768 (SUB x (MOVDconst [0])) => x
769 (SUBW x (MOVDconst [0])) => (ADDIW [0] x)
770
771 // Subtraction from zero.
772 (SUB (MOVDconst [0]) x) => (NEG x)
773 (SUBW (MOVDconst [0]) x) => (NEGW x)
774
775 // Fold negation into subtraction.
776 (NEG (SUB x y)) => (SUB y x)
777 (NEG <t> s:(ADDI [val] (SUB x y))) && s.Uses == 1 && ssa.Is32Bit(-val) => (ADDI [-val] (SUB <t> y x))
778
779 // Double negation.
780 (NEG (NEG x)) => x
781 (NEG <t> s:(ADDI [val] (NEG x))) && s.Uses == 1 && ssa.Is32Bit(-val) => (ADDI [-val] x)
782
783 // Addition of zero or two constants.
784 (ADDI [0] x) => x
785 (ADDI [x] (MOVDconst [y])) && ssa.Is32Bit(x + y) => (MOVDconst [x + y])
786
787 // ANDI with all zeros, all ones or two constants.
788 (ANDI [0] x) => (MOVDconst [0])
789 (ANDI [-1] x) => x
790 (ANDI [x] (MOVDconst [y])) => (MOVDconst [x & y])
791
792 // ORI with all zeroes, all ones or two constants.
793 (ORI [0] x) => x
794 (ORI [-1] x) => (MOVDconst [-1])
795 (ORI [x] (MOVDconst [y])) => (MOVDconst [x | y])
796
797 // Combine operations with immediate.
798 (ADDI [x] (ADDI [y] z)) && ssa.Is32Bit(x + y) => (ADDI [x + y] z)
799 (ANDI [x] (ANDI [y] z)) => (ANDI [x & y] z)
800 (ORI [x] (ORI [y] z)) => (ORI [x | y] z)
801
802 // Negation of a constant.
803 (NEG (MOVDconst [x])) => (MOVDconst [-x])
804 (NEGW (MOVDconst [x])) => (MOVDconst [int64(int32(-x))])
805
806 // Shift of a constant.
807 (SLLI [x] (MOVDconst [y])) && ssa.Is32Bit(y << uint32(x)) => (MOVDconst [y << uint32(x)])
808 (SRLI [x] (MOVDconst [y])) => (MOVDconst [int64(uint64(y) >> uint32(x))])
809 (SRAI [x] (MOVDconst [y])) => (MOVDconst [int64(y) >> uint32(x)])
810
811 // Combine doubling via addition with shift.
812 (SLLI <t> [c] (ADD x x)) && c < t.Size() * 8 - 1 => (SLLI [c+1] x)
813 (SLLI <t> [c] (ADD x x)) && c >= t.Size() * 8 - 1 => (MOVDconst [0])
814
815 // SLTI/SLTIU with constants.
816 (SLTI [x] (MOVDconst [y])) => (MOVDconst [ssa.B2i(int64(y) < int64(x))])
817 (SLTIU [x] (MOVDconst [y])) => (MOVDconst [ssa.B2i(uint64(y) < uint64(x))])
818
819 // SLTI/SLTIU with known outcomes.
820 (SLTI [x] (ANDI [y] _)) && y >= 0 && int64(y) < int64(x) => (MOVDconst [1])
821 (SLTIU [x] (ANDI [y] _)) && y >= 0 && uint64(y) < uint64(x) => (MOVDconst [1])
822 (SLTIU [x] (ORI [y] _)) && y >= 0 && uint64(y) >= uint64(x) => (MOVDconst [0])
823
824 // SLT/SLTU with known outcomes.
825 (SLT x x) => (MOVDconst [0])
826 (SLTU x x) => (MOVDconst [0])
827
828 // Deadcode for LoweredMuluhilo
829 (Select0 m:(LoweredMuluhilo x y)) && m.Uses == 1 => (MULHU x y)
830 (Select1 m:(LoweredMuluhilo x y)) && m.Uses == 1 => (MUL x y)
831
832 // Optimise bit tests with register shift values.
833 (S(EQ|NE)Z a:(AND (SLL (MOVDconst [1]) x) y)) && a.Uses == 1 => (S(EQ|NE)Z (ANDI <typ.UInt64> [1] (SRL <typ.UInt64> y x)))
834 (B(EQ|NE)Z a:(AND (SLL (MOVDconst [1]) x) y)) && a.Uses == 1 => (B(EQ|NE)Z (ANDI <typ.UInt64> [1] (SRL <typ.UInt64> y x)))
835 (S(EQ|NE)Z a:(MOVWUreg (AND (SLLW (MOVDconst [1]) x) y))) && a.Uses == 1 => (S(EQ|NE)Z (ANDI <typ.UInt64> [1] (SRLW <typ.UInt64> y x)))
836 (B(EQ|NE)Z a:(MOVWUreg (AND (SLLW (MOVDconst [1]) x) y))) && a.Uses == 1 => (B(EQ|NE)Z (ANDI <typ.UInt64> [1] (SRLW <typ.UInt64> y x)))
837
838 // Optimise bit tests with larger than 12 bit values.
839 (S(EQ|NE)Z a:(ANDI [x] y)) && ssa.IsPowerOfTwo(uint64(x)) && !ssa.Is12Bit(x) && a.Uses == 1 => (S(EQ|NE)Z (ANDI <typ.UInt64> [1] (SRLI <typ.UInt64> [ssa.Log64u(uint64(x))] y)))
840 (B(EQ|NE)Z a:(ANDI [x] y) yes no) && ssa.IsPowerOfTwo(uint64(x)) && !ssa.Is12Bit(x) && a.Uses == 1 => (B(EQ|NE)Z (ANDI <typ.UInt64> [1] (SRLI <typ.UInt64> [ssa.Log64u(uint64(x))] y)) yes no)
841 (S(EQ|NE)Z a:(AND (MOVDconst [x]) y)) && ssa.IsPowerOfTwo(uint64(x)) && !ssa.Is12Bit(x) && a.Uses == 1 => (S(EQ|NE)Z (ANDI <typ.UInt64> [1] (SRLI <typ.UInt64> [ssa.Log64u(uint64(x))] y)))
842 (B(EQ|NE)Z a:(AND (MOVDconst [x]) y) yes no) && ssa.IsPowerOfTwo(uint64(x)) && !ssa.Is12Bit(x) && a.Uses == 1 => (B(EQ|NE)Z (ANDI <typ.UInt64> [1] (SRLI <typ.UInt64> [ssa.Log64u(uint64(x))] y)) yes no)
843
844 // Combine small shifts into bit tests.
845 (S(EQ|NE)Z a:(ANDI [x] (SRLI [y] z))) && ssa.IsPowerOfTwo(uint64(x)) && ssa.Is12Bit(x << y) && a.Uses == 1 => (S(EQ|NE)Z (ANDI <typ.UInt64> [x << y] z))
846 (B(EQ|NE)Z a:(ANDI [x] (SRLI [y] z)) yes no) && ssa.IsPowerOfTwo(uint64(x)) && ssa.Is12Bit(x << y) && a.Uses == 1 => (B(EQ|NE)Z (ANDI <typ.UInt64> [x << y] z) yes no)
847
848 // Fuse multiply with addition/subtraction.
849 (FADD(S|D) a (FMUL(S|D) x y)) && a.Block.Func.UseFMA(v) => (FMADD(S|D) x y a)
850 (FSUB(S|D) a (FMUL(S|D) x y)) && a.Block.Func.UseFMA(v) => (FNMSUB(S|D) x y a)
851 (FSUB(S|D) (FMUL(S|D) x y) a) && a.Block.Func.UseFMA(v) => (FMSUB(S|D) x y a)
852
853 // Merge negation into fused multiply-add and multiply-subtract.
854 //
855 // Key:
856 //
857 // [+ -](x * y [+ -] z).
858 // _ N A S
859 // D U
860 // D B
861 //
862 // Note: multiplication commutativity handled by rule generator.
863 (F(MADD|NMADD|MSUB|NMSUB)S neg:(FNEGS x) y z) && neg.Uses == 1 => (F(NMSUB|MSUB|NMADD|MADD)S x y z)
864 (F(MADD|NMADD|MSUB|NMSUB)S x y neg:(FNEGS z)) && neg.Uses == 1 => (F(MSUB|NMSUB|MADD|NMADD)S x y z)
865 (F(MADD|NMADD|MSUB|NMSUB)D neg:(FNEGD x) y z) && neg.Uses == 1 => (F(NMSUB|MSUB|NMADD|MADD)D x y z)
866 (F(MADD|NMADD|MSUB|NMSUB)D x y neg:(FNEGD z)) && neg.Uses == 1 => (F(MSUB|NMSUB|MADD|NMADD)D x y z)
867
868 // Test for -∞ (bit 0) using 64 bit classify instruction.
869 (FLTD x (FMOVDconst [-math.MaxFloat64])) => (ANDI [0b00_0000_0001] (FCLASSD x))
870 (FLED (FMOVDconst [-math.MaxFloat64]) x) => (SNEZ (ANDI <typ.Int64> [0b00_1111_1110] (FCLASSD x)))
871 (FEQD x (FMOVDconst [math.Inf(-1)])) => (ANDI [0b00_0000_0001] (FCLASSD x))
872 (FNED x (FMOVDconst [math.Inf(-1)])) => (SEQZ (ANDI <typ.Int64> [0b00_0000_0001] (FCLASSD x)))
873
874 // Test for +∞ (bit 7) using 64 bit classify instruction.
875 (FLTD (FMOVDconst [math.MaxFloat64]) x) => (SNEZ (ANDI <typ.Int64> [0b00_1000_0000] (FCLASSD x)))
876 (FLED x (FMOVDconst [math.MaxFloat64])) => (SNEZ (ANDI <typ.Int64> [0b00_0111_1111] (FCLASSD x)))
877 (FEQD x (FMOVDconst [math.Inf(1)])) => (SNEZ (ANDI <typ.Int64> [0b00_1000_0000] (FCLASSD x)))
878 (FNED x (FMOVDconst [math.Inf(1)])) => (SEQZ (ANDI <typ.Int64> [0b00_1000_0000] (FCLASSD x)))
879
880 // Test for subnormal numbers using 64 bit classify instruction.
881 (FLTD x (FMOVDconst [+0x1p-1022])) => (SNEZ (ANDI <typ.Int64> [0b00_0011_1111] (FCLASSD x)))
882 (FLED (FMOVDconst [+0x1p-1022]) x) => (SNEZ (ANDI <typ.Int64> [0b00_1100_0000] (FCLASSD x)))
883 (FLED x (FMOVDconst [-0x1p-1022])) => (SNEZ (ANDI <typ.Int64> [0b00_0000_0011] (FCLASSD x)))
884 (FLTD (FMOVDconst [-0x1p-1022]) x) => (SNEZ (ANDI <typ.Int64> [0b00_1111_1100] (FCLASSD x)))
885
886 // Absorb conversion between 32 bit and 64 bit if both src and dst are 32 bit.
887 (FCVTSD (F(ABS|SQRT)D (FCVTDS X))) => (F(ABS|SQRT)S X)
888
889 // Absorb unary sign bit operations into 64 bit classify instruction.
890 (S(EQ|NE)Z (ANDI [c] (FCLASSD (FNEGD x)))) => (S(EQ|NE)Z (ANDI <typ.Int64> [(c&0b11_0000_0000)|int64(bits.Reverse8(uint8(c))&0b1111_1111)] (FCLASSD x)))
891 (S(EQ|NE)Z (ANDI [c] (FCLASSD (FABSD x)))) => (S(EQ|NE)Z (ANDI <typ.Int64> [(c&0b11_1111_0000)|int64(bits.Reverse8(uint8(c))&0b0000_1111)] (FCLASSD x)))
892 (B(EQ|NE)Z (ANDI [c] (FCLASSD (FNEGD x))) yes no) => (B(EQ|NE)Z (ANDI <typ.Int64> [(c&0b11_0000_0000)|int64(bits.Reverse8(uint8(c))&0b1111_1111)] (FCLASSD x)) yes no)
893 (B(EQ|NE)Z (ANDI [c] (FCLASSD (FABSD x))) yes no) => (B(EQ|NE)Z (ANDI <typ.Int64> [(c&0b11_1111_0000)|int64(bits.Reverse8(uint8(c))&0b0000_1111)] (FCLASSD x)) yes no)
894
895 //
896 // Optimisations for rva22u64 and above.
897 //
898
899 // Combine left shift and addition.
900 (ADD (SLLI [1] x) y) && buildcfg.GORISCV64 >= 22 => (SH1ADD x y)
901 (ADD (SLLI [2] x) y) && buildcfg.GORISCV64 >= 22 => (SH2ADD x y)
902 (ADD (SLLI [3] x) y) && buildcfg.GORISCV64 >= 22 => (SH3ADD x y)
903
904 // Integer minimum and maximum.
905 (Min64 x y) && buildcfg.GORISCV64 >= 22 => (MIN x y)
906 (Max64 x y) && buildcfg.GORISCV64 >= 22 => (MAX x y)
907 (Min64u x y) && buildcfg.GORISCV64 >= 22 => (MINU x y)
908 (Max64u x y) && buildcfg.GORISCV64 >= 22 => (MAXU x y)
909
910 // Conditional selection (note that these will only be emitted for rva23u64 and above)
911 (CondSelect <t> x y cond) =>
912 (OR (CZEROEQZ <t> x (MOVBUreg <typ.UInt64> cond)) (CZERONEZ <t> y (MOVBUreg <typ.UInt64> cond)))
913 (CZERO(EQ|NE)Z x (SNEZ y)) => (CZERO(EQ|NE)Z x y)
914 (CZERO(EQ|NE)Z x (SEQZ y)) => (CZERO(NE|EQ)Z x y)
915 (CZERO(EQ|NE)Z x (NEG y)) => (CZERO(EQ|NE)Z x y)
916 (CZEROEQZ x x) => x
917 (CZERONEZ x x) => (MOVDconst [0])
918 (CZERO(EQ|NE)Z (MOVDconst [0]) _) => (MOVDconst [0])
919
920 // Optimize conditional arithmetic operations
921 (OR (CZEROEQZ <t> x cond) (CZERONEZ <t> ((ADD|SUB|OR|XOR|SUBW) x y) cond)) => ((ADD|SUB|OR|XOR|SUBW) x (CZERONEZ <t> y cond))
922 (OR (CZEROEQZ <t> ((ADD|SUB|OR|XOR|SUBW) x y) cond) (CZERONEZ <t> x cond)) => ((ADD|SUB|OR|XOR|SUBW) x (CZEROEQZ <t> y cond))
923 (OR x:(CZEROEQZ z cond) (CZERONEZ y:(AND z _) cond)) => (OR y x)
924 (OR (CZEROEQZ x:(AND z _) cond) y:(CZERONEZ z cond)) => (OR x y)
925 (OR x:(CZEROEQZ z cond) (CZERONEZ y:(ANDI <t> [c] z) cond)) => (OR y x)
926 (OR (CZEROEQZ x:(ANDI <t> [c] z) cond) y:(CZERONEZ z cond)) => (OR x y)
927 (OR (CZEROEQZ <t> x cond) (CZERONEZ <t> ((ADDI|ORI|XORI) [c] x) cond)) => ((ADD|OR|XOR) x (CZERONEZ <t> (MOVDconst [c]) cond))
928 (OR (CZEROEQZ <t> ((ADDI|ORI|XORI) [c] x) cond) (CZERONEZ <t> x cond)) => ((ADD|OR|XOR) x (CZEROEQZ <t> (MOVDconst [c]) cond))
929
930 // Strength reduction for multiplication by a constant.
931 (MUL x (MOVDconst [c])) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) && buildcfg.GORISCV64 >= 22 => (SLLI [ssa.Log64(c/3)] (SH1ADD <x.Type> x x))
932 (MUL x (MOVDconst [c])) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) && buildcfg.GORISCV64 >= 22 => (SLLI [ssa.Log64(c/5)] (SH2ADD <x.Type> x x))
933 (MUL x (MOVDconst [c])) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) && buildcfg.GORISCV64 >= 22 => (SLLI [ssa.Log64(c/9)] (SH3ADD <x.Type> x x))
934
935 // 32-bit multiply by constant (int32/uint32).
936 (MULW x (MOVDconst [c])) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) && buildcfg.GORISCV64 >= 22 => (SLLIW [ssa.Log64(c/3)] (SH1ADD <x.Type> x x))
937 (MULW x (MOVDconst [c])) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) && buildcfg.GORISCV64 >= 22 => (SLLIW [ssa.Log64(c/5)] (SH2ADD <x.Type> x x))
938 (MULW x (MOVDconst [c])) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) && buildcfg.GORISCV64 >= 22 => (SLLIW [ssa.Log64(c/9)] (SH3ADD <x.Type> x x))
939
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