Source file src/cmd/compile/internal/ssagen/simdWasmintrinsics.go

     1  // Code generated by 'wasmgen'; DO NOT EDIT.
     2  
     3  package ssagen
     4  
     5  import (
     6  	"cmd/compile/internal/ir"
     7  	"cmd/compile/internal/ssa"
     8  	"cmd/compile/internal/types"
     9  	"cmd/internal/sys"
    10  )
    11  
    12  func initWasmSIMD() {
    13  	makeSimdOp1 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    14  		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    15  			return s.newValue1(op, types.TypeVec128, args[0])
    16  		}
    17  	}
    18  	makeSimdOp2 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    19  		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    20  			return s.newValue2(op, types.TypeVec128, args[0], args[1])
    21  		}
    22  	}
    23  	makeSimdOp3 := func(op ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    24  		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    25  			return s.newValue3(op, types.TypeVec128, args[0], args[1], args[2])
    26  		}
    27  	}
    28  
    29  	// "As" is a type pun, just return the bits
    30  	makeAsOp := func() func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    31  		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    32  			return args[0]
    33  		}
    34  	}
    35  
    36  	// converting to a mask is an not-equals comparison with zero, zero obtained by x XOR x.
    37  	makeToMask := func(op, xor ssa.Op) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    38  		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    39  			return s.newValue2(op, types.TypeVec128, args[0], s.newValue2(xor, n.Type(), args[0], args[0]))
    40  		}
    41  	}
    42  
    43  	makeSimdOp1Imm8 := func(op ssa.Op, immLimit uint64) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    44  		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    45  			t := n.Type()
    46  			if args[1].Op == ssa.OpConst8 {
    47  				return s.newValue1I(op, t, args[1].AuxInt, args[0])
    48  			}
    49  			return immJumpTableN(s, args[1], n, immLimit, func(sNew *state, idx int) {
    50  				// Encode as int8 due to requirement of AuxInt, check its comment for details.
    51  				s.vars[n] = sNew.newValue1I(op, t, int64(int8(idx)), args[0])
    52  			})
    53  		}
    54  	}
    55  
    56  	makeSimdOp2Imm8 := func(op ssa.Op, immLimit uint64) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    57  		return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
    58  			t := types.TypeVec128
    59  			if args[1].Op == ssa.OpConst8 {
    60  				return s.newValue2I(op, t, args[1].AuxInt, args[0], args[2])
    61  			}
    62  			return immJumpTableN(s, args[1], n, immLimit, func(sNew *state, idx int) {
    63  				// Encode as int8 due to requirement of AuxInt, check its comment for details.
    64  				s.vars[n] = sNew.newValue2I(op, t, int64(int8(idx)), args[0], args[2])
    65  			})
    66  		}
    67  	}
    68  
    69  	addWasmSIMD := func(pkg, fn string, builder func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value) {
    70  		intrinsics.add(sys.ArchWasm, pkg, fn, builder)
    71  	}
    72  
    73  	addWasmSIMD("simd/archsimd", "Int8x16.Abs", makeSimdOp1(ssa.OpAbsInt8x16))
    74  	addWasmSIMD("simd/archsimd", "Int16x8.Abs", makeSimdOp1(ssa.OpAbsInt16x8))
    75  	addWasmSIMD("simd/archsimd", "Int32x4.Abs", makeSimdOp1(ssa.OpAbsInt32x4))
    76  	addWasmSIMD("simd/archsimd", "Float32x4.Abs", makeSimdOp1(ssa.OpAbsFloat32x4))
    77  	addWasmSIMD("simd/archsimd", "Int64x2.Abs", makeSimdOp1(ssa.OpAbsInt64x2))
    78  	addWasmSIMD("simd/archsimd", "Float64x2.Abs", makeSimdOp1(ssa.OpAbsFloat64x2))
    79  	addWasmSIMD("simd/archsimd", "Int8x16.Add", makeSimdOp2(ssa.OpAddInt8x16))
    80  	addWasmSIMD("simd/archsimd", "Uint8x16.Add", makeSimdOp2(ssa.OpAddUint8x16))
    81  	addWasmSIMD("simd/archsimd", "Int16x8.Add", makeSimdOp2(ssa.OpAddInt16x8))
    82  	addWasmSIMD("simd/archsimd", "Uint16x8.Add", makeSimdOp2(ssa.OpAddUint16x8))
    83  	addWasmSIMD("simd/archsimd", "Int32x4.Add", makeSimdOp2(ssa.OpAddInt32x4))
    84  	addWasmSIMD("simd/archsimd", "Uint32x4.Add", makeSimdOp2(ssa.OpAddUint32x4))
    85  	addWasmSIMD("simd/archsimd", "Float32x4.Add", makeSimdOp2(ssa.OpAddFloat32x4))
    86  	addWasmSIMD("simd/archsimd", "Int64x2.Add", makeSimdOp2(ssa.OpAddInt64x2))
    87  	addWasmSIMD("simd/archsimd", "Uint64x2.Add", makeSimdOp2(ssa.OpAddUint64x2))
    88  	addWasmSIMD("simd/archsimd", "Float64x2.Add", makeSimdOp2(ssa.OpAddFloat64x2))
    89  	addWasmSIMD("simd/archsimd", "Int8x16.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedInt8x16))
    90  	addWasmSIMD("simd/archsimd", "Uint8x16.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedUint8x16))
    91  	addWasmSIMD("simd/archsimd", "Int16x8.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedInt16x8))
    92  	addWasmSIMD("simd/archsimd", "Uint16x8.AddSaturated", makeSimdOp2(ssa.OpAddSaturatedUint16x8))
    93  	addWasmSIMD("simd/archsimd", "Int8x16.And", makeSimdOp2(ssa.OpAndInt8x16))
    94  	addWasmSIMD("simd/archsimd", "Uint8x16.And", makeSimdOp2(ssa.OpAndUint8x16))
    95  	addWasmSIMD("simd/archsimd", "Mask8x16.And", makeSimdOp2(ssa.OpAndInt8x16))
    96  	addWasmSIMD("simd/archsimd", "Int16x8.And", makeSimdOp2(ssa.OpAndInt16x8))
    97  	addWasmSIMD("simd/archsimd", "Uint16x8.And", makeSimdOp2(ssa.OpAndUint16x8))
    98  	addWasmSIMD("simd/archsimd", "Mask16x8.And", makeSimdOp2(ssa.OpAndInt16x8))
    99  	addWasmSIMD("simd/archsimd", "Int32x4.And", makeSimdOp2(ssa.OpAndInt32x4))
   100  	addWasmSIMD("simd/archsimd", "Uint32x4.And", makeSimdOp2(ssa.OpAndUint32x4))
   101  	addWasmSIMD("simd/archsimd", "Mask32x4.And", makeSimdOp2(ssa.OpAndInt32x4))
   102  	addWasmSIMD("simd/archsimd", "Int64x2.And", makeSimdOp2(ssa.OpAndInt64x2))
   103  	addWasmSIMD("simd/archsimd", "Uint64x2.And", makeSimdOp2(ssa.OpAndUint64x2))
   104  	addWasmSIMD("simd/archsimd", "Mask64x2.And", makeSimdOp2(ssa.OpAndInt64x2))
   105  	addWasmSIMD("simd/archsimd", "Int8x16.AndNot", makeSimdOp2(ssa.OpAndNotInt8x16))
   106  	addWasmSIMD("simd/archsimd", "Uint8x16.AndNot", makeSimdOp2(ssa.OpAndNotUint8x16))
   107  	addWasmSIMD("simd/archsimd", "Mask8x16.AndNot", makeSimdOp2(ssa.OpAndNotInt8x16))
   108  	addWasmSIMD("simd/archsimd", "Int16x8.AndNot", makeSimdOp2(ssa.OpAndNotInt16x8))
   109  	addWasmSIMD("simd/archsimd", "Uint16x8.AndNot", makeSimdOp2(ssa.OpAndNotUint16x8))
   110  	addWasmSIMD("simd/archsimd", "Mask16x8.AndNot", makeSimdOp2(ssa.OpAndNotInt16x8))
   111  	addWasmSIMD("simd/archsimd", "Int32x4.AndNot", makeSimdOp2(ssa.OpAndNotInt32x4))
   112  	addWasmSIMD("simd/archsimd", "Uint32x4.AndNot", makeSimdOp2(ssa.OpAndNotUint32x4))
   113  	addWasmSIMD("simd/archsimd", "Mask32x4.AndNot", makeSimdOp2(ssa.OpAndNotInt32x4))
   114  	addWasmSIMD("simd/archsimd", "Int64x2.AndNot", makeSimdOp2(ssa.OpAndNotInt64x2))
   115  	addWasmSIMD("simd/archsimd", "Uint64x2.AndNot", makeSimdOp2(ssa.OpAndNotUint64x2))
   116  	addWasmSIMD("simd/archsimd", "Mask64x2.AndNot", makeSimdOp2(ssa.OpAndNotInt64x2))
   117  	addWasmSIMD("simd/archsimd", "Uint8x16.Average", makeSimdOp2(ssa.OpAverageUint8x16))
   118  	addWasmSIMD("simd/archsimd", "Uint16x8.Average", makeSimdOp2(ssa.OpAverageUint16x8))
   119  	addWasmSIMD("simd/archsimd", "Int8x16.BitSelect", makeSimdOp3(ssa.OpBitSelectInt8x16))
   120  	addWasmSIMD("simd/archsimd", "Uint8x16.BitSelect", makeSimdOp3(ssa.OpBitSelectUint8x16))
   121  	addWasmSIMD("simd/archsimd", "Int16x8.BitSelect", makeSimdOp3(ssa.OpBitSelectInt16x8))
   122  	addWasmSIMD("simd/archsimd", "Uint16x8.BitSelect", makeSimdOp3(ssa.OpBitSelectUint16x8))
   123  	addWasmSIMD("simd/archsimd", "Int32x4.BitSelect", makeSimdOp3(ssa.OpBitSelectInt32x4))
   124  	addWasmSIMD("simd/archsimd", "Uint32x4.BitSelect", makeSimdOp3(ssa.OpBitSelectUint32x4))
   125  	addWasmSIMD("simd/archsimd", "Int64x2.BitSelect", makeSimdOp3(ssa.OpBitSelectInt64x2))
   126  	addWasmSIMD("simd/archsimd", "Uint64x2.BitSelect", makeSimdOp3(ssa.OpBitSelectUint64x2))
   127  	addWasmSIMD("simd/archsimd", "Float32x4.Ceil", makeSimdOp1(ssa.OpCeilFloat32x4))
   128  	addWasmSIMD("simd/archsimd", "Float64x2.Ceil", makeSimdOp1(ssa.OpCeilFloat64x2))
   129  	addWasmSIMD("simd/archsimd", "Int32x4.ConvertLo2ToFloat64", makeSimdOp1(ssa.OpConvertLo2ToFloat64Int32x4))
   130  	addWasmSIMD("simd/archsimd", "Uint32x4.ConvertLo2ToFloat64", makeSimdOp1(ssa.OpConvertLo2ToFloat64Uint32x4))
   131  	addWasmSIMD("simd/archsimd", "Int32x4.ConvertToFloat32", makeSimdOp1(ssa.OpConvertToFloat32Int32x4))
   132  	addWasmSIMD("simd/archsimd", "Uint32x4.ConvertToFloat32", makeSimdOp1(ssa.OpConvertToFloat32Uint32x4))
   133  	addWasmSIMD("simd/archsimd", "Float32x4.ConvertToInt32", makeSimdOp1(ssa.OpConvertToInt32Float32x4))
   134  	addWasmSIMD("simd/archsimd", "Float32x4.ConvertToUint32", makeSimdOp1(ssa.OpConvertToUint32Float32x4))
   135  	addWasmSIMD("simd/archsimd", "Float32x4.Div", makeSimdOp2(ssa.OpDivFloat32x4))
   136  	addWasmSIMD("simd/archsimd", "Float64x2.Div", makeSimdOp2(ssa.OpDivFloat64x2))
   137  	addWasmSIMD("simd/archsimd", "Int8x16.Equal", makeSimdOp2(ssa.OpEqualInt8x16))
   138  	addWasmSIMD("simd/archsimd", "Uint8x16.Equal", makeSimdOp2(ssa.OpEqualUint8x16))
   139  	addWasmSIMD("simd/archsimd", "Int16x8.Equal", makeSimdOp2(ssa.OpEqualInt16x8))
   140  	addWasmSIMD("simd/archsimd", "Uint16x8.Equal", makeSimdOp2(ssa.OpEqualUint16x8))
   141  	addWasmSIMD("simd/archsimd", "Int32x4.Equal", makeSimdOp2(ssa.OpEqualInt32x4))
   142  	addWasmSIMD("simd/archsimd", "Uint32x4.Equal", makeSimdOp2(ssa.OpEqualUint32x4))
   143  	addWasmSIMD("simd/archsimd", "Float32x4.Equal", makeSimdOp2(ssa.OpEqualFloat32x4))
   144  	addWasmSIMD("simd/archsimd", "Int64x2.Equal", makeSimdOp2(ssa.OpEqualInt64x2))
   145  	addWasmSIMD("simd/archsimd", "Uint64x2.Equal", makeSimdOp2(ssa.OpEqualUint64x2))
   146  	addWasmSIMD("simd/archsimd", "Float64x2.Equal", makeSimdOp2(ssa.OpEqualFloat64x2))
   147  	addWasmSIMD("simd/archsimd", "Int32x4.ExtendHi2ToInt64", makeSimdOp1(ssa.OpExtendHi2ToInt64Int32x4))
   148  	addWasmSIMD("simd/archsimd", "Uint32x4.ExtendHi2ToUint64", makeSimdOp1(ssa.OpExtendHi2ToUint64Uint32x4))
   149  	addWasmSIMD("simd/archsimd", "Int16x8.ExtendHi4ToInt32", makeSimdOp1(ssa.OpExtendHi4ToInt32Int16x8))
   150  	addWasmSIMD("simd/archsimd", "Uint16x8.ExtendHi4ToUint32", makeSimdOp1(ssa.OpExtendHi4ToUint32Uint16x8))
   151  	addWasmSIMD("simd/archsimd", "Int8x16.ExtendHi8ToInt16", makeSimdOp1(ssa.OpExtendHi8ToInt16Int8x16))
   152  	addWasmSIMD("simd/archsimd", "Uint8x16.ExtendHi8ToUint16", makeSimdOp1(ssa.OpExtendHi8ToUint16Uint8x16))
   153  	addWasmSIMD("simd/archsimd", "Int32x4.ExtendLo2ToInt64", makeSimdOp1(ssa.OpExtendLo2ToInt64Int32x4))
   154  	addWasmSIMD("simd/archsimd", "Uint32x4.ExtendLo2ToUint64", makeSimdOp1(ssa.OpExtendLo2ToUint64Uint32x4))
   155  	addWasmSIMD("simd/archsimd", "Int16x8.ExtendLo4ToInt32", makeSimdOp1(ssa.OpExtendLo4ToInt32Int16x8))
   156  	addWasmSIMD("simd/archsimd", "Uint16x8.ExtendLo4ToUint32", makeSimdOp1(ssa.OpExtendLo4ToUint32Uint16x8))
   157  	addWasmSIMD("simd/archsimd", "Int8x16.ExtendLo8ToInt16", makeSimdOp1(ssa.OpExtendLo8ToInt16Int8x16))
   158  	addWasmSIMD("simd/archsimd", "Uint8x16.ExtendLo8ToUint16", makeSimdOp1(ssa.OpExtendLo8ToUint16Uint8x16))
   159  	addWasmSIMD("simd/archsimd", "Float32x4.Floor", makeSimdOp1(ssa.OpFloorFloat32x4))
   160  	addWasmSIMD("simd/archsimd", "Float64x2.Floor", makeSimdOp1(ssa.OpFloorFloat64x2))
   161  	addWasmSIMD("simd/archsimd", "Int8x16.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt8x16, 16))
   162  	addWasmSIMD("simd/archsimd", "Uint8x16.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint8x16, 16))
   163  	addWasmSIMD("simd/archsimd", "Int16x8.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt16x8, 8))
   164  	addWasmSIMD("simd/archsimd", "Uint16x8.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint16x8, 8))
   165  	addWasmSIMD("simd/archsimd", "Int32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt32x4, 4))
   166  	addWasmSIMD("simd/archsimd", "Uint32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint32x4, 4))
   167  	addWasmSIMD("simd/archsimd", "Float32x4.GetElem", makeSimdOp1Imm8(ssa.OpGetElemFloat32x4, 4))
   168  	addWasmSIMD("simd/archsimd", "Int64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemInt64x2, 2))
   169  	addWasmSIMD("simd/archsimd", "Uint64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemUint64x2, 2))
   170  	addWasmSIMD("simd/archsimd", "Float64x2.GetElem", makeSimdOp1Imm8(ssa.OpGetElemFloat64x2, 2))
   171  	addWasmSIMD("simd/archsimd", "Int8x16.Greater", makeSimdOp2(ssa.OpGreaterInt8x16))
   172  	addWasmSIMD("simd/archsimd", "Uint8x16.Greater", makeSimdOp2(ssa.OpGreaterUint8x16))
   173  	addWasmSIMD("simd/archsimd", "Int16x8.Greater", makeSimdOp2(ssa.OpGreaterInt16x8))
   174  	addWasmSIMD("simd/archsimd", "Uint16x8.Greater", makeSimdOp2(ssa.OpGreaterUint16x8))
   175  	addWasmSIMD("simd/archsimd", "Int32x4.Greater", makeSimdOp2(ssa.OpGreaterInt32x4))
   176  	addWasmSIMD("simd/archsimd", "Uint32x4.Greater", makeSimdOp2(ssa.OpGreaterUint32x4))
   177  	addWasmSIMD("simd/archsimd", "Float32x4.Greater", makeSimdOp2(ssa.OpGreaterFloat32x4))
   178  	addWasmSIMD("simd/archsimd", "Int64x2.Greater", makeSimdOp2(ssa.OpGreaterInt64x2))
   179  	addWasmSIMD("simd/archsimd", "Float64x2.Greater", makeSimdOp2(ssa.OpGreaterFloat64x2))
   180  	addWasmSIMD("simd/archsimd", "Int8x16.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt8x16))
   181  	addWasmSIMD("simd/archsimd", "Uint8x16.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint8x16))
   182  	addWasmSIMD("simd/archsimd", "Int16x8.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt16x8))
   183  	addWasmSIMD("simd/archsimd", "Uint16x8.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint16x8))
   184  	addWasmSIMD("simd/archsimd", "Int32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt32x4))
   185  	addWasmSIMD("simd/archsimd", "Uint32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualUint32x4))
   186  	addWasmSIMD("simd/archsimd", "Float32x4.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualFloat32x4))
   187  	addWasmSIMD("simd/archsimd", "Int64x2.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualInt64x2))
   188  	addWasmSIMD("simd/archsimd", "Float64x2.GreaterEqual", makeSimdOp2(ssa.OpGreaterEqualFloat64x2))
   189  	addWasmSIMD("simd/archsimd", "Int8x16.Less", makeSimdOp2(ssa.OpLessInt8x16))
   190  	addWasmSIMD("simd/archsimd", "Uint8x16.Less", makeSimdOp2(ssa.OpLessUint8x16))
   191  	addWasmSIMD("simd/archsimd", "Int16x8.Less", makeSimdOp2(ssa.OpLessInt16x8))
   192  	addWasmSIMD("simd/archsimd", "Uint16x8.Less", makeSimdOp2(ssa.OpLessUint16x8))
   193  	addWasmSIMD("simd/archsimd", "Int32x4.Less", makeSimdOp2(ssa.OpLessInt32x4))
   194  	addWasmSIMD("simd/archsimd", "Uint32x4.Less", makeSimdOp2(ssa.OpLessUint32x4))
   195  	addWasmSIMD("simd/archsimd", "Float32x4.Less", makeSimdOp2(ssa.OpLessFloat32x4))
   196  	addWasmSIMD("simd/archsimd", "Int64x2.Less", makeSimdOp2(ssa.OpLessInt64x2))
   197  	addWasmSIMD("simd/archsimd", "Float64x2.Less", makeSimdOp2(ssa.OpLessFloat64x2))
   198  	addWasmSIMD("simd/archsimd", "Int8x16.LessEqual", makeSimdOp2(ssa.OpLessEqualInt8x16))
   199  	addWasmSIMD("simd/archsimd", "Uint8x16.LessEqual", makeSimdOp2(ssa.OpLessEqualUint8x16))
   200  	addWasmSIMD("simd/archsimd", "Int16x8.LessEqual", makeSimdOp2(ssa.OpLessEqualInt16x8))
   201  	addWasmSIMD("simd/archsimd", "Uint16x8.LessEqual", makeSimdOp2(ssa.OpLessEqualUint16x8))
   202  	addWasmSIMD("simd/archsimd", "Int32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualInt32x4))
   203  	addWasmSIMD("simd/archsimd", "Uint32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualUint32x4))
   204  	addWasmSIMD("simd/archsimd", "Float32x4.LessEqual", makeSimdOp2(ssa.OpLessEqualFloat32x4))
   205  	addWasmSIMD("simd/archsimd", "Int64x2.LessEqual", makeSimdOp2(ssa.OpLessEqualInt64x2))
   206  	addWasmSIMD("simd/archsimd", "Float64x2.LessEqual", makeSimdOp2(ssa.OpLessEqualFloat64x2))
   207  	addWasmSIMD("simd/archsimd", "Int8x16.LookupOrZero", makeSimdOp2(ssa.OpLookupOrZeroInt8x16))
   208  	addWasmSIMD("simd/archsimd", "Int8x16.Max", makeSimdOp2(ssa.OpMaxInt8x16))
   209  	addWasmSIMD("simd/archsimd", "Uint8x16.Max", makeSimdOp2(ssa.OpMaxUint8x16))
   210  	addWasmSIMD("simd/archsimd", "Int16x8.Max", makeSimdOp2(ssa.OpMaxInt16x8))
   211  	addWasmSIMD("simd/archsimd", "Uint16x8.Max", makeSimdOp2(ssa.OpMaxUint16x8))
   212  	addWasmSIMD("simd/archsimd", "Int32x4.Max", makeSimdOp2(ssa.OpMaxInt32x4))
   213  	addWasmSIMD("simd/archsimd", "Uint32x4.Max", makeSimdOp2(ssa.OpMaxUint32x4))
   214  	addWasmSIMD("simd/archsimd", "Float32x4.Max", makeSimdOp2(ssa.OpMaxFloat32x4))
   215  	addWasmSIMD("simd/archsimd", "Float64x2.Max", makeSimdOp2(ssa.OpMaxFloat64x2))
   216  	addWasmSIMD("simd/archsimd", "Int8x16.Min", makeSimdOp2(ssa.OpMinInt8x16))
   217  	addWasmSIMD("simd/archsimd", "Uint8x16.Min", makeSimdOp2(ssa.OpMinUint8x16))
   218  	addWasmSIMD("simd/archsimd", "Int16x8.Min", makeSimdOp2(ssa.OpMinInt16x8))
   219  	addWasmSIMD("simd/archsimd", "Uint16x8.Min", makeSimdOp2(ssa.OpMinUint16x8))
   220  	addWasmSIMD("simd/archsimd", "Int32x4.Min", makeSimdOp2(ssa.OpMinInt32x4))
   221  	addWasmSIMD("simd/archsimd", "Uint32x4.Min", makeSimdOp2(ssa.OpMinUint32x4))
   222  	addWasmSIMD("simd/archsimd", "Float32x4.Min", makeSimdOp2(ssa.OpMinFloat32x4))
   223  	addWasmSIMD("simd/archsimd", "Float64x2.Min", makeSimdOp2(ssa.OpMinFloat64x2))
   224  	addWasmSIMD("simd/archsimd", "Int16x8.Mul", makeSimdOp2(ssa.OpMulInt16x8))
   225  	addWasmSIMD("simd/archsimd", "Uint16x8.Mul", makeSimdOp2(ssa.OpMulUint16x8))
   226  	addWasmSIMD("simd/archsimd", "Int32x4.Mul", makeSimdOp2(ssa.OpMulInt32x4))
   227  	addWasmSIMD("simd/archsimd", "Uint32x4.Mul", makeSimdOp2(ssa.OpMulUint32x4))
   228  	addWasmSIMD("simd/archsimd", "Float32x4.Mul", makeSimdOp2(ssa.OpMulFloat32x4))
   229  	addWasmSIMD("simd/archsimd", "Int64x2.Mul", makeSimdOp2(ssa.OpMulInt64x2))
   230  	addWasmSIMD("simd/archsimd", "Uint64x2.Mul", makeSimdOp2(ssa.OpMulUint64x2))
   231  	addWasmSIMD("simd/archsimd", "Float64x2.Mul", makeSimdOp2(ssa.OpMulFloat64x2))
   232  	addWasmSIMD("simd/archsimd", "Float32x4.MulAdd", makeSimdOp3(ssa.OpMulAddFloat32x4))
   233  	addWasmSIMD("simd/archsimd", "Float64x2.MulAdd", makeSimdOp3(ssa.OpMulAddFloat64x2))
   234  	addWasmSIMD("simd/archsimd", "Int8x16.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt8x16))
   235  	addWasmSIMD("simd/archsimd", "Uint8x16.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint8x16))
   236  	addWasmSIMD("simd/archsimd", "Int16x8.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt16x8))
   237  	addWasmSIMD("simd/archsimd", "Uint16x8.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint16x8))
   238  	addWasmSIMD("simd/archsimd", "Int32x4.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiInt32x4))
   239  	addWasmSIMD("simd/archsimd", "Uint32x4.MulWidenHi", makeSimdOp2(ssa.OpMulWidenHiUint32x4))
   240  	addWasmSIMD("simd/archsimd", "Int8x16.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt8x16))
   241  	addWasmSIMD("simd/archsimd", "Uint8x16.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint8x16))
   242  	addWasmSIMD("simd/archsimd", "Int16x8.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt16x8))
   243  	addWasmSIMD("simd/archsimd", "Uint16x8.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint16x8))
   244  	addWasmSIMD("simd/archsimd", "Int32x4.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoInt32x4))
   245  	addWasmSIMD("simd/archsimd", "Uint32x4.MulWidenLo", makeSimdOp2(ssa.OpMulWidenLoUint32x4))
   246  	addWasmSIMD("simd/archsimd", "Int8x16.Neg", makeSimdOp1(ssa.OpNegInt8x16))
   247  	addWasmSIMD("simd/archsimd", "Int16x8.Neg", makeSimdOp1(ssa.OpNegInt16x8))
   248  	addWasmSIMD("simd/archsimd", "Int32x4.Neg", makeSimdOp1(ssa.OpNegInt32x4))
   249  	addWasmSIMD("simd/archsimd", "Float32x4.Neg", makeSimdOp1(ssa.OpNegFloat32x4))
   250  	addWasmSIMD("simd/archsimd", "Int64x2.Neg", makeSimdOp1(ssa.OpNegInt64x2))
   251  	addWasmSIMD("simd/archsimd", "Float64x2.Neg", makeSimdOp1(ssa.OpNegFloat64x2))
   252  	addWasmSIMD("simd/archsimd", "Int8x16.Not", makeSimdOp1(ssa.OpNotInt8x16))
   253  	addWasmSIMD("simd/archsimd", "Uint8x16.Not", makeSimdOp1(ssa.OpNotUint8x16))
   254  	addWasmSIMD("simd/archsimd", "Int16x8.Not", makeSimdOp1(ssa.OpNotInt16x8))
   255  	addWasmSIMD("simd/archsimd", "Uint16x8.Not", makeSimdOp1(ssa.OpNotUint16x8))
   256  	addWasmSIMD("simd/archsimd", "Int32x4.Not", makeSimdOp1(ssa.OpNotInt32x4))
   257  	addWasmSIMD("simd/archsimd", "Uint32x4.Not", makeSimdOp1(ssa.OpNotUint32x4))
   258  	addWasmSIMD("simd/archsimd", "Int64x2.Not", makeSimdOp1(ssa.OpNotInt64x2))
   259  	addWasmSIMD("simd/archsimd", "Uint64x2.Not", makeSimdOp1(ssa.OpNotUint64x2))
   260  	addWasmSIMD("simd/archsimd", "Int8x16.NotEqual", makeSimdOp2(ssa.OpNotEqualInt8x16))
   261  	addWasmSIMD("simd/archsimd", "Uint8x16.NotEqual", makeSimdOp2(ssa.OpNotEqualUint8x16))
   262  	addWasmSIMD("simd/archsimd", "Int16x8.NotEqual", makeSimdOp2(ssa.OpNotEqualInt16x8))
   263  	addWasmSIMD("simd/archsimd", "Uint16x8.NotEqual", makeSimdOp2(ssa.OpNotEqualUint16x8))
   264  	addWasmSIMD("simd/archsimd", "Int32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualInt32x4))
   265  	addWasmSIMD("simd/archsimd", "Uint32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualUint32x4))
   266  	addWasmSIMD("simd/archsimd", "Float32x4.NotEqual", makeSimdOp2(ssa.OpNotEqualFloat32x4))
   267  	addWasmSIMD("simd/archsimd", "Int64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualInt64x2))
   268  	addWasmSIMD("simd/archsimd", "Uint64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualUint64x2))
   269  	addWasmSIMD("simd/archsimd", "Float64x2.NotEqual", makeSimdOp2(ssa.OpNotEqualFloat64x2))
   270  	addWasmSIMD("simd/archsimd", "Int8x16.OnesCount", makeSimdOp1(ssa.OpOnesCountInt8x16))
   271  	addWasmSIMD("simd/archsimd", "Int8x16.Or", makeSimdOp2(ssa.OpOrInt8x16))
   272  	addWasmSIMD("simd/archsimd", "Uint8x16.Or", makeSimdOp2(ssa.OpOrUint8x16))
   273  	addWasmSIMD("simd/archsimd", "Mask8x16.Or", makeSimdOp2(ssa.OpOrInt8x16))
   274  	addWasmSIMD("simd/archsimd", "Int16x8.Or", makeSimdOp2(ssa.OpOrInt16x8))
   275  	addWasmSIMD("simd/archsimd", "Uint16x8.Or", makeSimdOp2(ssa.OpOrUint16x8))
   276  	addWasmSIMD("simd/archsimd", "Mask16x8.Or", makeSimdOp2(ssa.OpOrInt16x8))
   277  	addWasmSIMD("simd/archsimd", "Int32x4.Or", makeSimdOp2(ssa.OpOrInt32x4))
   278  	addWasmSIMD("simd/archsimd", "Uint32x4.Or", makeSimdOp2(ssa.OpOrUint32x4))
   279  	addWasmSIMD("simd/archsimd", "Mask32x4.Or", makeSimdOp2(ssa.OpOrInt32x4))
   280  	addWasmSIMD("simd/archsimd", "Int64x2.Or", makeSimdOp2(ssa.OpOrInt64x2))
   281  	addWasmSIMD("simd/archsimd", "Uint64x2.Or", makeSimdOp2(ssa.OpOrUint64x2))
   282  	addWasmSIMD("simd/archsimd", "Mask64x2.Or", makeSimdOp2(ssa.OpOrInt64x2))
   283  	addWasmSIMD("simd/archsimd", "Int8x16.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt8x16))
   284  	addWasmSIMD("simd/archsimd", "Uint8x16.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint8x16))
   285  	addWasmSIMD("simd/archsimd", "Int16x8.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt16x8))
   286  	addWasmSIMD("simd/archsimd", "Uint16x8.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint16x8))
   287  	addWasmSIMD("simd/archsimd", "Int32x4.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt32x4))
   288  	addWasmSIMD("simd/archsimd", "Uint32x4.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint32x4))
   289  	addWasmSIMD("simd/archsimd", "Int64x2.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarInt64x2))
   290  	addWasmSIMD("simd/archsimd", "Uint64x2.RotateAllLeft", makeSimdOp2(ssa.OpRotateAllLeftVarUint64x2))
   291  	addWasmSIMD("simd/archsimd", "Int8x16.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt8x16))
   292  	addWasmSIMD("simd/archsimd", "Uint8x16.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint8x16))
   293  	addWasmSIMD("simd/archsimd", "Int16x8.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt16x8))
   294  	addWasmSIMD("simd/archsimd", "Uint16x8.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint16x8))
   295  	addWasmSIMD("simd/archsimd", "Int32x4.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt32x4))
   296  	addWasmSIMD("simd/archsimd", "Uint32x4.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint32x4))
   297  	addWasmSIMD("simd/archsimd", "Int64x2.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarInt64x2))
   298  	addWasmSIMD("simd/archsimd", "Uint64x2.RotateAllRight", makeSimdOp2(ssa.OpRotateAllRightVarUint64x2))
   299  	addWasmSIMD("simd/archsimd", "Float32x4.Round", makeSimdOp1(ssa.OpRoundFloat32x4))
   300  	addWasmSIMD("simd/archsimd", "Float64x2.Round", makeSimdOp1(ssa.OpRoundFloat64x2))
   301  	addWasmSIMD("simd/archsimd", "Int8x16.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt8x16, 16))
   302  	addWasmSIMD("simd/archsimd", "Uint8x16.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint8x16, 16))
   303  	addWasmSIMD("simd/archsimd", "Int16x8.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt16x8, 8))
   304  	addWasmSIMD("simd/archsimd", "Uint16x8.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint16x8, 8))
   305  	addWasmSIMD("simd/archsimd", "Int32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt32x4, 4))
   306  	addWasmSIMD("simd/archsimd", "Uint32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint32x4, 4))
   307  	addWasmSIMD("simd/archsimd", "Float32x4.SetElem", makeSimdOp2Imm8(ssa.OpSetElemFloat32x4, 4))
   308  	addWasmSIMD("simd/archsimd", "Int64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemInt64x2, 2))
   309  	addWasmSIMD("simd/archsimd", "Uint64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemUint64x2, 2))
   310  	addWasmSIMD("simd/archsimd", "Float64x2.SetElem", makeSimdOp2Imm8(ssa.OpSetElemFloat64x2, 2))
   311  	addWasmSIMD("simd/archsimd", "Int8x16.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt8x16))
   312  	addWasmSIMD("simd/archsimd", "Uint8x16.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint8x16))
   313  	addWasmSIMD("simd/archsimd", "Int16x8.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt16x8))
   314  	addWasmSIMD("simd/archsimd", "Uint16x8.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint16x8))
   315  	addWasmSIMD("simd/archsimd", "Int32x4.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt32x4))
   316  	addWasmSIMD("simd/archsimd", "Uint32x4.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint32x4))
   317  	addWasmSIMD("simd/archsimd", "Int64x2.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftInt64x2))
   318  	addWasmSIMD("simd/archsimd", "Uint64x2.ShiftAllLeft", makeSimdOp2(ssa.OpShiftAllLeftUint64x2))
   319  	addWasmSIMD("simd/archsimd", "Int8x16.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt8x16))
   320  	addWasmSIMD("simd/archsimd", "Uint8x16.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint8x16))
   321  	addWasmSIMD("simd/archsimd", "Int16x8.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt16x8))
   322  	addWasmSIMD("simd/archsimd", "Uint16x8.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint16x8))
   323  	addWasmSIMD("simd/archsimd", "Int32x4.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt32x4))
   324  	addWasmSIMD("simd/archsimd", "Uint32x4.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint32x4))
   325  	addWasmSIMD("simd/archsimd", "Int64x2.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightInt64x2))
   326  	addWasmSIMD("simd/archsimd", "Uint64x2.ShiftAllRight", makeSimdOp2(ssa.OpShiftAllRightUint64x2))
   327  	addWasmSIMD("simd/archsimd", "Float32x4.Sqrt", makeSimdOp1(ssa.OpSqrtFloat32x4))
   328  	addWasmSIMD("simd/archsimd", "Float64x2.Sqrt", makeSimdOp1(ssa.OpSqrtFloat64x2))
   329  	addWasmSIMD("simd/archsimd", "Int8x16.Sub", makeSimdOp2(ssa.OpSubInt8x16))
   330  	addWasmSIMD("simd/archsimd", "Uint8x16.Sub", makeSimdOp2(ssa.OpSubUint8x16))
   331  	addWasmSIMD("simd/archsimd", "Int16x8.Sub", makeSimdOp2(ssa.OpSubInt16x8))
   332  	addWasmSIMD("simd/archsimd", "Uint16x8.Sub", makeSimdOp2(ssa.OpSubUint16x8))
   333  	addWasmSIMD("simd/archsimd", "Int32x4.Sub", makeSimdOp2(ssa.OpSubInt32x4))
   334  	addWasmSIMD("simd/archsimd", "Uint32x4.Sub", makeSimdOp2(ssa.OpSubUint32x4))
   335  	addWasmSIMD("simd/archsimd", "Float32x4.Sub", makeSimdOp2(ssa.OpSubFloat32x4))
   336  	addWasmSIMD("simd/archsimd", "Int64x2.Sub", makeSimdOp2(ssa.OpSubInt64x2))
   337  	addWasmSIMD("simd/archsimd", "Uint64x2.Sub", makeSimdOp2(ssa.OpSubUint64x2))
   338  	addWasmSIMD("simd/archsimd", "Float64x2.Sub", makeSimdOp2(ssa.OpSubFloat64x2))
   339  	addWasmSIMD("simd/archsimd", "Int8x16.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedInt8x16))
   340  	addWasmSIMD("simd/archsimd", "Uint8x16.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedUint8x16))
   341  	addWasmSIMD("simd/archsimd", "Int16x8.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedInt16x8))
   342  	addWasmSIMD("simd/archsimd", "Uint16x8.SubSaturated", makeSimdOp2(ssa.OpSubSaturatedUint16x8))
   343  	addWasmSIMD("simd/archsimd", "Float32x4.Trunc", makeSimdOp1(ssa.OpTruncFloat32x4))
   344  	addWasmSIMD("simd/archsimd", "Float64x2.Trunc", makeSimdOp1(ssa.OpTruncFloat64x2))
   345  	addWasmSIMD("simd/archsimd", "Int8x16.Xor", makeSimdOp2(ssa.OpXorInt8x16))
   346  	addWasmSIMD("simd/archsimd", "Uint8x16.Xor", makeSimdOp2(ssa.OpXorUint8x16))
   347  	addWasmSIMD("simd/archsimd", "Mask8x16.Xor", makeSimdOp2(ssa.OpXorInt8x16))
   348  	addWasmSIMD("simd/archsimd", "Int16x8.Xor", makeSimdOp2(ssa.OpXorInt16x8))
   349  	addWasmSIMD("simd/archsimd", "Uint16x8.Xor", makeSimdOp2(ssa.OpXorUint16x8))
   350  	addWasmSIMD("simd/archsimd", "Mask16x8.Xor", makeSimdOp2(ssa.OpXorInt16x8))
   351  	addWasmSIMD("simd/archsimd", "Int32x4.Xor", makeSimdOp2(ssa.OpXorInt32x4))
   352  	addWasmSIMD("simd/archsimd", "Uint32x4.Xor", makeSimdOp2(ssa.OpXorUint32x4))
   353  	addWasmSIMD("simd/archsimd", "Mask32x4.Xor", makeSimdOp2(ssa.OpXorInt32x4))
   354  	addWasmSIMD("simd/archsimd", "Int64x2.Xor", makeSimdOp2(ssa.OpXorInt64x2))
   355  	addWasmSIMD("simd/archsimd", "Uint64x2.Xor", makeSimdOp2(ssa.OpXorUint64x2))
   356  	addWasmSIMD("simd/archsimd", "Mask64x2.Xor", makeSimdOp2(ssa.OpXorInt64x2))
   357  	addWasmSIMD("simd/archsimd", "Int8x16.ToMask", makeToMask(ssa.OpNotEqualInt8x16, ssa.OpXorInt8x16))
   358  	addWasmSIMD("simd/archsimd", "Mask8x16.ToInt8x16", makeAsOp())
   359  	addWasmSIMD("simd/archsimd", "Int16x8.ToMask", makeToMask(ssa.OpNotEqualInt16x8, ssa.OpXorInt16x8))
   360  	addWasmSIMD("simd/archsimd", "Mask16x8.ToInt16x8", makeAsOp())
   361  	addWasmSIMD("simd/archsimd", "Int32x4.ToMask", makeToMask(ssa.OpNotEqualInt32x4, ssa.OpXorInt32x4))
   362  	addWasmSIMD("simd/archsimd", "Mask32x4.ToInt32x4", makeAsOp())
   363  	addWasmSIMD("simd/archsimd", "Int64x2.ToMask", makeToMask(ssa.OpNotEqualInt64x2, ssa.OpXorInt64x2))
   364  	addWasmSIMD("simd/archsimd", "Mask64x2.ToInt64x2", makeAsOp())
   365  	addWasmSIMD("simd/archsimd", "LoadInt8x16Array", simdLoad())
   366  	addWasmSIMD("simd/archsimd", "Int8x16.StoreArray", simdStore())
   367  	addWasmSIMD("simd/archsimd", "LoadInt16x8Array", simdLoad())
   368  	addWasmSIMD("simd/archsimd", "Int16x8.StoreArray", simdStore())
   369  	addWasmSIMD("simd/archsimd", "LoadInt32x4Array", simdLoad())
   370  	addWasmSIMD("simd/archsimd", "Int32x4.StoreArray", simdStore())
   371  	addWasmSIMD("simd/archsimd", "LoadInt64x2Array", simdLoad())
   372  	addWasmSIMD("simd/archsimd", "Int64x2.StoreArray", simdStore())
   373  	addWasmSIMD("simd/archsimd", "LoadUint8x16Array", simdLoad())
   374  	addWasmSIMD("simd/archsimd", "Uint8x16.StoreArray", simdStore())
   375  	addWasmSIMD("simd/archsimd", "LoadUint16x8Array", simdLoad())
   376  	addWasmSIMD("simd/archsimd", "Uint16x8.StoreArray", simdStore())
   377  	addWasmSIMD("simd/archsimd", "LoadUint32x4Array", simdLoad())
   378  	addWasmSIMD("simd/archsimd", "Uint32x4.StoreArray", simdStore())
   379  	addWasmSIMD("simd/archsimd", "LoadUint64x2Array", simdLoad())
   380  	addWasmSIMD("simd/archsimd", "Uint64x2.StoreArray", simdStore())
   381  	addWasmSIMD("simd/archsimd", "LoadFloat32x4Array", simdLoad())
   382  	addWasmSIMD("simd/archsimd", "Float32x4.StoreArray", simdStore())
   383  	addWasmSIMD("simd/archsimd", "LoadFloat64x2Array", simdLoad())
   384  	addWasmSIMD("simd/archsimd", "Float64x2.StoreArray", simdStore())
   385  	addWasmSIMD("simd/archsimd", "Int8x16.AsInt16x8", makeAsOp())
   386  	addWasmSIMD("simd/archsimd", "Int8x16.AsInt32x4", makeAsOp())
   387  	addWasmSIMD("simd/archsimd", "Int8x16.AsInt64x2", makeAsOp())
   388  	addWasmSIMD("simd/archsimd", "Int8x16.AsUint8x16", makeAsOp())
   389  	addWasmSIMD("simd/archsimd", "Int8x16.AsUint16x8", makeAsOp())
   390  	addWasmSIMD("simd/archsimd", "Int8x16.AsUint32x4", makeAsOp())
   391  	addWasmSIMD("simd/archsimd", "Int8x16.AsUint64x2", makeAsOp())
   392  	addWasmSIMD("simd/archsimd", "Int8x16.AsFloat32x4", makeAsOp())
   393  	addWasmSIMD("simd/archsimd", "Int8x16.AsFloat64x2", makeAsOp())
   394  	addWasmSIMD("simd/archsimd", "Int16x8.AsInt8x16", makeAsOp())
   395  	addWasmSIMD("simd/archsimd", "Int16x8.AsInt32x4", makeAsOp())
   396  	addWasmSIMD("simd/archsimd", "Int16x8.AsInt64x2", makeAsOp())
   397  	addWasmSIMD("simd/archsimd", "Int16x8.AsUint8x16", makeAsOp())
   398  	addWasmSIMD("simd/archsimd", "Int16x8.AsUint16x8", makeAsOp())
   399  	addWasmSIMD("simd/archsimd", "Int16x8.AsUint32x4", makeAsOp())
   400  	addWasmSIMD("simd/archsimd", "Int16x8.AsUint64x2", makeAsOp())
   401  	addWasmSIMD("simd/archsimd", "Int16x8.AsFloat32x4", makeAsOp())
   402  	addWasmSIMD("simd/archsimd", "Int16x8.AsFloat64x2", makeAsOp())
   403  	addWasmSIMD("simd/archsimd", "Int32x4.AsInt8x16", makeAsOp())
   404  	addWasmSIMD("simd/archsimd", "Int32x4.AsInt16x8", makeAsOp())
   405  	addWasmSIMD("simd/archsimd", "Int32x4.AsInt64x2", makeAsOp())
   406  	addWasmSIMD("simd/archsimd", "Int32x4.AsUint8x16", makeAsOp())
   407  	addWasmSIMD("simd/archsimd", "Int32x4.AsUint16x8", makeAsOp())
   408  	addWasmSIMD("simd/archsimd", "Int32x4.AsUint32x4", makeAsOp())
   409  	addWasmSIMD("simd/archsimd", "Int32x4.AsUint64x2", makeAsOp())
   410  	addWasmSIMD("simd/archsimd", "Int32x4.AsFloat32x4", makeAsOp())
   411  	addWasmSIMD("simd/archsimd", "Int32x4.AsFloat64x2", makeAsOp())
   412  	addWasmSIMD("simd/archsimd", "Int64x2.AsInt8x16", makeAsOp())
   413  	addWasmSIMD("simd/archsimd", "Int64x2.AsInt16x8", makeAsOp())
   414  	addWasmSIMD("simd/archsimd", "Int64x2.AsInt32x4", makeAsOp())
   415  	addWasmSIMD("simd/archsimd", "Int64x2.AsUint8x16", makeAsOp())
   416  	addWasmSIMD("simd/archsimd", "Int64x2.AsUint16x8", makeAsOp())
   417  	addWasmSIMD("simd/archsimd", "Int64x2.AsUint32x4", makeAsOp())
   418  	addWasmSIMD("simd/archsimd", "Int64x2.AsUint64x2", makeAsOp())
   419  	addWasmSIMD("simd/archsimd", "Int64x2.AsFloat32x4", makeAsOp())
   420  	addWasmSIMD("simd/archsimd", "Int64x2.AsFloat64x2", makeAsOp())
   421  	addWasmSIMD("simd/archsimd", "Uint8x16.AsInt8x16", makeAsOp())
   422  	addWasmSIMD("simd/archsimd", "Uint8x16.AsInt16x8", makeAsOp())
   423  	addWasmSIMD("simd/archsimd", "Uint8x16.AsInt32x4", makeAsOp())
   424  	addWasmSIMD("simd/archsimd", "Uint8x16.AsInt64x2", makeAsOp())
   425  	addWasmSIMD("simd/archsimd", "Uint8x16.AsUint16x8", makeAsOp())
   426  	addWasmSIMD("simd/archsimd", "Uint8x16.AsUint32x4", makeAsOp())
   427  	addWasmSIMD("simd/archsimd", "Uint8x16.AsUint64x2", makeAsOp())
   428  	addWasmSIMD("simd/archsimd", "Uint8x16.AsFloat32x4", makeAsOp())
   429  	addWasmSIMD("simd/archsimd", "Uint8x16.AsFloat64x2", makeAsOp())
   430  	addWasmSIMD("simd/archsimd", "Uint16x8.AsInt8x16", makeAsOp())
   431  	addWasmSIMD("simd/archsimd", "Uint16x8.AsInt16x8", makeAsOp())
   432  	addWasmSIMD("simd/archsimd", "Uint16x8.AsInt32x4", makeAsOp())
   433  	addWasmSIMD("simd/archsimd", "Uint16x8.AsInt64x2", makeAsOp())
   434  	addWasmSIMD("simd/archsimd", "Uint16x8.AsUint8x16", makeAsOp())
   435  	addWasmSIMD("simd/archsimd", "Uint16x8.AsUint32x4", makeAsOp())
   436  	addWasmSIMD("simd/archsimd", "Uint16x8.AsUint64x2", makeAsOp())
   437  	addWasmSIMD("simd/archsimd", "Uint16x8.AsFloat32x4", makeAsOp())
   438  	addWasmSIMD("simd/archsimd", "Uint16x8.AsFloat64x2", makeAsOp())
   439  	addWasmSIMD("simd/archsimd", "Uint32x4.AsInt8x16", makeAsOp())
   440  	addWasmSIMD("simd/archsimd", "Uint32x4.AsInt16x8", makeAsOp())
   441  	addWasmSIMD("simd/archsimd", "Uint32x4.AsInt32x4", makeAsOp())
   442  	addWasmSIMD("simd/archsimd", "Uint32x4.AsInt64x2", makeAsOp())
   443  	addWasmSIMD("simd/archsimd", "Uint32x4.AsUint8x16", makeAsOp())
   444  	addWasmSIMD("simd/archsimd", "Uint32x4.AsUint16x8", makeAsOp())
   445  	addWasmSIMD("simd/archsimd", "Uint32x4.AsUint64x2", makeAsOp())
   446  	addWasmSIMD("simd/archsimd", "Uint32x4.AsFloat32x4", makeAsOp())
   447  	addWasmSIMD("simd/archsimd", "Uint32x4.AsFloat64x2", makeAsOp())
   448  	addWasmSIMD("simd/archsimd", "Uint64x2.AsInt8x16", makeAsOp())
   449  	addWasmSIMD("simd/archsimd", "Uint64x2.AsInt16x8", makeAsOp())
   450  	addWasmSIMD("simd/archsimd", "Uint64x2.AsInt32x4", makeAsOp())
   451  	addWasmSIMD("simd/archsimd", "Uint64x2.AsInt64x2", makeAsOp())
   452  	addWasmSIMD("simd/archsimd", "Uint64x2.AsUint8x16", makeAsOp())
   453  	addWasmSIMD("simd/archsimd", "Uint64x2.AsUint16x8", makeAsOp())
   454  	addWasmSIMD("simd/archsimd", "Uint64x2.AsUint32x4", makeAsOp())
   455  	addWasmSIMD("simd/archsimd", "Uint64x2.AsFloat32x4", makeAsOp())
   456  	addWasmSIMD("simd/archsimd", "Uint64x2.AsFloat64x2", makeAsOp())
   457  	addWasmSIMD("simd/archsimd", "Float32x4.AsInt8x16", makeAsOp())
   458  	addWasmSIMD("simd/archsimd", "Float32x4.AsInt16x8", makeAsOp())
   459  	addWasmSIMD("simd/archsimd", "Float32x4.AsInt32x4", makeAsOp())
   460  	addWasmSIMD("simd/archsimd", "Float32x4.AsInt64x2", makeAsOp())
   461  	addWasmSIMD("simd/archsimd", "Float32x4.AsUint8x16", makeAsOp())
   462  	addWasmSIMD("simd/archsimd", "Float32x4.AsUint16x8", makeAsOp())
   463  	addWasmSIMD("simd/archsimd", "Float32x4.AsUint32x4", makeAsOp())
   464  	addWasmSIMD("simd/archsimd", "Float32x4.AsUint64x2", makeAsOp())
   465  	addWasmSIMD("simd/archsimd", "Float32x4.AsFloat64x2", makeAsOp())
   466  	addWasmSIMD("simd/archsimd", "Float64x2.AsInt8x16", makeAsOp())
   467  	addWasmSIMD("simd/archsimd", "Float64x2.AsInt16x8", makeAsOp())
   468  	addWasmSIMD("simd/archsimd", "Float64x2.AsInt32x4", makeAsOp())
   469  	addWasmSIMD("simd/archsimd", "Float64x2.AsInt64x2", makeAsOp())
   470  	addWasmSIMD("simd/archsimd", "Float64x2.AsUint8x16", makeAsOp())
   471  	addWasmSIMD("simd/archsimd", "Float64x2.AsUint16x8", makeAsOp())
   472  	addWasmSIMD("simd/archsimd", "Float64x2.AsUint32x4", makeAsOp())
   473  	addWasmSIMD("simd/archsimd", "Float64x2.AsUint64x2", makeAsOp())
   474  	addWasmSIMD("simd/archsimd", "Float64x2.AsFloat32x4", makeAsOp())
   475  	addWasmSIMD("simd/archsimd", "Uint32x4.BitsToFloat32", makeAsOp())
   476  	addWasmSIMD("simd/archsimd", "Float32x4.ToBits", makeAsOp())
   477  	addWasmSIMD("simd/archsimd", "Uint64x2.BitsToFloat64", makeAsOp())
   478  	addWasmSIMD("simd/archsimd", "Float64x2.ToBits", makeAsOp())
   479  	addWasmSIMD("simd/archsimd", "Uint8x16.BitsToInt8", makeAsOp())
   480  	addWasmSIMD("simd/archsimd", "Uint8x16.ConvertToInt8", makeAsOp())
   481  	addWasmSIMD("simd/archsimd", "Int8x16.ConvertToUint8", makeAsOp())
   482  	addWasmSIMD("simd/archsimd", "Int8x16.ToBits", makeAsOp())
   483  	addWasmSIMD("simd/archsimd", "Uint16x8.BitsToInt16", makeAsOp())
   484  	addWasmSIMD("simd/archsimd", "Uint16x8.ConvertToInt16", makeAsOp())
   485  	addWasmSIMD("simd/archsimd", "Int16x8.ConvertToUint16", makeAsOp())
   486  	addWasmSIMD("simd/archsimd", "Int16x8.ToBits", makeAsOp())
   487  	addWasmSIMD("simd/archsimd", "Uint32x4.BitsToInt32", makeAsOp())
   488  	addWasmSIMD("simd/archsimd", "Uint32x4.ConvertToInt32", makeAsOp())
   489  	addWasmSIMD("simd/archsimd", "Int32x4.ConvertToUint32", makeAsOp())
   490  	addWasmSIMD("simd/archsimd", "Int32x4.ToBits", makeAsOp())
   491  	addWasmSIMD("simd/archsimd", "Uint64x2.BitsToInt64", makeAsOp())
   492  	addWasmSIMD("simd/archsimd", "Uint64x2.ConvertToInt64", makeAsOp())
   493  	addWasmSIMD("simd/archsimd", "Int64x2.ConvertToUint64", makeAsOp())
   494  	addWasmSIMD("simd/archsimd", "Int64x2.ToBits", makeAsOp())
   495  	addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint16s", makeAsOp())
   496  	addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint32s", makeAsOp())
   497  	addWasmSIMD("simd/archsimd", "Uint8x16.ReshapeToUint64s", makeAsOp())
   498  	addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint8s", makeAsOp())
   499  	addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint32s", makeAsOp())
   500  	addWasmSIMD("simd/archsimd", "Uint16x8.ReshapeToUint64s", makeAsOp())
   501  	addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint8s", makeAsOp())
   502  	addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint16s", makeAsOp())
   503  	addWasmSIMD("simd/archsimd", "Uint32x4.ReshapeToUint64s", makeAsOp())
   504  	addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint8s", makeAsOp())
   505  	addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint16s", makeAsOp())
   506  	addWasmSIMD("simd/archsimd", "Uint64x2.ReshapeToUint32s", makeAsOp())
   507  }
   508  

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