a.out.go

     1  // cmd/7c/7.out.h  from Vita Nuova.
     2  // https://bitbucket.org/plan9-from-bell-labs/9-cc/src/master/src/cmd/7c/7.out.h
     3  //
     4  // 	Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
     5  // 	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     6  // 	Portions Copyright © 1997-1999 Vita Nuova Limited
     7  // 	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
     8  // 	Portions Copyright © 2004,2006 Bruce Ellis
     9  // 	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
    10  // 	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
    11  // 	Portions Copyright © 2009 The Go Authors. All rights reserved.
    12  //
    13  // Permission is hereby granted, free of charge, to any person obtaining a copy
    14  // of this software and associated documentation files (the "Software"), to deal
    15  // in the Software without restriction, including without limitation the rights
    16  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    17  // copies of the Software, and to permit persons to whom the Software is
    18  // furnished to do so, subject to the following conditions:
    19  //
    20  // The above copyright notice and this permission notice shall be included in
    21  // all copies or substantial portions of the Software.
    22  //
    23  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    24  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    25  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    26  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    27  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    28  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    29  // THE SOFTWARE.
    30  
    31  package arm64
    32  
    33  import "cmd/internal/obj"
    34  
    35  const (
    36  	NSNAME = 8
    37  	NSYM   = 50
    38  	NREG   = 32 /* number of general registers */
    39  	NFREG  = 32 /* number of floating point registers */
    40  )
    41  
    42  // General purpose registers, kept in the low bits of Prog.Reg.
    43  const (
    44  	// integer
    45  	REG_R0 = obj.RBaseARM64 + iota
    46  	REG_R1
    47  	REG_R2
    48  	REG_R3
    49  	REG_R4
    50  	REG_R5
    51  	REG_R6
    52  	REG_R7
    53  	REG_R8
    54  	REG_R9
    55  	REG_R10
    56  	REG_R11
    57  	REG_R12
    58  	REG_R13
    59  	REG_R14
    60  	REG_R15
    61  	REG_R16
    62  	REG_R17
    63  	REG_R18
    64  	REG_R19
    65  	REG_R20
    66  	REG_R21
    67  	REG_R22
    68  	REG_R23
    69  	REG_R24
    70  	REG_R25
    71  	REG_R26
    72  	REG_R27
    73  	REG_R28
    74  	REG_R29
    75  	REG_R30
    76  	REG_R31
    77  
    78  	// scalar floating point
    79  	REG_F0
    80  	REG_F1
    81  	REG_F2
    82  	REG_F3
    83  	REG_F4
    84  	REG_F5
    85  	REG_F6
    86  	REG_F7
    87  	REG_F8
    88  	REG_F9
    89  	REG_F10
    90  	REG_F11
    91  	REG_F12
    92  	REG_F13
    93  	REG_F14
    94  	REG_F15
    95  	REG_F16
    96  	REG_F17
    97  	REG_F18
    98  	REG_F19
    99  	REG_F20
   100  	REG_F21
   101  	REG_F22
   102  	REG_F23
   103  	REG_F24
   104  	REG_F25
   105  	REG_F26
   106  	REG_F27
   107  	REG_F28
   108  	REG_F29
   109  	REG_F30
   110  	REG_F31
   111  
   112  	// SIMD
   113  	REG_V0
   114  	REG_V1
   115  	REG_V2
   116  	REG_V3
   117  	REG_V4
   118  	REG_V5
   119  	REG_V6
   120  	REG_V7
   121  	REG_V8
   122  	REG_V9
   123  	REG_V10
   124  	REG_V11
   125  	REG_V12
   126  	REG_V13
   127  	REG_V14
   128  	REG_V15
   129  	REG_V16
   130  	REG_V17
   131  	REG_V18
   132  	REG_V19
   133  	REG_V20
   134  	REG_V21
   135  	REG_V22
   136  	REG_V23
   137  	REG_V24
   138  	REG_V25
   139  	REG_V26
   140  	REG_V27
   141  	REG_V28
   142  	REG_V29
   143  	REG_V30
   144  	REG_V31
   145  
   146  	// SVE (Scalable Vector Extension) scalable vector registers
   147  	// The order matters, make sure that each
   148  	// kind of register starts numbering from the lowest bit.
   149  	REG_Z0
   150  	REG_Z1
   151  	REG_Z2
   152  	REG_Z3
   153  	REG_Z4
   154  	REG_Z5
   155  	REG_Z6
   156  	REG_Z7
   157  	REG_Z8
   158  	REG_Z9
   159  	REG_Z10
   160  	REG_Z11
   161  	REG_Z12
   162  	REG_Z13
   163  	REG_Z14
   164  	REG_Z15
   165  	REG_Z16
   166  	REG_Z17
   167  	REG_Z18
   168  	REG_Z19
   169  	REG_Z20
   170  	REG_Z21
   171  	REG_Z22
   172  	REG_Z23
   173  	REG_Z24
   174  	REG_Z25
   175  	REG_Z26
   176  	REG_Z27
   177  	REG_Z28
   178  	REG_Z29
   179  	REG_Z30
   180  	REG_Z31
   181  
   182  	REG_P0
   183  	REG_P1
   184  	REG_P2
   185  	REG_P3
   186  	REG_P4
   187  	REG_P5
   188  	REG_P6
   189  	REG_P7
   190  	REG_P8
   191  	REG_P9
   192  	REG_P10
   193  	REG_P11
   194  	REG_P12
   195  	REG_P13
   196  	REG_P14
   197  	REG_P15
   198  
   199  	REG_PN0
   200  	REG_PN1
   201  	REG_PN2
   202  	REG_PN3
   203  	REG_PN4
   204  	REG_PN5
   205  	REG_PN6
   206  	REG_PN7
   207  	REG_PN8
   208  	REG_PN9
   209  	REG_PN10
   210  	REG_PN11
   211  	REG_PN12
   212  	REG_PN13
   213  	REG_PN14
   214  	REG_PN15
   215  
   216  	REG_RSP = (REG_PN15 + 1) | 0x1f // to differentiate ZR/SP, REG_RSP&0x1f = 31
   217  )
   218  
   219  // bits 0-4 indicates register: Vn
   220  // bits 5-8 indicates arrangement: <T>
   221  // TODO: consider putting the register and arrangement in different fields of an
   222  // [obj.Prog] to make the bit pattern less confusing.
   223  const (
   224  	REG_ARNG      = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
   225  	REG_ELEM                                         // Vn.<T>[index]
   226  	REG_ZARNG                                        // Zn.<T>
   227  	REG_ZARNGELEM                                    // Zn.<T>[index]
   228  	// PZELEM is taking a portion of the P or Z register.
   229  	// Since it does not have an arrangement, it interpret bit 5 differently:
   230  	// bit 5 = 0: Z register
   231  	// bit 5 = 1: P register
   232  	REG_PZELEM  // Zn[index] or Pn[index] or PNd[index]
   233  	REG_PARNGZM // Pn.<T> or Pn/M, Pn/Z
   234  	// This currently overlaps with REG_EXT, if more arrangements are to be added,
   235  	// move REG_EXT to a higher range and update RBase.*.
   236  	REG_PARNGZM_END
   237  )
   238  
   239  // Not registers, but flags that can be combined with regular register
   240  // constants to indicate extended register conversion. When checking,
   241  // you should subtract obj.RBaseARM64 first. From this difference, bit 12
   242  // indicates extended register, bits 8-10 select the conversion mode.
   243  // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.
   244  const REG_LSL = obj.RBaseARM64 + 1<<9
   245  const REG_EXT = obj.RBaseARM64 + 1<<12
   246  
   247  const (
   248  	REG_UXTB = REG_EXT + iota<<8
   249  	REG_UXTH
   250  	REG_UXTW
   251  	REG_UXTX
   252  	REG_SXTB
   253  	REG_SXTH
   254  	REG_SXTW
   255  	REG_SXTX
   256  )
   257  
   258  // Special registers, after subtracting obj.RBaseARM64, bit 13 indicates
   259  // a special register and the low bits select the register.
   260  // SYSREG_END is the last item in the automatically generated system register
   261  // declaration, and it is defined in the sysRegEnc.go file.
   262  // Define the special register after REG_SPECIAL, the first value of it should be
   263  // REG_{name} = SYSREG_END + iota.
   264  const (
   265  	REG_SPECIAL = obj.RBaseARM64 + 1<<13
   266  )
   267  
   268  // Register assignments:
   269  //
   270  // compiler allocates R0 up as temps
   271  // compiler allocates register variables R7-R25
   272  // compiler allocates external registers R26 down
   273  //
   274  // compiler allocates register variables F7-F26
   275  // compiler allocates external registers F26 down
   276  const (
   277  	REGMIN = REG_R7  // register variables allocated from here to REGMAX
   278  	REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scratch register in trampoline
   279  	REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scratch register in trampoline
   280  	REGPR  = REG_R18 // ARM64 platform register, unused in the Go toolchain
   281  	REGMAX = REG_R25
   282  
   283  	REGCTXT = REG_R26 // environment for closures
   284  	REGTMP  = REG_R27 // reserved for liblink
   285  	REGG    = REG_R28 // G
   286  	REGFP   = REG_R29 // frame pointer
   287  	REGLINK = REG_R30
   288  
   289  	// ARM64 uses R31 as both stack pointer and zero register,
   290  	// depending on the instruction. To differentiate RSP from ZR,
   291  	// we use a different numeric value for REGZERO and REGSP.
   292  	REGZERO = REG_R31
   293  	REGSP   = REG_RSP
   294  
   295  	FREGRET = REG_F0
   296  	FREGMIN = REG_F7  // first register variable
   297  	FREGMAX = REG_F26 // last register variable for 7g only
   298  	FREGEXT = REG_F26 // first external register
   299  )
   300  
   301  // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf
   302  var ARM64DWARFRegisters = map[int16]int16{
   303  	REG_R0:  0,
   304  	REG_R1:  1,
   305  	REG_R2:  2,
   306  	REG_R3:  3,
   307  	REG_R4:  4,
   308  	REG_R5:  5,
   309  	REG_R6:  6,
   310  	REG_R7:  7,
   311  	REG_R8:  8,
   312  	REG_R9:  9,
   313  	REG_R10: 10,
   314  	REG_R11: 11,
   315  	REG_R12: 12,
   316  	REG_R13: 13,
   317  	REG_R14: 14,
   318  	REG_R15: 15,
   319  	REG_R16: 16,
   320  	REG_R17: 17,
   321  	REG_R18: 18,
   322  	REG_R19: 19,
   323  	REG_R20: 20,
   324  	REG_R21: 21,
   325  	REG_R22: 22,
   326  	REG_R23: 23,
   327  	REG_R24: 24,
   328  	REG_R25: 25,
   329  	REG_R26: 26,
   330  	REG_R27: 27,
   331  	REG_R28: 28,
   332  	REG_R29: 29,
   333  	REG_R30: 30,
   334  
   335  	// SVE predicate registers
   336  	REG_P0:  48,
   337  	REG_P1:  49,
   338  	REG_P2:  50,
   339  	REG_P3:  51,
   340  	REG_P4:  52,
   341  	REG_P5:  53,
   342  	REG_P6:  54,
   343  	REG_P7:  55,
   344  	REG_P8:  56,
   345  	REG_P9:  57,
   346  	REG_P10: 58,
   347  	REG_P11: 59,
   348  	REG_P12: 60,
   349  	REG_P13: 61,
   350  	REG_P14: 62,
   351  	REG_P15: 63,
   352  
   353  	// floating point
   354  	REG_F0:  64,
   355  	REG_F1:  65,
   356  	REG_F2:  66,
   357  	REG_F3:  67,
   358  	REG_F4:  68,
   359  	REG_F5:  69,
   360  	REG_F6:  70,
   361  	REG_F7:  71,
   362  	REG_F8:  72,
   363  	REG_F9:  73,
   364  	REG_F10: 74,
   365  	REG_F11: 75,
   366  	REG_F12: 76,
   367  	REG_F13: 77,
   368  	REG_F14: 78,
   369  	REG_F15: 79,
   370  	REG_F16: 80,
   371  	REG_F17: 81,
   372  	REG_F18: 82,
   373  	REG_F19: 83,
   374  	REG_F20: 84,
   375  	REG_F21: 85,
   376  	REG_F22: 86,
   377  	REG_F23: 87,
   378  	REG_F24: 88,
   379  	REG_F25: 89,
   380  	REG_F26: 90,
   381  	REG_F27: 91,
   382  	REG_F28: 92,
   383  	REG_F29: 93,
   384  	REG_F30: 94,
   385  	REG_F31: 95,
   386  
   387  	// SIMD
   388  	REG_V0:  64,
   389  	REG_V1:  65,
   390  	REG_V2:  66,
   391  	REG_V3:  67,
   392  	REG_V4:  68,
   393  	REG_V5:  69,
   394  	REG_V6:  70,
   395  	REG_V7:  71,
   396  	REG_V8:  72,
   397  	REG_V9:  73,
   398  	REG_V10: 74,
   399  	REG_V11: 75,
   400  	REG_V12: 76,
   401  	REG_V13: 77,
   402  	REG_V14: 78,
   403  	REG_V15: 79,
   404  	REG_V16: 80,
   405  	REG_V17: 81,
   406  	REG_V18: 82,
   407  	REG_V19: 83,
   408  	REG_V20: 84,
   409  	REG_V21: 85,
   410  	REG_V22: 86,
   411  	REG_V23: 87,
   412  	REG_V24: 88,
   413  	REG_V25: 89,
   414  	REG_V26: 90,
   415  	REG_V27: 91,
   416  	REG_V28: 92,
   417  	REG_V29: 93,
   418  	REG_V30: 94,
   419  	REG_V31: 95,
   420  
   421  	// SVE vector registers
   422  	REG_Z0:  96,
   423  	REG_Z1:  97,
   424  	REG_Z2:  98,
   425  	REG_Z3:  99,
   426  	REG_Z4:  100,
   427  	REG_Z5:  101,
   428  	REG_Z6:  102,
   429  	REG_Z7:  103,
   430  	REG_Z8:  104,
   431  	REG_Z9:  105,
   432  	REG_Z10: 106,
   433  	REG_Z11: 107,
   434  	REG_Z12: 108,
   435  	REG_Z13: 109,
   436  	REG_Z14: 110,
   437  	REG_Z15: 111,
   438  	REG_Z16: 112,
   439  	REG_Z17: 113,
   440  	REG_Z18: 114,
   441  	REG_Z19: 115,
   442  	REG_Z20: 116,
   443  	REG_Z21: 117,
   444  	REG_Z22: 118,
   445  	REG_Z23: 119,
   446  	REG_Z24: 120,
   447  	REG_Z25: 121,
   448  	REG_Z26: 122,
   449  	REG_Z27: 123,
   450  	REG_Z28: 124,
   451  	REG_Z29: 125,
   452  	REG_Z30: 126,
   453  	REG_Z31: 127,
   454  }
   455  
   456  const (
   457  	BIG = 2048 - 8
   458  )
   459  
   460  const (
   461  	/* mark flags */
   462  	LABEL = 1 << iota
   463  	LEAF
   464  	FLOAT
   465  	BRANCH
   466  	LOAD
   467  	FCMP
   468  	SYNC
   469  	LIST
   470  	FOLL
   471  	NOSCHED
   472  )
   473  
   474  //go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64
   475  const (
   476  	// optab is sorted based on the order of these constants
   477  	// and the first match is chosen.
   478  	// The more specific class needs to come earlier.
   479  	C_NONE   = iota + 1 // starting from 1, leave unclassified Addr's class as 0
   480  	C_REG               // R0..R30
   481  	C_ZREG              // R0..R30, ZR
   482  	C_RSP               // R0..R30, RSP
   483  	C_FREG              // F0..F31
   484  	C_VREG              // V0..V31
   485  	C_PAIR              // (Rn, Rm)
   486  	C_SHIFT             // Rn<<2
   487  	C_EXTREG            // Rn.UXTB[<<3]
   488  	C_SPR               // REG_NZCV
   489  	C_COND              // condition code, EQ, NE, etc.
   490  	C_SPOP              // special operand, PLDL1KEEP, VMALLE1IS, etc.
   491  	C_ARNG              // Vn.<T>
   492  	C_ELEM              // Vn.<T>[index]
   493  	C_LIST              // [V1, V2, V3]
   494  
   495  	C_ZCON     // $0
   496  	C_ABCON0   // could be C_ADDCON0 or C_BITCON
   497  	C_ADDCON0  // 12-bit unsigned, unshifted
   498  	C_ABCON    // could be C_ADDCON or C_BITCON
   499  	C_AMCON    // could be C_ADDCON or C_MOVCON
   500  	C_ADDCON   // 12-bit unsigned, shifted left by 0 or 12
   501  	C_MBCON    // could be C_MOVCON or C_BITCON
   502  	C_MOVCON   // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
   503  	C_BITCON   // bitfield and logical immediate masks
   504  	C_ADDCON2  // 24-bit constant
   505  	C_LCON     // 32-bit constant
   506  	C_MOVCON2  // a constant that can be loaded with one MOVZ/MOVN and one MOVK
   507  	C_MOVCON3  // a constant that can be loaded with one MOVZ/MOVN and two MOVKs
   508  	C_VCON     // 64-bit constant
   509  	C_FCON     // floating-point constant
   510  	C_VCONADDR // 64-bit memory address
   511  
   512  	C_AACON  // ADDCON offset in auto constant $a(FP)
   513  	C_AACON2 // 24-bit offset in auto constant $a(FP)
   514  	C_LACON  // 32-bit offset in auto constant $a(FP)
   515  	C_AECON  // ADDCON offset in extern constant $e(SB)
   516  
   517  	// TODO(aram): only one branch class should be enough
   518  	C_SBRA // for TYPE_BRANCH
   519  	C_LBRA
   520  
   521  	C_ZAUTO       // 0(RSP)
   522  	C_NSAUTO_16   // -256 <= x < 0, 0 mod 16
   523  	C_NSAUTO_8    // -256 <= x < 0, 0 mod 8
   524  	C_NSAUTO_4    // -256 <= x < 0, 0 mod 4
   525  	C_NSAUTO      // -256 <= x < 0
   526  	C_NPAUTO_16   // -512 <= x < 0, 0 mod 16
   527  	C_NPAUTO      // -512 <= x < 0, 0 mod 8
   528  	C_NQAUTO_16   // -1024 <= x < 0, 0 mod 16
   529  	C_NAUTO4K     // -4095 <= x < 0
   530  	C_PSAUTO_16   // 0 to 255, 0 mod 16
   531  	C_PSAUTO_8    // 0 to 255, 0 mod 8
   532  	C_PSAUTO_4    // 0 to 255, 0 mod 4
   533  	C_PSAUTO      // 0 to 255
   534  	C_PPAUTO_16   // 0 to 504, 0 mod 16
   535  	C_PPAUTO      // 0 to 504, 0 mod 8
   536  	C_PQAUTO_16   // 0 to 1008, 0 mod 16
   537  	C_UAUTO4K_16  // 0 to 4095, 0 mod 16
   538  	C_UAUTO4K_8   // 0 to 4095, 0 mod 8
   539  	C_UAUTO4K_4   // 0 to 4095, 0 mod 4
   540  	C_UAUTO4K_2   // 0 to 4095, 0 mod 2
   541  	C_UAUTO4K     // 0 to 4095
   542  	C_UAUTO8K_16  // 0 to 8190, 0 mod 16
   543  	C_UAUTO8K_8   // 0 to 8190, 0 mod 8
   544  	C_UAUTO8K_4   // 0 to 8190, 0 mod 4
   545  	C_UAUTO8K     // 0 to 8190, 0 mod 2  + C_PSAUTO
   546  	C_UAUTO16K_16 // 0 to 16380, 0 mod 16
   547  	C_UAUTO16K_8  // 0 to 16380, 0 mod 8
   548  	C_UAUTO16K    // 0 to 16380, 0 mod 4 + C_PSAUTO
   549  	C_UAUTO32K_16 // 0 to 32760, 0 mod 16 + C_PSAUTO
   550  	C_UAUTO32K    // 0 to 32760, 0 mod 8 + C_PSAUTO
   551  	C_UAUTO64K    // 0 to 65520, 0 mod 16 + C_PSAUTO
   552  	C_LAUTOPOOL   // any other constant up to 64 bits (needs pool literal)
   553  	C_LAUTO       // any other constant up to 64 bits
   554  
   555  	C_SEXT1  // 0 to 4095, direct
   556  	C_SEXT2  // 0 to 8190
   557  	C_SEXT4  // 0 to 16380
   558  	C_SEXT8  // 0 to 32760
   559  	C_SEXT16 // 0 to 65520
   560  	C_LEXT
   561  
   562  	C_ZOREG     // 0(R)
   563  	C_NSOREG_16 // must mirror C_NSAUTO_16, etc
   564  	C_NSOREG_8
   565  	C_NSOREG_4
   566  	C_NSOREG
   567  	C_NPOREG_16
   568  	C_NPOREG
   569  	C_NQOREG_16
   570  	C_NOREG4K
   571  	C_PSOREG_16
   572  	C_PSOREG_8
   573  	C_PSOREG_4
   574  	C_PSOREG
   575  	C_PPOREG_16
   576  	C_PPOREG
   577  	C_PQOREG_16
   578  	C_UOREG4K_16
   579  	C_UOREG4K_8
   580  	C_UOREG4K_4
   581  	C_UOREG4K_2
   582  	C_UOREG4K
   583  	C_UOREG8K_16
   584  	C_UOREG8K_8
   585  	C_UOREG8K_4
   586  	C_UOREG8K
   587  	C_UOREG16K_16
   588  	C_UOREG16K_8
   589  	C_UOREG16K
   590  	C_UOREG32K_16
   591  	C_UOREG32K
   592  	C_UOREG64K
   593  	C_LOREGPOOL
   594  	C_LOREG
   595  
   596  	C_ADDR // TODO(aram): explain difference from C_VCONADDR
   597  
   598  	// The GOT slot for a symbol in -dynlink mode.
   599  	C_GOTADDR
   600  
   601  	// TLS "var" in local exec mode: will become a constant offset from
   602  	// thread local base that is ultimately chosen by the program linker.
   603  	C_TLS_LE
   604  
   605  	// TLS "var" in initial exec mode: will become a memory address (chosen
   606  	// by the program linker) that the dynamic linker will fill with the
   607  	// offset from the thread local base.
   608  	C_TLS_IE
   609  
   610  	C_ROFF // register offset (including register extended)
   611  
   612  	C_GOK
   613  	C_TEXTSIZE
   614  	C_NCLASS // must be last
   615  )
   616  
   617  const (
   618  	C_XPRE  = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
   619  	C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
   620  )
   621  
   622  type AClass uint16 // operand type
   623  
   624  // [insts] is sorted based on the order of these constants and the first match is chosen.
   625  const (
   626  	AC_NONE AClass = iota
   627  	// TODO: probably make this AClass split into AC_REG (R0...R30), AC_RSP (R0...R30, RSP), AC_ZR (R0...R30, ZR).
   628  	AC_SPZGREG // general purpose registers R0..R30 and RSP and ZR
   629  	AC_VREG    // vector registers, such as V1
   630  	AC_ZREG    // the scalable vector registers, such as Z1
   631  	AC_PREG    // the scalable predicate registers, such as P1
   632  	AC_PREGZM  // Pg.Z or Pg.M
   633  	AC_PREGIDX // P8[1] or PN1[1] or Z1[1]
   634  	AC_ZREGIDX // P8[1] or PN1[1] or Z1[1]
   635  	AC_PREGSEL // P0[R1, 1], index is calculated as R1 + 1
   636  	AC_ARNG    // vector register with arrangement, such as Z1.D
   637  	AC_ARNGIDX // vector register with arrangement and index, such as Z1.D[1]
   638  
   639  	AC_IMM // constants
   640  
   641  	AC_REGLIST1      // list of 1 vector register, such as [Z1]
   642  	AC_REGLIST2      // list of 2 vector registers, such as [Z0, Z8]
   643  	AC_REGLIST3      // list of 3 vector registers, such as [Z1, Z2, Z3]
   644  	AC_REGLIST4      // list of 4 vector registers, such as [Z0, Z4, Z8, Z12]
   645  	AC_REGLIST_RANGE // list of vector register lists in range format, such as [Z0-Z4].
   646  
   647  	AC_MEMOFF      // address with optional constant offset, the offset is an immediate, such as 4(Z1.D)
   648  	AC_MEMOFFMULVL // address with optional constant offset, the offset is an immediate multiplied by the vector's in-memory size, such as (2*VL)(Z1.D)
   649  	AC_MEMEXT      // address with register offset with extensions, such as (Z2.D.UXTW<<3)(RSP)
   650  
   651  	AC_PREG_PATTERN // register with pattern, such as VL1*3(P1.D)
   652  	AC_REG_PATTERN  // register with pattern, such as VL1*3(R1)
   653  	AC_ZREG_PATTERN // register with pattern, such as VL1*3(Z1.D)
   654  
   655  	AC_SPECIAL // VL*i pattern, one of: VL*2, VL*4, or prefetch pattern, such as PLDL1KEEP, more patterns might come in the future.
   656  )
   657  
   658  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
   659  
   660  const (
   661  	AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
   662  	AADCS
   663  	AADCSW
   664  	AADCW
   665  	AADD
   666  	AADDS
   667  	AADDSW
   668  	AADDW
   669  	AADR
   670  	AADRP
   671  	AAESD
   672  	AAESE
   673  	AAESIMC
   674  	AAESMC
   675  	AAND
   676  	AANDS
   677  	AANDSW
   678  	AANDW
   679  	AASR
   680  	AASRW
   681  	AAT
   682  	ABCC
   683  	ABCS
   684  	ABEQ
   685  	ABFI
   686  	ABFIW
   687  	ABFM
   688  	ABFMW
   689  	ABFXIL
   690  	ABFXILW
   691  	ABGE
   692  	ABGT
   693  	ABHI
   694  	ABHS
   695  	ABIC
   696  	ABICS
   697  	ABICSW
   698  	ABICW
   699  	ABLE
   700  	ABLO
   701  	ABLS
   702  	ABLT
   703  	ABMI
   704  	ABNE
   705  	ABPL
   706  	ABRK
   707  	ABVC
   708  	ABVS
   709  	ACASAD
   710  	ACASALB
   711  	ACASALD
   712  	ACASALH
   713  	ACASALW
   714  	ACASAW
   715  	ACASB
   716  	ACASD
   717  	ACASH
   718  	ACASLD
   719  	ACASLW
   720  	ACASPAD
   721  	ACASPALD
   722  	ACASPALW
   723  	ACASPAW
   724  	ACASPD
   725  	ACASPLD
   726  	ACASPLW
   727  	ACASPW
   728  	ACASW
   729  	ACBNZ
   730  	ACBNZW
   731  	ACBZ
   732  	ACBZW
   733  	ACCMN
   734  	ACCMNW
   735  	ACCMP
   736  	ACCMPW
   737  	ACINC
   738  	ACINCW
   739  	ACINV
   740  	ACINVW
   741  	ACLREX
   742  	ACLS
   743  	ACLSW
   744  	ACLZ
   745  	ACLZW
   746  	ACMN
   747  	ACMNW
   748  	ACMP
   749  	ACMPW
   750  	ACNEG
   751  	ACNEGW
   752  	ACRC32B
   753  	ACRC32CB
   754  	ACRC32CH
   755  	ACRC32CW
   756  	ACRC32CX
   757  	ACRC32H
   758  	ACRC32W
   759  	ACRC32X
   760  	ACSEL
   761  	ACSELW
   762  	ACSET
   763  	ACSETM
   764  	ACSETMW
   765  	ACSETW
   766  	ACSINC
   767  	ACSINCW
   768  	ACSINV
   769  	ACSINVW
   770  	ACSNEG
   771  	ACSNEGW
   772  	ADC
   773  	ADCPS1
   774  	ADCPS2
   775  	ADCPS3
   776  	ADMB
   777  	ADRPS
   778  	ADSB
   779  	ADWORD
   780  	AEON
   781  	AEONW
   782  	AEOR
   783  	AEORW
   784  	AERET
   785  	AEXTR
   786  	AEXTRW
   787  	AFABSD
   788  	AFABSS
   789  	AFADDD
   790  	AFADDS
   791  	AFCCMPD
   792  	AFCCMPED
   793  	AFCCMPES
   794  	AFCCMPS
   795  	AFCMPD
   796  	AFCMPED
   797  	AFCMPES
   798  	AFCMPS
   799  	AFCSELD
   800  	AFCSELS
   801  	AFCVTDH
   802  	AFCVTDS
   803  	AFCVTHD
   804  	AFCVTHS
   805  	AFCVTSD
   806  	AFCVTSH
   807  	AFCVTZSD
   808  	AFCVTZSDW
   809  	AFCVTZSS
   810  	AFCVTZSSW
   811  	AFCVTZUD
   812  	AFCVTZUDW
   813  	AFCVTZUS
   814  	AFCVTZUSW
   815  	AFDIVD
   816  	AFDIVS
   817  	AFLDPD
   818  	AFLDPQ
   819  	AFLDPS
   820  	AFMADDD
   821  	AFMADDS
   822  	AFMAXD
   823  	AFMAXNMD
   824  	AFMAXNMS
   825  	AFMAXS
   826  	AFMIND
   827  	AFMINNMD
   828  	AFMINNMS
   829  	AFMINS
   830  	AFMOVD
   831  	AFMOVQ
   832  	AFMOVS
   833  	AFMSUBD
   834  	AFMSUBS
   835  	AFMULD
   836  	AFMULS
   837  	AFNEGD
   838  	AFNEGS
   839  	AFNMADDD
   840  	AFNMADDS
   841  	AFNMSUBD
   842  	AFNMSUBS
   843  	AFNMULD
   844  	AFNMULS
   845  	AFRINTAD
   846  	AFRINTAS
   847  	AFRINTID
   848  	AFRINTIS
   849  	AFRINTMD
   850  	AFRINTMS
   851  	AFRINTND
   852  	AFRINTNS
   853  	AFRINTPD
   854  	AFRINTPS
   855  	AFRINTXD
   856  	AFRINTXS
   857  	AFRINTZD
   858  	AFRINTZS
   859  	AFSQRTD
   860  	AFSQRTS
   861  	AFSTPD
   862  	AFSTPQ
   863  	AFSTPS
   864  	AFSUBD
   865  	AFSUBS
   866  	AHINT
   867  	AHLT
   868  	AHVC
   869  	AIC
   870  	AISB
   871  	ALDADDAB
   872  	ALDADDAD
   873  	ALDADDAH
   874  	ALDADDALB
   875  	ALDADDALD
   876  	ALDADDALH
   877  	ALDADDALW
   878  	ALDADDAW
   879  	ALDADDB
   880  	ALDADDD
   881  	ALDADDH
   882  	ALDADDLB
   883  	ALDADDLD
   884  	ALDADDLH
   885  	ALDADDLW
   886  	ALDADDW
   887  	ALDAR
   888  	ALDARB
   889  	ALDARH
   890  	ALDARW
   891  	ALDAXP
   892  	ALDAXPW
   893  	ALDAXR
   894  	ALDAXRB
   895  	ALDAXRH
   896  	ALDAXRW
   897  	ALDCLRAB
   898  	ALDCLRAD
   899  	ALDCLRAH
   900  	ALDCLRALB
   901  	ALDCLRALD
   902  	ALDCLRALH
   903  	ALDCLRALW
   904  	ALDCLRAW
   905  	ALDCLRB
   906  	ALDCLRD
   907  	ALDCLRH
   908  	ALDCLRLB
   909  	ALDCLRLD
   910  	ALDCLRLH
   911  	ALDCLRLW
   912  	ALDCLRW
   913  	ALDEORAB
   914  	ALDEORAD
   915  	ALDEORAH
   916  	ALDEORALB
   917  	ALDEORALD
   918  	ALDEORALH
   919  	ALDEORALW
   920  	ALDEORAW
   921  	ALDEORB
   922  	ALDEORD
   923  	ALDEORH
   924  	ALDEORLB
   925  	ALDEORLD
   926  	ALDEORLH
   927  	ALDEORLW
   928  	ALDEORW
   929  	ALDORAB
   930  	ALDORAD
   931  	ALDORAH
   932  	ALDORALB
   933  	ALDORALD
   934  	ALDORALH
   935  	ALDORALW
   936  	ALDORAW
   937  	ALDORB
   938  	ALDORD
   939  	ALDORH
   940  	ALDORLB
   941  	ALDORLD
   942  	ALDORLH
   943  	ALDORLW
   944  	ALDORW
   945  	ALDP
   946  	ALDPSW
   947  	ALDPW
   948  	ALDXP
   949  	ALDXPW
   950  	ALDXR
   951  	ALDXRB
   952  	ALDXRH
   953  	ALDXRW
   954  	ALSL
   955  	ALSLW
   956  	ALSR
   957  	ALSRW
   958  	AMADD
   959  	AMADDW
   960  	AMNEG
   961  	AMNEGW
   962  	AMOVB
   963  	AMOVBU
   964  	AMOVD
   965  	AMOVH
   966  	AMOVHU
   967  	AMOVK
   968  	AMOVKW
   969  	AMOVN
   970  	AMOVNW
   971  	AMOVP
   972  	AMOVPD
   973  	AMOVPQ
   974  	AMOVPS
   975  	AMOVPSW
   976  	AMOVPW
   977  	AMOVW
   978  	AMOVWU
   979  	AMOVZ
   980  	AMOVZW
   981  	AMRS
   982  	AMSR
   983  	AMSUB
   984  	AMSUBW
   985  	AMUL
   986  	AMULW
   987  	AMVN
   988  	AMVNW
   989  	ANEG
   990  	ANEGS
   991  	ANEGSW
   992  	ANEGW
   993  	ANGC
   994  	ANGCS
   995  	ANGCSW
   996  	ANGCW
   997  	ANOOP
   998  	AORN
   999  	AORNW
  1000  	AORR
  1001  	AORRW
  1002  	APRFM
  1003  	APRFUM
  1004  	ARBIT
  1005  	ARBITW
  1006  	AREM
  1007  	AREMW
  1008  	AREV
  1009  	AREV16
  1010  	AREV16W
  1011  	AREV32
  1012  	AREVW
  1013  	AROR
  1014  	ARORW
  1015  	ARPRFM
  1016  	ASB
  1017  	ASBC
  1018  	ASBCS
  1019  	ASBCSW
  1020  	ASBCW
  1021  	ASBFIZ
  1022  	ASBFIZW
  1023  	ASBFM
  1024  	ASBFMW
  1025  	ASBFX
  1026  	ASBFXW
  1027  	ASCVTFD
  1028  	ASCVTFS
  1029  	ASCVTFWD
  1030  	ASCVTFWS
  1031  	ASDIV
  1032  	ASDIVW
  1033  	ASEV
  1034  	ASEVL
  1035  	ASHA1C
  1036  	ASHA1H
  1037  	ASHA1M
  1038  	ASHA1P
  1039  	ASHA1SU0
  1040  	ASHA1SU1
  1041  	ASHA256H
  1042  	ASHA256H2
  1043  	ASHA256SU0
  1044  	ASHA256SU1
  1045  	ASHA512H
  1046  	ASHA512H2
  1047  	ASHA512SU0
  1048  	ASHA512SU1
  1049  	ASMADDL
  1050  	ASMC
  1051  	ASMNEGL
  1052  	ASMSUBL
  1053  	ASMULH
  1054  	ASMULL
  1055  	ASTLR
  1056  	ASTLRB
  1057  	ASTLRH
  1058  	ASTLRW
  1059  	ASTLXP
  1060  	ASTLXPW
  1061  	ASTLXR
  1062  	ASTLXRB
  1063  	ASTLXRH
  1064  	ASTLXRW
  1065  	ASTP
  1066  	ASTPW
  1067  	ASTXP
  1068  	ASTXPW
  1069  	ASTXR
  1070  	ASTXRB
  1071  	ASTXRH
  1072  	ASTXRW
  1073  	ASUB
  1074  	ASUBS
  1075  	ASUBSW
  1076  	ASUBW
  1077  	ASVC
  1078  	ASWPAB
  1079  	ASWPAD
  1080  	ASWPAH
  1081  	ASWPALB
  1082  	ASWPALD
  1083  	ASWPALH
  1084  	ASWPALW
  1085  	ASWPAW
  1086  	ASWPB
  1087  	ASWPD
  1088  	ASWPH
  1089  	ASWPLB
  1090  	ASWPLD
  1091  	ASWPLH
  1092  	ASWPLW
  1093  	ASWPW
  1094  	ASXTB
  1095  	ASXTBW
  1096  	ASXTH
  1097  	ASXTHW
  1098  	ASXTW
  1099  	ASYS
  1100  	ASYSL
  1101  	ATBNZ
  1102  	ATBZ
  1103  	ATLBI
  1104  	ATST
  1105  	ATSTW
  1106  	AUBFIZ
  1107  	AUBFIZW
  1108  	AUBFM
  1109  	AUBFMW
  1110  	AUBFX
  1111  	AUBFXW
  1112  	AUCVTFD
  1113  	AUCVTFS
  1114  	AUCVTFWD
  1115  	AUCVTFWS
  1116  	AUDIV
  1117  	AUDIVW
  1118  	AUMADDL
  1119  	AUMNEGL
  1120  	AUMSUBL
  1121  	AUMULH
  1122  	AUMULL
  1123  	AUREM
  1124  	AUREMW
  1125  	AUXTB
  1126  	AUXTBW
  1127  	AUXTH
  1128  	AUXTHW
  1129  	AUXTW
  1130  	AVADD
  1131  	AVADDP
  1132  	AVSHADD
  1133  	AVSRHADD
  1134  	AVADDV
  1135  	AVFMAXV
  1136  	AVFMAXNMV
  1137  	AVFMINV
  1138  	AVFMINNMV
  1139  	AVSMAXV
  1140  	AVSMINV
  1141  	AVUMAXV
  1142  	AVUMINV
  1143  	AVAND
  1144  	AVBCAX
  1145  	AVBIF
  1146  	AVBIT
  1147  	AVBSL
  1148  	AVCMEQ
  1149  	AVCLS
  1150  	AVCLZ
  1151  	AVCMGE
  1152  	AVCMGT
  1153  	AVCMHI
  1154  	AVCMHS
  1155  	AVCMLE
  1156  	AVCMLT
  1157  	AVCMTST
  1158  	AVCNT
  1159  	AVDUP
  1160  	AVEOR
  1161  	AVEOR3
  1162  	AVEXT
  1163  	AVFMLA
  1164  	AVFMLS
  1165  	AVFCMEQ
  1166  	AVFCMGE
  1167  	AVFCMGT
  1168  	AVFCMLE
  1169  	AVFCMLT
  1170  	AVFADDP
  1171  	AVFADD
  1172  	AVFSUB
  1173  	AVFMUL
  1174  	AVFDIV
  1175  	AVFMAX
  1176  	AVFMAXNM
  1177  	AVFMAXP
  1178  	AVFMIN
  1179  	AVFMINNM
  1180  	AVFMINP
  1181  	AVFMAXNMP
  1182  	AVFMINNMP
  1183  	AVSQADD
  1184  	AVUQADD
  1185  	AVSQSUB
  1186  	AVSQABS
  1187  	AVSQNEG
  1188  	AVUQSUB
  1189  	AVUHADD
  1190  	AVURHADD
  1191  	AVMUL
  1192  	AVMLA
  1193  	AVMLS
  1194  	AVLD1
  1195  	AVLD1R
  1196  	AVLD2
  1197  	AVLD2R
  1198  	AVLD3
  1199  	AVLD3R
  1200  	AVLD4
  1201  	AVLD4R
  1202  	AVMOV
  1203  	AVMOVD
  1204  	AVMOVI
  1205  	AVMOVQ
  1206  	AVMOVS
  1207  	AVORR
  1208  	AVORN
  1209  	AVBIC
  1210  	AVPMULL
  1211  	AVPMULL2
  1212  	AVSMLAL
  1213  	AVSMLAL2
  1214  	AVSMLSL
  1215  	AVSMLSL2
  1216  	AVSMULL
  1217  	AVSMULL2
  1218  	AVUMLAL
  1219  	AVUMLAL2
  1220  	AVUMLSL
  1221  	AVUMLSL2
  1222  	AVUMULL
  1223  	AVUMULL2
  1224  	AVRAX1
  1225  	AVRBIT
  1226  	AVREV16
  1227  	AVREV32
  1228  	AVREV64
  1229  	AVABS
  1230  	AVFABS
  1231  	AVFNEG
  1232  	AVFSQRT
  1233  	AVFRINTN
  1234  	AVFRINTP
  1235  	AVFRINTM
  1236  	AVFRINTZ
  1237  	AVNEG
  1238  	AVNOT
  1239  	AVSHL
  1240  	AVSHRN
  1241  	AVSHRN2
  1242  	AVSLI
  1243  	AVSQSHL
  1244  	AVSSHL
  1245  	AVUSHL
  1246  	AVUQSHL
  1247  	AVSRI
  1248  	AVST1
  1249  	AVST2
  1250  	AVST3
  1251  	AVST4
  1252  	AVSUB
  1253  	AVSMAX
  1254  	AVSMIN
  1255  	AVSMAXP
  1256  	AVSMINP
  1257  	AVTBL
  1258  	AVTBX
  1259  	AVTRN1
  1260  	AVTRN2
  1261  	AVUADDLV
  1262  	AVUADDW
  1263  	AVUADDW2
  1264  	AVUMAX
  1265  	AVUMIN
  1266  	AVUMAXP
  1267  	AVUMINP
  1268  	AVUSHLL
  1269  	AVUSHLL2
  1270  	AVUSHR
  1271  	AVSRSHR
  1272  	AVSSHR
  1273  	AVUSRA
  1274  	AVUXTL
  1275  	AVUXTL2
  1276  	AVXTN
  1277  	AVXTN2
  1278  	AVSSHLL
  1279  	AVSSHLL2
  1280  	AVSXTL
  1281  	AVSXTL2
  1282  	AVSQXTN
  1283  	AVSQXTN2
  1284  	AVSQXTUN
  1285  	AVSQXTUN2
  1286  	AVUQXTN
  1287  	AVUQXTN2
  1288  	AVFCVTZS
  1289  	AVFCVTZU
  1290  	AVSCVTF
  1291  	AVUCVTF
  1292  	AVFCVTN
  1293  	AVFCVTN2
  1294  	AVFCVTL
  1295  	AVFCVTL2
  1296  	AVUZP1
  1297  	AVUZP2
  1298  	AVXAR
  1299  	AVZIP1
  1300  	AVZIP2
  1301  	AWFE
  1302  	AWFI
  1303  	AWORD
  1304  	AYIELD
  1305  	ABTI
  1306  	APACIASP
  1307  	AAUTIASP
  1308  	APACIBSP
  1309  	AAUTIBSP
  1310  	AAUTIA1716
  1311  	AAUTIB1716
  1312  	ASVESTART
  1313  	AB  = obj.AJMP
  1314  	ABL = obj.ACALL
  1315  )
  1316  
  1317  const (
  1318  	// shift types
  1319  	SHIFT_LL  = 0 << 22
  1320  	SHIFT_LR  = 1 << 22
  1321  	SHIFT_AR  = 2 << 22
  1322  	SHIFT_ROR = 3 << 22
  1323  )
  1324  
  1325  // Arrangement for ARM64 SIMD instructions
  1326  const (
  1327  	// arrangement types
  1328  	ARNG_8B = iota
  1329  	ARNG_16B
  1330  	ARNG_1D
  1331  	ARNG_4H
  1332  	ARNG_8H
  1333  	ARNG_2S
  1334  	ARNG_4S
  1335  	ARNG_2D
  1336  	ARNG_1Q
  1337  	ARNG_B
  1338  	ARNG_H
  1339  	ARNG_S
  1340  	ARNG_D
  1341  	ARNG_Q
  1342  	PRED_M
  1343  	PRED_Z
  1344  )
  1345  
  1346  //go:generate stringer -type SpecialOperand -trimprefix SPOP_
  1347  type SpecialOperand int
  1348  
  1349  const (
  1350  	// PRFM
  1351  	SPOP_PLDL1KEEP SpecialOperand = obj.SpecialOperandARM64Base + iota     // must be the first one
  1352  	SPOP_BEGIN     SpecialOperand = obj.SpecialOperandARM64Base + iota - 1 // set as the lower bound
  1353  	SPOP_PLDL1STRM
  1354  	SPOP_PLDL2KEEP
  1355  	SPOP_PLDL2STRM
  1356  	SPOP_PLDL3KEEP
  1357  	SPOP_PLDL3STRM
  1358  	SPOP_PLIL1KEEP
  1359  	SPOP_PLIL1STRM
  1360  	SPOP_PLIL2KEEP
  1361  	SPOP_PLIL2STRM
  1362  	SPOP_PLIL3KEEP
  1363  	SPOP_PLIL3STRM
  1364  	SPOP_PSTL1KEEP
  1365  	SPOP_PSTL1STRM
  1366  	SPOP_PSTL2KEEP
  1367  	SPOP_PSTL2STRM
  1368  	SPOP_PSTL3KEEP
  1369  	SPOP_PSTL3STRM
  1370  
  1371  	// VL
  1372  	SPOP_VLx2
  1373  	SPOP_VLx4
  1374  
  1375  	// TLBI
  1376  	SPOP_VMALLE1IS
  1377  	SPOP_VAE1IS
  1378  	SPOP_ASIDE1IS
  1379  	SPOP_VAAE1IS
  1380  	SPOP_VALE1IS
  1381  	SPOP_VAALE1IS
  1382  	SPOP_VMALLE1
  1383  	SPOP_VAE1
  1384  	SPOP_ASIDE1
  1385  	SPOP_VAAE1
  1386  	SPOP_VALE1
  1387  	SPOP_VAALE1
  1388  	SPOP_IPAS2E1IS
  1389  	SPOP_IPAS2LE1IS
  1390  	SPOP_ALLE2IS
  1391  	SPOP_VAE2IS
  1392  	SPOP_ALLE1IS
  1393  	SPOP_VALE2IS
  1394  	SPOP_VMALLS12E1IS
  1395  	SPOP_IPAS2E1
  1396  	SPOP_IPAS2LE1
  1397  	SPOP_ALLE2
  1398  	SPOP_VAE2
  1399  	SPOP_ALLE1
  1400  	SPOP_VALE2
  1401  	SPOP_VMALLS12E1
  1402  	SPOP_ALLE3IS
  1403  	SPOP_VAE3IS
  1404  	SPOP_VALE3IS
  1405  	SPOP_ALLE3
  1406  	SPOP_VAE3
  1407  	SPOP_VALE3
  1408  	SPOP_VMALLE1OS
  1409  	SPOP_VAE1OS
  1410  	SPOP_ASIDE1OS
  1411  	SPOP_VAAE1OS
  1412  	SPOP_VALE1OS
  1413  	SPOP_VAALE1OS
  1414  	SPOP_RVAE1IS
  1415  	SPOP_RVAAE1IS
  1416  	SPOP_RVALE1IS
  1417  	SPOP_RVAALE1IS
  1418  	SPOP_RVAE1OS
  1419  	SPOP_RVAAE1OS
  1420  	SPOP_RVALE1OS
  1421  	SPOP_RVAALE1OS
  1422  	SPOP_RVAE1
  1423  	SPOP_RVAAE1
  1424  	SPOP_RVALE1
  1425  	SPOP_RVAALE1
  1426  	SPOP_RIPAS2E1IS
  1427  	SPOP_RIPAS2LE1IS
  1428  	SPOP_ALLE2OS
  1429  	SPOP_VAE2OS
  1430  	SPOP_ALLE1OS
  1431  	SPOP_VALE2OS
  1432  	SPOP_VMALLS12E1OS
  1433  	SPOP_RVAE2IS
  1434  	SPOP_RVALE2IS
  1435  	SPOP_IPAS2E1OS
  1436  	SPOP_RIPAS2E1
  1437  	SPOP_RIPAS2E1OS
  1438  	SPOP_IPAS2LE1OS
  1439  	SPOP_RIPAS2LE1
  1440  	SPOP_RIPAS2LE1OS
  1441  	SPOP_RVAE2OS
  1442  	SPOP_RVALE2OS
  1443  	SPOP_RVAE2
  1444  	SPOP_RVALE2
  1445  	SPOP_ALLE3OS
  1446  	SPOP_VAE3OS
  1447  	SPOP_VALE3OS
  1448  	SPOP_RVAE3IS
  1449  	SPOP_RVALE3IS
  1450  	SPOP_RVAE3OS
  1451  	SPOP_RVALE3OS
  1452  	SPOP_RVAE3
  1453  	SPOP_RVALE3
  1454  
  1455  	// DC
  1456  	SPOP_IVAC
  1457  	SPOP_ISW
  1458  	SPOP_CSW
  1459  	SPOP_CISW
  1460  	SPOP_ZVA
  1461  	SPOP_CVAC
  1462  	SPOP_CVAU
  1463  	SPOP_CIVAC
  1464  	SPOP_IGVAC
  1465  	SPOP_IGSW
  1466  	SPOP_IGDVAC
  1467  	SPOP_IGDSW
  1468  	SPOP_CGSW
  1469  	SPOP_CGDSW
  1470  	SPOP_CIGSW
  1471  	SPOP_CIGDSW
  1472  	SPOP_GVA
  1473  	SPOP_GZVA
  1474  	SPOP_CGVAC
  1475  	SPOP_CGDVAC
  1476  	SPOP_CGVAP
  1477  	SPOP_CGDVAP
  1478  	SPOP_CGVADP
  1479  	SPOP_CGDVADP
  1480  	SPOP_CIGVAC
  1481  	SPOP_CIGDVAC
  1482  	SPOP_CVAP
  1483  	SPOP_CVADP
  1484  
  1485  	// PSTATE fields
  1486  	SPOP_DAIFSet
  1487  	SPOP_DAIFClr
  1488  
  1489  	// Condition code, EQ, NE, etc. Their relative order to EQ matters.
  1490  	SPOP_EQ
  1491  	SPOP_NE
  1492  	SPOP_HS
  1493  	SPOP_LO
  1494  	SPOP_MI
  1495  	SPOP_PL
  1496  	SPOP_VS
  1497  	SPOP_VC
  1498  	SPOP_HI
  1499  	SPOP_LS
  1500  	SPOP_GE
  1501  	SPOP_LT
  1502  	SPOP_GT
  1503  	SPOP_LE
  1504  	SPOP_AL
  1505  	SPOP_NV
  1506  
  1507  	// Branch Target Indicator (BTI) targets
  1508  	SPOP_C
  1509  	SPOP_J
  1510  	SPOP_JC
  1511  
  1512  	// Range PReFetch of Memory (RPRFM)
  1513  	SPOP_PLDKEEP
  1514  	SPOP_PSTKEEP
  1515  	SPOP_PLDSTRM
  1516  	SPOP_PSTSTRM
  1517  
  1518  	SPOP_END
  1519  )
  1520
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