a.out.go

     1  // cmd/7c/7.out.h  from Vita Nuova.
     2  // https://bitbucket.org/plan9-from-bell-labs/9-cc/src/master/src/cmd/7c/7.out.h
     3  //
     4  // 	Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
     5  // 	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     6  // 	Portions Copyright © 1997-1999 Vita Nuova Limited
     7  // 	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
     8  // 	Portions Copyright © 2004,2006 Bruce Ellis
     9  // 	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
    10  // 	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
    11  // 	Portions Copyright © 2009 The Go Authors. All rights reserved.
    12  //
    13  // Permission is hereby granted, free of charge, to any person obtaining a copy
    14  // of this software and associated documentation files (the "Software"), to deal
    15  // in the Software without restriction, including without limitation the rights
    16  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    17  // copies of the Software, and to permit persons to whom the Software is
    18  // furnished to do so, subject to the following conditions:
    19  //
    20  // The above copyright notice and this permission notice shall be included in
    21  // all copies or substantial portions of the Software.
    22  //
    23  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    24  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    25  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    26  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    27  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    28  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    29  // THE SOFTWARE.
    30  
    31  package arm64
    32  
    33  import "cmd/internal/obj"
    34  
    35  const (
    36  	NSNAME = 8
    37  	NSYM   = 50
    38  	NREG   = 32 /* number of general registers */
    39  	NFREG  = 32 /* number of floating point registers */
    40  )
    41  
    42  // General purpose registers, kept in the low bits of Prog.Reg.
    43  const (
    44  	// integer
    45  	REG_R0 = obj.RBaseARM64 + iota
    46  	REG_R1
    47  	REG_R2
    48  	REG_R3
    49  	REG_R4
    50  	REG_R5
    51  	REG_R6
    52  	REG_R7
    53  	REG_R8
    54  	REG_R9
    55  	REG_R10
    56  	REG_R11
    57  	REG_R12
    58  	REG_R13
    59  	REG_R14
    60  	REG_R15
    61  	REG_R16
    62  	REG_R17
    63  	REG_R18
    64  	REG_R19
    65  	REG_R20
    66  	REG_R21
    67  	REG_R22
    68  	REG_R23
    69  	REG_R24
    70  	REG_R25
    71  	REG_R26
    72  	REG_R27
    73  	REG_R28
    74  	REG_R29
    75  	REG_R30
    76  	REG_R31
    77  
    78  	// scalar floating point
    79  	REG_F0
    80  	REG_F1
    81  	REG_F2
    82  	REG_F3
    83  	REG_F4
    84  	REG_F5
    85  	REG_F6
    86  	REG_F7
    87  	REG_F8
    88  	REG_F9
    89  	REG_F10
    90  	REG_F11
    91  	REG_F12
    92  	REG_F13
    93  	REG_F14
    94  	REG_F15
    95  	REG_F16
    96  	REG_F17
    97  	REG_F18
    98  	REG_F19
    99  	REG_F20
   100  	REG_F21
   101  	REG_F22
   102  	REG_F23
   103  	REG_F24
   104  	REG_F25
   105  	REG_F26
   106  	REG_F27
   107  	REG_F28
   108  	REG_F29
   109  	REG_F30
   110  	REG_F31
   111  
   112  	// SIMD
   113  	REG_V0
   114  	REG_V1
   115  	REG_V2
   116  	REG_V3
   117  	REG_V4
   118  	REG_V5
   119  	REG_V6
   120  	REG_V7
   121  	REG_V8
   122  	REG_V9
   123  	REG_V10
   124  	REG_V11
   125  	REG_V12
   126  	REG_V13
   127  	REG_V14
   128  	REG_V15
   129  	REG_V16
   130  	REG_V17
   131  	REG_V18
   132  	REG_V19
   133  	REG_V20
   134  	REG_V21
   135  	REG_V22
   136  	REG_V23
   137  	REG_V24
   138  	REG_V25
   139  	REG_V26
   140  	REG_V27
   141  	REG_V28
   142  	REG_V29
   143  	REG_V30
   144  	REG_V31
   145  
   146  	// SVE (Scalable Vector Extension) scalable vector registers
   147  	// The order matters, make sure that each
   148  	// kind of register starts numbering from the lowest bit.
   149  	REG_Z0
   150  	REG_Z1
   151  	REG_Z2
   152  	REG_Z3
   153  	REG_Z4
   154  	REG_Z5
   155  	REG_Z6
   156  	REG_Z7
   157  	REG_Z8
   158  	REG_Z9
   159  	REG_Z10
   160  	REG_Z11
   161  	REG_Z12
   162  	REG_Z13
   163  	REG_Z14
   164  	REG_Z15
   165  	REG_Z16
   166  	REG_Z17
   167  	REG_Z18
   168  	REG_Z19
   169  	REG_Z20
   170  	REG_Z21
   171  	REG_Z22
   172  	REG_Z23
   173  	REG_Z24
   174  	REG_Z25
   175  	REG_Z26
   176  	REG_Z27
   177  	REG_Z28
   178  	REG_Z29
   179  	REG_Z30
   180  	REG_Z31
   181  
   182  	REG_P0
   183  	REG_P1
   184  	REG_P2
   185  	REG_P3
   186  	REG_P4
   187  	REG_P5
   188  	REG_P6
   189  	REG_P7
   190  	REG_P8
   191  	REG_P9
   192  	REG_P10
   193  	REG_P11
   194  	REG_P12
   195  	REG_P13
   196  	REG_P14
   197  	REG_P15
   198  
   199  	REG_PN0
   200  	REG_PN1
   201  	REG_PN2
   202  	REG_PN3
   203  	REG_PN4
   204  	REG_PN5
   205  	REG_PN6
   206  	REG_PN7
   207  	REG_PN8
   208  	REG_PN9
   209  	REG_PN10
   210  	REG_PN11
   211  	REG_PN12
   212  	REG_PN13
   213  	REG_PN14
   214  	REG_PN15
   215  
   216  	REG_RSP = (REG_PN15 + 1) | 0x1f // to differentiate ZR/SP, REG_RSP&0x1f = 31
   217  )
   218  
   219  // bits 0-4 indicates register: Vn
   220  // bits 5-8 indicates arrangement: <T>
   221  const (
   222  	REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
   223  	REG_ELEM                                    // Vn.<T>[index]
   224  	REG_ELEM_END
   225  	REG_ZARNG   // Zn.<T>
   226  	REG_PARNGZM // Pn.<T> or Pn/M, Pn/Z
   227  	REG_PARNGZM_END
   228  )
   229  
   230  // Not registers, but flags that can be combined with regular register
   231  // constants to indicate extended register conversion. When checking,
   232  // you should subtract obj.RBaseARM64 first. From this difference, bit 12
   233  // indicates extended register, bits 8-10 select the conversion mode.
   234  // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.
   235  const REG_LSL = obj.RBaseARM64 + 1<<9
   236  const REG_EXT = obj.RBaseARM64 + 1<<12
   237  
   238  const (
   239  	REG_UXTB = REG_EXT + iota<<8
   240  	REG_UXTH
   241  	REG_UXTW
   242  	REG_UXTX
   243  	REG_SXTB
   244  	REG_SXTH
   245  	REG_SXTW
   246  	REG_SXTX
   247  )
   248  
   249  // Special registers, after subtracting obj.RBaseARM64, bit 13 indicates
   250  // a special register and the low bits select the register.
   251  // SYSREG_END is the last item in the automatically generated system register
   252  // declaration, and it is defined in the sysRegEnc.go file.
   253  // Define the special register after REG_SPECIAL, the first value of it should be
   254  // REG_{name} = SYSREG_END + iota.
   255  const (
   256  	REG_SPECIAL = obj.RBaseARM64 + 1<<13
   257  )
   258  
   259  // Register assignments:
   260  //
   261  // compiler allocates R0 up as temps
   262  // compiler allocates register variables R7-R25
   263  // compiler allocates external registers R26 down
   264  //
   265  // compiler allocates register variables F7-F26
   266  // compiler allocates external registers F26 down
   267  const (
   268  	REGMIN = REG_R7  // register variables allocated from here to REGMAX
   269  	REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scratch register in trampoline
   270  	REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scratch register in trampoline
   271  	REGPR  = REG_R18 // ARM64 platform register, unused in the Go toolchain
   272  	REGMAX = REG_R25
   273  
   274  	REGCTXT = REG_R26 // environment for closures
   275  	REGTMP  = REG_R27 // reserved for liblink
   276  	REGG    = REG_R28 // G
   277  	REGFP   = REG_R29 // frame pointer
   278  	REGLINK = REG_R30
   279  
   280  	// ARM64 uses R31 as both stack pointer and zero register,
   281  	// depending on the instruction. To differentiate RSP from ZR,
   282  	// we use a different numeric value for REGZERO and REGSP.
   283  	REGZERO = REG_R31
   284  	REGSP   = REG_RSP
   285  
   286  	FREGRET = REG_F0
   287  	FREGMIN = REG_F7  // first register variable
   288  	FREGMAX = REG_F26 // last register variable for 7g only
   289  	FREGEXT = REG_F26 // first external register
   290  )
   291  
   292  // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf
   293  var ARM64DWARFRegisters = map[int16]int16{
   294  	REG_R0:  0,
   295  	REG_R1:  1,
   296  	REG_R2:  2,
   297  	REG_R3:  3,
   298  	REG_R4:  4,
   299  	REG_R5:  5,
   300  	REG_R6:  6,
   301  	REG_R7:  7,
   302  	REG_R8:  8,
   303  	REG_R9:  9,
   304  	REG_R10: 10,
   305  	REG_R11: 11,
   306  	REG_R12: 12,
   307  	REG_R13: 13,
   308  	REG_R14: 14,
   309  	REG_R15: 15,
   310  	REG_R16: 16,
   311  	REG_R17: 17,
   312  	REG_R18: 18,
   313  	REG_R19: 19,
   314  	REG_R20: 20,
   315  	REG_R21: 21,
   316  	REG_R22: 22,
   317  	REG_R23: 23,
   318  	REG_R24: 24,
   319  	REG_R25: 25,
   320  	REG_R26: 26,
   321  	REG_R27: 27,
   322  	REG_R28: 28,
   323  	REG_R29: 29,
   324  	REG_R30: 30,
   325  
   326  	// SVE predicate registers
   327  	REG_P0:  48,
   328  	REG_P1:  49,
   329  	REG_P2:  50,
   330  	REG_P3:  51,
   331  	REG_P4:  52,
   332  	REG_P5:  53,
   333  	REG_P6:  54,
   334  	REG_P7:  55,
   335  	REG_P8:  56,
   336  	REG_P9:  57,
   337  	REG_P10: 58,
   338  	REG_P11: 59,
   339  	REG_P12: 60,
   340  	REG_P13: 61,
   341  	REG_P14: 62,
   342  	REG_P15: 63,
   343  
   344  	// floating point
   345  	REG_F0:  64,
   346  	REG_F1:  65,
   347  	REG_F2:  66,
   348  	REG_F3:  67,
   349  	REG_F4:  68,
   350  	REG_F5:  69,
   351  	REG_F6:  70,
   352  	REG_F7:  71,
   353  	REG_F8:  72,
   354  	REG_F9:  73,
   355  	REG_F10: 74,
   356  	REG_F11: 75,
   357  	REG_F12: 76,
   358  	REG_F13: 77,
   359  	REG_F14: 78,
   360  	REG_F15: 79,
   361  	REG_F16: 80,
   362  	REG_F17: 81,
   363  	REG_F18: 82,
   364  	REG_F19: 83,
   365  	REG_F20: 84,
   366  	REG_F21: 85,
   367  	REG_F22: 86,
   368  	REG_F23: 87,
   369  	REG_F24: 88,
   370  	REG_F25: 89,
   371  	REG_F26: 90,
   372  	REG_F27: 91,
   373  	REG_F28: 92,
   374  	REG_F29: 93,
   375  	REG_F30: 94,
   376  	REG_F31: 95,
   377  
   378  	// SIMD
   379  	REG_V0:  64,
   380  	REG_V1:  65,
   381  	REG_V2:  66,
   382  	REG_V3:  67,
   383  	REG_V4:  68,
   384  	REG_V5:  69,
   385  	REG_V6:  70,
   386  	REG_V7:  71,
   387  	REG_V8:  72,
   388  	REG_V9:  73,
   389  	REG_V10: 74,
   390  	REG_V11: 75,
   391  	REG_V12: 76,
   392  	REG_V13: 77,
   393  	REG_V14: 78,
   394  	REG_V15: 79,
   395  	REG_V16: 80,
   396  	REG_V17: 81,
   397  	REG_V18: 82,
   398  	REG_V19: 83,
   399  	REG_V20: 84,
   400  	REG_V21: 85,
   401  	REG_V22: 86,
   402  	REG_V23: 87,
   403  	REG_V24: 88,
   404  	REG_V25: 89,
   405  	REG_V26: 90,
   406  	REG_V27: 91,
   407  	REG_V28: 92,
   408  	REG_V29: 93,
   409  	REG_V30: 94,
   410  	REG_V31: 95,
   411  
   412  	// SVE vector registers
   413  	REG_Z0:  96,
   414  	REG_Z1:  97,
   415  	REG_Z2:  98,
   416  	REG_Z3:  99,
   417  	REG_Z4:  100,
   418  	REG_Z5:  101,
   419  	REG_Z6:  102,
   420  	REG_Z7:  103,
   421  	REG_Z8:  104,
   422  	REG_Z9:  105,
   423  	REG_Z10: 106,
   424  	REG_Z11: 107,
   425  	REG_Z12: 108,
   426  	REG_Z13: 109,
   427  	REG_Z14: 110,
   428  	REG_Z15: 111,
   429  	REG_Z16: 112,
   430  	REG_Z17: 113,
   431  	REG_Z18: 114,
   432  	REG_Z19: 115,
   433  	REG_Z20: 116,
   434  	REG_Z21: 117,
   435  	REG_Z22: 118,
   436  	REG_Z23: 119,
   437  	REG_Z24: 120,
   438  	REG_Z25: 121,
   439  	REG_Z26: 122,
   440  	REG_Z27: 123,
   441  	REG_Z28: 124,
   442  	REG_Z29: 125,
   443  	REG_Z30: 126,
   444  	REG_Z31: 127,
   445  }
   446  
   447  const (
   448  	BIG = 2048 - 8
   449  )
   450  
   451  const (
   452  	/* mark flags */
   453  	LABEL = 1 << iota
   454  	LEAF
   455  	FLOAT
   456  	BRANCH
   457  	LOAD
   458  	FCMP
   459  	SYNC
   460  	LIST
   461  	FOLL
   462  	NOSCHED
   463  )
   464  
   465  //go:generate go run ../mkcnames.go -i a.out.go -o anames7.go -p arm64
   466  const (
   467  	// optab is sorted based on the order of these constants
   468  	// and the first match is chosen.
   469  	// The more specific class needs to come earlier.
   470  	C_NONE   = iota + 1 // starting from 1, leave unclassified Addr's class as 0
   471  	C_REG               // R0..R30
   472  	C_ZREG              // R0..R30, ZR
   473  	C_RSP               // R0..R30, RSP
   474  	C_FREG              // F0..F31
   475  	C_VREG              // V0..V31
   476  	C_PAIR              // (Rn, Rm)
   477  	C_SHIFT             // Rn<<2
   478  	C_EXTREG            // Rn.UXTB[<<3]
   479  	C_SPR               // REG_NZCV
   480  	C_COND              // condition code, EQ, NE, etc.
   481  	C_SPOP              // special operand, PLDL1KEEP, VMALLE1IS, etc.
   482  	C_ARNG              // Vn.<T>
   483  	C_ELEM              // Vn.<T>[index]
   484  	C_LIST              // [V1, V2, V3]
   485  
   486  	C_ZCON     // $0
   487  	C_ABCON0   // could be C_ADDCON0 or C_BITCON
   488  	C_ADDCON0  // 12-bit unsigned, unshifted
   489  	C_ABCON    // could be C_ADDCON or C_BITCON
   490  	C_AMCON    // could be C_ADDCON or C_MOVCON
   491  	C_ADDCON   // 12-bit unsigned, shifted left by 0 or 12
   492  	C_MBCON    // could be C_MOVCON or C_BITCON
   493  	C_MOVCON   // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
   494  	C_BITCON   // bitfield and logical immediate masks
   495  	C_ADDCON2  // 24-bit constant
   496  	C_LCON     // 32-bit constant
   497  	C_MOVCON2  // a constant that can be loaded with one MOVZ/MOVN and one MOVK
   498  	C_MOVCON3  // a constant that can be loaded with one MOVZ/MOVN and two MOVKs
   499  	C_VCON     // 64-bit constant
   500  	C_FCON     // floating-point constant
   501  	C_VCONADDR // 64-bit memory address
   502  
   503  	C_AACON  // ADDCON offset in auto constant $a(FP)
   504  	C_AACON2 // 24-bit offset in auto constant $a(FP)
   505  	C_LACON  // 32-bit offset in auto constant $a(FP)
   506  	C_AECON  // ADDCON offset in extern constant $e(SB)
   507  
   508  	// TODO(aram): only one branch class should be enough
   509  	C_SBRA // for TYPE_BRANCH
   510  	C_LBRA
   511  
   512  	C_ZAUTO       // 0(RSP)
   513  	C_NSAUTO_16   // -256 <= x < 0, 0 mod 16
   514  	C_NSAUTO_8    // -256 <= x < 0, 0 mod 8
   515  	C_NSAUTO_4    // -256 <= x < 0, 0 mod 4
   516  	C_NSAUTO      // -256 <= x < 0
   517  	C_NPAUTO_16   // -512 <= x < 0, 0 mod 16
   518  	C_NPAUTO      // -512 <= x < 0, 0 mod 8
   519  	C_NQAUTO_16   // -1024 <= x < 0, 0 mod 16
   520  	C_NAUTO4K     // -4095 <= x < 0
   521  	C_PSAUTO_16   // 0 to 255, 0 mod 16
   522  	C_PSAUTO_8    // 0 to 255, 0 mod 8
   523  	C_PSAUTO_4    // 0 to 255, 0 mod 4
   524  	C_PSAUTO      // 0 to 255
   525  	C_PPAUTO_16   // 0 to 504, 0 mod 16
   526  	C_PPAUTO      // 0 to 504, 0 mod 8
   527  	C_PQAUTO_16   // 0 to 1008, 0 mod 16
   528  	C_UAUTO4K_16  // 0 to 4095, 0 mod 16
   529  	C_UAUTO4K_8   // 0 to 4095, 0 mod 8
   530  	C_UAUTO4K_4   // 0 to 4095, 0 mod 4
   531  	C_UAUTO4K_2   // 0 to 4095, 0 mod 2
   532  	C_UAUTO4K     // 0 to 4095
   533  	C_UAUTO8K_16  // 0 to 8190, 0 mod 16
   534  	C_UAUTO8K_8   // 0 to 8190, 0 mod 8
   535  	C_UAUTO8K_4   // 0 to 8190, 0 mod 4
   536  	C_UAUTO8K     // 0 to 8190, 0 mod 2  + C_PSAUTO
   537  	C_UAUTO16K_16 // 0 to 16380, 0 mod 16
   538  	C_UAUTO16K_8  // 0 to 16380, 0 mod 8
   539  	C_UAUTO16K    // 0 to 16380, 0 mod 4 + C_PSAUTO
   540  	C_UAUTO32K_16 // 0 to 32760, 0 mod 16 + C_PSAUTO
   541  	C_UAUTO32K    // 0 to 32760, 0 mod 8 + C_PSAUTO
   542  	C_UAUTO64K    // 0 to 65520, 0 mod 16 + C_PSAUTO
   543  	C_LAUTOPOOL   // any other constant up to 64 bits (needs pool literal)
   544  	C_LAUTO       // any other constant up to 64 bits
   545  
   546  	C_SEXT1  // 0 to 4095, direct
   547  	C_SEXT2  // 0 to 8190
   548  	C_SEXT4  // 0 to 16380
   549  	C_SEXT8  // 0 to 32760
   550  	C_SEXT16 // 0 to 65520
   551  	C_LEXT
   552  
   553  	C_ZOREG     // 0(R)
   554  	C_NSOREG_16 // must mirror C_NSAUTO_16, etc
   555  	C_NSOREG_8
   556  	C_NSOREG_4
   557  	C_NSOREG
   558  	C_NPOREG_16
   559  	C_NPOREG
   560  	C_NQOREG_16
   561  	C_NOREG4K
   562  	C_PSOREG_16
   563  	C_PSOREG_8
   564  	C_PSOREG_4
   565  	C_PSOREG
   566  	C_PPOREG_16
   567  	C_PPOREG
   568  	C_PQOREG_16
   569  	C_UOREG4K_16
   570  	C_UOREG4K_8
   571  	C_UOREG4K_4
   572  	C_UOREG4K_2
   573  	C_UOREG4K
   574  	C_UOREG8K_16
   575  	C_UOREG8K_8
   576  	C_UOREG8K_4
   577  	C_UOREG8K
   578  	C_UOREG16K_16
   579  	C_UOREG16K_8
   580  	C_UOREG16K
   581  	C_UOREG32K_16
   582  	C_UOREG32K
   583  	C_UOREG64K
   584  	C_LOREGPOOL
   585  	C_LOREG
   586  
   587  	C_ADDR // TODO(aram): explain difference from C_VCONADDR
   588  
   589  	// The GOT slot for a symbol in -dynlink mode.
   590  	C_GOTADDR
   591  
   592  	// TLS "var" in local exec mode: will become a constant offset from
   593  	// thread local base that is ultimately chosen by the program linker.
   594  	C_TLS_LE
   595  
   596  	// TLS "var" in initial exec mode: will become a memory address (chosen
   597  	// by the program linker) that the dynamic linker will fill with the
   598  	// offset from the thread local base.
   599  	C_TLS_IE
   600  
   601  	C_ROFF // register offset (including register extended)
   602  
   603  	C_GOK
   604  	C_TEXTSIZE
   605  	C_NCLASS // must be last
   606  )
   607  
   608  const (
   609  	C_XPRE  = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
   610  	C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
   611  )
   612  
   613  type AClass uint16 // operand type
   614  
   615  // [insts] is sorted based on the order of these constants and the first match is chosen.
   616  const (
   617  	AC_NONE    AClass = iota
   618  	AC_REG            // general purpose registers R0..R30 and ZR
   619  	AC_RSP            // general purpose registers R0..R30 and RSP
   620  	AC_VREG           // vector registers, such as V1
   621  	AC_ZREG           // the scalable vector registers, such as Z1
   622  	AC_PREG           // the scalable predicate registers, such as P1
   623  	AC_PREGZM         // Pg.Z or Pg.M
   624  	AC_REGIDX         // P8[1]
   625  	AC_ZREGIDX        // Z1[1]
   626  	AC_PREGIDX        // P0[R1, 1]
   627  	AC_ARNG           // vector register with arrangement, such as Z1.D
   628  	AC_ARNGIDX        // vector register with arrangement and index, such as Z1.D[1]
   629  
   630  	AC_IMM // constants
   631  
   632  	AC_REGLIST1      // list of 1 vector register, such as [Z1]
   633  	AC_REGLIST2      // list of 2 vector registers, such as [Z0, Z8]
   634  	AC_REGLIST3      // list of 3 vector registers, such as [Z1, Z2, Z3]
   635  	AC_REGLIST4      // list of 4 vector registers, such as [Z0, Z4, Z8, Z12]
   636  	AC_REGLIST_RANGE // list of vector register lists in range format, such as [Z0-Z4].
   637  
   638  	AC_MEMOFF      // address with optional constant offset, the offset is an immediate, such as 4(Z1.D)
   639  	AC_MEMOFFMULVL // address with optional constant offset, the offset is an immediate multiplied by the vector's in-memory size, such as (2*VL)(Z1.D)
   640  	AC_MEMEXT      // address with register offset with extensions, such as (Z2.D.UXTW<<3)(RSP)
   641  
   642  	AC_PREG_PATTERN // register with pattern, such as VL1*3(P1.D)
   643  	AC_REG_PATTERN  // register with pattern, such as VL1*3(R1)
   644  	AC_ZREG_PATTERN // register with pattern, such as VL1*3(Z1.D)
   645  
   646  	AC_SPECIAL // VL*i pattern, one of: VL*2, VL*4, or prefetch pattern, such as PLDL1KEEP, more patterns might come in the future.
   647  )
   648  
   649  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
   650  
   651  const (
   652  	AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
   653  	AADCS
   654  	AADCSW
   655  	AADCW
   656  	AADD
   657  	AADDS
   658  	AADDSW
   659  	AADDW
   660  	AADR
   661  	AADRP
   662  	AAESD
   663  	AAESE
   664  	AAESIMC
   665  	AAESMC
   666  	AAND
   667  	AANDS
   668  	AANDSW
   669  	AANDW
   670  	AASR
   671  	AASRW
   672  	AAT
   673  	ABCC
   674  	ABCS
   675  	ABEQ
   676  	ABFI
   677  	ABFIW
   678  	ABFM
   679  	ABFMW
   680  	ABFXIL
   681  	ABFXILW
   682  	ABGE
   683  	ABGT
   684  	ABHI
   685  	ABHS
   686  	ABIC
   687  	ABICS
   688  	ABICSW
   689  	ABICW
   690  	ABLE
   691  	ABLO
   692  	ABLS
   693  	ABLT
   694  	ABMI
   695  	ABNE
   696  	ABPL
   697  	ABRK
   698  	ABVC
   699  	ABVS
   700  	ACASAD
   701  	ACASALB
   702  	ACASALD
   703  	ACASALH
   704  	ACASALW
   705  	ACASAW
   706  	ACASB
   707  	ACASD
   708  	ACASH
   709  	ACASLD
   710  	ACASLW
   711  	ACASPD
   712  	ACASPW
   713  	ACASW
   714  	ACBNZ
   715  	ACBNZW
   716  	ACBZ
   717  	ACBZW
   718  	ACCMN
   719  	ACCMNW
   720  	ACCMP
   721  	ACCMPW
   722  	ACINC
   723  	ACINCW
   724  	ACINV
   725  	ACINVW
   726  	ACLREX
   727  	ACLS
   728  	ACLSW
   729  	ACLZ
   730  	ACLZW
   731  	ACMN
   732  	ACMNW
   733  	ACMP
   734  	ACMPW
   735  	ACNEG
   736  	ACNEGW
   737  	ACRC32B
   738  	ACRC32CB
   739  	ACRC32CH
   740  	ACRC32CW
   741  	ACRC32CX
   742  	ACRC32H
   743  	ACRC32W
   744  	ACRC32X
   745  	ACSEL
   746  	ACSELW
   747  	ACSET
   748  	ACSETM
   749  	ACSETMW
   750  	ACSETW
   751  	ACSINC
   752  	ACSINCW
   753  	ACSINV
   754  	ACSINVW
   755  	ACSNEG
   756  	ACSNEGW
   757  	ADC
   758  	ADCPS1
   759  	ADCPS2
   760  	ADCPS3
   761  	ADMB
   762  	ADRPS
   763  	ADSB
   764  	ADWORD
   765  	AEON
   766  	AEONW
   767  	AEOR
   768  	AEORW
   769  	AERET
   770  	AEXTR
   771  	AEXTRW
   772  	AFABSD
   773  	AFABSS
   774  	AFADDD
   775  	AFADDS
   776  	AFCCMPD
   777  	AFCCMPED
   778  	AFCCMPES
   779  	AFCCMPS
   780  	AFCMPD
   781  	AFCMPED
   782  	AFCMPES
   783  	AFCMPS
   784  	AFCSELD
   785  	AFCSELS
   786  	AFCVTDH
   787  	AFCVTDS
   788  	AFCVTHD
   789  	AFCVTHS
   790  	AFCVTSD
   791  	AFCVTSH
   792  	AFCVTZSD
   793  	AFCVTZSDW
   794  	AFCVTZSS
   795  	AFCVTZSSW
   796  	AFCVTZUD
   797  	AFCVTZUDW
   798  	AFCVTZUS
   799  	AFCVTZUSW
   800  	AFDIVD
   801  	AFDIVS
   802  	AFLDPD
   803  	AFLDPQ
   804  	AFLDPS
   805  	AFMADDD
   806  	AFMADDS
   807  	AFMAXD
   808  	AFMAXNMD
   809  	AFMAXNMS
   810  	AFMAXS
   811  	AFMIND
   812  	AFMINNMD
   813  	AFMINNMS
   814  	AFMINS
   815  	AFMOVD
   816  	AFMOVQ
   817  	AFMOVS
   818  	AFMSUBD
   819  	AFMSUBS
   820  	AFMULD
   821  	AFMULS
   822  	AFNEGD
   823  	AFNEGS
   824  	AFNMADDD
   825  	AFNMADDS
   826  	AFNMSUBD
   827  	AFNMSUBS
   828  	AFNMULD
   829  	AFNMULS
   830  	AFRINTAD
   831  	AFRINTAS
   832  	AFRINTID
   833  	AFRINTIS
   834  	AFRINTMD
   835  	AFRINTMS
   836  	AFRINTND
   837  	AFRINTNS
   838  	AFRINTPD
   839  	AFRINTPS
   840  	AFRINTXD
   841  	AFRINTXS
   842  	AFRINTZD
   843  	AFRINTZS
   844  	AFSQRTD
   845  	AFSQRTS
   846  	AFSTPD
   847  	AFSTPQ
   848  	AFSTPS
   849  	AFSUBD
   850  	AFSUBS
   851  	AHINT
   852  	AHLT
   853  	AHVC
   854  	AIC
   855  	AISB
   856  	ALDADDAB
   857  	ALDADDAD
   858  	ALDADDAH
   859  	ALDADDALB
   860  	ALDADDALD
   861  	ALDADDALH
   862  	ALDADDALW
   863  	ALDADDAW
   864  	ALDADDB
   865  	ALDADDD
   866  	ALDADDH
   867  	ALDADDLB
   868  	ALDADDLD
   869  	ALDADDLH
   870  	ALDADDLW
   871  	ALDADDW
   872  	ALDAR
   873  	ALDARB
   874  	ALDARH
   875  	ALDARW
   876  	ALDAXP
   877  	ALDAXPW
   878  	ALDAXR
   879  	ALDAXRB
   880  	ALDAXRH
   881  	ALDAXRW
   882  	ALDCLRAB
   883  	ALDCLRAD
   884  	ALDCLRAH
   885  	ALDCLRALB
   886  	ALDCLRALD
   887  	ALDCLRALH
   888  	ALDCLRALW
   889  	ALDCLRAW
   890  	ALDCLRB
   891  	ALDCLRD
   892  	ALDCLRH
   893  	ALDCLRLB
   894  	ALDCLRLD
   895  	ALDCLRLH
   896  	ALDCLRLW
   897  	ALDCLRW
   898  	ALDEORAB
   899  	ALDEORAD
   900  	ALDEORAH
   901  	ALDEORALB
   902  	ALDEORALD
   903  	ALDEORALH
   904  	ALDEORALW
   905  	ALDEORAW
   906  	ALDEORB
   907  	ALDEORD
   908  	ALDEORH
   909  	ALDEORLB
   910  	ALDEORLD
   911  	ALDEORLH
   912  	ALDEORLW
   913  	ALDEORW
   914  	ALDORAB
   915  	ALDORAD
   916  	ALDORAH
   917  	ALDORALB
   918  	ALDORALD
   919  	ALDORALH
   920  	ALDORALW
   921  	ALDORAW
   922  	ALDORB
   923  	ALDORD
   924  	ALDORH
   925  	ALDORLB
   926  	ALDORLD
   927  	ALDORLH
   928  	ALDORLW
   929  	ALDORW
   930  	ALDP
   931  	ALDPSW
   932  	ALDPW
   933  	ALDXP
   934  	ALDXPW
   935  	ALDXR
   936  	ALDXRB
   937  	ALDXRH
   938  	ALDXRW
   939  	ALSL
   940  	ALSLW
   941  	ALSR
   942  	ALSRW
   943  	AMADD
   944  	AMADDW
   945  	AMNEG
   946  	AMNEGW
   947  	AMOVB
   948  	AMOVBU
   949  	AMOVD
   950  	AMOVH
   951  	AMOVHU
   952  	AMOVK
   953  	AMOVKW
   954  	AMOVN
   955  	AMOVNW
   956  	AMOVP
   957  	AMOVPD
   958  	AMOVPQ
   959  	AMOVPS
   960  	AMOVPSW
   961  	AMOVPW
   962  	AMOVW
   963  	AMOVWU
   964  	AMOVZ
   965  	AMOVZW
   966  	AMRS
   967  	AMSR
   968  	AMSUB
   969  	AMSUBW
   970  	AMUL
   971  	AMULW
   972  	AMVN
   973  	AMVNW
   974  	ANEG
   975  	ANEGS
   976  	ANEGSW
   977  	ANEGW
   978  	ANGC
   979  	ANGCS
   980  	ANGCSW
   981  	ANGCW
   982  	ANOOP
   983  	AORN
   984  	AORNW
   985  	AORR
   986  	AORRW
   987  	APRFM
   988  	APRFUM
   989  	ARBIT
   990  	ARBITW
   991  	AREM
   992  	AREMW
   993  	AREV
   994  	AREV16
   995  	AREV16W
   996  	AREV32
   997  	AREVW
   998  	AROR
   999  	ARORW
  1000  	ASB
  1001  	ASBC
  1002  	ASBCS
  1003  	ASBCSW
  1004  	ASBCW
  1005  	ASBFIZ
  1006  	ASBFIZW
  1007  	ASBFM
  1008  	ASBFMW
  1009  	ASBFX
  1010  	ASBFXW
  1011  	ASCVTFD
  1012  	ASCVTFS
  1013  	ASCVTFWD
  1014  	ASCVTFWS
  1015  	ASDIV
  1016  	ASDIVW
  1017  	ASEV
  1018  	ASEVL
  1019  	ASHA1C
  1020  	ASHA1H
  1021  	ASHA1M
  1022  	ASHA1P
  1023  	ASHA1SU0
  1024  	ASHA1SU1
  1025  	ASHA256H
  1026  	ASHA256H2
  1027  	ASHA256SU0
  1028  	ASHA256SU1
  1029  	ASHA512H
  1030  	ASHA512H2
  1031  	ASHA512SU0
  1032  	ASHA512SU1
  1033  	ASMADDL
  1034  	ASMC
  1035  	ASMNEGL
  1036  	ASMSUBL
  1037  	ASMULH
  1038  	ASMULL
  1039  	ASTLR
  1040  	ASTLRB
  1041  	ASTLRH
  1042  	ASTLRW
  1043  	ASTLXP
  1044  	ASTLXPW
  1045  	ASTLXR
  1046  	ASTLXRB
  1047  	ASTLXRH
  1048  	ASTLXRW
  1049  	ASTP
  1050  	ASTPW
  1051  	ASTXP
  1052  	ASTXPW
  1053  	ASTXR
  1054  	ASTXRB
  1055  	ASTXRH
  1056  	ASTXRW
  1057  	ASUB
  1058  	ASUBS
  1059  	ASUBSW
  1060  	ASUBW
  1061  	ASVC
  1062  	ASWPAB
  1063  	ASWPAD
  1064  	ASWPAH
  1065  	ASWPALB
  1066  	ASWPALD
  1067  	ASWPALH
  1068  	ASWPALW
  1069  	ASWPAW
  1070  	ASWPB
  1071  	ASWPD
  1072  	ASWPH
  1073  	ASWPLB
  1074  	ASWPLD
  1075  	ASWPLH
  1076  	ASWPLW
  1077  	ASWPW
  1078  	ASXTB
  1079  	ASXTBW
  1080  	ASXTH
  1081  	ASXTHW
  1082  	ASXTW
  1083  	ASYS
  1084  	ASYSL
  1085  	ATBNZ
  1086  	ATBZ
  1087  	ATLBI
  1088  	ATST
  1089  	ATSTW
  1090  	AUBFIZ
  1091  	AUBFIZW
  1092  	AUBFM
  1093  	AUBFMW
  1094  	AUBFX
  1095  	AUBFXW
  1096  	AUCVTFD
  1097  	AUCVTFS
  1098  	AUCVTFWD
  1099  	AUCVTFWS
  1100  	AUDIV
  1101  	AUDIVW
  1102  	AUMADDL
  1103  	AUMNEGL
  1104  	AUMSUBL
  1105  	AUMULH
  1106  	AUMULL
  1107  	AUREM
  1108  	AUREMW
  1109  	AUXTB
  1110  	AUXTBW
  1111  	AUXTH
  1112  	AUXTHW
  1113  	AUXTW
  1114  	AVADD
  1115  	AVADDP
  1116  	AVADDV
  1117  	AVAND
  1118  	AVBCAX
  1119  	AVBIF
  1120  	AVBIT
  1121  	AVBSL
  1122  	AVCMEQ
  1123  	AVCMTST
  1124  	AVCNT
  1125  	AVDUP
  1126  	AVEOR
  1127  	AVEOR3
  1128  	AVEXT
  1129  	AVFMLA
  1130  	AVFMLS
  1131  	AVLD1
  1132  	AVLD1R
  1133  	AVLD2
  1134  	AVLD2R
  1135  	AVLD3
  1136  	AVLD3R
  1137  	AVLD4
  1138  	AVLD4R
  1139  	AVMOV
  1140  	AVMOVD
  1141  	AVMOVI
  1142  	AVMOVQ
  1143  	AVMOVS
  1144  	AVORR
  1145  	AVPMULL
  1146  	AVPMULL2
  1147  	AVRAX1
  1148  	AVRBIT
  1149  	AVREV16
  1150  	AVREV32
  1151  	AVREV64
  1152  	AVSHL
  1153  	AVSLI
  1154  	AVSRI
  1155  	AVST1
  1156  	AVST2
  1157  	AVST3
  1158  	AVST4
  1159  	AVSUB
  1160  	AVTBL
  1161  	AVTBX
  1162  	AVTRN1
  1163  	AVTRN2
  1164  	AVUADDLV
  1165  	AVUADDW
  1166  	AVUADDW2
  1167  	AVUMAX
  1168  	AVUMIN
  1169  	AVUSHLL
  1170  	AVUSHLL2
  1171  	AVUSHR
  1172  	AVUSRA
  1173  	AVUXTL
  1174  	AVUXTL2
  1175  	AVUZP1
  1176  	AVUZP2
  1177  	AVXAR
  1178  	AVZIP1
  1179  	AVZIP2
  1180  	AWFE
  1181  	AWFI
  1182  	AWORD
  1183  	AYIELD
  1184  	ABTI
  1185  	APACIASP
  1186  	AAUTIASP
  1187  	APACIBSP
  1188  	AAUTIBSP
  1189  	AAUTIA1716
  1190  	AAUTIB1716
  1191  	ASVESTART
  1192  	AB  = obj.AJMP
  1193  	ABL = obj.ACALL
  1194  )
  1195  
  1196  const (
  1197  	// shift types
  1198  	SHIFT_LL  = 0 << 22
  1199  	SHIFT_LR  = 1 << 22
  1200  	SHIFT_AR  = 2 << 22
  1201  	SHIFT_ROR = 3 << 22
  1202  )
  1203  
  1204  // Arrangement for ARM64 SIMD instructions
  1205  const (
  1206  	// arrangement types
  1207  	ARNG_8B = iota
  1208  	ARNG_16B
  1209  	ARNG_1D
  1210  	ARNG_4H
  1211  	ARNG_8H
  1212  	ARNG_2S
  1213  	ARNG_4S
  1214  	ARNG_2D
  1215  	ARNG_1Q
  1216  	ARNG_B
  1217  	ARNG_H
  1218  	ARNG_S
  1219  	ARNG_D
  1220  	ARNG_Q
  1221  	PRED_M
  1222  	PRED_Z
  1223  )
  1224  
  1225  //go:generate stringer -type SpecialOperand -trimprefix SPOP_
  1226  type SpecialOperand int
  1227  
  1228  const (
  1229  	// PRFM
  1230  	SPOP_PLDL1KEEP SpecialOperand = obj.SpecialOperandARM64Base + iota     // must be the first one
  1231  	SPOP_BEGIN     SpecialOperand = obj.SpecialOperandARM64Base + iota - 1 // set as the lower bound
  1232  	SPOP_PLDL1STRM
  1233  	SPOP_PLDL2KEEP
  1234  	SPOP_PLDL2STRM
  1235  	SPOP_PLDL3KEEP
  1236  	SPOP_PLDL3STRM
  1237  	SPOP_PLIL1KEEP
  1238  	SPOP_PLIL1STRM
  1239  	SPOP_PLIL2KEEP
  1240  	SPOP_PLIL2STRM
  1241  	SPOP_PLIL3KEEP
  1242  	SPOP_PLIL3STRM
  1243  	SPOP_PSTL1KEEP
  1244  	SPOP_PSTL1STRM
  1245  	SPOP_PSTL2KEEP
  1246  	SPOP_PSTL2STRM
  1247  	SPOP_PSTL3KEEP
  1248  	SPOP_PSTL3STRM
  1249  
  1250  	// TLBI
  1251  	SPOP_VMALLE1IS
  1252  	SPOP_VAE1IS
  1253  	SPOP_ASIDE1IS
  1254  	SPOP_VAAE1IS
  1255  	SPOP_VALE1IS
  1256  	SPOP_VAALE1IS
  1257  	SPOP_VMALLE1
  1258  	SPOP_VAE1
  1259  	SPOP_ASIDE1
  1260  	SPOP_VAAE1
  1261  	SPOP_VALE1
  1262  	SPOP_VAALE1
  1263  	SPOP_IPAS2E1IS
  1264  	SPOP_IPAS2LE1IS
  1265  	SPOP_ALLE2IS
  1266  	SPOP_VAE2IS
  1267  	SPOP_ALLE1IS
  1268  	SPOP_VALE2IS
  1269  	SPOP_VMALLS12E1IS
  1270  	SPOP_IPAS2E1
  1271  	SPOP_IPAS2LE1
  1272  	SPOP_ALLE2
  1273  	SPOP_VAE2
  1274  	SPOP_ALLE1
  1275  	SPOP_VALE2
  1276  	SPOP_VMALLS12E1
  1277  	SPOP_ALLE3IS
  1278  	SPOP_VAE3IS
  1279  	SPOP_VALE3IS
  1280  	SPOP_ALLE3
  1281  	SPOP_VAE3
  1282  	SPOP_VALE3
  1283  	SPOP_VMALLE1OS
  1284  	SPOP_VAE1OS
  1285  	SPOP_ASIDE1OS
  1286  	SPOP_VAAE1OS
  1287  	SPOP_VALE1OS
  1288  	SPOP_VAALE1OS
  1289  	SPOP_RVAE1IS
  1290  	SPOP_RVAAE1IS
  1291  	SPOP_RVALE1IS
  1292  	SPOP_RVAALE1IS
  1293  	SPOP_RVAE1OS
  1294  	SPOP_RVAAE1OS
  1295  	SPOP_RVALE1OS
  1296  	SPOP_RVAALE1OS
  1297  	SPOP_RVAE1
  1298  	SPOP_RVAAE1
  1299  	SPOP_RVALE1
  1300  	SPOP_RVAALE1
  1301  	SPOP_RIPAS2E1IS
  1302  	SPOP_RIPAS2LE1IS
  1303  	SPOP_ALLE2OS
  1304  	SPOP_VAE2OS
  1305  	SPOP_ALLE1OS
  1306  	SPOP_VALE2OS
  1307  	SPOP_VMALLS12E1OS
  1308  	SPOP_RVAE2IS
  1309  	SPOP_RVALE2IS
  1310  	SPOP_IPAS2E1OS
  1311  	SPOP_RIPAS2E1
  1312  	SPOP_RIPAS2E1OS
  1313  	SPOP_IPAS2LE1OS
  1314  	SPOP_RIPAS2LE1
  1315  	SPOP_RIPAS2LE1OS
  1316  	SPOP_RVAE2OS
  1317  	SPOP_RVALE2OS
  1318  	SPOP_RVAE2
  1319  	SPOP_RVALE2
  1320  	SPOP_ALLE3OS
  1321  	SPOP_VAE3OS
  1322  	SPOP_VALE3OS
  1323  	SPOP_RVAE3IS
  1324  	SPOP_RVALE3IS
  1325  	SPOP_RVAE3OS
  1326  	SPOP_RVALE3OS
  1327  	SPOP_RVAE3
  1328  	SPOP_RVALE3
  1329  
  1330  	// DC
  1331  	SPOP_IVAC
  1332  	SPOP_ISW
  1333  	SPOP_CSW
  1334  	SPOP_CISW
  1335  	SPOP_ZVA
  1336  	SPOP_CVAC
  1337  	SPOP_CVAU
  1338  	SPOP_CIVAC
  1339  	SPOP_IGVAC
  1340  	SPOP_IGSW
  1341  	SPOP_IGDVAC
  1342  	SPOP_IGDSW
  1343  	SPOP_CGSW
  1344  	SPOP_CGDSW
  1345  	SPOP_CIGSW
  1346  	SPOP_CIGDSW
  1347  	SPOP_GVA
  1348  	SPOP_GZVA
  1349  	SPOP_CGVAC
  1350  	SPOP_CGDVAC
  1351  	SPOP_CGVAP
  1352  	SPOP_CGDVAP
  1353  	SPOP_CGVADP
  1354  	SPOP_CGDVADP
  1355  	SPOP_CIGVAC
  1356  	SPOP_CIGDVAC
  1357  	SPOP_CVAP
  1358  	SPOP_CVADP
  1359  
  1360  	// PSTATE fields
  1361  	SPOP_DAIFSet
  1362  	SPOP_DAIFClr
  1363  
  1364  	// Condition code, EQ, NE, etc. Their relative order to EQ matters.
  1365  	SPOP_EQ
  1366  	SPOP_NE
  1367  	SPOP_HS
  1368  	SPOP_LO
  1369  	SPOP_MI
  1370  	SPOP_PL
  1371  	SPOP_VS
  1372  	SPOP_VC
  1373  	SPOP_HI
  1374  	SPOP_LS
  1375  	SPOP_GE
  1376  	SPOP_LT
  1377  	SPOP_GT
  1378  	SPOP_LE
  1379  	SPOP_AL
  1380  	SPOP_NV
  1381  
  1382  	// Branch Target Indicator (BTI) targets
  1383  	SPOP_C
  1384  	SPOP_J
  1385  	SPOP_JC
  1386  
  1387  	SPOP_END
  1388  )
  1389
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