a.out.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  )
    10  
    11  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64
    12  
    13  const (
    14  	NSNAME = 8
    15  	NSYM   = 50
    16  	NREG   = 32 // number of general registers
    17  	NFREG  = 32 // number of floating point registers
    18  	NVREG  = 32 // number of LSX registers
    19  	NXREG  = 32 // number of LASX registers
    20  )
    21  
    22  const (
    23  	REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32
    24  	REG_R1
    25  	REG_R2
    26  	REG_R3
    27  	REG_R4
    28  	REG_R5
    29  	REG_R6
    30  	REG_R7
    31  	REG_R8
    32  	REG_R9
    33  	REG_R10
    34  	REG_R11
    35  	REG_R12
    36  	REG_R13
    37  	REG_R14
    38  	REG_R15
    39  	REG_R16
    40  	REG_R17
    41  	REG_R18
    42  	REG_R19
    43  	REG_R20
    44  	REG_R21
    45  	REG_R22
    46  	REG_R23
    47  	REG_R24
    48  	REG_R25
    49  	REG_R26
    50  	REG_R27
    51  	REG_R28
    52  	REG_R29
    53  	REG_R30
    54  	REG_R31
    55  
    56  	REG_F0 // must be a multiple of 32
    57  	REG_F1
    58  	REG_F2
    59  	REG_F3
    60  	REG_F4
    61  	REG_F5
    62  	REG_F6
    63  	REG_F7
    64  	REG_F8
    65  	REG_F9
    66  	REG_F10
    67  	REG_F11
    68  	REG_F12
    69  	REG_F13
    70  	REG_F14
    71  	REG_F15
    72  	REG_F16
    73  	REG_F17
    74  	REG_F18
    75  	REG_F19
    76  	REG_F20
    77  	REG_F21
    78  	REG_F22
    79  	REG_F23
    80  	REG_F24
    81  	REG_F25
    82  	REG_F26
    83  	REG_F27
    84  	REG_F28
    85  	REG_F29
    86  	REG_F30
    87  	REG_F31
    88  
    89  	REG_FCSR0 // must be a multiple of 32
    90  	REG_FCSR1
    91  	REG_FCSR2
    92  	REG_FCSR3 // only four registers are needed
    93  	REG_FCSR4
    94  	REG_FCSR5
    95  	REG_FCSR6
    96  	REG_FCSR7
    97  	REG_FCSR8
    98  	REG_FCSR9
    99  	REG_FCSR10
   100  	REG_FCSR11
   101  	REG_FCSR12
   102  	REG_FCSR13
   103  	REG_FCSR14
   104  	REG_FCSR15
   105  	REG_FCSR16
   106  	REG_FCSR17
   107  	REG_FCSR18
   108  	REG_FCSR19
   109  	REG_FCSR20
   110  	REG_FCSR21
   111  	REG_FCSR22
   112  	REG_FCSR23
   113  	REG_FCSR24
   114  	REG_FCSR25
   115  	REG_FCSR26
   116  	REG_FCSR27
   117  	REG_FCSR28
   118  	REG_FCSR29
   119  	REG_FCSR30
   120  	REG_FCSR31
   121  
   122  	REG_FCC0 // must be a multiple of 32
   123  	REG_FCC1
   124  	REG_FCC2
   125  	REG_FCC3
   126  	REG_FCC4
   127  	REG_FCC5
   128  	REG_FCC6
   129  	REG_FCC7 // only eight registers are needed
   130  	REG_FCC8
   131  	REG_FCC9
   132  	REG_FCC10
   133  	REG_FCC11
   134  	REG_FCC12
   135  	REG_FCC13
   136  	REG_FCC14
   137  	REG_FCC15
   138  	REG_FCC16
   139  	REG_FCC17
   140  	REG_FCC18
   141  	REG_FCC19
   142  	REG_FCC20
   143  	REG_FCC21
   144  	REG_FCC22
   145  	REG_FCC23
   146  	REG_FCC24
   147  	REG_FCC25
   148  	REG_FCC26
   149  	REG_FCC27
   150  	REG_FCC28
   151  	REG_FCC29
   152  	REG_FCC30
   153  	REG_FCC31
   154  
   155  	// LSX: 128-bit vector register
   156  	REG_V0
   157  	REG_V1
   158  	REG_V2
   159  	REG_V3
   160  	REG_V4
   161  	REG_V5
   162  	REG_V6
   163  	REG_V7
   164  	REG_V8
   165  	REG_V9
   166  	REG_V10
   167  	REG_V11
   168  	REG_V12
   169  	REG_V13
   170  	REG_V14
   171  	REG_V15
   172  	REG_V16
   173  	REG_V17
   174  	REG_V18
   175  	REG_V19
   176  	REG_V20
   177  	REG_V21
   178  	REG_V22
   179  	REG_V23
   180  	REG_V24
   181  	REG_V25
   182  	REG_V26
   183  	REG_V27
   184  	REG_V28
   185  	REG_V29
   186  	REG_V30
   187  	REG_V31
   188  
   189  	// LASX: 256-bit vector register
   190  	REG_X0
   191  	REG_X1
   192  	REG_X2
   193  	REG_X3
   194  	REG_X4
   195  	REG_X5
   196  	REG_X6
   197  	REG_X7
   198  	REG_X8
   199  	REG_X9
   200  	REG_X10
   201  	REG_X11
   202  	REG_X12
   203  	REG_X13
   204  	REG_X14
   205  	REG_X15
   206  	REG_X16
   207  	REG_X17
   208  	REG_X18
   209  	REG_X19
   210  	REG_X20
   211  	REG_X21
   212  	REG_X22
   213  	REG_X23
   214  	REG_X24
   215  	REG_X25
   216  	REG_X26
   217  	REG_X27
   218  	REG_X28
   219  	REG_X29
   220  	REG_X30
   221  	REG_X31
   222  
   223  	REG_SPECIAL = REG_FCSR0
   224  
   225  	REGZERO = REG_R0 // set to zero
   226  	REGLINK = REG_R1
   227  	REGSP   = REG_R3
   228  	REGCTXT = REG_R29 // context for closures
   229  	REGG    = REG_R22 // G in loong64
   230  	REGTMP  = REG_R30 // used by the assembler
   231  	FREGRET = REG_F0  // not use
   232  )
   233  
   234  var LOONG64DWARFRegisters = map[int16]int16{}
   235  
   236  func init() {
   237  	// f assigns dwarfregisters[from:to] = (base):(to-from+base)
   238  	f := func(from, to, base int16) {
   239  		for r := from; r <= to; r++ {
   240  			LOONG64DWARFRegisters[r] = (r - from) + base
   241  		}
   242  	}
   243  	f(REG_R0, REG_R31, 0)
   244  	f(REG_F0, REG_F31, 32)
   245  
   246  	// The lower bits of V and X registers are alias to F registers
   247  	f(REG_V0, REG_V31, 32)
   248  	f(REG_X0, REG_X31, 32)
   249  }
   250  
   251  const (
   252  	BIG_8  = 128 - 2 // FIXME (not sure if -2 is appropriate)
   253  	BIG_9  = 256 - 2
   254  	BIG_10 = 512 - 2
   255  	BIG_11 = 1024 - 2
   256  	BIG_12 = 2046
   257  	BIG_16 = 32768 - 2
   258  	BIG_32 = 2147483648 - 2
   259  )
   260  
   261  const (
   262  	// mark flags
   263  	LABEL  = 1 << 0
   264  	LEAF   = 1 << 1
   265  	SYNC   = 1 << 2
   266  	BRANCH = 1 << 3
   267  )
   268  
   269  // Arrangement for Loong64 SIMD instructions
   270  const (
   271  	// arrangement types
   272  	ARNG_32B int16 = iota
   273  	ARNG_16H
   274  	ARNG_8W
   275  	ARNG_4V
   276  	ARNG_2Q
   277  	ARNG_16B
   278  	ARNG_8H
   279  	ARNG_4W
   280  	ARNG_2V
   281  	ARNG_B
   282  	ARNG_H
   283  	ARNG_W
   284  	ARNG_V
   285  	ARNG_BU
   286  	ARNG_HU
   287  	ARNG_WU
   288  	ARNG_VU
   289  )
   290  
   291  // LoongArch64 SIMD extension type
   292  const (
   293  	LSX int16 = iota
   294  	LASX
   295  )
   296  
   297  // bits 0-4 indicates register: Vn or Xn
   298  // bits 5-9 indicates arrangement: <T>
   299  // bits 10 indicates SMID type: 0: LSX, 1: LASX
   300  const (
   301  	REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn.<T>
   302  	REG_ELEM                                               // Vn.<T>[index]
   303  	REG_ELEM_END
   304  )
   305  
   306  const (
   307  	EXT_REG_SHIFT = 0
   308  	EXT_REG_MASK  = 0x1f
   309  
   310  	EXT_TYPE_SHIFT = 5
   311  	EXT_TYPE_MASK  = 0x1f
   312  
   313  	EXT_SIMDTYPE_SHIFT = 10
   314  	EXT_SIMDTYPE_MASK  = 0x1
   315  )
   316  
   317  const (
   318  	REG_LAST = REG_ELEM_END // the last defined register
   319  )
   320  
   321  //go:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
   322  const (
   323  	C_NONE = iota
   324  	C_REG
   325  	C_FREG
   326  	C_FCSRREG
   327  	C_FCCREG
   328  	C_VREG
   329  	C_XREG
   330  	C_ARNG // Vn.<T>
   331  	C_ELEM // Vn.<T>[index]
   332  
   333  	C_ZCON
   334  	C_U1CON      // 1 bit unsigned constant
   335  	C_U2CON      // 2 bit unsigned constant
   336  	C_U3CON      // 3 bit unsigned constant
   337  	C_U4CON      // 4 bit unsigned constant
   338  	C_U5CON      // 5 bit unsigned constant
   339  	C_U6CON      // 6 bit unsigned constant
   340  	C_U7CON      // 7 bit unsigned constant
   341  	C_U8CON      // 8 bit unsigned constant
   342  	C_S5CON      // 5 bit signed constant
   343  	C_US12CON    // same as C_S12CON, increase the priority of C_S12CON in special cases.
   344  	C_UU12CON    // same as C_U12CON, increase the priority of C_U12CON in special cases.
   345  	C_S12CON     // 12 bit signed constant, -0x800 < v <= 0x7ff
   346  	C_U12CON     // 12 bit unsigned constant, 0 < v <= 0xfff
   347  	C_12CON      // 12 bit signed constant, or 12 bit unsigned constant
   348  	C_S13CON20_0 // 13 bit signed constant, low 12 bits 0
   349  	C_S13CON     // 13 bit signed constant
   350  	C_U13CON20_0 // 13 bit unsigned constant, low 12 bits 0
   351  	C_U13CON     // 13 bit unsigned constant
   352  	C_13CON      // 13 bit signed constant, or 13 bit unsigned constant
   353  	C_U15CON     // 15 bit unsigned constant
   354  	C_U15CON20_0 // 15 bit unsigned constant, low 12 bits 0
   355  	C_32CON20_0  // 32 bit signed, low 12 bits 0
   356  	C_32CON      // other 32 bit signed
   357  
   358  	// 64 bit signed, lo32 bits 0, hi20 bits are not 0, hi12 bits can
   359  	// be obtained by sign extension of the hi20 bits.
   360  	C_DCON20S_0
   361  	// 64 bit signed, lo52 bits 0, hi12 bits are not 0.
   362  	C_DCON12_0
   363  	// 64 bit signed, lo32 bits 0, hi32 bits are not 0.
   364  	C_DCON32_0
   365  	// 64 bit signed, lo12 bits 0, lo20 bits are not 0, hi20 bits can be
   366  	// obtained by sign extension of the lo20 bits, other bits are not 0.
   367  	C_DCON12_20S
   368  	// 64 bit signed, lo12 bits 0, hi20 bits are not 0, hi12 bits can be
   369  	// obtained by sign extension of the hi20 bits, other bits are not 0.
   370  	C_DCON20S_20
   371  	// 64 bit signed, lo12 bits 0, other bits are not 0.
   372  	C_DCON32_20
   373  	// 64 bit signed, lo12 bits are not 0, 12~51 bits can be obtained
   374  	// by sign extension of the lo12 bits, other bits are not 0.
   375  	C_DCON12_12S
   376  	// 64 bit signed, hi20 bits and lo12 bits are not 0, hi12 bits can
   377  	// be obtained by sign extension of the hi20 bits, lo20 bits can
   378  	// be obtained by sign extension of the lo12 bits.
   379  	C_DCON20S_12S
   380  	// 64 bit signed, lo12 bits are not 0, lo20 bits can be obtained by sign
   381  	// extension of the lo12 bits, other bits are not 0.
   382  	C_DCON32_12S
   383  	// 64 bit signed, lo20 and lo12 bits are not 0, hi20 bits can be obtained by sign
   384  	// extension of the lo20 bits. other bits are not 0.
   385  	C_DCON12_32S
   386  	// 64 bit signed, hi20 bits are not 0, hi12 bits can be obtained by sign
   387  	// extension of the hi20 bits, lo32 bits are not 0.
   388  	C_DCON20S_32
   389  	// 64 bit signed, 12~51 bits 0, other bits are not 0.
   390  	C_DCON12_12U
   391  	// 64 bit signed, lo20 bits 0, hi20 bits are not 0, hi12 bits can be
   392  	// obtained by sign extension of the hi20 bits, lo12 bits are not 0.
   393  	C_DCON20S_12U
   394  	// 64 bit signed, lo20 bits 0, other bits are not 0.
   395  	C_DCON32_12U
   396  	// other 64
   397  	C_DCON
   398  
   399  	C_SACON   // $n(REG) where n <= int12
   400  	C_LACON   // $n(REG) where int12 < n <= int32
   401  	C_DACON   // $n(REG) where int32 < n
   402  	C_EXTADDR // external symbol address
   403  	C_BRAN
   404  	C_SAUTO
   405  	C_LAUTO
   406  	C_ZOREG    // An $0+reg memory op
   407  	C_SOREG_8  // An $n+reg memory arg where n is a 8 bit signed offset
   408  	C_SOREG_9  // An $n+reg memory arg where n is a 9 bit signed offset
   409  	C_SOREG_10 // An $n+reg memory arg where n is a 10 bit signed offset
   410  	C_SOREG_11 // An $n+reg memory arg where n is a 11 bit signed offset
   411  	C_SOREG_12 // An $n+reg memory arg where n is a 12 bit signed offset
   412  	C_SOREG_16 // An $n+reg memory arg where n is a 16 bit signed offset
   413  	C_LOREG_32 // An $n+reg memory arg where n is a 32 bit signed offset
   414  	C_LOREG_64 // An $n+reg memory arg where n is a 64 bit signed offset
   415  	C_ROFF     // register offset
   416  	C_ADDR
   417  	C_TLS_LE
   418  	C_TLS_IE
   419  	C_GOTADDR
   420  	C_TEXTSIZE
   421  
   422  	C_GOK
   423  	C_NCLASS // must be the last
   424  )
   425  
   426  const (
   427  	AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota
   428  	AABSF
   429  	AADD
   430  	AADDD
   431  	AADDF
   432  
   433  	AADDW
   434  	AAND
   435  	ABEQ
   436  	ABGEZ
   437  	ABLEZ
   438  	ABGTZ
   439  	ABLTZ
   440  	ABFPF
   441  	ABFPT
   442  
   443  	ABNE
   444  	ABREAK
   445  
   446  	ACMPEQD
   447  	ACMPEQF
   448  
   449  	ACMPGED // ACMPGED -> fcmp.sle.d
   450  	ACMPGEF // ACMPGEF -> fcmp.sle.s
   451  	ACMPGTD // ACMPGTD -> fcmp.slt.d
   452  	ACMPGTF // ACMPGTF -> fcmp.slt.s
   453  
   454  	ALU12IW
   455  	ALU32ID
   456  	ALU52ID
   457  	APCALAU12I
   458  	APCADDU12I
   459  	AJIRL
   460  	ABGE
   461  	ABLT
   462  	ABLTU
   463  	ABGEU
   464  
   465  	ADIV
   466  	ADIVD
   467  	ADIVF
   468  	ADIVU
   469  	ADIVW
   470  	ADIVWU
   471  
   472  	ALL
   473  	ALLV
   474  
   475  	ALUI
   476  
   477  	AMOVB
   478  	AMOVBU
   479  
   480  	AMOVD
   481  	AMOVDF
   482  	AMOVDW
   483  	AMOVF
   484  	AMOVFD
   485  	AMOVFW
   486  
   487  	AMOVH
   488  	AMOVHU
   489  	AMOVW
   490  
   491  	AMOVWD
   492  	AMOVWF
   493  
   494  	AMUL
   495  	AMULD
   496  	AMULF
   497  	AMULH
   498  	AMULHU
   499  	AMULW
   500  	ANEGD
   501  	ANEGF
   502  
   503  	ANEGW
   504  	ANEGV
   505  
   506  	ANOOP // hardware nop
   507  	ANOR
   508  	AOR
   509  	AREM
   510  	AREMW
   511  	AREMU
   512  	AREMWU
   513  
   514  	ARFE
   515  
   516  	ASC
   517  	ASCV
   518  
   519  	ASGT
   520  	ASGTU
   521  
   522  	ASLL
   523  	ASQRTD
   524  	ASQRTF
   525  	ASRA
   526  	ASRL
   527  	AROTR
   528  	ASUB
   529  	ASUBD
   530  	ASUBF
   531  
   532  	ASUBW
   533  	ADBAR
   534  	ASYSCALL
   535  
   536  	ATEQ
   537  	ATNE
   538  
   539  	AWORD
   540  
   541  	AXOR
   542  
   543  	AMASKEQZ
   544  	AMASKNEZ
   545  
   546  	// 64-bit
   547  	AMOVV
   548  
   549  	ASLLV
   550  	ASRAV
   551  	ASRLV
   552  	AROTRV
   553  	ADIVV
   554  	ADIVVU
   555  
   556  	AREMV
   557  	AREMVU
   558  
   559  	AMULV
   560  	AMULVU
   561  	AMULHV
   562  	AMULHVU
   563  	AADDV
   564  	AADDVU
   565  	ASUBV
   566  	ASUBVU
   567  
   568  	// 64-bit FP
   569  	ATRUNCFV
   570  	ATRUNCDV
   571  	ATRUNCFW
   572  	ATRUNCDW
   573  
   574  	AMOVWU
   575  	AMOVFV
   576  	AMOVDV
   577  	AMOVVF
   578  	AMOVVD
   579  
   580  	// 2.2.1.2
   581  	AADDV16
   582  
   583  	// 2.2.1.3
   584  	AALSLW
   585  	AALSLWU
   586  	AALSLV
   587  
   588  	// 2.2.1.8
   589  	AORN
   590  	AANDN
   591  
   592  	// 2.2.1.12
   593  	AMULWVW
   594  	AMULWVWU
   595  
   596  	// 2.2.7. Atomic Memory Access Instructions
   597  	AAMSWAPB
   598  	AAMSWAPH
   599  	AAMSWAPW
   600  	AAMSWAPV
   601  	AAMCASB
   602  	AAMCASH
   603  	AAMCASW
   604  	AAMCASV
   605  	AAMADDW
   606  	AAMADDV
   607  	AAMANDW
   608  	AAMANDV
   609  	AAMORW
   610  	AAMORV
   611  	AAMXORW
   612  	AAMXORV
   613  	AAMMAXW
   614  	AAMMAXV
   615  	AAMMINW
   616  	AAMMINV
   617  	AAMMAXWU
   618  	AAMMAXVU
   619  	AAMMINWU
   620  	AAMMINVU
   621  	AAMSWAPDBB
   622  	AAMSWAPDBH
   623  	AAMSWAPDBW
   624  	AAMSWAPDBV
   625  	AAMCASDBB
   626  	AAMCASDBH
   627  	AAMCASDBW
   628  	AAMCASDBV
   629  	AAMADDDBW
   630  	AAMADDDBV
   631  	AAMANDDBW
   632  	AAMANDDBV
   633  	AAMORDBW
   634  	AAMORDBV
   635  	AAMXORDBW
   636  	AAMXORDBV
   637  	AAMMAXDBW
   638  	AAMMAXDBV
   639  	AAMMINDBW
   640  	AAMMINDBV
   641  	AAMMAXDBWU
   642  	AAMMAXDBVU
   643  	AAMMINDBWU
   644  	AAMMINDBVU
   645  
   646  	// 2.2.3.1
   647  	AEXTWB
   648  	AEXTWH
   649  
   650  	// 2.2.3.2
   651  	ACLOW
   652  	ACLOV
   653  	ACLZW
   654  	ACLZV
   655  	ACTOW
   656  	ACTOV
   657  	ACTZW
   658  	ACTZV
   659  
   660  	// 2.2.3.4
   661  	AREVBV
   662  	AREVB2W
   663  	AREVB4H
   664  	AREVB2H
   665  
   666  	// 2.2.3.5
   667  	AREVH2W
   668  	AREVHV
   669  
   670  	// 2.2.3.6
   671  	ABITREV4B
   672  	ABITREV8B
   673  
   674  	// 2.2.3.7
   675  	ABITREVW
   676  	ABITREVV
   677  
   678  	// 2.2.3.8
   679  	ABSTRINSW
   680  	ABSTRINSV
   681  
   682  	// 2.2.3.9
   683  	ABSTRPICKW
   684  	ABSTRPICKV
   685  
   686  	// 2.2.5.3
   687  	AMOVWP
   688  	AMOVVP
   689  
   690  	// 2.2.5.4. Prefetch Instructions
   691  	APRELD
   692  	APRELDX
   693  
   694  	// 2.2.9. CRC Check Instructions
   695  	ACRCWBW
   696  	ACRCWHW
   697  	ACRCWWW
   698  	ACRCWVW
   699  	ACRCCWBW
   700  	ACRCCWHW
   701  	ACRCCWWW
   702  	ACRCCWVW
   703  
   704  	// 2.2.10. Other Miscellaneous Instructions
   705  	ARDTIMELW
   706  	ARDTIMEHW
   707  	ARDTIMED
   708  	ACPUCFG
   709  
   710  	// 3.2.1.2
   711  	AFMADDF
   712  	AFMADDD
   713  	AFMSUBF
   714  	AFMSUBD
   715  	AFNMADDF
   716  	AFNMADDD
   717  	AFNMSUBF
   718  	AFNMSUBD
   719  
   720  	// 3.2.1.3
   721  	AFMINF
   722  	AFMIND
   723  	AFMAXF
   724  	AFMAXD
   725  
   726  	// 3.2.1.4
   727  	AFMAXAF
   728  	AFMAXAD
   729  	AFMINAF
   730  	AFMINAD
   731  
   732  	// 3.2.1.7
   733  	AFCOPYSGF
   734  	AFCOPYSGD
   735  	AFSCALEBF
   736  	AFSCALEBD
   737  	AFLOGBF
   738  	AFLOGBD
   739  
   740  	// 3.2.1.8
   741  	AFCLASSF
   742  	AFCLASSD
   743  
   744  	// 3.2.3.2
   745  	AFFINTFW
   746  	AFFINTFV
   747  	AFFINTDW
   748  	AFFINTDV
   749  	AFTINTWF
   750  	AFTINTWD
   751  	AFTINTVF
   752  	AFTINTVD
   753  
   754  	// 3.2.3.3
   755  	AFTINTRPWF
   756  	AFTINTRPWD
   757  	AFTINTRPVF
   758  	AFTINTRPVD
   759  	AFTINTRMWF
   760  	AFTINTRMWD
   761  	AFTINTRMVF
   762  	AFTINTRMVD
   763  	AFTINTRZWF
   764  	AFTINTRZWD
   765  	AFTINTRZVF
   766  	AFTINTRZVD
   767  	AFTINTRNEWF
   768  	AFTINTRNEWD
   769  	AFTINTRNEVF
   770  	AFTINTRNEVD
   771  
   772  	// 3.2.4.2
   773  	AFSEL
   774  
   775  	// LSX and LASX memory access instructions
   776  	AVMOVQ
   777  	AXVMOVQ
   778  
   779  	// LSX and LASX arithmetic instructions
   780  	AVADDB
   781  	AVADDH
   782  	AVADDW
   783  	AVADDV
   784  	AVADDQ
   785  	AXVADDB
   786  	AXVADDH
   787  	AXVADDW
   788  	AXVADDV
   789  	AXVADDQ
   790  	AVSUBB
   791  	AVSUBH
   792  	AVSUBW
   793  	AVSUBV
   794  	AVSUBQ
   795  	AXVSUBB
   796  	AXVSUBH
   797  	AXVSUBW
   798  	AXVSUBV
   799  	AXVSUBQ
   800  	AVADDBU
   801  	AVADDHU
   802  	AVADDWU
   803  	AVADDVU
   804  	AVSUBBU
   805  	AVSUBHU
   806  	AVSUBWU
   807  	AVSUBVU
   808  	AXVADDBU
   809  	AXVADDHU
   810  	AXVADDWU
   811  	AXVADDVU
   812  	AXVSUBBU
   813  	AXVSUBHU
   814  	AXVSUBWU
   815  	AXVSUBVU
   816  	AVSADDB
   817  	AVSADDH
   818  	AVSADDW
   819  	AVSADDV
   820  	AVSSUBB
   821  	AVSSUBH
   822  	AVSSUBW
   823  	AVSSUBV
   824  	AVSADDBU
   825  	AVSADDHU
   826  	AVSADDWU
   827  	AVSADDVU
   828  	AVSSUBBU
   829  	AVSSUBHU
   830  	AVSSUBWU
   831  	AVSSUBVU
   832  	AXVSADDB
   833  	AXVSADDH
   834  	AXVSADDW
   835  	AXVSADDV
   836  	AXVSSUBB
   837  	AXVSSUBH
   838  	AXVSSUBW
   839  	AXVSSUBV
   840  	AXVSADDBU
   841  	AXVSADDHU
   842  	AXVSADDWU
   843  	AXVSADDVU
   844  	AXVSSUBBU
   845  	AXVSSUBHU
   846  	AXVSSUBWU
   847  	AXVSSUBVU
   848  
   849  	// LSX and LASX Bit-manipulation Instructions
   850  	AVANDB
   851  	AVORB
   852  	AVXORB
   853  	AVNORB
   854  	AXVANDB
   855  	AXVORB
   856  	AXVXORB
   857  	AXVNORB
   858  	AVANDV
   859  	AVORV
   860  	AVXORV
   861  	AVNORV
   862  	AVANDNV
   863  	AVORNV
   864  	AXVANDV
   865  	AXVORV
   866  	AXVXORV
   867  	AXVNORV
   868  	AXVANDNV
   869  	AXVORNV
   870  
   871  	AVPCNTB
   872  	AVPCNTH
   873  	AVPCNTW
   874  	AVPCNTV
   875  	AXVPCNTB
   876  	AXVPCNTH
   877  	AXVPCNTW
   878  	AXVPCNTV
   879  
   880  	AVBITCLRB
   881  	AVBITCLRH
   882  	AVBITCLRW
   883  	AVBITCLRV
   884  	AVBITSETB
   885  	AVBITSETH
   886  	AVBITSETW
   887  	AVBITSETV
   888  	AVBITREVB
   889  	AVBITREVH
   890  	AVBITREVW
   891  	AVBITREVV
   892  	AXVBITCLRB
   893  	AXVBITCLRH
   894  	AXVBITCLRW
   895  	AXVBITCLRV
   896  	AXVBITSETB
   897  	AXVBITSETH
   898  	AXVBITSETW
   899  	AXVBITSETV
   900  	AXVBITREVB
   901  	AXVBITREVH
   902  	AXVBITREVW
   903  	AXVBITREVV
   904  
   905  	// LSX and LASX integer comparison instruction
   906  	AVSEQB
   907  	AXVSEQB
   908  	AVSEQH
   909  	AXVSEQH
   910  	AVSEQW
   911  	AXVSEQW
   912  	AVSEQV
   913  	AXVSEQV
   914  
   915  	AVSLTB
   916  	AVSLTH
   917  	AVSLTW
   918  	AVSLTV
   919  	AVSLTBU
   920  	AVSLTHU
   921  	AVSLTWU
   922  	AVSLTVU
   923  	AXVSLTB
   924  	AXVSLTH
   925  	AXVSLTW
   926  	AXVSLTV
   927  	AXVSLTBU
   928  	AXVSLTHU
   929  	AXVSLTWU
   930  	AXVSLTVU
   931  
   932  	// LSX and LASX integer div and mod instructions
   933  	AVDIVB
   934  	AVDIVH
   935  	AVDIVW
   936  	AVDIVV
   937  	AVDIVBU
   938  	AVDIVHU
   939  	AVDIVWU
   940  	AVDIVVU
   941  	AVMODB
   942  	AVMODH
   943  	AVMODW
   944  	AVMODV
   945  	AVMODBU
   946  	AVMODHU
   947  	AVMODWU
   948  	AVMODVU
   949  	AXVDIVB
   950  	AXVDIVH
   951  	AXVDIVW
   952  	AXVDIVV
   953  	AXVDIVBU
   954  	AXVDIVHU
   955  	AXVDIVWU
   956  	AXVDIVVU
   957  	AXVMODB
   958  	AXVMODH
   959  	AXVMODW
   960  	AXVMODV
   961  	AXVMODBU
   962  	AXVMODHU
   963  	AXVMODWU
   964  	AXVMODVU
   965  
   966  	// LSX and LASX shift operation instructions
   967  	AVSLLB
   968  	AVSLLH
   969  	AVSLLW
   970  	AVSLLV
   971  	AVSRLB
   972  	AVSRLH
   973  	AVSRLW
   974  	AVSRLV
   975  	AVSRAB
   976  	AVSRAH
   977  	AVSRAW
   978  	AVSRAV
   979  	AVROTRB
   980  	AVROTRH
   981  	AVROTRW
   982  	AVROTRV
   983  	AXVSLLB
   984  	AXVSLLH
   985  	AXVSLLW
   986  	AXVSLLV
   987  	AXVSRLB
   988  	AXVSRLH
   989  	AXVSRLW
   990  	AXVSRLV
   991  	AXVSRAB
   992  	AXVSRAH
   993  	AXVSRAW
   994  	AXVSRAV
   995  	AXVROTRB
   996  	AXVROTRH
   997  	AXVROTRW
   998  	AXVROTRV
   999  
  1000  	// LSX and LASX move and shuffle instructions
  1001  	AVILVLB
  1002  	AVILVLH
  1003  	AVILVLW
  1004  	AVILVLV
  1005  	AVILVHB
  1006  	AVILVHH
  1007  	AVILVHW
  1008  	AVILVHV
  1009  	AXVILVLB
  1010  	AXVILVLH
  1011  	AXVILVLW
  1012  	AXVILVLV
  1013  	AXVILVHB
  1014  	AXVILVHH
  1015  	AXVILVHW
  1016  	AXVILVHV
  1017  
  1018  	// LSX and LASX integer mul instructions
  1019  	AVMULB
  1020  	AVMULH
  1021  	AVMULW
  1022  	AVMULV
  1023  	AVMUHB
  1024  	AVMUHH
  1025  	AVMUHW
  1026  	AVMUHV
  1027  	AVMUHBU
  1028  	AVMUHHU
  1029  	AVMUHWU
  1030  	AVMUHVU
  1031  	AXVMULB
  1032  	AXVMULH
  1033  	AXVMULW
  1034  	AXVMULV
  1035  	AXVMUHB
  1036  	AXVMUHH
  1037  	AXVMUHW
  1038  	AXVMUHV
  1039  	AXVMUHBU
  1040  	AXVMUHHU
  1041  	AXVMUHWU
  1042  	AXVMUHVU
  1043  
  1044  	// LSX and LASX floating point instructions
  1045  	AVFSQRTF
  1046  	AVFSQRTD
  1047  	AVFRECIPF
  1048  	AVFRECIPD
  1049  	AVFRSQRTF
  1050  	AVFRSQRTD
  1051  	AXVFSQRTF
  1052  	AXVFSQRTD
  1053  	AXVFRECIPF
  1054  	AXVFRECIPD
  1055  	AXVFRSQRTF
  1056  	AXVFRSQRTD
  1057  
  1058  	AVADDF
  1059  	AVADDD
  1060  	AVSUBF
  1061  	AVSUBD
  1062  	AVMULF
  1063  	AVMULD
  1064  	AVDIVF
  1065  	AVDIVD
  1066  	AXVADDF
  1067  	AXVADDD
  1068  	AXVSUBF
  1069  	AXVSUBD
  1070  	AXVMULF
  1071  	AXVMULD
  1072  	AXVDIVF
  1073  	AXVDIVD
  1074  
  1075  	AVFCLASSF
  1076  	AVFCLASSD
  1077  	AXVFCLASSF
  1078  	AXVFCLASSD
  1079  
  1080  	// LSX and LASX floating point conversion instructions
  1081  	AVFRINTRNEF
  1082  	AVFRINTRNED
  1083  	AVFRINTRZF
  1084  	AVFRINTRZD
  1085  	AVFRINTRPF
  1086  	AVFRINTRPD
  1087  	AVFRINTRMF
  1088  	AVFRINTRMD
  1089  	AVFRINTF
  1090  	AVFRINTD
  1091  	AXVFRINTRNEF
  1092  	AXVFRINTRNED
  1093  	AXVFRINTRZF
  1094  	AXVFRINTRZD
  1095  	AXVFRINTRPF
  1096  	AXVFRINTRPD
  1097  	AXVFRINTRMF
  1098  	AXVFRINTRMD
  1099  	AXVFRINTF
  1100  	AXVFRINTD
  1101  
  1102  	// LSX and LASX integer neg instructions
  1103  	AVNEGB
  1104  	AVNEGH
  1105  	AVNEGW
  1106  	AVNEGV
  1107  	AXVNEGB
  1108  	AXVNEGH
  1109  	AXVNEGW
  1110  	AXVNEGV
  1111  
  1112  	// LSX and LASX mul instructions that operate on even or odd positions
  1113  	AVMULWEVHB
  1114  	AVMULWEVWH
  1115  	AVMULWEVVW
  1116  	AVMULWEVQV
  1117  	AVMULWODHB
  1118  	AVMULWODWH
  1119  	AVMULWODVW
  1120  	AVMULWODQV
  1121  	AVMULWEVHBU
  1122  	AVMULWEVWHU
  1123  	AVMULWEVVWU
  1124  	AVMULWEVQVU
  1125  	AVMULWODHBU
  1126  	AVMULWODWHU
  1127  	AVMULWODVWU
  1128  	AVMULWODQVU
  1129  	AXVMULWEVHB
  1130  	AXVMULWEVWH
  1131  	AXVMULWEVVW
  1132  	AXVMULWEVQV
  1133  	AXVMULWODHB
  1134  	AXVMULWODWH
  1135  	AXVMULWODVW
  1136  	AXVMULWODQV
  1137  	AXVMULWEVHBU
  1138  	AXVMULWEVWHU
  1139  	AXVMULWEVVWU
  1140  	AXVMULWEVQVU
  1141  	AXVMULWODHBU
  1142  	AXVMULWODWHU
  1143  	AXVMULWODVWU
  1144  	AXVMULWODQVU
  1145  	AVMULWEVHBUB
  1146  	AVMULWEVWHUH
  1147  	AVMULWEVVWUW
  1148  	AVMULWEVQVUV
  1149  	AVMULWODHBUB
  1150  	AVMULWODWHUH
  1151  	AVMULWODVWUW
  1152  	AVMULWODQVUV
  1153  	AXVMULWEVHBUB
  1154  	AXVMULWEVWHUH
  1155  	AXVMULWEVVWUW
  1156  	AXVMULWEVQVUV
  1157  	AXVMULWODHBUB
  1158  	AXVMULWODWHUH
  1159  	AXVMULWODVWUW
  1160  	AXVMULWODQVUV
  1161  
  1162  	AVADDWEVHB
  1163  	AVADDWEVWH
  1164  	AVADDWEVVW
  1165  	AVADDWEVQV
  1166  	AVSUBWEVHB
  1167  	AVSUBWEVWH
  1168  	AVSUBWEVVW
  1169  	AVSUBWEVQV
  1170  	AVADDWODHB
  1171  	AVADDWODWH
  1172  	AVADDWODVW
  1173  	AVADDWODQV
  1174  	AVSUBWODHB
  1175  	AVSUBWODWH
  1176  	AVSUBWODVW
  1177  	AVSUBWODQV
  1178  	AXVADDWEVHB
  1179  	AXVADDWEVWH
  1180  	AXVADDWEVVW
  1181  	AXVADDWEVQV
  1182  	AXVSUBWEVHB
  1183  	AXVSUBWEVWH
  1184  	AXVSUBWEVVW
  1185  	AXVSUBWEVQV
  1186  	AXVADDWODHB
  1187  	AXVADDWODWH
  1188  	AXVADDWODVW
  1189  	AXVADDWODQV
  1190  	AXVSUBWODHB
  1191  	AXVSUBWODWH
  1192  	AXVSUBWODVW
  1193  	AXVSUBWODQV
  1194  	AVADDWEVHBU
  1195  	AVADDWEVWHU
  1196  	AVADDWEVVWU
  1197  	AVADDWEVQVU
  1198  	AVSUBWEVHBU
  1199  	AVSUBWEVWHU
  1200  	AVSUBWEVVWU
  1201  	AVSUBWEVQVU
  1202  	AVADDWODHBU
  1203  	AVADDWODWHU
  1204  	AVADDWODVWU
  1205  	AVADDWODQVU
  1206  	AVSUBWODHBU
  1207  	AVSUBWODWHU
  1208  	AVSUBWODVWU
  1209  	AVSUBWODQVU
  1210  	AXVADDWEVHBU
  1211  	AXVADDWEVWHU
  1212  	AXVADDWEVVWU
  1213  	AXVADDWEVQVU
  1214  	AXVSUBWEVHBU
  1215  	AXVSUBWEVWHU
  1216  	AXVSUBWEVVWU
  1217  	AXVSUBWEVQVU
  1218  	AXVADDWODHBU
  1219  	AXVADDWODWHU
  1220  	AXVADDWODVWU
  1221  	AXVADDWODQVU
  1222  	AXVSUBWODHBU
  1223  	AXVSUBWODWHU
  1224  	AXVSUBWODVWU
  1225  	AXVSUBWODQVU
  1226  
  1227  	AVMADDB
  1228  	AVMADDH
  1229  	AVMADDW
  1230  	AVMADDV
  1231  	AVMSUBB
  1232  	AVMSUBH
  1233  	AVMSUBW
  1234  	AVMSUBV
  1235  
  1236  	AXVMADDB
  1237  	AXVMADDH
  1238  	AXVMADDW
  1239  	AXVMADDV
  1240  	AXVMSUBB
  1241  	AXVMSUBH
  1242  	AXVMSUBW
  1243  	AXVMSUBV
  1244  
  1245  	AVMADDWEVHB
  1246  	AVMADDWEVWH
  1247  	AVMADDWEVVW
  1248  	AVMADDWEVQV
  1249  	AVMADDWODHB
  1250  	AVMADDWODWH
  1251  	AVMADDWODVW
  1252  	AVMADDWODQV
  1253  
  1254  	AVMADDWEVHBU
  1255  	AVMADDWEVWHU
  1256  	AVMADDWEVVWU
  1257  	AVMADDWEVQVU
  1258  	AVMADDWODHBU
  1259  	AVMADDWODWHU
  1260  	AVMADDWODVWU
  1261  	AVMADDWODQVU
  1262  
  1263  	AVMADDWEVHBUB
  1264  	AVMADDWEVWHUH
  1265  	AVMADDWEVVWUW
  1266  	AVMADDWEVQVUV
  1267  	AVMADDWODHBUB
  1268  	AVMADDWODWHUH
  1269  	AVMADDWODVWUW
  1270  	AVMADDWODQVUV
  1271  
  1272  	AXVMADDWEVHB
  1273  	AXVMADDWEVWH
  1274  	AXVMADDWEVVW
  1275  	AXVMADDWEVQV
  1276  	AXVMADDWODHB
  1277  	AXVMADDWODWH
  1278  	AXVMADDWODVW
  1279  	AXVMADDWODQV
  1280  
  1281  	AXVMADDWEVHBU
  1282  	AXVMADDWEVWHU
  1283  	AXVMADDWEVVWU
  1284  	AXVMADDWEVQVU
  1285  	AXVMADDWODHBU
  1286  	AXVMADDWODWHU
  1287  	AXVMADDWODVWU
  1288  	AXVMADDWODQVU
  1289  
  1290  	AXVMADDWEVHBUB
  1291  	AXVMADDWEVWHUH
  1292  	AXVMADDWEVVWUW
  1293  	AXVMADDWEVQVUV
  1294  	AXVMADDWODHBUB
  1295  	AXVMADDWODWHUH
  1296  	AXVMADDWODVWUW
  1297  	AXVMADDWODQVUV
  1298  
  1299  	AVSHUF4IB
  1300  	AVSHUF4IH
  1301  	AVSHUF4IW
  1302  	AVSHUF4IV
  1303  	AXVSHUF4IB
  1304  	AXVSHUF4IH
  1305  	AXVSHUF4IW
  1306  	AXVSHUF4IV
  1307  
  1308  	AVSHUFB
  1309  	AVSHUFH
  1310  	AVSHUFW
  1311  	AVSHUFV
  1312  	AXVSHUFB
  1313  	AXVSHUFH
  1314  	AXVSHUFW
  1315  	AXVSHUFV
  1316  
  1317  	AVPERMIW
  1318  	AXVPERMIW
  1319  	AXVPERMIV
  1320  	AXVPERMIQ
  1321  
  1322  	AVEXTRINSB
  1323  	AVEXTRINSH
  1324  	AVEXTRINSW
  1325  	AVEXTRINSV
  1326  	AXVEXTRINSB
  1327  	AXVEXTRINSH
  1328  	AXVEXTRINSW
  1329  	AXVEXTRINSV
  1330  
  1331  	AVSETEQV
  1332  	AVSETNEV
  1333  	AVSETANYEQB
  1334  	AVSETANYEQH
  1335  	AVSETANYEQW
  1336  	AVSETANYEQV
  1337  	AVSETALLNEB
  1338  	AVSETALLNEH
  1339  	AVSETALLNEW
  1340  	AVSETALLNEV
  1341  	AXVSETEQV
  1342  	AXVSETNEV
  1343  	AXVSETANYEQB
  1344  	AXVSETANYEQH
  1345  	AXVSETANYEQW
  1346  	AXVSETANYEQV
  1347  	AXVSETALLNEB
  1348  	AXVSETALLNEH
  1349  	AXVSETALLNEW
  1350  	AXVSETALLNEV
  1351  
  1352  	ALAST
  1353  
  1354  	// aliases
  1355  	AJMP = obj.AJMP
  1356  	AJAL = obj.ACALL
  1357  	ARET = obj.ARET
  1358  )
  1359  
  1360  func init() {
  1361  	// The asm encoder generally assumes that the lowest 5 bits of the
  1362  	// REG_XX constants match the machine instruction encoding, i.e.
  1363  	// the lowest 5 bits is the register number.
  1364  	// Check this here.
  1365  	if REG_R0%32 != 0 {
  1366  		panic("REG_R0 is not a multiple of 32")
  1367  	}
  1368  	if REG_F0%32 != 0 {
  1369  		panic("REG_F0 is not a multiple of 32")
  1370  	}
  1371  	if REG_FCSR0%32 != 0 {
  1372  		panic("REG_FCSR0 is not a multiple of 32")
  1373  	}
  1374  	if REG_FCC0%32 != 0 {
  1375  		panic("REG_FCC0 is not a multiple of 32")
  1376  	}
  1377  	if REG_V0%32 != 0 {
  1378  		panic("REG_V0 is not a multiple of 32")
  1379  	}
  1380  	if REG_X0%32 != 0 {
  1381  		panic("REG_X0 is not a multiple of 32")
  1382  	}
  1383  }
  1384
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