a.out.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  )
    10  
    11  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64
    12  
    13  const (
    14  	NSNAME = 8
    15  	NSYM   = 50
    16  	NREG   = 32 // number of general registers
    17  	NFREG  = 32 // number of floating point registers
    18  	NVREG  = 32 // number of LSX registers
    19  	NXREG  = 32 // number of LASX registers
    20  )
    21  
    22  const (
    23  	REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32
    24  	REG_R1
    25  	REG_R2
    26  	REG_R3
    27  	REG_R4
    28  	REG_R5
    29  	REG_R6
    30  	REG_R7
    31  	REG_R8
    32  	REG_R9
    33  	REG_R10
    34  	REG_R11
    35  	REG_R12
    36  	REG_R13
    37  	REG_R14
    38  	REG_R15
    39  	REG_R16
    40  	REG_R17
    41  	REG_R18
    42  	REG_R19
    43  	REG_R20
    44  	REG_R21
    45  	REG_R22
    46  	REG_R23
    47  	REG_R24
    48  	REG_R25
    49  	REG_R26
    50  	REG_R27
    51  	REG_R28
    52  	REG_R29
    53  	REG_R30
    54  	REG_R31
    55  
    56  	REG_F0 // must be a multiple of 32
    57  	REG_F1
    58  	REG_F2
    59  	REG_F3
    60  	REG_F4
    61  	REG_F5
    62  	REG_F6
    63  	REG_F7
    64  	REG_F8
    65  	REG_F9
    66  	REG_F10
    67  	REG_F11
    68  	REG_F12
    69  	REG_F13
    70  	REG_F14
    71  	REG_F15
    72  	REG_F16
    73  	REG_F17
    74  	REG_F18
    75  	REG_F19
    76  	REG_F20
    77  	REG_F21
    78  	REG_F22
    79  	REG_F23
    80  	REG_F24
    81  	REG_F25
    82  	REG_F26
    83  	REG_F27
    84  	REG_F28
    85  	REG_F29
    86  	REG_F30
    87  	REG_F31
    88  
    89  	REG_FCSR0 // must be a multiple of 32
    90  	REG_FCSR1
    91  	REG_FCSR2
    92  	REG_FCSR3 // only four registers are needed
    93  	REG_FCSR4
    94  	REG_FCSR5
    95  	REG_FCSR6
    96  	REG_FCSR7
    97  	REG_FCSR8
    98  	REG_FCSR9
    99  	REG_FCSR10
   100  	REG_FCSR11
   101  	REG_FCSR12
   102  	REG_FCSR13
   103  	REG_FCSR14
   104  	REG_FCSR15
   105  	REG_FCSR16
   106  	REG_FCSR17
   107  	REG_FCSR18
   108  	REG_FCSR19
   109  	REG_FCSR20
   110  	REG_FCSR21
   111  	REG_FCSR22
   112  	REG_FCSR23
   113  	REG_FCSR24
   114  	REG_FCSR25
   115  	REG_FCSR26
   116  	REG_FCSR27
   117  	REG_FCSR28
   118  	REG_FCSR29
   119  	REG_FCSR30
   120  	REG_FCSR31
   121  
   122  	REG_FCC0 // must be a multiple of 32
   123  	REG_FCC1
   124  	REG_FCC2
   125  	REG_FCC3
   126  	REG_FCC4
   127  	REG_FCC5
   128  	REG_FCC6
   129  	REG_FCC7 // only eight registers are needed
   130  	REG_FCC8
   131  	REG_FCC9
   132  	REG_FCC10
   133  	REG_FCC11
   134  	REG_FCC12
   135  	REG_FCC13
   136  	REG_FCC14
   137  	REG_FCC15
   138  	REG_FCC16
   139  	REG_FCC17
   140  	REG_FCC18
   141  	REG_FCC19
   142  	REG_FCC20
   143  	REG_FCC21
   144  	REG_FCC22
   145  	REG_FCC23
   146  	REG_FCC24
   147  	REG_FCC25
   148  	REG_FCC26
   149  	REG_FCC27
   150  	REG_FCC28
   151  	REG_FCC29
   152  	REG_FCC30
   153  	REG_FCC31
   154  
   155  	// LSX: 128-bit vector register
   156  	REG_V0
   157  	REG_V1
   158  	REG_V2
   159  	REG_V3
   160  	REG_V4
   161  	REG_V5
   162  	REG_V6
   163  	REG_V7
   164  	REG_V8
   165  	REG_V9
   166  	REG_V10
   167  	REG_V11
   168  	REG_V12
   169  	REG_V13
   170  	REG_V14
   171  	REG_V15
   172  	REG_V16
   173  	REG_V17
   174  	REG_V18
   175  	REG_V19
   176  	REG_V20
   177  	REG_V21
   178  	REG_V22
   179  	REG_V23
   180  	REG_V24
   181  	REG_V25
   182  	REG_V26
   183  	REG_V27
   184  	REG_V28
   185  	REG_V29
   186  	REG_V30
   187  	REG_V31
   188  
   189  	// LASX: 256-bit vector register
   190  	REG_X0
   191  	REG_X1
   192  	REG_X2
   193  	REG_X3
   194  	REG_X4
   195  	REG_X5
   196  	REG_X6
   197  	REG_X7
   198  	REG_X8
   199  	REG_X9
   200  	REG_X10
   201  	REG_X11
   202  	REG_X12
   203  	REG_X13
   204  	REG_X14
   205  	REG_X15
   206  	REG_X16
   207  	REG_X17
   208  	REG_X18
   209  	REG_X19
   210  	REG_X20
   211  	REG_X21
   212  	REG_X22
   213  	REG_X23
   214  	REG_X24
   215  	REG_X25
   216  	REG_X26
   217  	REG_X27
   218  	REG_X28
   219  	REG_X29
   220  	REG_X30
   221  	REG_X31
   222  
   223  	REG_SPECIAL = REG_FCSR0
   224  
   225  	REGZERO = REG_R0 // set to zero
   226  	REGLINK = REG_R1
   227  	REGSP   = REG_R3
   228  	REGCTXT = REG_R29 // context for closures
   229  	REGG    = REG_R22 // G in loong64
   230  	REGTMP  = REG_R30 // used by the assembler
   231  	FREGRET = REG_F0  // not use
   232  )
   233  
   234  var LOONG64DWARFRegisters = map[int16]int16{}
   235  
   236  func init() {
   237  	// f assigns dwarfregisters[from:to] = (base):(to-from+base)
   238  	f := func(from, to, base int16) {
   239  		for r := int16(from); r <= to; r++ {
   240  			LOONG64DWARFRegisters[r] = (r - from) + base
   241  		}
   242  	}
   243  	f(REG_R0, REG_R31, 0)
   244  	f(REG_F0, REG_F31, 32)
   245  
   246  	// The lower bits of V and X registers are alias to F registers
   247  	f(REG_V0, REG_V31, 32)
   248  	f(REG_X0, REG_X31, 32)
   249  }
   250  
   251  const (
   252  	BIG = 2046
   253  )
   254  
   255  const (
   256  	// mark flags
   257  	LABEL  = 1 << 0
   258  	LEAF   = 1 << 1
   259  	SYNC   = 1 << 2
   260  	BRANCH = 1 << 3
   261  )
   262  
   263  // Arrangement for Loong64 SIMD instructions
   264  const (
   265  	// arrangement types
   266  	ARNG_32B int16 = iota
   267  	ARNG_16H
   268  	ARNG_8W
   269  	ARNG_4V
   270  	ARNG_2Q
   271  	ARNG_16B
   272  	ARNG_8H
   273  	ARNG_4W
   274  	ARNG_2V
   275  	ARNG_B
   276  	ARNG_H
   277  	ARNG_W
   278  	ARNG_V
   279  	ARNG_BU
   280  	ARNG_HU
   281  	ARNG_WU
   282  	ARNG_VU
   283  )
   284  
   285  // LoongArch64 SIMD extension type
   286  const (
   287  	LSX int16 = iota
   288  	LASX
   289  )
   290  
   291  // bits 0-4 indicates register: Vn or Xn
   292  // bits 5-9 indicates arrangement: <T>
   293  // bits 10 indicates SMID type: 0: LSX, 1: LASX
   294  const (
   295  	REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn.<T>
   296  	REG_ELEM                                               // Vn.<T>[index]
   297  	REG_ELEM_END
   298  )
   299  
   300  const (
   301  	EXT_REG_SHIFT = 0
   302  	EXT_REG_MASK  = 0x1f
   303  
   304  	EXT_TYPE_SHIFT = 5
   305  	EXT_TYPE_MASK  = 0x1f
   306  
   307  	EXT_SIMDTYPE_SHIFT = 10
   308  	EXT_SIMDTYPE_MASK  = 0x1
   309  )
   310  
   311  const (
   312  	REG_LAST = REG_ELEM_END // the last defined register
   313  )
   314  
   315  //go:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
   316  const (
   317  	C_NONE = iota
   318  	C_REG
   319  	C_FREG
   320  	C_FCSRREG
   321  	C_FCCREG
   322  	C_VREG
   323  	C_XREG
   324  	C_ARNG // Vn.<T>
   325  	C_ELEM // Vn.<T>[index]
   326  
   327  	C_ZCON
   328  	C_U1CON      // 1 bit unsigned constant
   329  	C_U2CON      // 2 bit unsigned constant
   330  	C_U3CON      // 3 bit unsigned constant
   331  	C_U4CON      // 4 bit unsigned constant
   332  	C_U5CON      // 5 bit unsigned constant
   333  	C_U6CON      // 6 bit unsigned constant
   334  	C_U7CON      // 7 bit unsigned constant
   335  	C_U8CON      // 8 bit unsigned constant
   336  	C_S5CON      // 5 bit signed constant
   337  	C_US12CON    // same as C_S12CON, increase the priority of C_S12CON in special cases.
   338  	C_UU12CON    // same as C_U12CON, increase the priority of C_U12CON in special cases.
   339  	C_S12CON     // 12 bit signed constant, -0x800 < v <= 0x7ff
   340  	C_U12CON     // 12 bit unsigned constant, 0 < v <= 0xfff
   341  	C_12CON      // 12 bit signed constant, or 12 bit unsigned constant
   342  	C_S13CON20_0 // 13 bit signed constant, low 12 bits 0
   343  	C_S13CON     // 13 bit signed constant
   344  	C_U13CON20_0 // 13 bit unsigned constant, low 12 bits 0
   345  	C_U13CON     // 13 bit unsigned constant
   346  	C_13CON      // 13 bit signed constant, or 13 bit unsigned constant
   347  	C_U15CON     // 15 bit unsigned constant
   348  	C_U15CON20_0 // 15 bit unsigned constant, low 12 bits 0
   349  	C_32CON20_0  // 32 bit signed, low 12 bits 0
   350  	C_32CON      // other 32 bit signed
   351  
   352  	// 64 bit signed, lo32 bits 0, hi20 bits are not 0, hi12 bits can
   353  	// be obtained by sign extension of the hi20 bits.
   354  	C_DCON20S_0
   355  	// 64 bit signed, lo52 bits 0, hi12 bits are not 0.
   356  	C_DCON12_0
   357  	// 64 bit signed, lo32 bits 0, hi32 bits are not 0.
   358  	C_DCON32_0
   359  	// 64 bit signed, lo12 bits 0, lo20 bits are not 0, hi20 bits can be
   360  	// obtained by sign extension of the lo20 bits, other bits are not 0.
   361  	C_DCON12_20S
   362  	// 64 bit signed, lo12 bits 0, hi20 bits are not 0, hi12 bits can be
   363  	// obtained by sign extension of the hi20 bits, other bits are not 0.
   364  	C_DCON20S_20
   365  	// 64 bit signed, lo12 bits 0, other bits are not 0.
   366  	C_DCON32_20
   367  	// 64 bit signed, lo12 bits are not 0, 12~51 bits can be obtained
   368  	// by sign extension of the lo12 bits, other bits are not 0.
   369  	C_DCON12_12S
   370  	// 64 bit signed, hi20 bits and lo12 bits are not 0, hi12 bits can
   371  	// be obtained by sign extension of the hi20 bits, lo20 bits can
   372  	// be obtained by sign extension of the lo12 bits.
   373  	C_DCON20S_12S
   374  	// 64 bit signed, lo12 bits are not 0, lo20 bits can be obtained by sign
   375  	// extension of the lo12 bits, other bits are not 0.
   376  	C_DCON32_12S
   377  	// 64 bit signed, lo20 and lo12 bits are not 0, hi20 bits can be obtained by sign
   378  	// extension of the lo20 bits. other bits are not 0.
   379  	C_DCON12_32S
   380  	// 64 bit signed, hi20 bits are not 0, hi12 bits can be obtained by sign
   381  	// extension of the hi20 bits, lo32 bits are not 0.
   382  	C_DCON20S_32
   383  	// 64 bit signed, 12~51 bits 0, other bits are not 0.
   384  	C_DCON12_12U
   385  	// 64 bit signed, lo20 bits 0, hi20 bits are not 0, hi12 bits can be
   386  	// obtained by sign extension of the hi20 bits, lo12 bits are not 0.
   387  	C_DCON20S_12U
   388  	// 64 bit signed, lo20 bits 0, other bits are not 0.
   389  	C_DCON32_12U
   390  	// other 64
   391  	C_DCON
   392  
   393  	C_SACON   // $n(REG) where n <= int12
   394  	C_LACON   // $n(REG) where int12 < n <= int32
   395  	C_DACON   // $n(REG) where int32 < n
   396  	C_EXTADDR // external symbol address
   397  	C_BRAN
   398  	C_SAUTO
   399  	C_LAUTO
   400  	C_ZOREG
   401  	C_SOREG
   402  	C_LOREG
   403  	C_ROFF // register offset
   404  	C_ADDR
   405  	C_TLS_LE
   406  	C_TLS_IE
   407  	C_GOTADDR
   408  	C_TEXTSIZE
   409  
   410  	C_GOK
   411  	C_NCLASS // must be the last
   412  )
   413  
   414  const (
   415  	AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota
   416  	AABSF
   417  	AADD
   418  	AADDD
   419  	AADDF
   420  	AADDU
   421  
   422  	AADDW
   423  	AAND
   424  	ABEQ
   425  	ABGEZ
   426  	ABLEZ
   427  	ABGTZ
   428  	ABLTZ
   429  	ABFPF
   430  	ABFPT
   431  
   432  	ABNE
   433  	ABREAK
   434  
   435  	ACMPEQD
   436  	ACMPEQF
   437  
   438  	ACMPGED // ACMPGED -> fcmp.sle.d
   439  	ACMPGEF // ACMPGEF -> fcmp.sle.s
   440  	ACMPGTD // ACMPGTD -> fcmp.slt.d
   441  	ACMPGTF // ACMPGTF -> fcmp.slt.s
   442  
   443  	ALU12IW
   444  	ALU32ID
   445  	ALU52ID
   446  	APCALAU12I
   447  	APCADDU12I
   448  	AJIRL
   449  	ABGE
   450  	ABLT
   451  	ABLTU
   452  	ABGEU
   453  
   454  	ADIV
   455  	ADIVD
   456  	ADIVF
   457  	ADIVU
   458  	ADIVW
   459  
   460  	ALL
   461  	ALLV
   462  
   463  	ALUI
   464  
   465  	AMOVB
   466  	AMOVBU
   467  
   468  	AMOVD
   469  	AMOVDF
   470  	AMOVDW
   471  	AMOVF
   472  	AMOVFD
   473  	AMOVFW
   474  
   475  	AMOVH
   476  	AMOVHU
   477  	AMOVW
   478  
   479  	AMOVWD
   480  	AMOVWF
   481  
   482  	AMUL
   483  	AMULD
   484  	AMULF
   485  	AMULU
   486  	AMULH
   487  	AMULHU
   488  	AMULW
   489  	ANEGD
   490  	ANEGF
   491  
   492  	ANEGW
   493  	ANEGV
   494  
   495  	ANOOP // hardware nop
   496  	ANOR
   497  	AOR
   498  	AREM
   499  	AREMU
   500  
   501  	ARFE
   502  
   503  	ASC
   504  	ASCV
   505  
   506  	ASGT
   507  	ASGTU
   508  
   509  	ASLL
   510  	ASQRTD
   511  	ASQRTF
   512  	ASRA
   513  	ASRL
   514  	AROTR
   515  	ASUB
   516  	ASUBD
   517  	ASUBF
   518  
   519  	ASUBU
   520  	ASUBW
   521  	ADBAR
   522  	ASYSCALL
   523  
   524  	ATEQ
   525  	ATNE
   526  
   527  	AWORD
   528  
   529  	AXOR
   530  
   531  	AMASKEQZ
   532  	AMASKNEZ
   533  
   534  	// 64-bit
   535  	AMOVV
   536  
   537  	ASLLV
   538  	ASRAV
   539  	ASRLV
   540  	AROTRV
   541  	ADIVV
   542  	ADIVVU
   543  
   544  	AREMV
   545  	AREMVU
   546  
   547  	AMULV
   548  	AMULVU
   549  	AMULHV
   550  	AMULHVU
   551  	AADDV
   552  	AADDVU
   553  	ASUBV
   554  	ASUBVU
   555  
   556  	// 64-bit FP
   557  	ATRUNCFV
   558  	ATRUNCDV
   559  	ATRUNCFW
   560  	ATRUNCDW
   561  
   562  	AMOVWU
   563  	AMOVFV
   564  	AMOVDV
   565  	AMOVVF
   566  	AMOVVD
   567  
   568  	// 2.2.1.2
   569  	AADDV16
   570  
   571  	// 2.2.1.3
   572  	AALSLW
   573  	AALSLWU
   574  	AALSLV
   575  
   576  	// 2.2.1.8
   577  	AORN
   578  	AANDN
   579  
   580  	// 2.2.7. Atomic Memory Access Instructions
   581  	AAMSWAPB
   582  	AAMSWAPH
   583  	AAMSWAPW
   584  	AAMSWAPV
   585  	AAMCASB
   586  	AAMCASH
   587  	AAMCASW
   588  	AAMCASV
   589  	AAMADDW
   590  	AAMADDV
   591  	AAMANDW
   592  	AAMANDV
   593  	AAMORW
   594  	AAMORV
   595  	AAMXORW
   596  	AAMXORV
   597  	AAMMAXW
   598  	AAMMAXV
   599  	AAMMINW
   600  	AAMMINV
   601  	AAMMAXWU
   602  	AAMMAXVU
   603  	AAMMINWU
   604  	AAMMINVU
   605  	AAMSWAPDBB
   606  	AAMSWAPDBH
   607  	AAMSWAPDBW
   608  	AAMSWAPDBV
   609  	AAMCASDBB
   610  	AAMCASDBH
   611  	AAMCASDBW
   612  	AAMCASDBV
   613  	AAMADDDBW
   614  	AAMADDDBV
   615  	AAMANDDBW
   616  	AAMANDDBV
   617  	AAMORDBW
   618  	AAMORDBV
   619  	AAMXORDBW
   620  	AAMXORDBV
   621  	AAMMAXDBW
   622  	AAMMAXDBV
   623  	AAMMINDBW
   624  	AAMMINDBV
   625  	AAMMAXDBWU
   626  	AAMMAXDBVU
   627  	AAMMINDBWU
   628  	AAMMINDBVU
   629  
   630  	// 2.2.3.1
   631  	AEXTWB
   632  	AEXTWH
   633  
   634  	// 2.2.3.2
   635  	ACLOW
   636  	ACLOV
   637  	ACLZW
   638  	ACLZV
   639  	ACTOW
   640  	ACTOV
   641  	ACTZW
   642  	ACTZV
   643  
   644  	// 2.2.3.4
   645  	AREVBV
   646  	AREVB2W
   647  	AREVB4H
   648  	AREVB2H
   649  
   650  	// 2.2.3.5
   651  	AREVH2W
   652  	AREVHV
   653  
   654  	// 2.2.3.6
   655  	ABITREV4B
   656  	ABITREV8B
   657  
   658  	// 2.2.3.7
   659  	ABITREVW
   660  	ABITREVV
   661  
   662  	// 2.2.3.8
   663  	ABSTRINSW
   664  	ABSTRINSV
   665  
   666  	// 2.2.3.9
   667  	ABSTRPICKW
   668  	ABSTRPICKV
   669  
   670  	// 2.2.5.3
   671  	AMOVWP
   672  	AMOVVP
   673  
   674  	// 2.2.5.4. Prefetch Instructions
   675  	APRELD
   676  	APRELDX
   677  
   678  	// 2.2.9. CRC Check Instructions
   679  	ACRCWBW
   680  	ACRCWHW
   681  	ACRCWWW
   682  	ACRCWVW
   683  	ACRCCWBW
   684  	ACRCCWHW
   685  	ACRCCWWW
   686  	ACRCCWVW
   687  
   688  	// 2.2.10. Other Miscellaneous Instructions
   689  	ARDTIMELW
   690  	ARDTIMEHW
   691  	ARDTIMED
   692  	ACPUCFG
   693  
   694  	// 3.2.1.2
   695  	AFMADDF
   696  	AFMADDD
   697  	AFMSUBF
   698  	AFMSUBD
   699  	AFNMADDF
   700  	AFNMADDD
   701  	AFNMSUBF
   702  	AFNMSUBD
   703  
   704  	// 3.2.1.3
   705  	AFMINF
   706  	AFMIND
   707  	AFMAXF
   708  	AFMAXD
   709  
   710  	// 3.2.1.4
   711  	AFMAXAF
   712  	AFMAXAD
   713  	AFMINAF
   714  	AFMINAD
   715  
   716  	// 3.2.1.7
   717  	AFCOPYSGF
   718  	AFCOPYSGD
   719  	AFSCALEBF
   720  	AFSCALEBD
   721  	AFLOGBF
   722  	AFLOGBD
   723  
   724  	// 3.2.1.8
   725  	AFCLASSF
   726  	AFCLASSD
   727  
   728  	// 3.2.3.2
   729  	AFFINTFW
   730  	AFFINTFV
   731  	AFFINTDW
   732  	AFFINTDV
   733  	AFTINTWF
   734  	AFTINTWD
   735  	AFTINTVF
   736  	AFTINTVD
   737  
   738  	// 3.2.3.3
   739  	AFTINTRPWF
   740  	AFTINTRPWD
   741  	AFTINTRPVF
   742  	AFTINTRPVD
   743  	AFTINTRMWF
   744  	AFTINTRMWD
   745  	AFTINTRMVF
   746  	AFTINTRMVD
   747  	AFTINTRZWF
   748  	AFTINTRZWD
   749  	AFTINTRZVF
   750  	AFTINTRZVD
   751  	AFTINTRNEWF
   752  	AFTINTRNEWD
   753  	AFTINTRNEVF
   754  	AFTINTRNEVD
   755  
   756  	// 3.2.4.2
   757  	AFSEL
   758  
   759  	// LSX and LASX memory access instructions
   760  	AVMOVQ
   761  	AXVMOVQ
   762  
   763  	// LSX and LASX arithmetic instructions
   764  	AVADDB
   765  	AVADDH
   766  	AVADDW
   767  	AVADDV
   768  	AVADDQ
   769  	AXVADDB
   770  	AXVADDH
   771  	AXVADDW
   772  	AXVADDV
   773  	AXVADDQ
   774  	AVSUBB
   775  	AVSUBH
   776  	AVSUBW
   777  	AVSUBV
   778  	AVSUBQ
   779  	AXVSUBB
   780  	AXVSUBH
   781  	AXVSUBW
   782  	AXVSUBV
   783  	AXVSUBQ
   784  	AVADDBU
   785  	AVADDHU
   786  	AVADDWU
   787  	AVADDVU
   788  	AVSUBBU
   789  	AVSUBHU
   790  	AVSUBWU
   791  	AVSUBVU
   792  	AXVADDBU
   793  	AXVADDHU
   794  	AXVADDWU
   795  	AXVADDVU
   796  	AXVSUBBU
   797  	AXVSUBHU
   798  	AXVSUBWU
   799  	AXVSUBVU
   800  
   801  	// LSX and LASX Bit-manipulation Instructions
   802  	AVANDB
   803  	AVORB
   804  	AVXORB
   805  	AVNORB
   806  	AXVANDB
   807  	AXVORB
   808  	AXVXORB
   809  	AXVNORB
   810  	AVANDV
   811  	AVORV
   812  	AVXORV
   813  	AVNORV
   814  	AVANDNV
   815  	AVORNV
   816  	AXVANDV
   817  	AXVORV
   818  	AXVXORV
   819  	AXVNORV
   820  	AXVANDNV
   821  	AXVORNV
   822  
   823  	AVPCNTB
   824  	AVPCNTH
   825  	AVPCNTW
   826  	AVPCNTV
   827  	AXVPCNTB
   828  	AXVPCNTH
   829  	AXVPCNTW
   830  	AXVPCNTV
   831  
   832  	AVBITCLRB
   833  	AVBITCLRH
   834  	AVBITCLRW
   835  	AVBITCLRV
   836  	AVBITSETB
   837  	AVBITSETH
   838  	AVBITSETW
   839  	AVBITSETV
   840  	AVBITREVB
   841  	AVBITREVH
   842  	AVBITREVW
   843  	AVBITREVV
   844  	AXVBITCLRB
   845  	AXVBITCLRH
   846  	AXVBITCLRW
   847  	AXVBITCLRV
   848  	AXVBITSETB
   849  	AXVBITSETH
   850  	AXVBITSETW
   851  	AXVBITSETV
   852  	AXVBITREVB
   853  	AXVBITREVH
   854  	AXVBITREVW
   855  	AXVBITREVV
   856  
   857  	// LSX and LASX integer comparison instruction
   858  	AVSEQB
   859  	AXVSEQB
   860  	AVSEQH
   861  	AXVSEQH
   862  	AVSEQW
   863  	AXVSEQW
   864  	AVSEQV
   865  	AXVSEQV
   866  
   867  	// LSX and LASX integer div and mod instructions
   868  	AVDIVB
   869  	AVDIVH
   870  	AVDIVW
   871  	AVDIVV
   872  	AVDIVBU
   873  	AVDIVHU
   874  	AVDIVWU
   875  	AVDIVVU
   876  	AVMODB
   877  	AVMODH
   878  	AVMODW
   879  	AVMODV
   880  	AVMODBU
   881  	AVMODHU
   882  	AVMODWU
   883  	AVMODVU
   884  	AXVDIVB
   885  	AXVDIVH
   886  	AXVDIVW
   887  	AXVDIVV
   888  	AXVDIVBU
   889  	AXVDIVHU
   890  	AXVDIVWU
   891  	AXVDIVVU
   892  	AXVMODB
   893  	AXVMODH
   894  	AXVMODW
   895  	AXVMODV
   896  	AXVMODBU
   897  	AXVMODHU
   898  	AXVMODWU
   899  	AXVMODVU
   900  
   901  	// LSX and LASX shift operation instructions
   902  	AVSLLB
   903  	AVSLLH
   904  	AVSLLW
   905  	AVSLLV
   906  	AVSRLB
   907  	AVSRLH
   908  	AVSRLW
   909  	AVSRLV
   910  	AVSRAB
   911  	AVSRAH
   912  	AVSRAW
   913  	AVSRAV
   914  	AVROTRB
   915  	AVROTRH
   916  	AVROTRW
   917  	AVROTRV
   918  	AXVSLLB
   919  	AXVSLLH
   920  	AXVSLLW
   921  	AXVSLLV
   922  	AXVSRLB
   923  	AXVSRLH
   924  	AXVSRLW
   925  	AXVSRLV
   926  	AXVSRAB
   927  	AXVSRAH
   928  	AXVSRAW
   929  	AXVSRAV
   930  	AXVROTRB
   931  	AXVROTRH
   932  	AXVROTRW
   933  	AXVROTRV
   934  
   935  	// LSX and LASX move and shuffle instructions
   936  	AVILVLB
   937  	AVILVLH
   938  	AVILVLW
   939  	AVILVLV
   940  	AVILVHB
   941  	AVILVHH
   942  	AVILVHW
   943  	AVILVHV
   944  	AXVILVLB
   945  	AXVILVLH
   946  	AXVILVLW
   947  	AXVILVLV
   948  	AXVILVHB
   949  	AXVILVHH
   950  	AXVILVHW
   951  	AXVILVHV
   952  
   953  	// LSX and LASX integer mul instructions
   954  	AVMULB
   955  	AVMULH
   956  	AVMULW
   957  	AVMULV
   958  	AVMUHB
   959  	AVMUHH
   960  	AVMUHW
   961  	AVMUHV
   962  	AVMUHBU
   963  	AVMUHHU
   964  	AVMUHWU
   965  	AVMUHVU
   966  	AXVMULB
   967  	AXVMULH
   968  	AXVMULW
   969  	AXVMULV
   970  	AXVMUHB
   971  	AXVMUHH
   972  	AXVMUHW
   973  	AXVMUHV
   974  	AXVMUHBU
   975  	AXVMUHHU
   976  	AXVMUHWU
   977  	AXVMUHVU
   978  
   979  	// LSX and LASX floating point instructions
   980  	AVFSQRTF
   981  	AVFSQRTD
   982  	AVFRECIPF
   983  	AVFRECIPD
   984  	AVFRSQRTF
   985  	AVFRSQRTD
   986  	AXVFSQRTF
   987  	AXVFSQRTD
   988  	AXVFRECIPF
   989  	AXVFRECIPD
   990  	AXVFRSQRTF
   991  	AXVFRSQRTD
   992  
   993  	AVADDF
   994  	AVADDD
   995  	AVSUBF
   996  	AVSUBD
   997  	AVMULF
   998  	AVMULD
   999  	AVDIVF
  1000  	AVDIVD
  1001  	AXVADDF
  1002  	AXVADDD
  1003  	AXVSUBF
  1004  	AXVSUBD
  1005  	AXVMULF
  1006  	AXVMULD
  1007  	AXVDIVF
  1008  	AXVDIVD
  1009  
  1010  	AVFCLASSF
  1011  	AVFCLASSD
  1012  	AXVFCLASSF
  1013  	AXVFCLASSD
  1014  
  1015  	// LSX and LASX floating point conversion instructions
  1016  	AVFRINTRNEF
  1017  	AVFRINTRNED
  1018  	AVFRINTRZF
  1019  	AVFRINTRZD
  1020  	AVFRINTRPF
  1021  	AVFRINTRPD
  1022  	AVFRINTRMF
  1023  	AVFRINTRMD
  1024  	AVFRINTF
  1025  	AVFRINTD
  1026  	AXVFRINTRNEF
  1027  	AXVFRINTRNED
  1028  	AXVFRINTRZF
  1029  	AXVFRINTRZD
  1030  	AXVFRINTRPF
  1031  	AXVFRINTRPD
  1032  	AXVFRINTRMF
  1033  	AXVFRINTRMD
  1034  	AXVFRINTF
  1035  	AXVFRINTD
  1036  
  1037  	// LSX and LASX integer neg instructions
  1038  	AVNEGB
  1039  	AVNEGH
  1040  	AVNEGW
  1041  	AVNEGV
  1042  	AXVNEGB
  1043  	AXVNEGH
  1044  	AXVNEGW
  1045  	AXVNEGV
  1046  
  1047  	// LSX and LASX mul instructions that operate on even or odd positions
  1048  	AVMULWEVHB
  1049  	AVMULWEVWH
  1050  	AVMULWEVVW
  1051  	AVMULWEVQV
  1052  	AVMULWODHB
  1053  	AVMULWODWH
  1054  	AVMULWODVW
  1055  	AVMULWODQV
  1056  	AVMULWEVHBU
  1057  	AVMULWEVWHU
  1058  	AVMULWEVVWU
  1059  	AVMULWEVQVU
  1060  	AVMULWODHBU
  1061  	AVMULWODWHU
  1062  	AVMULWODVWU
  1063  	AVMULWODQVU
  1064  	AXVMULWEVHB
  1065  	AXVMULWEVWH
  1066  	AXVMULWEVVW
  1067  	AXVMULWEVQV
  1068  	AXVMULWODHB
  1069  	AXVMULWODWH
  1070  	AXVMULWODVW
  1071  	AXVMULWODQV
  1072  	AXVMULWEVHBU
  1073  	AXVMULWEVWHU
  1074  	AXVMULWEVVWU
  1075  	AXVMULWEVQVU
  1076  	AXVMULWODHBU
  1077  	AXVMULWODWHU
  1078  	AXVMULWODVWU
  1079  	AXVMULWODQVU
  1080  	AVMULWEVHBUB
  1081  	AVMULWEVWHUH
  1082  	AVMULWEVVWUW
  1083  	AVMULWEVQVUV
  1084  	AVMULWODHBUB
  1085  	AVMULWODWHUH
  1086  	AVMULWODVWUW
  1087  	AVMULWODQVUV
  1088  	AXVMULWEVHBUB
  1089  	AXVMULWEVWHUH
  1090  	AXVMULWEVVWUW
  1091  	AXVMULWEVQVUV
  1092  	AXVMULWODHBUB
  1093  	AXVMULWODWHUH
  1094  	AXVMULWODVWUW
  1095  	AXVMULWODQVUV
  1096  
  1097  	AVSHUF4IB
  1098  	AVSHUF4IH
  1099  	AVSHUF4IW
  1100  	AVSHUF4IV
  1101  	AXVSHUF4IB
  1102  	AXVSHUF4IH
  1103  	AXVSHUF4IW
  1104  	AXVSHUF4IV
  1105  
  1106  	AVSETEQV
  1107  	AVSETNEV
  1108  	AVSETANYEQB
  1109  	AVSETANYEQH
  1110  	AVSETANYEQW
  1111  	AVSETANYEQV
  1112  	AVSETALLNEB
  1113  	AVSETALLNEH
  1114  	AVSETALLNEW
  1115  	AVSETALLNEV
  1116  	AXVSETEQV
  1117  	AXVSETNEV
  1118  	AXVSETANYEQB
  1119  	AXVSETANYEQH
  1120  	AXVSETANYEQW
  1121  	AXVSETANYEQV
  1122  	AXVSETALLNEB
  1123  	AXVSETALLNEH
  1124  	AXVSETALLNEW
  1125  	AXVSETALLNEV
  1126  
  1127  	ALAST
  1128  
  1129  	// aliases
  1130  	AJMP = obj.AJMP
  1131  	AJAL = obj.ACALL
  1132  	ARET = obj.ARET
  1133  )
  1134  
  1135  func init() {
  1136  	// The asm encoder generally assumes that the lowest 5 bits of the
  1137  	// REG_XX constants match the machine instruction encoding, i.e.
  1138  	// the lowest 5 bits is the register number.
  1139  	// Check this here.
  1140  	if REG_R0%32 != 0 {
  1141  		panic("REG_R0 is not a multiple of 32")
  1142  	}
  1143  	if REG_F0%32 != 0 {
  1144  		panic("REG_F0 is not a multiple of 32")
  1145  	}
  1146  	if REG_FCSR0%32 != 0 {
  1147  		panic("REG_FCSR0 is not a multiple of 32")
  1148  	}
  1149  	if REG_FCC0%32 != 0 {
  1150  		panic("REG_FCC0 is not a multiple of 32")
  1151  	}
  1152  	if REG_V0%32 != 0 {
  1153  		panic("REG_V0 is not a multiple of 32")
  1154  	}
  1155  	if REG_X0%32 != 0 {
  1156  		panic("REG_X0 is not a multiple of 32")
  1157  	}
  1158  }
  1159
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