a.out.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  )
    10  
    11  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64
    12  
    13  const (
    14  	NSNAME = 8
    15  	NSYM   = 50
    16  	NREG   = 32 // number of general registers
    17  	NFREG  = 32 // number of floating point registers
    18  	NVREG  = 32 // number of LSX registers
    19  	NXREG  = 32 // number of LASX registers
    20  )
    21  
    22  const (
    23  	REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32
    24  	REG_R1
    25  	REG_R2
    26  	REG_R3
    27  	REG_R4
    28  	REG_R5
    29  	REG_R6
    30  	REG_R7
    31  	REG_R8
    32  	REG_R9
    33  	REG_R10
    34  	REG_R11
    35  	REG_R12
    36  	REG_R13
    37  	REG_R14
    38  	REG_R15
    39  	REG_R16
    40  	REG_R17
    41  	REG_R18
    42  	REG_R19
    43  	REG_R20
    44  	REG_R21
    45  	REG_R22
    46  	REG_R23
    47  	REG_R24
    48  	REG_R25
    49  	REG_R26
    50  	REG_R27
    51  	REG_R28
    52  	REG_R29
    53  	REG_R30
    54  	REG_R31
    55  
    56  	REG_F0 // must be a multiple of 32
    57  	REG_F1
    58  	REG_F2
    59  	REG_F3
    60  	REG_F4
    61  	REG_F5
    62  	REG_F6
    63  	REG_F7
    64  	REG_F8
    65  	REG_F9
    66  	REG_F10
    67  	REG_F11
    68  	REG_F12
    69  	REG_F13
    70  	REG_F14
    71  	REG_F15
    72  	REG_F16
    73  	REG_F17
    74  	REG_F18
    75  	REG_F19
    76  	REG_F20
    77  	REG_F21
    78  	REG_F22
    79  	REG_F23
    80  	REG_F24
    81  	REG_F25
    82  	REG_F26
    83  	REG_F27
    84  	REG_F28
    85  	REG_F29
    86  	REG_F30
    87  	REG_F31
    88  
    89  	REG_FCSR0 // must be a multiple of 32
    90  	REG_FCSR1
    91  	REG_FCSR2
    92  	REG_FCSR3 // only four registers are needed
    93  	REG_FCSR4
    94  	REG_FCSR5
    95  	REG_FCSR6
    96  	REG_FCSR7
    97  	REG_FCSR8
    98  	REG_FCSR9
    99  	REG_FCSR10
   100  	REG_FCSR11
   101  	REG_FCSR12
   102  	REG_FCSR13
   103  	REG_FCSR14
   104  	REG_FCSR15
   105  	REG_FCSR16
   106  	REG_FCSR17
   107  	REG_FCSR18
   108  	REG_FCSR19
   109  	REG_FCSR20
   110  	REG_FCSR21
   111  	REG_FCSR22
   112  	REG_FCSR23
   113  	REG_FCSR24
   114  	REG_FCSR25
   115  	REG_FCSR26
   116  	REG_FCSR27
   117  	REG_FCSR28
   118  	REG_FCSR29
   119  	REG_FCSR30
   120  	REG_FCSR31
   121  
   122  	REG_FCC0 // must be a multiple of 32
   123  	REG_FCC1
   124  	REG_FCC2
   125  	REG_FCC3
   126  	REG_FCC4
   127  	REG_FCC5
   128  	REG_FCC6
   129  	REG_FCC7 // only eight registers are needed
   130  	REG_FCC8
   131  	REG_FCC9
   132  	REG_FCC10
   133  	REG_FCC11
   134  	REG_FCC12
   135  	REG_FCC13
   136  	REG_FCC14
   137  	REG_FCC15
   138  	REG_FCC16
   139  	REG_FCC17
   140  	REG_FCC18
   141  	REG_FCC19
   142  	REG_FCC20
   143  	REG_FCC21
   144  	REG_FCC22
   145  	REG_FCC23
   146  	REG_FCC24
   147  	REG_FCC25
   148  	REG_FCC26
   149  	REG_FCC27
   150  	REG_FCC28
   151  	REG_FCC29
   152  	REG_FCC30
   153  	REG_FCC31
   154  
   155  	// LSX: 128-bit vector register
   156  	REG_V0
   157  	REG_V1
   158  	REG_V2
   159  	REG_V3
   160  	REG_V4
   161  	REG_V5
   162  	REG_V6
   163  	REG_V7
   164  	REG_V8
   165  	REG_V9
   166  	REG_V10
   167  	REG_V11
   168  	REG_V12
   169  	REG_V13
   170  	REG_V14
   171  	REG_V15
   172  	REG_V16
   173  	REG_V17
   174  	REG_V18
   175  	REG_V19
   176  	REG_V20
   177  	REG_V21
   178  	REG_V22
   179  	REG_V23
   180  	REG_V24
   181  	REG_V25
   182  	REG_V26
   183  	REG_V27
   184  	REG_V28
   185  	REG_V29
   186  	REG_V30
   187  	REG_V31
   188  
   189  	// LASX: 256-bit vector register
   190  	REG_X0
   191  	REG_X1
   192  	REG_X2
   193  	REG_X3
   194  	REG_X4
   195  	REG_X5
   196  	REG_X6
   197  	REG_X7
   198  	REG_X8
   199  	REG_X9
   200  	REG_X10
   201  	REG_X11
   202  	REG_X12
   203  	REG_X13
   204  	REG_X14
   205  	REG_X15
   206  	REG_X16
   207  	REG_X17
   208  	REG_X18
   209  	REG_X19
   210  	REG_X20
   211  	REG_X21
   212  	REG_X22
   213  	REG_X23
   214  	REG_X24
   215  	REG_X25
   216  	REG_X26
   217  	REG_X27
   218  	REG_X28
   219  	REG_X29
   220  	REG_X30
   221  	REG_X31
   222  
   223  	REG_SPECIAL = REG_FCSR0
   224  
   225  	REGZERO = REG_R0 // set to zero
   226  	REGLINK = REG_R1
   227  	REGSP   = REG_R3
   228  	REGCTXT = REG_R29 // context for closures
   229  	REGG    = REG_R22 // G in loong64
   230  	REGTMP  = REG_R30 // used by the assembler
   231  	FREGRET = REG_F0  // not use
   232  )
   233  
   234  var LOONG64DWARFRegisters = map[int16]int16{}
   235  
   236  func init() {
   237  	// f assigns dwarfregisters[from:to] = (base):(to-from+base)
   238  	f := func(from, to, base int16) {
   239  		for r := from; r <= to; r++ {
   240  			LOONG64DWARFRegisters[r] = (r - from) + base
   241  		}
   242  	}
   243  	f(REG_R0, REG_R31, 0)
   244  	f(REG_F0, REG_F31, 32)
   245  
   246  	// The lower bits of V and X registers are alias to F registers
   247  	f(REG_V0, REG_V31, 32)
   248  	f(REG_X0, REG_X31, 32)
   249  }
   250  
   251  const (
   252  	BIG_8  = 128 - 2 // FIXME (not sure if -2 is appropriate)
   253  	BIG_9  = 256 - 2
   254  	BIG_10 = 512 - 2
   255  	BIG_11 = 1024 - 2
   256  	BIG_12 = 2046
   257  	BIG_16 = 32768 - 2
   258  	BIG_32 = 2147483648 - 2
   259  )
   260  
   261  const (
   262  	// mark flags
   263  	LABEL  = 1 << 0
   264  	LEAF   = 1 << 1
   265  	SYNC   = 1 << 2
   266  	BRANCH = 1 << 3
   267  )
   268  
   269  // Arrangement for Loong64 SIMD instructions
   270  const (
   271  	// arrangement types
   272  	ARNG_32B int16 = iota
   273  	ARNG_16H
   274  	ARNG_8W
   275  	ARNG_4V
   276  	ARNG_2Q
   277  	ARNG_16B
   278  	ARNG_8H
   279  	ARNG_4W
   280  	ARNG_2V
   281  	ARNG_B
   282  	ARNG_H
   283  	ARNG_W
   284  	ARNG_V
   285  	ARNG_BU
   286  	ARNG_HU
   287  	ARNG_WU
   288  	ARNG_VU
   289  )
   290  
   291  // LoongArch64 SIMD extension type
   292  const (
   293  	LSX int16 = iota
   294  	LASX
   295  )
   296  
   297  // bits 0-4 indicates register: Vn or Xn
   298  // bits 5-9 indicates arrangement: <T>
   299  // bits 10 indicates SMID type: 0: LSX, 1: LASX
   300  const (
   301  	REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn.<T>
   302  	REG_ELEM                                               // Vn.<T>[index]
   303  	REG_ELEM_END
   304  )
   305  
   306  const (
   307  	EXT_REG_SHIFT = 0
   308  	EXT_REG_MASK  = 0x1f
   309  
   310  	EXT_TYPE_SHIFT = 5
   311  	EXT_TYPE_MASK  = 0x1f
   312  
   313  	EXT_SIMDTYPE_SHIFT = 10
   314  	EXT_SIMDTYPE_MASK  = 0x1
   315  )
   316  
   317  const (
   318  	REG_LAST = REG_ELEM_END // the last defined register
   319  )
   320  
   321  //go:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
   322  const (
   323  	C_NONE = iota
   324  	C_REG
   325  	C_FREG
   326  	C_FCSRREG
   327  	C_FCCREG
   328  	C_VREG
   329  	C_XREG
   330  	C_ARNG // Vn.<T>
   331  	C_ELEM // Vn.<T>[index]
   332  
   333  	C_ZCON
   334  	C_U1CON      // 1 bit unsigned constant
   335  	C_U2CON      // 2 bit unsigned constant
   336  	C_U3CON      // 3 bit unsigned constant
   337  	C_U4CON      // 4 bit unsigned constant
   338  	C_U5CON      // 5 bit unsigned constant
   339  	C_U6CON      // 6 bit unsigned constant
   340  	C_U7CON      // 7 bit unsigned constant
   341  	C_U8CON      // 8 bit unsigned constant
   342  	C_S5CON      // 5 bit signed constant
   343  	C_US12CON    // same as C_S12CON, increase the priority of C_S12CON in special cases.
   344  	C_UU12CON    // same as C_U12CON, increase the priority of C_U12CON in special cases.
   345  	C_S12CON     // 12 bit signed constant, -0x800 < v <= 0x7ff
   346  	C_U12CON     // 12 bit unsigned constant, 0 < v <= 0xfff
   347  	C_12CON      // 12 bit signed constant, or 12 bit unsigned constant
   348  	C_S13CON20_0 // 13 bit signed constant, low 12 bits 0
   349  	C_S13CON     // 13 bit signed constant
   350  	C_U13CON20_0 // 13 bit unsigned constant, low 12 bits 0
   351  	C_U13CON     // 13 bit unsigned constant
   352  	C_13CON      // 13 bit signed constant, or 13 bit unsigned constant
   353  	C_U15CON     // 15 bit unsigned constant
   354  	C_U15CON20_0 // 15 bit unsigned constant, low 12 bits 0
   355  	C_32CON20_0  // 32 bit signed, low 12 bits 0
   356  	C_32CON      // other 32 bit signed
   357  
   358  	// 64 bit signed, lo32 bits 0, hi20 bits are not 0, hi12 bits can
   359  	// be obtained by sign extension of the hi20 bits.
   360  	C_DCON20S_0
   361  	// 64 bit signed, lo52 bits 0, hi12 bits are not 0.
   362  	C_DCON12_0
   363  	// 64 bit signed, lo32 bits 0, hi32 bits are not 0.
   364  	C_DCON32_0
   365  	// 64 bit signed, lo12 bits 0, lo20 bits are not 0, hi20 bits can be
   366  	// obtained by sign extension of the lo20 bits, other bits are not 0.
   367  	C_DCON12_20S
   368  	// 64 bit signed, lo12 bits 0, hi20 bits are not 0, hi12 bits can be
   369  	// obtained by sign extension of the hi20 bits, other bits are not 0.
   370  	C_DCON20S_20
   371  	// 64 bit signed, lo12 bits 0, other bits are not 0.
   372  	C_DCON32_20
   373  	// 64 bit signed, lo12 bits are not 0, 12~51 bits can be obtained
   374  	// by sign extension of the lo12 bits, other bits are not 0.
   375  	C_DCON12_12S
   376  	// 64 bit signed, hi20 bits and lo12 bits are not 0, hi12 bits can
   377  	// be obtained by sign extension of the hi20 bits, lo20 bits can
   378  	// be obtained by sign extension of the lo12 bits.
   379  	C_DCON20S_12S
   380  	// 64 bit signed, lo12 bits are not 0, lo20 bits can be obtained by sign
   381  	// extension of the lo12 bits, other bits are not 0.
   382  	C_DCON32_12S
   383  	// 64 bit signed, lo20 and lo12 bits are not 0, hi20 bits can be obtained by sign
   384  	// extension of the lo20 bits. other bits are not 0.
   385  	C_DCON12_32S
   386  	// 64 bit signed, hi20 bits are not 0, hi12 bits can be obtained by sign
   387  	// extension of the hi20 bits, lo32 bits are not 0.
   388  	C_DCON20S_32
   389  	// 64 bit signed, 12~51 bits 0, other bits are not 0.
   390  	C_DCON12_12U
   391  	// 64 bit signed, lo20 bits 0, hi20 bits are not 0, hi12 bits can be
   392  	// obtained by sign extension of the hi20 bits, lo12 bits are not 0.
   393  	C_DCON20S_12U
   394  	// 64 bit signed, lo20 bits 0, other bits are not 0.
   395  	C_DCON32_12U
   396  	// other 64
   397  	C_DCON
   398  
   399  	C_SACON   // $n(REG) where n <= int12
   400  	C_LACON   // $n(REG) where int12 < n <= int32
   401  	C_DACON   // $n(REG) where int32 < n
   402  	C_EXTADDR // external symbol address
   403  	C_BRAN
   404  	C_SAUTO
   405  	C_LAUTO
   406  	C_ZOREG    // An $0+reg memory op
   407  	C_SOREG_8  // An $n+reg memory arg where n is a 8 bit signed offset
   408  	C_SOREG_9  // An $n+reg memory arg where n is a 9 bit signed offset
   409  	C_SOREG_10 // An $n+reg memory arg where n is a 10 bit signed offset
   410  	C_SOREG_11 // An $n+reg memory arg where n is a 11 bit signed offset
   411  	C_SOREG_12 // An $n+reg memory arg where n is a 12 bit signed offset
   412  	C_SOREG_16 // An $n+reg memory arg where n is a 16 bit signed offset
   413  	C_LOREG_32 // An $n+reg memory arg where n is a 32 bit signed offset
   414  	C_LOREG_64 // An $n+reg memory arg where n is a 64 bit signed offset
   415  	C_ROFF     // register offset
   416  	C_ADDR
   417  	C_TLS_LE
   418  	C_TLS_IE
   419  	C_GOTADDR
   420  	C_TEXTSIZE
   421  
   422  	C_GOK
   423  	C_NCLASS // must be the last
   424  )
   425  
   426  const (
   427  	AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota
   428  	AABSF
   429  	AADD
   430  	AADDD
   431  	AADDF
   432  	AADDU
   433  
   434  	AADDW
   435  	AAND
   436  	ABEQ
   437  	ABGEZ
   438  	ABLEZ
   439  	ABGTZ
   440  	ABLTZ
   441  	ABFPF
   442  	ABFPT
   443  
   444  	ABNE
   445  	ABREAK
   446  
   447  	ACMPEQD
   448  	ACMPEQF
   449  
   450  	ACMPGED // ACMPGED -> fcmp.sle.d
   451  	ACMPGEF // ACMPGEF -> fcmp.sle.s
   452  	ACMPGTD // ACMPGTD -> fcmp.slt.d
   453  	ACMPGTF // ACMPGTF -> fcmp.slt.s
   454  
   455  	ALU12IW
   456  	ALU32ID
   457  	ALU52ID
   458  	APCALAU12I
   459  	APCADDU12I
   460  	AJIRL
   461  	ABGE
   462  	ABLT
   463  	ABLTU
   464  	ABGEU
   465  
   466  	ADIV
   467  	ADIVD
   468  	ADIVF
   469  	ADIVU
   470  	ADIVW
   471  
   472  	ALL
   473  	ALLV
   474  
   475  	ALUI
   476  
   477  	AMOVB
   478  	AMOVBU
   479  
   480  	AMOVD
   481  	AMOVDF
   482  	AMOVDW
   483  	AMOVF
   484  	AMOVFD
   485  	AMOVFW
   486  
   487  	AMOVH
   488  	AMOVHU
   489  	AMOVW
   490  
   491  	AMOVWD
   492  	AMOVWF
   493  
   494  	AMUL
   495  	AMULD
   496  	AMULF
   497  	AMULU
   498  	AMULH
   499  	AMULHU
   500  	AMULW
   501  	ANEGD
   502  	ANEGF
   503  
   504  	ANEGW
   505  	ANEGV
   506  
   507  	ANOOP // hardware nop
   508  	ANOR
   509  	AOR
   510  	AREM
   511  	AREMU
   512  
   513  	ARFE
   514  
   515  	ASC
   516  	ASCV
   517  
   518  	ASGT
   519  	ASGTU
   520  
   521  	ASLL
   522  	ASQRTD
   523  	ASQRTF
   524  	ASRA
   525  	ASRL
   526  	AROTR
   527  	ASUB
   528  	ASUBD
   529  	ASUBF
   530  
   531  	ASUBU
   532  	ASUBW
   533  	ADBAR
   534  	ASYSCALL
   535  
   536  	ATEQ
   537  	ATNE
   538  
   539  	AWORD
   540  
   541  	AXOR
   542  
   543  	AMASKEQZ
   544  	AMASKNEZ
   545  
   546  	// 64-bit
   547  	AMOVV
   548  
   549  	ASLLV
   550  	ASRAV
   551  	ASRLV
   552  	AROTRV
   553  	ADIVV
   554  	ADIVVU
   555  
   556  	AREMV
   557  	AREMVU
   558  
   559  	AMULV
   560  	AMULVU
   561  	AMULHV
   562  	AMULHVU
   563  	AADDV
   564  	AADDVU
   565  	ASUBV
   566  	ASUBVU
   567  
   568  	// 64-bit FP
   569  	ATRUNCFV
   570  	ATRUNCDV
   571  	ATRUNCFW
   572  	ATRUNCDW
   573  
   574  	AMOVWU
   575  	AMOVFV
   576  	AMOVDV
   577  	AMOVVF
   578  	AMOVVD
   579  
   580  	// 2.2.1.2
   581  	AADDV16
   582  
   583  	// 2.2.1.3
   584  	AALSLW
   585  	AALSLWU
   586  	AALSLV
   587  
   588  	// 2.2.1.8
   589  	AORN
   590  	AANDN
   591  
   592  	// 2.2.7. Atomic Memory Access Instructions
   593  	AAMSWAPB
   594  	AAMSWAPH
   595  	AAMSWAPW
   596  	AAMSWAPV
   597  	AAMCASB
   598  	AAMCASH
   599  	AAMCASW
   600  	AAMCASV
   601  	AAMADDW
   602  	AAMADDV
   603  	AAMANDW
   604  	AAMANDV
   605  	AAMORW
   606  	AAMORV
   607  	AAMXORW
   608  	AAMXORV
   609  	AAMMAXW
   610  	AAMMAXV
   611  	AAMMINW
   612  	AAMMINV
   613  	AAMMAXWU
   614  	AAMMAXVU
   615  	AAMMINWU
   616  	AAMMINVU
   617  	AAMSWAPDBB
   618  	AAMSWAPDBH
   619  	AAMSWAPDBW
   620  	AAMSWAPDBV
   621  	AAMCASDBB
   622  	AAMCASDBH
   623  	AAMCASDBW
   624  	AAMCASDBV
   625  	AAMADDDBW
   626  	AAMADDDBV
   627  	AAMANDDBW
   628  	AAMANDDBV
   629  	AAMORDBW
   630  	AAMORDBV
   631  	AAMXORDBW
   632  	AAMXORDBV
   633  	AAMMAXDBW
   634  	AAMMAXDBV
   635  	AAMMINDBW
   636  	AAMMINDBV
   637  	AAMMAXDBWU
   638  	AAMMAXDBVU
   639  	AAMMINDBWU
   640  	AAMMINDBVU
   641  
   642  	// 2.2.3.1
   643  	AEXTWB
   644  	AEXTWH
   645  
   646  	// 2.2.3.2
   647  	ACLOW
   648  	ACLOV
   649  	ACLZW
   650  	ACLZV
   651  	ACTOW
   652  	ACTOV
   653  	ACTZW
   654  	ACTZV
   655  
   656  	// 2.2.3.4
   657  	AREVBV
   658  	AREVB2W
   659  	AREVB4H
   660  	AREVB2H
   661  
   662  	// 2.2.3.5
   663  	AREVH2W
   664  	AREVHV
   665  
   666  	// 2.2.3.6
   667  	ABITREV4B
   668  	ABITREV8B
   669  
   670  	// 2.2.3.7
   671  	ABITREVW
   672  	ABITREVV
   673  
   674  	// 2.2.3.8
   675  	ABSTRINSW
   676  	ABSTRINSV
   677  
   678  	// 2.2.3.9
   679  	ABSTRPICKW
   680  	ABSTRPICKV
   681  
   682  	// 2.2.5.3
   683  	AMOVWP
   684  	AMOVVP
   685  
   686  	// 2.2.5.4. Prefetch Instructions
   687  	APRELD
   688  	APRELDX
   689  
   690  	// 2.2.9. CRC Check Instructions
   691  	ACRCWBW
   692  	ACRCWHW
   693  	ACRCWWW
   694  	ACRCWVW
   695  	ACRCCWBW
   696  	ACRCCWHW
   697  	ACRCCWWW
   698  	ACRCCWVW
   699  
   700  	// 2.2.10. Other Miscellaneous Instructions
   701  	ARDTIMELW
   702  	ARDTIMEHW
   703  	ARDTIMED
   704  	ACPUCFG
   705  
   706  	// 3.2.1.2
   707  	AFMADDF
   708  	AFMADDD
   709  	AFMSUBF
   710  	AFMSUBD
   711  	AFNMADDF
   712  	AFNMADDD
   713  	AFNMSUBF
   714  	AFNMSUBD
   715  
   716  	// 3.2.1.3
   717  	AFMINF
   718  	AFMIND
   719  	AFMAXF
   720  	AFMAXD
   721  
   722  	// 3.2.1.4
   723  	AFMAXAF
   724  	AFMAXAD
   725  	AFMINAF
   726  	AFMINAD
   727  
   728  	// 3.2.1.7
   729  	AFCOPYSGF
   730  	AFCOPYSGD
   731  	AFSCALEBF
   732  	AFSCALEBD
   733  	AFLOGBF
   734  	AFLOGBD
   735  
   736  	// 3.2.1.8
   737  	AFCLASSF
   738  	AFCLASSD
   739  
   740  	// 3.2.3.2
   741  	AFFINTFW
   742  	AFFINTFV
   743  	AFFINTDW
   744  	AFFINTDV
   745  	AFTINTWF
   746  	AFTINTWD
   747  	AFTINTVF
   748  	AFTINTVD
   749  
   750  	// 3.2.3.3
   751  	AFTINTRPWF
   752  	AFTINTRPWD
   753  	AFTINTRPVF
   754  	AFTINTRPVD
   755  	AFTINTRMWF
   756  	AFTINTRMWD
   757  	AFTINTRMVF
   758  	AFTINTRMVD
   759  	AFTINTRZWF
   760  	AFTINTRZWD
   761  	AFTINTRZVF
   762  	AFTINTRZVD
   763  	AFTINTRNEWF
   764  	AFTINTRNEWD
   765  	AFTINTRNEVF
   766  	AFTINTRNEVD
   767  
   768  	// 3.2.4.2
   769  	AFSEL
   770  
   771  	// LSX and LASX memory access instructions
   772  	AVMOVQ
   773  	AXVMOVQ
   774  
   775  	// LSX and LASX arithmetic instructions
   776  	AVADDB
   777  	AVADDH
   778  	AVADDW
   779  	AVADDV
   780  	AVADDQ
   781  	AXVADDB
   782  	AXVADDH
   783  	AXVADDW
   784  	AXVADDV
   785  	AXVADDQ
   786  	AVSUBB
   787  	AVSUBH
   788  	AVSUBW
   789  	AVSUBV
   790  	AVSUBQ
   791  	AXVSUBB
   792  	AXVSUBH
   793  	AXVSUBW
   794  	AXVSUBV
   795  	AXVSUBQ
   796  	AVADDBU
   797  	AVADDHU
   798  	AVADDWU
   799  	AVADDVU
   800  	AVSUBBU
   801  	AVSUBHU
   802  	AVSUBWU
   803  	AVSUBVU
   804  	AXVADDBU
   805  	AXVADDHU
   806  	AXVADDWU
   807  	AXVADDVU
   808  	AXVSUBBU
   809  	AXVSUBHU
   810  	AXVSUBWU
   811  	AXVSUBVU
   812  
   813  	// LSX and LASX Bit-manipulation Instructions
   814  	AVANDB
   815  	AVORB
   816  	AVXORB
   817  	AVNORB
   818  	AXVANDB
   819  	AXVORB
   820  	AXVXORB
   821  	AXVNORB
   822  	AVANDV
   823  	AVORV
   824  	AVXORV
   825  	AVNORV
   826  	AVANDNV
   827  	AVORNV
   828  	AXVANDV
   829  	AXVORV
   830  	AXVXORV
   831  	AXVNORV
   832  	AXVANDNV
   833  	AXVORNV
   834  
   835  	AVPCNTB
   836  	AVPCNTH
   837  	AVPCNTW
   838  	AVPCNTV
   839  	AXVPCNTB
   840  	AXVPCNTH
   841  	AXVPCNTW
   842  	AXVPCNTV
   843  
   844  	AVBITCLRB
   845  	AVBITCLRH
   846  	AVBITCLRW
   847  	AVBITCLRV
   848  	AVBITSETB
   849  	AVBITSETH
   850  	AVBITSETW
   851  	AVBITSETV
   852  	AVBITREVB
   853  	AVBITREVH
   854  	AVBITREVW
   855  	AVBITREVV
   856  	AXVBITCLRB
   857  	AXVBITCLRH
   858  	AXVBITCLRW
   859  	AXVBITCLRV
   860  	AXVBITSETB
   861  	AXVBITSETH
   862  	AXVBITSETW
   863  	AXVBITSETV
   864  	AXVBITREVB
   865  	AXVBITREVH
   866  	AXVBITREVW
   867  	AXVBITREVV
   868  
   869  	// LSX and LASX integer comparison instruction
   870  	AVSEQB
   871  	AXVSEQB
   872  	AVSEQH
   873  	AXVSEQH
   874  	AVSEQW
   875  	AXVSEQW
   876  	AVSEQV
   877  	AXVSEQV
   878  
   879  	// LSX and LASX integer div and mod instructions
   880  	AVDIVB
   881  	AVDIVH
   882  	AVDIVW
   883  	AVDIVV
   884  	AVDIVBU
   885  	AVDIVHU
   886  	AVDIVWU
   887  	AVDIVVU
   888  	AVMODB
   889  	AVMODH
   890  	AVMODW
   891  	AVMODV
   892  	AVMODBU
   893  	AVMODHU
   894  	AVMODWU
   895  	AVMODVU
   896  	AXVDIVB
   897  	AXVDIVH
   898  	AXVDIVW
   899  	AXVDIVV
   900  	AXVDIVBU
   901  	AXVDIVHU
   902  	AXVDIVWU
   903  	AXVDIVVU
   904  	AXVMODB
   905  	AXVMODH
   906  	AXVMODW
   907  	AXVMODV
   908  	AXVMODBU
   909  	AXVMODHU
   910  	AXVMODWU
   911  	AXVMODVU
   912  
   913  	// LSX and LASX shift operation instructions
   914  	AVSLLB
   915  	AVSLLH
   916  	AVSLLW
   917  	AVSLLV
   918  	AVSRLB
   919  	AVSRLH
   920  	AVSRLW
   921  	AVSRLV
   922  	AVSRAB
   923  	AVSRAH
   924  	AVSRAW
   925  	AVSRAV
   926  	AVROTRB
   927  	AVROTRH
   928  	AVROTRW
   929  	AVROTRV
   930  	AXVSLLB
   931  	AXVSLLH
   932  	AXVSLLW
   933  	AXVSLLV
   934  	AXVSRLB
   935  	AXVSRLH
   936  	AXVSRLW
   937  	AXVSRLV
   938  	AXVSRAB
   939  	AXVSRAH
   940  	AXVSRAW
   941  	AXVSRAV
   942  	AXVROTRB
   943  	AXVROTRH
   944  	AXVROTRW
   945  	AXVROTRV
   946  
   947  	// LSX and LASX move and shuffle instructions
   948  	AVILVLB
   949  	AVILVLH
   950  	AVILVLW
   951  	AVILVLV
   952  	AVILVHB
   953  	AVILVHH
   954  	AVILVHW
   955  	AVILVHV
   956  	AXVILVLB
   957  	AXVILVLH
   958  	AXVILVLW
   959  	AXVILVLV
   960  	AXVILVHB
   961  	AXVILVHH
   962  	AXVILVHW
   963  	AXVILVHV
   964  
   965  	// LSX and LASX integer mul instructions
   966  	AVMULB
   967  	AVMULH
   968  	AVMULW
   969  	AVMULV
   970  	AVMUHB
   971  	AVMUHH
   972  	AVMUHW
   973  	AVMUHV
   974  	AVMUHBU
   975  	AVMUHHU
   976  	AVMUHWU
   977  	AVMUHVU
   978  	AXVMULB
   979  	AXVMULH
   980  	AXVMULW
   981  	AXVMULV
   982  	AXVMUHB
   983  	AXVMUHH
   984  	AXVMUHW
   985  	AXVMUHV
   986  	AXVMUHBU
   987  	AXVMUHHU
   988  	AXVMUHWU
   989  	AXVMUHVU
   990  
   991  	// LSX and LASX floating point instructions
   992  	AVFSQRTF
   993  	AVFSQRTD
   994  	AVFRECIPF
   995  	AVFRECIPD
   996  	AVFRSQRTF
   997  	AVFRSQRTD
   998  	AXVFSQRTF
   999  	AXVFSQRTD
  1000  	AXVFRECIPF
  1001  	AXVFRECIPD
  1002  	AXVFRSQRTF
  1003  	AXVFRSQRTD
  1004  
  1005  	AVADDF
  1006  	AVADDD
  1007  	AVSUBF
  1008  	AVSUBD
  1009  	AVMULF
  1010  	AVMULD
  1011  	AVDIVF
  1012  	AVDIVD
  1013  	AXVADDF
  1014  	AXVADDD
  1015  	AXVSUBF
  1016  	AXVSUBD
  1017  	AXVMULF
  1018  	AXVMULD
  1019  	AXVDIVF
  1020  	AXVDIVD
  1021  
  1022  	AVFCLASSF
  1023  	AVFCLASSD
  1024  	AXVFCLASSF
  1025  	AXVFCLASSD
  1026  
  1027  	// LSX and LASX floating point conversion instructions
  1028  	AVFRINTRNEF
  1029  	AVFRINTRNED
  1030  	AVFRINTRZF
  1031  	AVFRINTRZD
  1032  	AVFRINTRPF
  1033  	AVFRINTRPD
  1034  	AVFRINTRMF
  1035  	AVFRINTRMD
  1036  	AVFRINTF
  1037  	AVFRINTD
  1038  	AXVFRINTRNEF
  1039  	AXVFRINTRNED
  1040  	AXVFRINTRZF
  1041  	AXVFRINTRZD
  1042  	AXVFRINTRPF
  1043  	AXVFRINTRPD
  1044  	AXVFRINTRMF
  1045  	AXVFRINTRMD
  1046  	AXVFRINTF
  1047  	AXVFRINTD
  1048  
  1049  	// LSX and LASX integer neg instructions
  1050  	AVNEGB
  1051  	AVNEGH
  1052  	AVNEGW
  1053  	AVNEGV
  1054  	AXVNEGB
  1055  	AXVNEGH
  1056  	AXVNEGW
  1057  	AXVNEGV
  1058  
  1059  	// LSX and LASX mul instructions that operate on even or odd positions
  1060  	AVMULWEVHB
  1061  	AVMULWEVWH
  1062  	AVMULWEVVW
  1063  	AVMULWEVQV
  1064  	AVMULWODHB
  1065  	AVMULWODWH
  1066  	AVMULWODVW
  1067  	AVMULWODQV
  1068  	AVMULWEVHBU
  1069  	AVMULWEVWHU
  1070  	AVMULWEVVWU
  1071  	AVMULWEVQVU
  1072  	AVMULWODHBU
  1073  	AVMULWODWHU
  1074  	AVMULWODVWU
  1075  	AVMULWODQVU
  1076  	AXVMULWEVHB
  1077  	AXVMULWEVWH
  1078  	AXVMULWEVVW
  1079  	AXVMULWEVQV
  1080  	AXVMULWODHB
  1081  	AXVMULWODWH
  1082  	AXVMULWODVW
  1083  	AXVMULWODQV
  1084  	AXVMULWEVHBU
  1085  	AXVMULWEVWHU
  1086  	AXVMULWEVVWU
  1087  	AXVMULWEVQVU
  1088  	AXVMULWODHBU
  1089  	AXVMULWODWHU
  1090  	AXVMULWODVWU
  1091  	AXVMULWODQVU
  1092  	AVMULWEVHBUB
  1093  	AVMULWEVWHUH
  1094  	AVMULWEVVWUW
  1095  	AVMULWEVQVUV
  1096  	AVMULWODHBUB
  1097  	AVMULWODWHUH
  1098  	AVMULWODVWUW
  1099  	AVMULWODQVUV
  1100  	AXVMULWEVHBUB
  1101  	AXVMULWEVWHUH
  1102  	AXVMULWEVVWUW
  1103  	AXVMULWEVQVUV
  1104  	AXVMULWODHBUB
  1105  	AXVMULWODWHUH
  1106  	AXVMULWODVWUW
  1107  	AXVMULWODQVUV
  1108  
  1109  	AVSHUF4IB
  1110  	AVSHUF4IH
  1111  	AVSHUF4IW
  1112  	AVSHUF4IV
  1113  	AXVSHUF4IB
  1114  	AXVSHUF4IH
  1115  	AXVSHUF4IW
  1116  	AXVSHUF4IV
  1117  
  1118  	AVPERMIW
  1119  	AXVPERMIW
  1120  	AXVPERMIV
  1121  	AXVPERMIQ
  1122  
  1123  	AVSETEQV
  1124  	AVSETNEV
  1125  	AVSETANYEQB
  1126  	AVSETANYEQH
  1127  	AVSETANYEQW
  1128  	AVSETANYEQV
  1129  	AVSETALLNEB
  1130  	AVSETALLNEH
  1131  	AVSETALLNEW
  1132  	AVSETALLNEV
  1133  	AXVSETEQV
  1134  	AXVSETNEV
  1135  	AXVSETANYEQB
  1136  	AXVSETANYEQH
  1137  	AXVSETANYEQW
  1138  	AXVSETANYEQV
  1139  	AXVSETALLNEB
  1140  	AXVSETALLNEH
  1141  	AXVSETALLNEW
  1142  	AXVSETALLNEV
  1143  
  1144  	ALAST
  1145  
  1146  	// aliases
  1147  	AJMP = obj.AJMP
  1148  	AJAL = obj.ACALL
  1149  	ARET = obj.ARET
  1150  )
  1151  
  1152  func init() {
  1153  	// The asm encoder generally assumes that the lowest 5 bits of the
  1154  	// REG_XX constants match the machine instruction encoding, i.e.
  1155  	// the lowest 5 bits is the register number.
  1156  	// Check this here.
  1157  	if REG_R0%32 != 0 {
  1158  		panic("REG_R0 is not a multiple of 32")
  1159  	}
  1160  	if REG_F0%32 != 0 {
  1161  		panic("REG_F0 is not a multiple of 32")
  1162  	}
  1163  	if REG_FCSR0%32 != 0 {
  1164  		panic("REG_FCSR0 is not a multiple of 32")
  1165  	}
  1166  	if REG_FCC0%32 != 0 {
  1167  		panic("REG_FCC0 is not a multiple of 32")
  1168  	}
  1169  	if REG_V0%32 != 0 {
  1170  		panic("REG_V0 is not a multiple of 32")
  1171  	}
  1172  	if REG_X0%32 != 0 {
  1173  		panic("REG_X0 is not a multiple of 32")
  1174  	}
  1175  }
  1176
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