a.out.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  )
    10  
    11  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64
    12  
    13  const (
    14  	NSNAME = 8
    15  	NSYM   = 50
    16  	NREG   = 32 // number of general registers
    17  	NFREG  = 32 // number of floating point registers
    18  	NVREG  = 32 // number of LSX registers
    19  	NXREG  = 32 // number of LASX registers
    20  )
    21  
    22  const (
    23  	REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32
    24  	REG_R1
    25  	REG_R2
    26  	REG_R3
    27  	REG_R4
    28  	REG_R5
    29  	REG_R6
    30  	REG_R7
    31  	REG_R8
    32  	REG_R9
    33  	REG_R10
    34  	REG_R11
    35  	REG_R12
    36  	REG_R13
    37  	REG_R14
    38  	REG_R15
    39  	REG_R16
    40  	REG_R17
    41  	REG_R18
    42  	REG_R19
    43  	REG_R20
    44  	REG_R21
    45  	REG_R22
    46  	REG_R23
    47  	REG_R24
    48  	REG_R25
    49  	REG_R26
    50  	REG_R27
    51  	REG_R28
    52  	REG_R29
    53  	REG_R30
    54  	REG_R31
    55  
    56  	REG_F0 // must be a multiple of 32
    57  	REG_F1
    58  	REG_F2
    59  	REG_F3
    60  	REG_F4
    61  	REG_F5
    62  	REG_F6
    63  	REG_F7
    64  	REG_F8
    65  	REG_F9
    66  	REG_F10
    67  	REG_F11
    68  	REG_F12
    69  	REG_F13
    70  	REG_F14
    71  	REG_F15
    72  	REG_F16
    73  	REG_F17
    74  	REG_F18
    75  	REG_F19
    76  	REG_F20
    77  	REG_F21
    78  	REG_F22
    79  	REG_F23
    80  	REG_F24
    81  	REG_F25
    82  	REG_F26
    83  	REG_F27
    84  	REG_F28
    85  	REG_F29
    86  	REG_F30
    87  	REG_F31
    88  
    89  	REG_FCSR0 // must be a multiple of 32
    90  	REG_FCSR1
    91  	REG_FCSR2
    92  	REG_FCSR3 // only four registers are needed
    93  	REG_FCSR4
    94  	REG_FCSR5
    95  	REG_FCSR6
    96  	REG_FCSR7
    97  	REG_FCSR8
    98  	REG_FCSR9
    99  	REG_FCSR10
   100  	REG_FCSR11
   101  	REG_FCSR12
   102  	REG_FCSR13
   103  	REG_FCSR14
   104  	REG_FCSR15
   105  	REG_FCSR16
   106  	REG_FCSR17
   107  	REG_FCSR18
   108  	REG_FCSR19
   109  	REG_FCSR20
   110  	REG_FCSR21
   111  	REG_FCSR22
   112  	REG_FCSR23
   113  	REG_FCSR24
   114  	REG_FCSR25
   115  	REG_FCSR26
   116  	REG_FCSR27
   117  	REG_FCSR28
   118  	REG_FCSR29
   119  	REG_FCSR30
   120  	REG_FCSR31
   121  
   122  	REG_FCC0 // must be a multiple of 32
   123  	REG_FCC1
   124  	REG_FCC2
   125  	REG_FCC3
   126  	REG_FCC4
   127  	REG_FCC5
   128  	REG_FCC6
   129  	REG_FCC7 // only eight registers are needed
   130  	REG_FCC8
   131  	REG_FCC9
   132  	REG_FCC10
   133  	REG_FCC11
   134  	REG_FCC12
   135  	REG_FCC13
   136  	REG_FCC14
   137  	REG_FCC15
   138  	REG_FCC16
   139  	REG_FCC17
   140  	REG_FCC18
   141  	REG_FCC19
   142  	REG_FCC20
   143  	REG_FCC21
   144  	REG_FCC22
   145  	REG_FCC23
   146  	REG_FCC24
   147  	REG_FCC25
   148  	REG_FCC26
   149  	REG_FCC27
   150  	REG_FCC28
   151  	REG_FCC29
   152  	REG_FCC30
   153  	REG_FCC31
   154  
   155  	// LSX: 128-bit vector register
   156  	REG_V0
   157  	REG_V1
   158  	REG_V2
   159  	REG_V3
   160  	REG_V4
   161  	REG_V5
   162  	REG_V6
   163  	REG_V7
   164  	REG_V8
   165  	REG_V9
   166  	REG_V10
   167  	REG_V11
   168  	REG_V12
   169  	REG_V13
   170  	REG_V14
   171  	REG_V15
   172  	REG_V16
   173  	REG_V17
   174  	REG_V18
   175  	REG_V19
   176  	REG_V20
   177  	REG_V21
   178  	REG_V22
   179  	REG_V23
   180  	REG_V24
   181  	REG_V25
   182  	REG_V26
   183  	REG_V27
   184  	REG_V28
   185  	REG_V29
   186  	REG_V30
   187  	REG_V31
   188  
   189  	// LASX: 256-bit vector register
   190  	REG_X0
   191  	REG_X1
   192  	REG_X2
   193  	REG_X3
   194  	REG_X4
   195  	REG_X5
   196  	REG_X6
   197  	REG_X7
   198  	REG_X8
   199  	REG_X9
   200  	REG_X10
   201  	REG_X11
   202  	REG_X12
   203  	REG_X13
   204  	REG_X14
   205  	REG_X15
   206  	REG_X16
   207  	REG_X17
   208  	REG_X18
   209  	REG_X19
   210  	REG_X20
   211  	REG_X21
   212  	REG_X22
   213  	REG_X23
   214  	REG_X24
   215  	REG_X25
   216  	REG_X26
   217  	REG_X27
   218  	REG_X28
   219  	REG_X29
   220  	REG_X30
   221  	REG_X31
   222  
   223  	REG_SPECIAL = REG_FCSR0
   224  
   225  	REGZERO = REG_R0 // set to zero
   226  	REGLINK = REG_R1
   227  	REGSP   = REG_R3
   228  	REGRT1  = REG_R20 // reserved for runtime, duffzero and duffcopy
   229  	REGRT2  = REG_R21 // reserved for runtime, duffcopy
   230  	REGCTXT = REG_R29 // context for closures
   231  	REGG    = REG_R22 // G in loong64
   232  	REGTMP  = REG_R30 // used by the assembler
   233  	FREGRET = REG_F0  // not use
   234  )
   235  
   236  var LOONG64DWARFRegisters = map[int16]int16{}
   237  
   238  func init() {
   239  	// f assigns dwarfregisters[from:to] = (base):(to-from+base)
   240  	f := func(from, to, base int16) {
   241  		for r := int16(from); r <= to; r++ {
   242  			LOONG64DWARFRegisters[r] = (r - from) + base
   243  		}
   244  	}
   245  	f(REG_R0, REG_R31, 0)
   246  	f(REG_F0, REG_F31, 32)
   247  
   248  	// The lower bits of V and X registers are alias to F registers
   249  	f(REG_V0, REG_V31, 32)
   250  	f(REG_X0, REG_X31, 32)
   251  }
   252  
   253  const (
   254  	BIG = 2046
   255  )
   256  
   257  const (
   258  	// mark flags
   259  	LABEL  = 1 << 0
   260  	LEAF   = 1 << 1
   261  	SYNC   = 1 << 2
   262  	BRANCH = 1 << 3
   263  )
   264  
   265  // Arrangement for Loong64 SIMD instructions
   266  const (
   267  	// arrangement types
   268  	ARNG_32B int16 = iota
   269  	ARNG_16H
   270  	ARNG_8W
   271  	ARNG_4V
   272  	ARNG_2Q
   273  	ARNG_16B
   274  	ARNG_8H
   275  	ARNG_4W
   276  	ARNG_2V
   277  	ARNG_B
   278  	ARNG_H
   279  	ARNG_W
   280  	ARNG_V
   281  	ARNG_BU
   282  	ARNG_HU
   283  	ARNG_WU
   284  	ARNG_VU
   285  )
   286  
   287  // LoongArch64 SIMD extension type
   288  const (
   289  	LSX int16 = iota
   290  	LASX
   291  )
   292  
   293  // bits 0-4 indicates register: Vn or Xn
   294  // bits 5-9 indicates arrangement: <T>
   295  // bits 10 indicates SMID type: 0: LSX, 1: LASX
   296  const (
   297  	REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn.<T>
   298  	REG_ELEM                                               // Vn.<T>[index]
   299  	REG_ELEM_END
   300  )
   301  
   302  const (
   303  	EXT_REG_SHIFT = 0
   304  	EXT_REG_MASK  = 0x1f
   305  
   306  	EXT_TYPE_SHIFT = 5
   307  	EXT_TYPE_MASK  = 0x1f
   308  
   309  	EXT_SIMDTYPE_SHIFT = 10
   310  	EXT_SIMDTYPE_MASK  = 0x1
   311  )
   312  
   313  const (
   314  	REG_LAST = REG_ELEM_END // the last defined register
   315  )
   316  
   317  //go:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
   318  const (
   319  	C_NONE = iota
   320  	C_REG
   321  	C_FREG
   322  	C_FCSRREG
   323  	C_FCCREG
   324  	C_VREG
   325  	C_XREG
   326  	C_ARNG // Vn.<T>
   327  	C_ELEM // Vn.<T>[index]
   328  
   329  	C_ZCON
   330  	C_U1CON      // 1 bit unsigned constant
   331  	C_U2CON      // 2 bit unsigned constant
   332  	C_U3CON      // 3 bit unsigned constant
   333  	C_U4CON      // 4 bit unsigned constant
   334  	C_U5CON      // 5 bit unsigned constant
   335  	C_U6CON      // 6 bit unsigned constant
   336  	C_U7CON      // 7 bit unsigned constant
   337  	C_U8CON      // 8 bit unsigned constant
   338  	C_S5CON      // 5 bit signed constant
   339  	C_US12CON    // same as C_S12CON, increase the priority of C_S12CON in special cases.
   340  	C_UU12CON    // same as C_U12CON, increase the priority of C_U12CON in special cases.
   341  	C_S12CON     // 12 bit signed constant, -0x800 < v <= 0x7ff
   342  	C_U12CON     // 12 bit unsigned constant, 0 < v <= 0xfff
   343  	C_12CON      // 12 bit signed constant, or 12 bit unsigned constant
   344  	C_S13CON20_0 // 13 bit signed constant, low 12 bits 0
   345  	C_S13CON     // 13 bit signed constant
   346  	C_U13CON20_0 // 13 bit unsigned constant, low 12 bits 0
   347  	C_U13CON     // 13 bit unsigned constant
   348  	C_13CON      // 13 bit signed constant, or 13 bit unsigned constant
   349  	C_U15CON     // 15 bit unsigned constant
   350  	C_U15CON20_0 // 15 bit unsigned constant, low 12 bits 0
   351  	C_32CON20_0  // 32 bit signed, low 12 bits 0
   352  	C_32CON      // other 32 bit signed
   353  
   354  	// 64 bit signed, lo32 bits 0, hi20 bits are not 0, hi12 bits can
   355  	// be obtained by sign extension of the hi20 bits.
   356  	C_DCON20S_0
   357  	// 64 bit signed, lo52 bits 0, hi12 bits are not 0.
   358  	C_DCON12_0
   359  	// 64 bit signed, lo32 bits 0, hi32 bits are not 0.
   360  	C_DCON32_0
   361  	// 64 bit signed, lo12 bits 0, lo20 bits are not 0, hi20 bits can be
   362  	// obtained by sign extension of the lo20 bits, other bits are not 0.
   363  	C_DCON12_20S
   364  	// 64 bit signed, lo12 bits 0, hi20 bits are not 0, hi12 bits can be
   365  	// obtained by sign extension of the hi20 bits, other bits are not 0.
   366  	C_DCON20S_20
   367  	// 64 bit signed, lo12 bits 0, other bits are not 0.
   368  	C_DCON32_20
   369  	// 64 bit signed, lo12 bits are not 0, 12~51 bits can be obtained
   370  	// by sign extension of the lo12 bits, other bits are not 0.
   371  	C_DCON12_12S
   372  	// 64 bit signed, hi20 bits and lo12 bits are not 0, hi12 bits can
   373  	// be obtained by sign extension of the hi20 bits, lo20 bits can
   374  	// be obtained by sign extension of the lo12 bits.
   375  	C_DCON20S_12S
   376  	// 64 bit signed, lo12 bits are not 0, lo20 bits can be obtained by sign
   377  	// extension of the lo12 bits, other bits are not 0.
   378  	C_DCON32_12S
   379  	// 64 bit signed, lo20 and lo12 bits are not 0, hi20 bits can be obtained by sign
   380  	// extension of the lo20 bits. other bits are not 0.
   381  	C_DCON12_32S
   382  	// 64 bit signed, hi20 bits are not 0, hi12 bits can be obtained by sign
   383  	// extension of the hi20 bits, lo32 bits are not 0.
   384  	C_DCON20S_32
   385  	// 64 bit signed, 12~51 bits 0, other bits are not 0.
   386  	C_DCON12_12U
   387  	// 64 bit signed, lo20 bits 0, hi20 bits are not 0, hi12 bits can be
   388  	// obtained by sign extension of the hi20 bits, lo12 bits are not 0.
   389  	C_DCON20S_12U
   390  	// 64 bit signed, lo20 bits 0, other bits are not 0.
   391  	C_DCON32_12U
   392  	// other 64
   393  	C_DCON
   394  
   395  	C_SACON   // $n(REG) where n <= int12
   396  	C_LACON   // $n(REG) where int12 < n <= int32
   397  	C_DACON   // $n(REG) where int32 < n
   398  	C_EXTADDR // external symbol address
   399  	C_BRAN
   400  	C_SAUTO
   401  	C_LAUTO
   402  	C_ZOREG
   403  	C_SOREG
   404  	C_LOREG
   405  	C_ROFF // register offset
   406  	C_ADDR
   407  	C_TLS_LE
   408  	C_TLS_IE
   409  	C_GOTADDR
   410  	C_TEXTSIZE
   411  
   412  	C_GOK
   413  	C_NCLASS // must be the last
   414  )
   415  
   416  const (
   417  	AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota
   418  	AABSF
   419  	AADD
   420  	AADDD
   421  	AADDF
   422  	AADDU
   423  
   424  	AADDW
   425  	AAND
   426  	ABEQ
   427  	ABGEZ
   428  	ABLEZ
   429  	ABGTZ
   430  	ABLTZ
   431  	ABFPF
   432  	ABFPT
   433  
   434  	ABNE
   435  	ABREAK
   436  
   437  	ACMPEQD
   438  	ACMPEQF
   439  
   440  	ACMPGED // ACMPGED -> fcmp.sle.d
   441  	ACMPGEF // ACMPGEF -> fcmp.sle.s
   442  	ACMPGTD // ACMPGTD -> fcmp.slt.d
   443  	ACMPGTF // ACMPGTF -> fcmp.slt.s
   444  
   445  	ALU12IW
   446  	ALU32ID
   447  	ALU52ID
   448  	APCALAU12I
   449  	APCADDU12I
   450  	AJIRL
   451  	ABGE
   452  	ABLT
   453  	ABLTU
   454  	ABGEU
   455  
   456  	ADIV
   457  	ADIVD
   458  	ADIVF
   459  	ADIVU
   460  	ADIVW
   461  
   462  	ALL
   463  	ALLV
   464  
   465  	ALUI
   466  
   467  	AMOVB
   468  	AMOVBU
   469  
   470  	AMOVD
   471  	AMOVDF
   472  	AMOVDW
   473  	AMOVF
   474  	AMOVFD
   475  	AMOVFW
   476  
   477  	AMOVH
   478  	AMOVHU
   479  	AMOVW
   480  
   481  	AMOVWD
   482  	AMOVWF
   483  
   484  	AMUL
   485  	AMULD
   486  	AMULF
   487  	AMULU
   488  	AMULH
   489  	AMULHU
   490  	AMULW
   491  	ANEGD
   492  	ANEGF
   493  
   494  	ANEGW
   495  	ANEGV
   496  
   497  	ANOOP // hardware nop
   498  	ANOR
   499  	AOR
   500  	AREM
   501  	AREMU
   502  
   503  	ARFE
   504  
   505  	ASC
   506  	ASCV
   507  
   508  	ASGT
   509  	ASGTU
   510  
   511  	ASLL
   512  	ASQRTD
   513  	ASQRTF
   514  	ASRA
   515  	ASRL
   516  	AROTR
   517  	ASUB
   518  	ASUBD
   519  	ASUBF
   520  
   521  	ASUBU
   522  	ASUBW
   523  	ADBAR
   524  	ASYSCALL
   525  
   526  	ATEQ
   527  	ATNE
   528  
   529  	AWORD
   530  
   531  	AXOR
   532  
   533  	AMASKEQZ
   534  	AMASKNEZ
   535  
   536  	// 64-bit
   537  	AMOVV
   538  
   539  	ASLLV
   540  	ASRAV
   541  	ASRLV
   542  	AROTRV
   543  	ADIVV
   544  	ADIVVU
   545  
   546  	AREMV
   547  	AREMVU
   548  
   549  	AMULV
   550  	AMULVU
   551  	AMULHV
   552  	AMULHVU
   553  	AADDV
   554  	AADDVU
   555  	ASUBV
   556  	ASUBVU
   557  
   558  	// 64-bit FP
   559  	ATRUNCFV
   560  	ATRUNCDV
   561  	ATRUNCFW
   562  	ATRUNCDW
   563  
   564  	AMOVWU
   565  	AMOVFV
   566  	AMOVDV
   567  	AMOVVF
   568  	AMOVVD
   569  
   570  	// 2.2.1.8
   571  	AORN
   572  	AANDN
   573  
   574  	// 2.2.7. Atomic Memory Access Instructions
   575  	AAMSWAPB
   576  	AAMSWAPH
   577  	AAMSWAPW
   578  	AAMSWAPV
   579  	AAMCASB
   580  	AAMCASH
   581  	AAMCASW
   582  	AAMCASV
   583  	AAMADDW
   584  	AAMADDV
   585  	AAMANDW
   586  	AAMANDV
   587  	AAMORW
   588  	AAMORV
   589  	AAMXORW
   590  	AAMXORV
   591  	AAMMAXW
   592  	AAMMAXV
   593  	AAMMINW
   594  	AAMMINV
   595  	AAMMAXWU
   596  	AAMMAXVU
   597  	AAMMINWU
   598  	AAMMINVU
   599  	AAMSWAPDBB
   600  	AAMSWAPDBH
   601  	AAMSWAPDBW
   602  	AAMSWAPDBV
   603  	AAMCASDBB
   604  	AAMCASDBH
   605  	AAMCASDBW
   606  	AAMCASDBV
   607  	AAMADDDBW
   608  	AAMADDDBV
   609  	AAMANDDBW
   610  	AAMANDDBV
   611  	AAMORDBW
   612  	AAMORDBV
   613  	AAMXORDBW
   614  	AAMXORDBV
   615  	AAMMAXDBW
   616  	AAMMAXDBV
   617  	AAMMINDBW
   618  	AAMMINDBV
   619  	AAMMAXDBWU
   620  	AAMMAXDBVU
   621  	AAMMINDBWU
   622  	AAMMINDBVU
   623  
   624  	// 2.2.3.1
   625  	AEXTWB
   626  	AEXTWH
   627  
   628  	// 2.2.3.2
   629  	ACLOW
   630  	ACLOV
   631  	ACLZW
   632  	ACLZV
   633  	ACTOW
   634  	ACTOV
   635  	ACTZW
   636  	ACTZV
   637  
   638  	// 2.2.3.4
   639  	AREVBV
   640  	AREVB2W
   641  	AREVB4H
   642  	AREVB2H
   643  
   644  	// 2.2.3.5
   645  	AREVH2W
   646  	AREVHV
   647  
   648  	// 2.2.3.6
   649  	ABITREV4B
   650  	ABITREV8B
   651  
   652  	// 2.2.3.7
   653  	ABITREVW
   654  	ABITREVV
   655  
   656  	// 2.2.3.8
   657  	ABSTRINSW
   658  	ABSTRINSV
   659  
   660  	// 2.2.3.9
   661  	ABSTRPICKW
   662  	ABSTRPICKV
   663  
   664  	// 2.2.5.4. Prefetch Instructions
   665  	APRELD
   666  	APRELDX
   667  
   668  	// 2.2.9. CRC Check Instructions
   669  	ACRCWBW
   670  	ACRCWHW
   671  	ACRCWWW
   672  	ACRCWVW
   673  	ACRCCWBW
   674  	ACRCCWHW
   675  	ACRCCWWW
   676  	ACRCCWVW
   677  
   678  	// 2.2.10. Other Miscellaneous Instructions
   679  	ARDTIMELW
   680  	ARDTIMEHW
   681  	ARDTIMED
   682  	ACPUCFG
   683  
   684  	// 3.2.1.2
   685  	AFMADDF
   686  	AFMADDD
   687  	AFMSUBF
   688  	AFMSUBD
   689  	AFNMADDF
   690  	AFNMADDD
   691  	AFNMSUBF
   692  	AFNMSUBD
   693  
   694  	// 3.2.1.3
   695  	AFMINF
   696  	AFMIND
   697  	AFMAXF
   698  	AFMAXD
   699  
   700  	// 3.2.1.4
   701  	AFMAXAF
   702  	AFMAXAD
   703  	AFMINAF
   704  	AFMINAD
   705  
   706  	// 3.2.1.7
   707  	AFCOPYSGF
   708  	AFCOPYSGD
   709  	AFSCALEBF
   710  	AFSCALEBD
   711  	AFLOGBF
   712  	AFLOGBD
   713  
   714  	// 3.2.1.8
   715  	AFCLASSF
   716  	AFCLASSD
   717  
   718  	// 3.2.3.2
   719  	AFFINTFW
   720  	AFFINTFV
   721  	AFFINTDW
   722  	AFFINTDV
   723  	AFTINTWF
   724  	AFTINTWD
   725  	AFTINTVF
   726  	AFTINTVD
   727  
   728  	// 3.2.3.3
   729  	AFTINTRPWF
   730  	AFTINTRPWD
   731  	AFTINTRPVF
   732  	AFTINTRPVD
   733  	AFTINTRMWF
   734  	AFTINTRMWD
   735  	AFTINTRMVF
   736  	AFTINTRMVD
   737  	AFTINTRZWF
   738  	AFTINTRZWD
   739  	AFTINTRZVF
   740  	AFTINTRZVD
   741  	AFTINTRNEWF
   742  	AFTINTRNEWD
   743  	AFTINTRNEVF
   744  	AFTINTRNEVD
   745  
   746  	// LSX and LASX memory access instructions
   747  	AVMOVQ
   748  	AXVMOVQ
   749  
   750  	// LSX and LASX arithmetic instructions
   751  	AVADDB
   752  	AVADDH
   753  	AVADDW
   754  	AVADDV
   755  	AVADDQ
   756  	AXVADDB
   757  	AXVADDH
   758  	AXVADDW
   759  	AXVADDV
   760  	AXVADDQ
   761  	AVSUBB
   762  	AVSUBH
   763  	AVSUBW
   764  	AVSUBV
   765  	AVSUBQ
   766  	AXVSUBB
   767  	AXVSUBH
   768  	AXVSUBW
   769  	AXVSUBV
   770  	AXVSUBQ
   771  	AVADDBU
   772  	AVADDHU
   773  	AVADDWU
   774  	AVADDVU
   775  	AVSUBBU
   776  	AVSUBHU
   777  	AVSUBWU
   778  	AVSUBVU
   779  	AXVADDBU
   780  	AXVADDHU
   781  	AXVADDWU
   782  	AXVADDVU
   783  	AXVSUBBU
   784  	AXVSUBHU
   785  	AXVSUBWU
   786  	AXVSUBVU
   787  
   788  	// LSX and LASX Bit-manipulation Instructions
   789  	AVANDB
   790  	AVORB
   791  	AVXORB
   792  	AVNORB
   793  	AXVANDB
   794  	AXVORB
   795  	AXVXORB
   796  	AXVNORB
   797  	AVANDV
   798  	AVORV
   799  	AVXORV
   800  	AVNORV
   801  	AVANDNV
   802  	AVORNV
   803  	AXVANDV
   804  	AXVORV
   805  	AXVXORV
   806  	AXVNORV
   807  	AXVANDNV
   808  	AXVORNV
   809  
   810  	AVPCNTB
   811  	AVPCNTH
   812  	AVPCNTW
   813  	AVPCNTV
   814  	AXVPCNTB
   815  	AXVPCNTH
   816  	AXVPCNTW
   817  	AXVPCNTV
   818  
   819  	// LSX and LASX integer comparison instruction
   820  	AVSEQB
   821  	AXVSEQB
   822  	AVSEQH
   823  	AXVSEQH
   824  	AVSEQW
   825  	AXVSEQW
   826  	AVSEQV
   827  	AXVSEQV
   828  
   829  	// LSX and LASX integer div and mod instructions
   830  	AVDIVB
   831  	AVDIVH
   832  	AVDIVW
   833  	AVDIVV
   834  	AVDIVBU
   835  	AVDIVHU
   836  	AVDIVWU
   837  	AVDIVVU
   838  	AVMODB
   839  	AVMODH
   840  	AVMODW
   841  	AVMODV
   842  	AVMODBU
   843  	AVMODHU
   844  	AVMODWU
   845  	AVMODVU
   846  	AXVDIVB
   847  	AXVDIVH
   848  	AXVDIVW
   849  	AXVDIVV
   850  	AXVDIVBU
   851  	AXVDIVHU
   852  	AXVDIVWU
   853  	AXVDIVVU
   854  	AXVMODB
   855  	AXVMODH
   856  	AXVMODW
   857  	AXVMODV
   858  	AXVMODBU
   859  	AXVMODHU
   860  	AXVMODWU
   861  	AXVMODVU
   862  
   863  	// LSX and LASX shift operation instructions
   864  	AVSLLB
   865  	AVSLLH
   866  	AVSLLW
   867  	AVSLLV
   868  	AVSRLB
   869  	AVSRLH
   870  	AVSRLW
   871  	AVSRLV
   872  	AVSRAB
   873  	AVSRAH
   874  	AVSRAW
   875  	AVSRAV
   876  	AVROTRB
   877  	AVROTRH
   878  	AVROTRW
   879  	AVROTRV
   880  	AXVSLLB
   881  	AXVSLLH
   882  	AXVSLLW
   883  	AXVSLLV
   884  	AXVSRLB
   885  	AXVSRLH
   886  	AXVSRLW
   887  	AXVSRLV
   888  	AXVSRAB
   889  	AXVSRAH
   890  	AXVSRAW
   891  	AXVSRAV
   892  	AXVROTRB
   893  	AXVROTRH
   894  	AXVROTRW
   895  	AXVROTRV
   896  
   897  	// LSX and LASX move and shuffle instructions
   898  	AVILVLB
   899  	AVILVLH
   900  	AVILVLW
   901  	AVILVLV
   902  	AVILVHB
   903  	AVILVHH
   904  	AVILVHW
   905  	AVILVHV
   906  	AXVILVLB
   907  	AXVILVLH
   908  	AXVILVLW
   909  	AXVILVLV
   910  	AXVILVHB
   911  	AXVILVHH
   912  	AXVILVHW
   913  	AXVILVHV
   914  
   915  	// LSX and LASX integer mul instructions
   916  	AVMULB
   917  	AVMULH
   918  	AVMULW
   919  	AVMULV
   920  	AVMUHB
   921  	AVMUHH
   922  	AVMUHW
   923  	AVMUHV
   924  	AVMUHBU
   925  	AVMUHHU
   926  	AVMUHWU
   927  	AVMUHVU
   928  	AXVMULB
   929  	AXVMULH
   930  	AXVMULW
   931  	AXVMULV
   932  	AXVMUHB
   933  	AXVMUHH
   934  	AXVMUHW
   935  	AXVMUHV
   936  	AXVMUHBU
   937  	AXVMUHHU
   938  	AXVMUHWU
   939  	AXVMUHVU
   940  
   941  	// LSX and LASX floating point instructions
   942  	AVFSQRTF
   943  	AVFSQRTD
   944  	AVFRECIPF
   945  	AVFRECIPD
   946  	AVFRSQRTF
   947  	AVFRSQRTD
   948  	AXVFSQRTF
   949  	AXVFSQRTD
   950  	AXVFRECIPF
   951  	AXVFRECIPD
   952  	AXVFRSQRTF
   953  	AXVFRSQRTD
   954  
   955  	AVADDF
   956  	AVADDD
   957  	AVSUBF
   958  	AVSUBD
   959  	AVMULF
   960  	AVMULD
   961  	AVDIVF
   962  	AVDIVD
   963  	AXVADDF
   964  	AXVADDD
   965  	AXVSUBF
   966  	AXVSUBD
   967  	AXVMULF
   968  	AXVMULD
   969  	AXVDIVF
   970  	AXVDIVD
   971  
   972  	AVFCLASSF
   973  	AVFCLASSD
   974  	AXVFCLASSF
   975  	AXVFCLASSD
   976  
   977  	// LSX and LASX floating point conversion instructions
   978  	AVFRINTRNEF
   979  	AVFRINTRNED
   980  	AVFRINTRZF
   981  	AVFRINTRZD
   982  	AVFRINTRPF
   983  	AVFRINTRPD
   984  	AVFRINTRMF
   985  	AVFRINTRMD
   986  	AVFRINTF
   987  	AVFRINTD
   988  	AXVFRINTRNEF
   989  	AXVFRINTRNED
   990  	AXVFRINTRZF
   991  	AXVFRINTRZD
   992  	AXVFRINTRPF
   993  	AXVFRINTRPD
   994  	AXVFRINTRMF
   995  	AXVFRINTRMD
   996  	AXVFRINTF
   997  	AXVFRINTD
   998  
   999  	// LSX and LASX integer neg instructions
  1000  	AVNEGB
  1001  	AVNEGH
  1002  	AVNEGW
  1003  	AVNEGV
  1004  	AXVNEGB
  1005  	AXVNEGH
  1006  	AXVNEGW
  1007  	AXVNEGV
  1008  
  1009  	// LSX and LASX mul instructions that operate on even or odd positions
  1010  	AVMULWEVHB
  1011  	AVMULWEVWH
  1012  	AVMULWEVVW
  1013  	AVMULWEVQV
  1014  	AVMULWODHB
  1015  	AVMULWODWH
  1016  	AVMULWODVW
  1017  	AVMULWODQV
  1018  	AVMULWEVHBU
  1019  	AVMULWEVWHU
  1020  	AVMULWEVVWU
  1021  	AVMULWEVQVU
  1022  	AVMULWODHBU
  1023  	AVMULWODWHU
  1024  	AVMULWODVWU
  1025  	AVMULWODQVU
  1026  	AXVMULWEVHB
  1027  	AXVMULWEVWH
  1028  	AXVMULWEVVW
  1029  	AXVMULWEVQV
  1030  	AXVMULWODHB
  1031  	AXVMULWODWH
  1032  	AXVMULWODVW
  1033  	AXVMULWODQV
  1034  	AXVMULWEVHBU
  1035  	AXVMULWEVWHU
  1036  	AXVMULWEVVWU
  1037  	AXVMULWEVQVU
  1038  	AXVMULWODHBU
  1039  	AXVMULWODWHU
  1040  	AXVMULWODVWU
  1041  	AXVMULWODQVU
  1042  	AVMULWEVHBUB
  1043  	AVMULWEVWHUH
  1044  	AVMULWEVVWUW
  1045  	AVMULWEVQVUV
  1046  	AVMULWODHBUB
  1047  	AVMULWODWHUH
  1048  	AVMULWODVWUW
  1049  	AVMULWODQVUV
  1050  	AXVMULWEVHBUB
  1051  	AXVMULWEVWHUH
  1052  	AXVMULWEVVWUW
  1053  	AXVMULWEVQVUV
  1054  	AXVMULWODHBUB
  1055  	AXVMULWODWHUH
  1056  	AXVMULWODVWUW
  1057  	AXVMULWODQVUV
  1058  
  1059  	AVSHUF4IB
  1060  	AVSHUF4IH
  1061  	AVSHUF4IW
  1062  	AVSHUF4IV
  1063  	AXVSHUF4IB
  1064  	AXVSHUF4IH
  1065  	AXVSHUF4IW
  1066  	AXVSHUF4IV
  1067  
  1068  	AVSETEQV
  1069  	AVSETNEV
  1070  	AVSETANYEQB
  1071  	AVSETANYEQH
  1072  	AVSETANYEQW
  1073  	AVSETANYEQV
  1074  	AVSETALLNEB
  1075  	AVSETALLNEH
  1076  	AVSETALLNEW
  1077  	AVSETALLNEV
  1078  	AXVSETEQV
  1079  	AXVSETNEV
  1080  	AXVSETANYEQB
  1081  	AXVSETANYEQH
  1082  	AXVSETANYEQW
  1083  	AXVSETANYEQV
  1084  	AXVSETALLNEB
  1085  	AXVSETALLNEH
  1086  	AXVSETALLNEW
  1087  	AXVSETALLNEV
  1088  
  1089  	ALAST
  1090  
  1091  	// aliases
  1092  	AJMP = obj.AJMP
  1093  	AJAL = obj.ACALL
  1094  	ARET = obj.ARET
  1095  )
  1096  
  1097  func init() {
  1098  	// The asm encoder generally assumes that the lowest 5 bits of the
  1099  	// REG_XX constants match the machine instruction encoding, i.e.
  1100  	// the lowest 5 bits is the register number.
  1101  	// Check this here.
  1102  	if REG_R0%32 != 0 {
  1103  		panic("REG_R0 is not a multiple of 32")
  1104  	}
  1105  	if REG_F0%32 != 0 {
  1106  		panic("REG_F0 is not a multiple of 32")
  1107  	}
  1108  	if REG_FCSR0%32 != 0 {
  1109  		panic("REG_FCSR0 is not a multiple of 32")
  1110  	}
  1111  	if REG_FCC0%32 != 0 {
  1112  		panic("REG_FCC0 is not a multiple of 32")
  1113  	}
  1114  	if REG_V0%32 != 0 {
  1115  		panic("REG_V0 is not a multiple of 32")
  1116  	}
  1117  	if REG_X0%32 != 0 {
  1118  		panic("REG_X0 is not a multiple of 32")
  1119  	}
  1120  }
  1121
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