list.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  	"fmt"
    10  )
    11  
    12  func init() {
    13  	obj.RegisterRegister(obj.RBaseLOONG64, REG_LAST, rconv)
    14  	obj.RegisterOpcode(obj.ABaseLoong64, Anames)
    15  }
    16  
    17  func arrange(a int16) string {
    18  	switch a {
    19  	case ARNG_32B:
    20  		return "B32"
    21  	case ARNG_16H:
    22  		return "H16"
    23  	case ARNG_8W:
    24  		return "W8"
    25  	case ARNG_4V:
    26  		return "V4"
    27  	case ARNG_2Q:
    28  		return "Q2"
    29  	case ARNG_16B:
    30  		return "B16"
    31  	case ARNG_8H:
    32  		return "H8"
    33  	case ARNG_4W:
    34  		return "W4"
    35  	case ARNG_2V:
    36  		return "V2"
    37  	case ARNG_B:
    38  		return "B"
    39  	case ARNG_H:
    40  		return "H"
    41  	case ARNG_W:
    42  		return "W"
    43  	case ARNG_V:
    44  		return "V"
    45  	case ARNG_BU:
    46  		return "BU"
    47  	case ARNG_HU:
    48  		return "HU"
    49  	case ARNG_WU:
    50  		return "WU"
    51  	case ARNG_VU:
    52  		return "VU"
    53  	default:
    54  		return "ARNG_???"
    55  	}
    56  }
    57  
    58  func rconv(r int) string {
    59  	switch {
    60  	case r == 0:
    61  		return "NONE"
    62  	case r == REGG:
    63  		// Special case.
    64  		return "g"
    65  	case REG_R0 <= r && r <= REG_R31:
    66  		return fmt.Sprintf("R%d", r-REG_R0)
    67  	case REG_F0 <= r && r <= REG_F31:
    68  		return fmt.Sprintf("F%d", r-REG_F0)
    69  	case REG_FCSR0 <= r && r <= REG_FCSR31:
    70  		return fmt.Sprintf("FCSR%d", r-REG_FCSR0)
    71  	case REG_FCC0 <= r && r <= REG_FCC31:
    72  		return fmt.Sprintf("FCC%d", r-REG_FCC0)
    73  	case REG_V0 <= r && r <= REG_V31:
    74  		return fmt.Sprintf("V%d", r-REG_V0)
    75  	case REG_X0 <= r && r <= REG_X31:
    76  		return fmt.Sprintf("X%d", r-REG_X0)
    77  	}
    78  
    79  	// bits 0-4 indicates register: Vn or Xn
    80  	// bits 5-9 indicates arrangement: <T>
    81  	// bits 10 indicates SMID type: 0: LSX, 1: LASX
    82  	simd_type := (int16(r) >> EXT_SIMDTYPE_SHIFT) & EXT_SIMDTYPE_MASK
    83  	reg_num := (int16(r) >> EXT_REG_SHIFT) & EXT_REG_MASK
    84  	arng_type := (int16(r) >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
    85  	reg_prefix := "#"
    86  	switch simd_type {
    87  	case LSX:
    88  		reg_prefix = "V"
    89  	case LASX:
    90  		reg_prefix = "X"
    91  	}
    92  
    93  	switch {
    94  	case REG_ARNG <= r && r < REG_ELEM:
    95  		return fmt.Sprintf("%s%d.%s", reg_prefix, reg_num, arrange(arng_type))
    96  
    97  	case REG_ELEM <= r && r < REG_ELEM_END:
    98  		return fmt.Sprintf("%s%d.%s", reg_prefix, reg_num, arrange(arng_type))
    99  	}
   100  
   101  	return fmt.Sprintf("badreg(%d)", r-obj.RBaseLOONG64)
   102  }
   103  
   104  func DRconv(a int) string {
   105  	s := "C_??"
   106  	if a >= C_NONE && a <= C_NCLASS {
   107  		s = cnames0[a]
   108  	}
   109  	return s
   110  }
   111
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