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30 package ppc64
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "encoding/binary"
36 "fmt"
37 "internal/buildcfg"
38 "log"
39 "math"
40 "math/bits"
41 "sort"
42 )
43
44
45
46
47 type ctxt9 struct {
48 ctxt *obj.Link
49 newprog obj.ProgAlloc
50 cursym *obj.LSym
51 autosize int32
52 instoffset int64
53 pc int64
54 }
55
56
57
58 const (
59 r0iszero = 1
60 )
61
62 const (
63
64 PFX_R_ABS = 0
65 PFX_R_PCREL = 1
66 )
67
68 const (
69
70 NOP = 0x60000000
71 )
72
73 type Optab struct {
74 as obj.As
75 a1 uint8
76 a2 uint8
77 a3 uint8
78 a4 uint8
79 a5 uint8
80 a6 uint8
81 type_ int8
82 size int8
83
84
85
86
87
88 ispfx bool
89
90 asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32)
91 }
92
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107
108
109 var optab []Optab
110
111 var optabBase = []Optab{
112 {as: obj.ATEXT, a1: C_LOREG, a6: C_TEXTSIZE, type_: 0, size: 0},
113 {as: obj.ATEXT, a1: C_LOREG, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
114 {as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE, type_: 0, size: 0},
115 {as: obj.ATEXT, a1: C_ADDR, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
116
117 {as: AADD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
118 {as: AADD, a1: C_REG, a6: C_REG, type_: 2, size: 4},
119 {as: AADD, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
120 {as: AADD, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
121 {as: AADD, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 22, size: 8},
122 {as: AADD, a1: C_U16CON, a6: C_REG, type_: 22, size: 8},
123 {as: AADDIS, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 20, size: 4},
124 {as: AADDIS, a1: C_S16CON, a6: C_REG, type_: 20, size: 4},
125 {as: AADDC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
126 {as: AADDC, a1: C_REG, a6: C_REG, type_: 2, size: 4},
127 {as: AADDC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
128 {as: AADDC, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
129 {as: AADDC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
130 {as: AADDC, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
131 {as: AAND, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
132 {as: AAND, a1: C_REG, a6: C_REG, type_: 6, size: 4},
133 {as: AANDCC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
134 {as: AANDCC, a1: C_REG, a6: C_REG, type_: 6, size: 4},
135 {as: AANDCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
136 {as: AANDCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
137 {as: AANDCC, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
138 {as: AANDCC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
139 {as: AANDCC, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
140 {as: AANDCC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
141 {as: AANDISCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
142 {as: AANDISCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
143 {as: AMULLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
144 {as: AMULLW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
145 {as: AMULLW, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
146 {as: AMULLW, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
147 {as: AMULLW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
148 {as: AMULLW, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
149 {as: ASUBC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
150 {as: ASUBC, a1: C_REG, a6: C_REG, type_: 10, size: 4},
151 {as: ASUBC, a1: C_REG, a3: C_S16CON, a6: C_REG, type_: 27, size: 4},
152 {as: ASUBC, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 28, size: 12},
153 {as: AOR, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
154 {as: AOR, a1: C_REG, a6: C_REG, type_: 6, size: 4},
155 {as: AOR, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
156 {as: AOR, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
157 {as: AOR, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
158 {as: AOR, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
159 {as: AOR, a1: C_U32CON, a2: C_REG, a6: C_REG, type_: 21, size: 8},
160 {as: AOR, a1: C_U32CON, a6: C_REG, type_: 21, size: 8},
161 {as: AOR, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
162 {as: AOR, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
163 {as: AORIS, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
164 {as: AORIS, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
165 {as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
166 {as: ADIVW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
167 {as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
168 {as: ASUB, a1: C_REG, a6: C_REG, type_: 10, size: 4},
169 {as: ASLW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
170 {as: ASLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
171 {as: ASLD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
172 {as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
173 {as: ASLD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
174 {as: ASLD, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
175 {as: AEXTSWSLI, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
176 {as: AEXTSWSLI, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
177 {as: ASLW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 57, size: 4},
178 {as: ASLW, a1: C_U15CON, a6: C_REG, type_: 57, size: 4},
179 {as: ASRAW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
180 {as: ASRAW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
181 {as: ASRAW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
182 {as: ASRAW, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
183 {as: ASRAD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
184 {as: ASRAD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
185 {as: ASRAD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
186 {as: ASRAD, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
187 {as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
188 {as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
189 {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
190 {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
191 {as: ACLRLSLWI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 62, size: 4},
192 {as: ARLDMI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 30, size: 4},
193 {as: ARLDC, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
194 {as: ARLDC, a1: C_REG, a3: C_U8CON, a4: C_U8CON, a6: C_REG, type_: 9, size: 4},
195 {as: ARLDCL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
196 {as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
197 {as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
198 {as: ARLDICL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
199 {as: ARLDCL, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
200 {as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4},
201 {as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4},
202 {as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
203 {as: AFABS, a6: C_FREG, type_: 33, size: 4},
204 {as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4},
205 {as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4},
206 {as: AFMUL, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 32, size: 4},
207
208 {as: AMOVBU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
209 {as: AMOVBU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
210 {as: AMOVBU, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
211 {as: AMOVBU, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
212
213 {as: AMOVBZU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
214 {as: AMOVBZU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
215 {as: AMOVBZU, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
216 {as: AMOVBZU, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
217
218 {as: AMOVHBR, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
219 {as: AMOVHBR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
220
221 {as: AMOVB, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
222 {as: AMOVB, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
223 {as: AMOVB, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
224 {as: AMOVB, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
225 {as: AMOVB, a1: C_REG, a6: C_REG, type_: 13, size: 4},
226
227 {as: AMOVBZ, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
228 {as: AMOVBZ, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
229 {as: AMOVBZ, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
230 {as: AMOVBZ, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
231 {as: AMOVBZ, a1: C_REG, a6: C_REG, type_: 13, size: 4},
232
233 {as: AMOVD, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
234 {as: AMOVD, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
235 {as: AMOVD, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
236 {as: AMOVD, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
237 {as: AMOVD, a1: C_SOREG, a6: C_SPR, type_: 107, size: 8},
238 {as: AMOVD, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
239 {as: AMOVD, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
240 {as: AMOVD, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
241 {as: AMOVD, a1: C_SPR, a6: C_SOREG, type_: 106, size: 8},
242 {as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
243 {as: AMOVD, a1: C_REG, a6: C_REG, type_: 13, size: 4},
244
245 {as: AMOVW, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
246 {as: AMOVW, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
247 {as: AMOVW, a1: C_CREG, a6: C_REG, type_: 68, size: 4},
248 {as: AMOVW, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
249 {as: AMOVW, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
250 {as: AMOVW, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
251 {as: AMOVW, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
252 {as: AMOVW, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
253 {as: AMOVW, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
254 {as: AMOVW, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
255 {as: AMOVW, a1: C_REG, a6: C_REG, type_: 13, size: 4},
256
257 {as: AFMOVD, a1: C_S16CON, a6: C_FREG, type_: 24, size: 8},
258 {as: AFMOVD, a1: C_SOREG, a6: C_FREG, type_: 8, size: 4},
259 {as: AFMOVD, a1: C_XOREG, a6: C_FREG, type_: 109, size: 4},
260 {as: AFMOVD, a1: C_ZCON, a6: C_FREG, type_: 24, size: 4},
261 {as: AFMOVD, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
262 {as: AFMOVD, a1: C_FREG, a6: C_SOREG, type_: 7, size: 4},
263 {as: AFMOVD, a1: C_FREG, a6: C_XOREG, type_: 108, size: 4},
264
265 {as: AFMOVSX, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
266 {as: AFMOVSX, a1: C_FREG, a6: C_XOREG, type_: 44, size: 4},
267
268 {as: AFMOVSZ, a1: C_ZOREG, a6: C_FREG, type_: 45, size: 4},
269 {as: AFMOVSZ, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
270
271 {as: AMOVFL, a1: C_CREG, a6: C_CREG, type_: 67, size: 4},
272 {as: AMOVFL, a1: C_FPSCR, a6: C_CREG, type_: 73, size: 4},
273 {as: AMOVFL, a1: C_FPSCR, a6: C_FREG, type_: 53, size: 4},
274 {as: AMOVFL, a1: C_FREG, a3: C_32CON, a6: C_FPSCR, type_: 64, size: 4},
275 {as: AMOVFL, a1: C_FREG, a6: C_FPSCR, type_: 64, size: 4},
276 {as: AMOVFL, a1: C_32CON, a6: C_FPSCR, type_: 65, size: 4},
277 {as: AMOVFL, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
278 {as: AMOVFL, a1: C_REG, a6: C_32CON, type_: 69, size: 4},
279
280 {as: ASYSCALL, type_: 5, size: 4},
281 {as: ASYSCALL, a1: C_REG, type_: 77, size: 12},
282 {as: ASYSCALL, a1: C_U15CON, type_: 77, size: 12},
283 {as: ABEQ, a6: C_BRA, type_: 16, size: 4},
284 {as: ABEQ, a1: C_CREG, a6: C_BRA, type_: 16, size: 4},
285 {as: ABEQ, a1: C_CREG, a6: C_LR, type_: 17, size: 4},
286 {as: ABR, a6: C_BRA, type_: 11, size: 4},
287 {as: ABR, a6: C_BRAPIC, type_: 11, size: 8},
288 {as: ABR, a6: C_LR, type_: 18, size: 4},
289 {as: ABR, a6: C_CTR, type_: 18, size: 4},
290 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_BRA, type_: 16, size: 4},
291 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_LR, type_: 18, size: 4},
292 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a3: C_U15CON, a6: C_LR, type_: 18, size: 4},
293 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_CTR, type_: 18, size: 4},
294 {as: ABDNZ, a6: C_BRA, type_: 16, size: 4},
295 {as: ASYNC, type_: 46, size: 4},
296 {as: AWORD, a1: C_32CON, type_: 40, size: 4},
297 {as: ADWORD, a1: C_64CON, type_: 31, size: 8},
298 {as: ADWORD, a1: C_LACON, type_: 31, size: 8},
299 {as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4},
300 {as: AEXTSB, a1: C_REG, a6: C_REG, type_: 48, size: 4},
301 {as: AEXTSB, a6: C_REG, type_: 48, size: 4},
302 {as: AISEL, a1: C_U5CON, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
303 {as: AISEL, a1: C_CRBIT, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
304 {as: ANEG, a1: C_REG, a6: C_REG, type_: 47, size: 4},
305 {as: ANEG, a6: C_REG, type_: 47, size: 4},
306 {as: AREM, a1: C_REG, a6: C_REG, type_: 50, size: 12},
307 {as: AREM, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 12},
308 {as: AREMU, a1: C_REG, a6: C_REG, type_: 50, size: 16},
309 {as: AREMU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 16},
310 {as: AREMD, a1: C_REG, a6: C_REG, type_: 51, size: 12},
311 {as: AREMD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 51, size: 12},
312 {as: AMTFSB0, a1: C_U15CON, type_: 52, size: 4},
313
314 {as: APOPCNTD, a1: C_REG, a6: C_REG, type_: 93, size: 4},
315 {as: ACMPB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 92, size: 4},
316 {as: ACMPEQB, a1: C_REG, a2: C_REG, a6: C_CREG, type_: 92, size: 4},
317 {as: ACMPEQB, a1: C_REG, a6: C_REG, type_: 70, size: 4},
318 {as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_U15CON, type_: 92, size: 4},
319 {as: AFTSQRT, a1: C_FREG, a6: C_U15CON, type_: 93, size: 4},
320 {as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4},
321 {as: ADARN, a1: C_U15CON, a6: C_REG, type_: 92, size: 4},
322 {as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4},
323 {as: AADDEX, a1: C_REG, a2: C_REG, a3: C_U15CON, a6: C_REG, type_: 94, size: 4},
324 {as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4},
325
326
327 {as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4},
328 {as: AVCLZLSBB, a1: C_VREG, a6: C_REG, type_: 85, size: 4},
329
330
331
332
333 {as: ALVEBX, a1: C_XOREG, a6: C_VREG, type_: 45, size: 4},
334
335
336 {as: ASTVEBX, a1: C_VREG, a6: C_XOREG, type_: 44, size: 4},
337
338
339 {as: AVAND, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
340 {as: AVOR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
341
342
343 {as: AVADDUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
344 {as: AVADDCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
345 {as: AVADDUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
346 {as: AVADDSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
347 {as: AVADDE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
348
349
350 {as: AVSUBUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
351 {as: AVSUBCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
352 {as: AVSUBUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
353 {as: AVSUBSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
354 {as: AVSUBE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
355
356
357 {as: AVMULESB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
358 {as: AVPMSUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
359 {as: AVMSUMUDM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
360
361
362 {as: AVR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
363
364
365 {as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
366 {as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
367 {as: AVSOI, a1: C_U16CON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
368
369
370 {as: AVCLZ, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
371 {as: AVPOPCNT, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
372
373
374 {as: AVCMPEQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
375 {as: AVCMPGT, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
376 {as: AVCMPNEZB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
377
378
379 {as: AVMRGOW, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
380
381
382 {as: AVPERM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
383
384
385 {as: AVBPERMQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
386
387
388 {as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
389
390
391 {as: AVSPLTB, a1: C_S16CON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
392 {as: AVSPLTISB, a1: C_S16CON, a6: C_VREG, type_: 82, size: 4},
393
394
395 {as: AVCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
396 {as: AVNCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
397 {as: AVSBOX, a1: C_VREG, a6: C_VREG, type_: 82, size: 4},
398
399
400 {as: AVSHASIGMA, a1: C_U16CON, a2: C_VREG, a3: C_U16CON, a6: C_VREG, type_: 82, size: 4},
401
402
403 {as: ALXVD2X, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
404 {as: ALXV, a1: C_SOREG, a6: C_VSREG, type_: 96, size: 4},
405 {as: ALXVL, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 98, size: 4},
406
407
408 {as: ASTXVD2X, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
409 {as: ASTXV, a1: C_VSREG, a6: C_SOREG, type_: 97, size: 4},
410 {as: ASTXVL, a1: C_VSREG, a2: C_REG, a6: C_REG, type_: 99, size: 4},
411
412
413 {as: ALXSDX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
414
415
416 {as: ASTXSDX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
417
418
419 {as: ALXSIWAX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
420
421
422 {as: ASTXSIWX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
423
424
425 {as: AMFVSRD, a1: C_VSREG, a6: C_REG, type_: 88, size: 4},
426 {as: AMFVSRD, a1: C_FREG, a6: C_REG, type_: 88, size: 4},
427
428
429 {as: AMTVSRD, a1: C_REG, a6: C_VSREG, type_: 104, size: 4},
430 {as: AMTVSRD, a1: C_REG, a6: C_FREG, type_: 104, size: 4},
431 {as: AMTVSRDD, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 104, size: 4},
432
433
434 {as: AXXLAND, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 90, size: 4},
435 {as: AXXLAND, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
436
437
438 {as: AXXSEL, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a6: C_VSREG, type_: 91, size: 4},
439
440
441 {as: AXXMRGHW, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
442
443
444 {as: AXXSPLTW, a1: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 89, size: 4},
445 {as: AXXSPLTIB, a1: C_U15CON, a6: C_VSREG, type_: 100, size: 4},
446
447
448 {as: AXXPERM, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
449
450
451 {as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 90, size: 4},
452
453
454 {as: AXXBRQ, a1: C_VSREG, a6: C_VSREG, type_: 101, size: 4},
455
456
457 {as: AXSCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
458
459
460 {as: AXVCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
461
462
463 {as: AXSCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
464
465
466 {as: AXSCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
467
468
469 {as: AXVCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
470
471
472 {as: AXVCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
473
474 {as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4},
475 {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
476 {as: ACMP, a1: C_REG, a6: C_S16CON, type_: 70, size: 4},
477 {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_S16CON, type_: 70, size: 4},
478 {as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4},
479 {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
480 {as: ACMPU, a1: C_REG, a6: C_U16CON, type_: 70, size: 4},
481 {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_U16CON, type_: 70, size: 4},
482 {as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4},
483 {as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4},
484 {as: ATW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 60, size: 4},
485 {as: ATW, a1: C_32CON, a2: C_REG, a6: C_S16CON, type_: 61, size: 4},
486 {as: ADCBF, a1: C_SOREG, type_: 43, size: 4},
487 {as: ADCBF, a1: C_XOREG, type_: 43, size: 4},
488 {as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_U15CON, type_: 43, size: 4},
489 {as: ADCBF, a1: C_SOREG, a6: C_U15CON, type_: 43, size: 4},
490 {as: ADCBF, a1: C_XOREG, a6: C_U15CON, type_: 43, size: 4},
491 {as: ASTDCCC, a1: C_REG, a2: C_REG, a6: C_XOREG, type_: 44, size: 4},
492 {as: ASTDCCC, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
493 {as: ALDAR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
494 {as: ALDAR, a1: C_XOREG, a3: C_U16CON, a6: C_REG, type_: 45, size: 4},
495 {as: AEIEIO, type_: 46, size: 4},
496 {as: ATLBIE, a1: C_REG, type_: 49, size: 4},
497 {as: ATLBIE, a1: C_U15CON, a6: C_REG, type_: 49, size: 4},
498 {as: ASLBMFEE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
499 {as: ASLBMTE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
500 {as: ASTSW, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
501 {as: ASTSW, a1: C_REG, a3: C_32CON, a6: C_ZOREG, type_: 41, size: 4},
502 {as: ALSW, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
503 {as: ALSW, a1: C_ZOREG, a3: C_32CON, a6: C_REG, type_: 42, size: 4},
504
505 {as: obj.AUNDEF, type_: 78, size: 4},
506 {as: obj.APCDATA, a1: C_32CON, a6: C_32CON, type_: 0, size: 0},
507 {as: obj.AFUNCDATA, a1: C_U15CON, a6: C_ADDR, type_: 0, size: 0},
508 {as: obj.ANOP, type_: 0, size: 0},
509 {as: obj.ANOP, a1: C_32CON, type_: 0, size: 0},
510 {as: obj.ANOP, a1: C_REG, type_: 0, size: 0},
511 {as: obj.ANOP, a1: C_FREG, type_: 0, size: 0},
512 {as: obj.ADUFFZERO, a6: C_BRA, type_: 11, size: 4},
513 {as: obj.ADUFFCOPY, a6: C_BRA, type_: 11, size: 4},
514 {as: obj.APCALIGN, a1: C_32CON, type_: 0, size: 0},
515 }
516
517
518
519 type PrefixableOptab struct {
520 Optab
521 minGOPPC64 int
522 pfxsize int8
523 }
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539 var prefixableOptab = []PrefixableOptab{
540 {Optab: Optab{as: AMOVD, a1: C_S34CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
541 {Optab: Optab{as: AMOVD, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
542 {Optab: Optab{as: AMOVD, a1: C_TLS_LE, a6: C_REG, type_: 79, size: 8}, minGOPPC64: 10, pfxsize: 8},
543 {Optab: Optab{as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 12}, minGOPPC64: 10, pfxsize: 12},
544 {Optab: Optab{as: AMOVD, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
545 {Optab: Optab{as: AMOVD, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
546 {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
547 {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
548
549 {Optab: Optab{as: AMOVW, a1: C_32CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
550 {Optab: Optab{as: AMOVW, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
551 {Optab: Optab{as: AMOVW, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
552 {Optab: Optab{as: AMOVW, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
553 {Optab: Optab{as: AMOVW, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
554 {Optab: Optab{as: AMOVW, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
555
556 {Optab: Optab{as: AMOVB, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
557 {Optab: Optab{as: AMOVB, a1: C_LOREG, a6: C_REG, type_: 36, size: 12}, minGOPPC64: 10, pfxsize: 12},
558 {Optab: Optab{as: AMOVB, a1: C_ADDR, a6: C_REG, type_: 75, size: 12}, minGOPPC64: 10, pfxsize: 12},
559 {Optab: Optab{as: AMOVB, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
560
561 {Optab: Optab{as: AMOVBZ, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
562 {Optab: Optab{as: AMOVBZ, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
563 {Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
564 {Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
565
566 {Optab: Optab{as: AFMOVD, a1: C_LOREG, a6: C_FREG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
567 {Optab: Optab{as: AFMOVD, a1: C_ADDR, a6: C_FREG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
568 {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
569 {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
570
571 {Optab: Optab{as: AADD, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
572 {Optab: Optab{as: AADD, a1: C_32CON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
573 {Optab: Optab{as: AADD, a1: C_S34CON, a2: C_REG, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
574 {Optab: Optab{as: AADD, a1: C_S34CON, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
575 }
576
577 var oprange [ALAST & obj.AMask][]Optab
578
579 var xcmp [C_NCLASS][C_NCLASS]bool
580
581 var pfxEnabled = false
582 var buildOpCfg = ""
583
584
585 func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
586 switch a {
587 case 8, 16, 32, 64:
588
589
590
591
592 if ctxt.Headtype != objabi.Haix && cursym.Func().Align < int32(a) {
593 cursym.Func().Align = int32(a)
594 }
595 if pc&(a-1) != 0 {
596 return int(a - (pc & (a - 1)))
597 }
598 default:
599 ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
600 }
601 return 0
602 }
603
604 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
605 p := cursym.Func().Text
606 if p == nil || p.Link == nil {
607 return
608 }
609
610 if oprange[AANDN&obj.AMask] == nil {
611 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
612 }
613
614 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
615
616 pc := int64(0)
617 p.Pc = pc
618
619 var m int
620 var o *Optab
621 for p = p.Link; p != nil; p = p.Link {
622 p.Pc = pc
623 o = c.oplook(p)
624 m = int(o.size)
625 if m == 0 {
626 if p.As == obj.APCALIGN {
627 a := c.vregoff(&p.From)
628 m = addpad(pc, a, ctxt, cursym)
629 } else {
630 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
631 ctxt.Diag("zero-width instruction\n%v", p)
632 }
633 continue
634 }
635 }
636 pc += int64(m)
637 }
638
639 c.cursym.Size = pc
640
641
647 bflag := 1
648
649 var otxt int64
650 var q *obj.Prog
651 var out [5]uint32
652 var falign int32
653 for bflag != 0 {
654 bflag = 0
655 pc = 0
656 falign = 0
657 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
658 p.Pc = pc
659 o = c.oplook(p)
660
661
662 if (o.type_ == 16 || o.type_ == 17) && p.To.Target() != nil {
663 otxt = p.To.Target().Pc - pc
664 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
665
666
667
668 tgt := p.To.Target()
669 p.To.SetTarget(p.Link)
670 o.asmout(&c, p, o, &out)
671 p.To.SetTarget(tgt)
672
673 bo := int64(out[0]>>21) & 31
674 bi := int16((out[0] >> 16) & 31)
675 invertible := false
676
677 if bo&0x14 == 0x14 {
678
679 } else if bo&0x10 == 0x10 {
680
681 bo ^= 0x2
682 invertible = true
683 } else if bo&0x04 == 0x04 {
684
685 bo ^= 0x8
686 invertible = true
687 }
688
689 if invertible {
690
691
692
693
694
695
696
697
698 p.As = ABC
699 p.From = obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: bo}
700 q = c.newprog()
701 q.As = ABR
702 q.To.Type = obj.TYPE_BRANCH
703 q.To.SetTarget(p.To.Target())
704 q.Link = p.Link
705 p.To.SetTarget(p.Link)
706 p.Link = q
707 p.Reg = REG_CRBIT0 + bi
708 } else {
709
710
711
712
713
714
715
716
717
718
719 q = c.newprog()
720 q.Link = p.Link
721 p.Link = q
722 q.As = ABR
723 q.To.Type = obj.TYPE_BRANCH
724 q.To.SetTarget(p.To.Target())
725 p.To.SetTarget(q)
726 q = c.newprog()
727 q.Link = p.Link
728 p.Link = q
729 q.As = ABR
730 q.To.Type = obj.TYPE_BRANCH
731 q.To.SetTarget(q.Link.Link)
732 }
733 bflag = 1
734 }
735 }
736
737 m = int(o.size)
738 if m == 0 {
739 if p.As == obj.APCALIGN {
740 a := c.vregoff(&p.From)
741 m = addpad(pc, a, ctxt, cursym)
742 } else {
743 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
744 ctxt.Diag("zero-width instruction\n%v", p)
745 }
746 continue
747 }
748 }
749
750
751
752
753 if o.ispfx {
754 mark := p.Mark &^ PFX_X64B
755 if pc&63 == 60 {
756 p.Pc += 4
757 m += 4
758 mark |= PFX_X64B
759 }
760
761
762
763
764
765
766 if mark != p.Mark {
767 bflag = 1
768 p.Mark = mark
769 }
770
771
772
773
774
775
776 switch p.Pc & 31 {
777 case 28:
778 falign = 64
779 case 12:
780 if falign < 64 {
781 falign = 32
782 }
783 }
784 }
785
786 pc += int64(m)
787 }
788
789 c.cursym.Size = pc
790 }
791
792 c.cursym.Size = pc
793 c.cursym.Func().Align = falign
794 c.cursym.Grow(c.cursym.Size)
795
796
797
798 bp := c.cursym.P
799 var i int32
800 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
801 c.pc = p.Pc
802 o = c.oplook(p)
803 if int(o.size) > 4*len(out) {
804 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
805 }
806
807 if o.type_ == 0 && p.As == obj.APCALIGN {
808 aln := c.vregoff(&p.From)
809 v := addpad(p.Pc, aln, c.ctxt, c.cursym)
810 if v > 0 {
811
812 for i = 0; i < int32(v/4); i++ {
813 c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
814 bp = bp[4:]
815 }
816 }
817 } else {
818 if p.Mark&PFX_X64B != 0 {
819 c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
820 bp = bp[4:]
821 }
822 o.asmout(&c, p, o, &out)
823 for i = 0; i < int32(o.size/4); i++ {
824 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
825 bp = bp[4:]
826 }
827 }
828 }
829 }
830
831 func isint32(v int64) bool {
832 return int64(int32(v)) == v
833 }
834
835 func isuint32(v uint64) bool {
836 return uint64(uint32(v)) == v
837 }
838
839 func (c *ctxt9) aclassreg(reg int16) int {
840 if REG_R0 <= reg && reg <= REG_R31 {
841 return C_REGP + int(reg&1)
842 }
843 if REG_F0 <= reg && reg <= REG_F31 {
844 return C_FREGP + int(reg&1)
845 }
846 if REG_V0 <= reg && reg <= REG_V31 {
847 return C_VREG
848 }
849 if REG_VS0 <= reg && reg <= REG_VS63 {
850 return C_VSREGP + int(reg&1)
851 }
852 if REG_CR0 <= reg && reg <= REG_CR7 || reg == REG_CR {
853 return C_CREG
854 }
855 if REG_CR0LT <= reg && reg <= REG_CR7SO {
856 return C_CRBIT
857 }
858 if REG_SPR0 <= reg && reg <= REG_SPR0+1023 {
859 switch reg {
860 case REG_LR:
861 return C_LR
862
863 case REG_CTR:
864 return C_CTR
865 }
866
867 return C_SPR
868 }
869 if REG_A0 <= reg && reg <= REG_A7 {
870 return C_AREG
871 }
872 if reg == REG_FPSCR {
873 return C_FPSCR
874 }
875 return C_GOK
876 }
877
878 func (c *ctxt9) aclass(a *obj.Addr) int {
879 switch a.Type {
880 case obj.TYPE_NONE:
881 return C_NONE
882
883 case obj.TYPE_REG:
884 return c.aclassreg(a.Reg)
885
886 case obj.TYPE_MEM:
887 if a.Index != 0 {
888 if a.Name != obj.NAME_NONE || a.Offset != 0 {
889 c.ctxt.Logf("Unexpected Instruction operand index %d offset %d class %d \n", a.Index, a.Offset, a.Class)
890
891 }
892 return C_XOREG
893 }
894 switch a.Name {
895 case obj.NAME_GOTREF, obj.NAME_TOCREF:
896 return C_ADDR
897
898 case obj.NAME_EXTERN,
899 obj.NAME_STATIC:
900 c.instoffset = a.Offset
901 if a.Sym == nil {
902 break
903 } else if a.Sym.Type == objabi.STLSBSS {
904
905 if c.ctxt.Flag_shared {
906 return C_TLS_IE
907 }
908
909 return C_TLS_LE
910 } else {
911 return C_ADDR
912 }
913
914 case obj.NAME_AUTO:
915 a.Reg = REGSP
916 c.instoffset = int64(c.autosize) + a.Offset
917 if c.instoffset >= -BIG && c.instoffset < BIG {
918 return C_SOREG
919 }
920 return C_LOREG
921
922 case obj.NAME_PARAM:
923 a.Reg = REGSP
924 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
925 if c.instoffset >= -BIG && c.instoffset < BIG {
926 return C_SOREG
927 }
928 return C_LOREG
929
930 case obj.NAME_NONE:
931 c.instoffset = a.Offset
932 if a.Offset == 0 && a.Index == 0 {
933 return C_ZOREG
934 } else if c.instoffset >= -BIG && c.instoffset < BIG {
935 return C_SOREG
936 } else {
937 return C_LOREG
938 }
939 }
940
941 return C_GOK
942
943 case obj.TYPE_TEXTSIZE:
944 return C_TEXTSIZE
945
946 case obj.TYPE_FCONST:
947
948
949 f64 := a.Val.(float64)
950 if f64 == 0 {
951 if math.Signbit(f64) {
952 return C_S16CON
953 }
954 return C_ZCON
955 }
956 log.Fatalf("Unexpected nonzero FCONST operand %v", a)
957
958 case obj.TYPE_CONST,
959 obj.TYPE_ADDR:
960 switch a.Name {
961 case obj.NAME_NONE:
962 c.instoffset = a.Offset
963 if a.Reg != 0 {
964 if -BIG <= c.instoffset && c.instoffset < BIG {
965 return C_SACON
966 }
967 if isint32(c.instoffset) {
968 return C_LACON
969 }
970 return C_DACON
971 }
972
973 case obj.NAME_EXTERN,
974 obj.NAME_STATIC:
975 s := a.Sym
976 if s == nil {
977 return C_GOK
978 }
979 c.instoffset = a.Offset
980 return C_LACON
981
982 case obj.NAME_AUTO:
983 a.Reg = REGSP
984 c.instoffset = int64(c.autosize) + a.Offset
985 if c.instoffset >= -BIG && c.instoffset < BIG {
986 return C_SACON
987 }
988 return C_LACON
989
990 case obj.NAME_PARAM:
991 a.Reg = REGSP
992 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
993 if c.instoffset >= -BIG && c.instoffset < BIG {
994 return C_SACON
995 }
996 return C_LACON
997
998 default:
999 return C_GOK
1000 }
1001
1002 if c.instoffset >= 0 {
1003 sbits := bits.Len64(uint64(c.instoffset))
1004 switch {
1005 case sbits <= 5:
1006 return C_ZCON + sbits
1007 case sbits <= 8:
1008 return C_U8CON
1009 case sbits <= 15:
1010 return C_U15CON
1011 case sbits <= 16:
1012 return C_U16CON
1013 case sbits <= 31:
1014 return C_U31CON
1015 case sbits <= 32:
1016 return C_U32CON
1017 case sbits <= 33:
1018 return C_S34CON
1019 default:
1020 return C_64CON
1021 }
1022 } else {
1023 sbits := bits.Len64(uint64(^c.instoffset))
1024 switch {
1025 case sbits <= 15:
1026 return C_S16CON
1027 case sbits <= 31:
1028 return C_S32CON
1029 case sbits <= 33:
1030 return C_S34CON
1031 default:
1032 return C_64CON
1033 }
1034 }
1035
1036 case obj.TYPE_BRANCH:
1037 if a.Sym != nil && c.ctxt.Flag_dynlink && !pfxEnabled {
1038 return C_BRAPIC
1039 }
1040 return C_BRA
1041 }
1042
1043 return C_GOK
1044 }
1045
1046 func prasm(p *obj.Prog) {
1047 fmt.Printf("%v\n", p)
1048 }
1049
1050 func (c *ctxt9) oplook(p *obj.Prog) *Optab {
1051 a1 := int(p.Optab)
1052 if a1 != 0 {
1053 return &optab[a1-1]
1054 }
1055 a1 = int(p.From.Class)
1056 if a1 == 0 {
1057 a1 = c.aclass(&p.From) + 1
1058 p.From.Class = int8(a1)
1059 }
1060 a1--
1061
1062 argsv := [3]int{C_NONE + 1, C_NONE + 1, C_NONE + 1}
1063 for i, ap := range p.RestArgs {
1064 argsv[i] = int(ap.Addr.Class)
1065 if argsv[i] == 0 {
1066 argsv[i] = c.aclass(&ap.Addr) + 1
1067 ap.Addr.Class = int8(argsv[i])
1068 }
1069
1070 }
1071 a3 := argsv[0] - 1
1072 a4 := argsv[1] - 1
1073 a5 := argsv[2] - 1
1074
1075 a6 := int(p.To.Class)
1076 if a6 == 0 {
1077 a6 = c.aclass(&p.To) + 1
1078 p.To.Class = int8(a6)
1079 }
1080 a6--
1081
1082 a2 := C_NONE
1083 if p.Reg != 0 {
1084 a2 = c.aclassreg(p.Reg)
1085 }
1086
1087
1088 ops := oprange[p.As&obj.AMask]
1089 c1 := &xcmp[a1]
1090 c2 := &xcmp[a2]
1091 c3 := &xcmp[a3]
1092 c4 := &xcmp[a4]
1093 c5 := &xcmp[a5]
1094 c6 := &xcmp[a6]
1095 for i := range ops {
1096 op := &ops[i]
1097 if c1[op.a1] && c2[op.a2] && c3[op.a3] && c4[op.a4] && c5[op.a5] && c6[op.a6] {
1098 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1099 return op
1100 }
1101 }
1102
1103 c.ctxt.Diag("illegal combination %v %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5), DRconv(a6))
1104 prasm(p)
1105 if ops == nil {
1106 ops = optab
1107 }
1108 return &ops[0]
1109 }
1110
1111
1112
1113
1114
1115
1116
1117 func cmp(a int, b int) bool {
1118 if a == b {
1119 return true
1120 }
1121 switch a {
1122
1123 case C_SPR:
1124 if b == C_LR || b == C_CTR {
1125 return true
1126 }
1127
1128 case C_U1CON:
1129 return cmp(C_ZCON, b)
1130 case C_U2CON:
1131 return cmp(C_U1CON, b)
1132 case C_U3CON:
1133 return cmp(C_U2CON, b)
1134 case C_U4CON:
1135 return cmp(C_U3CON, b)
1136 case C_U5CON:
1137 return cmp(C_U4CON, b)
1138 case C_U8CON:
1139 return cmp(C_U5CON, b)
1140 case C_U15CON:
1141 return cmp(C_U8CON, b)
1142 case C_S16CON:
1143 return cmp(C_U15CON, b)
1144 case C_U16CON:
1145 return cmp(C_U15CON, b)
1146 case C_16CON:
1147 return cmp(C_S16CON, b) || cmp(C_U16CON, b)
1148 case C_U31CON:
1149 return cmp(C_U16CON, b)
1150 case C_U32CON:
1151 return cmp(C_U31CON, b)
1152 case C_S32CON:
1153 return cmp(C_U31CON, b) || cmp(C_S16CON, b)
1154 case C_32CON:
1155 return cmp(C_S32CON, b) || cmp(C_U32CON, b)
1156 case C_S34CON:
1157 return cmp(C_32CON, b)
1158 case C_64CON:
1159 return cmp(C_S34CON, b)
1160
1161 case C_LACON:
1162 return cmp(C_SACON, b)
1163
1164 case C_SOREG:
1165 return cmp(C_ZOREG, b)
1166
1167 case C_LOREG:
1168 return cmp(C_SOREG, b)
1169
1170 case C_XOREG:
1171 return cmp(C_REG, b) || cmp(C_ZOREG, b)
1172
1173
1174 case C_REG:
1175 return cmp(C_REGP, b) || (b == C_ZCON && r0iszero != 0)
1176 case C_FREG:
1177 return cmp(C_FREGP, b)
1178 case C_VSREG:
1179
1180 return cmp(C_VSREGP, b) || cmp(C_VREG, b)
1181
1182 case C_ANY:
1183 return true
1184 }
1185
1186 return false
1187 }
1188
1189
1190
1191
1192 func optabLess(i, j int) bool {
1193 p1 := &optab[i]
1194 p2 := &optab[j]
1195 n := int(p1.as) - int(p2.as)
1196
1197 if n != 0 {
1198 return n < 0
1199 }
1200
1201
1202 n = int(p1.size) - int(p2.size)
1203 if n != 0 {
1204 return n < 0
1205 }
1206
1207
1208 n = int(p1.a1) - int(p2.a1)
1209 if n != 0 {
1210 return n < 0
1211 }
1212 n = int(p1.a2) - int(p2.a2)
1213 if n != 0 {
1214 return n < 0
1215 }
1216 n = int(p1.a3) - int(p2.a3)
1217 if n != 0 {
1218 return n < 0
1219 }
1220 n = int(p1.a4) - int(p2.a4)
1221 if n != 0 {
1222 return n < 0
1223 }
1224 n = int(p1.a5) - int(p2.a5)
1225 if n != 0 {
1226 return n < 0
1227 }
1228 n = int(p1.a6) - int(p2.a6)
1229 if n != 0 {
1230 return n < 0
1231 }
1232 return false
1233 }
1234
1235
1236
1237
1238 func opset(a, b0 obj.As) {
1239 oprange[a&obj.AMask] = oprange[b0]
1240 }
1241
1242
1243
1244 func NeedTOCpointer(ctxt *obj.Link) bool {
1245 return !pfxEnabled && ctxt.Flag_shared
1246 }
1247
1248
1249 func buildop(ctxt *obj.Link) {
1250
1251 pfxEnabled = buildcfg.GOPPC64 >= 10 && buildcfg.GOOS == "linux"
1252 cfg := fmt.Sprintf("power%d/%s/%s", buildcfg.GOPPC64, buildcfg.GOARCH, buildcfg.GOOS)
1253 if cfg == buildOpCfg {
1254
1255
1256
1257 return
1258 }
1259 buildOpCfg = cfg
1260
1261
1262 prefixOptab := make([]Optab, 0, len(prefixableOptab))
1263 for _, entry := range prefixableOptab {
1264 entry := entry
1265 if pfxEnabled && buildcfg.GOPPC64 >= entry.minGOPPC64 {
1266
1267 entry.ispfx = true
1268 entry.size = entry.pfxsize
1269 }
1270 prefixOptab = append(prefixOptab, entry.Optab)
1271
1272 }
1273
1274 for i := 0; i < C_NCLASS; i++ {
1275 for n := 0; n < C_NCLASS; n++ {
1276 if cmp(n, i) {
1277 xcmp[i][n] = true
1278 }
1279 }
1280 }
1281
1282
1283 optab = make([]Optab, 0, len(optabBase)+len(optabGen)+len(prefixOptab))
1284 optab = append(optab, optabBase...)
1285 optab = append(optab, optabGen...)
1286 optab = append(optab, prefixOptab...)
1287 sort.Slice(optab, optabLess)
1288
1289 for i := range optab {
1290
1291 if optab[i].asmout == nil {
1292 optab[i].asmout = asmout
1293 }
1294 }
1295
1296 for i := 0; i < len(optab); {
1297 r := optab[i].as
1298 r0 := r & obj.AMask
1299 start := i
1300 for i < len(optab) && optab[i].as == r {
1301 i++
1302 }
1303 oprange[r0] = optab[start:i]
1304
1305 switch r {
1306 default:
1307 if !opsetGen(r) {
1308 ctxt.Diag("unknown op in build: %v", r)
1309 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
1310 }
1311
1312 case ADCBF:
1313 opset(ADCBI, r0)
1314
1315 opset(ADCBST, r0)
1316 opset(ADCBT, r0)
1317 opset(ADCBTST, r0)
1318 opset(ADCBZ, r0)
1319 opset(AICBI, r0)
1320
1321 case ASTDCCC:
1322 opset(ASTWCCC, r0)
1323 opset(ASTHCCC, r0)
1324 opset(ASTBCCC, r0)
1325
1326 case AREM:
1327 opset(AREM, r0)
1328
1329 case AREMU:
1330 opset(AREMU, r0)
1331
1332 case AREMD:
1333 opset(AREMDU, r0)
1334
1335 case AMULLW:
1336 opset(AMULLD, r0)
1337
1338 case ADIVW:
1339 opset(AMULHW, r0)
1340
1341 opset(AMULHWCC, r0)
1342 opset(AMULHWU, r0)
1343 opset(AMULHWUCC, r0)
1344 opset(AMULLWCC, r0)
1345 opset(AMULLWVCC, r0)
1346 opset(AMULLWV, r0)
1347 opset(ADIVWCC, r0)
1348 opset(ADIVWV, r0)
1349 opset(ADIVWVCC, r0)
1350 opset(ADIVWU, r0)
1351 opset(ADIVWUCC, r0)
1352 opset(ADIVWUV, r0)
1353 opset(ADIVWUVCC, r0)
1354 opset(AMODUD, r0)
1355 opset(AMODUW, r0)
1356 opset(AMODSD, r0)
1357 opset(AMODSW, r0)
1358 opset(AADDCC, r0)
1359 opset(AADDCV, r0)
1360 opset(AADDCVCC, r0)
1361 opset(AADDV, r0)
1362 opset(AADDVCC, r0)
1363 opset(AADDE, r0)
1364 opset(AADDECC, r0)
1365 opset(AADDEV, r0)
1366 opset(AADDEVCC, r0)
1367 opset(AMULHD, r0)
1368 opset(AMULHDCC, r0)
1369 opset(AMULHDU, r0)
1370 opset(AMULHDUCC, r0)
1371 opset(AMULLDCC, r0)
1372 opset(AMULLDVCC, r0)
1373 opset(AMULLDV, r0)
1374 opset(ADIVD, r0)
1375 opset(ADIVDCC, r0)
1376 opset(ADIVDE, r0)
1377 opset(ADIVDEU, r0)
1378 opset(ADIVDECC, r0)
1379 opset(ADIVDEUCC, r0)
1380 opset(ADIVDVCC, r0)
1381 opset(ADIVDV, r0)
1382 opset(ADIVDU, r0)
1383 opset(ADIVDUV, r0)
1384 opset(ADIVDUVCC, r0)
1385 opset(ADIVDUCC, r0)
1386
1387 case ACRAND:
1388 opset(ACRANDN, r0)
1389 opset(ACREQV, r0)
1390 opset(ACRNAND, r0)
1391 opset(ACRNOR, r0)
1392 opset(ACROR, r0)
1393 opset(ACRORN, r0)
1394 opset(ACRXOR, r0)
1395
1396 case APOPCNTD:
1397 opset(APOPCNTW, r0)
1398 opset(APOPCNTB, r0)
1399 opset(ACNTTZW, r0)
1400 opset(ACNTTZWCC, r0)
1401 opset(ACNTTZD, r0)
1402 opset(ACNTTZDCC, r0)
1403
1404 case ACOPY:
1405 opset(APASTECC, r0)
1406
1407 case AMADDHD:
1408 opset(AMADDHDU, r0)
1409 opset(AMADDLD, r0)
1410
1411 case AMOVBZ:
1412 opset(AMOVH, r0)
1413 opset(AMOVHZ, r0)
1414
1415 case AMOVBZU:
1416 opset(AMOVHU, r0)
1417
1418 opset(AMOVHZU, r0)
1419 opset(AMOVWU, r0)
1420 opset(AMOVWZU, r0)
1421 opset(AMOVDU, r0)
1422 opset(AMOVMW, r0)
1423
1424 case ALVEBX:
1425 opset(ALVEHX, r0)
1426 opset(ALVEWX, r0)
1427 opset(ALVX, r0)
1428 opset(ALVXL, r0)
1429 opset(ALVSL, r0)
1430 opset(ALVSR, r0)
1431
1432 case ASTVEBX:
1433 opset(ASTVEHX, r0)
1434 opset(ASTVEWX, r0)
1435 opset(ASTVX, r0)
1436 opset(ASTVXL, r0)
1437
1438 case AVAND:
1439 opset(AVAND, r0)
1440 opset(AVANDC, r0)
1441 opset(AVNAND, r0)
1442
1443 case AVMRGOW:
1444 opset(AVMRGEW, r0)
1445
1446 case AVOR:
1447 opset(AVOR, r0)
1448 opset(AVORC, r0)
1449 opset(AVXOR, r0)
1450 opset(AVNOR, r0)
1451 opset(AVEQV, r0)
1452
1453 case AVADDUM:
1454 opset(AVADDUBM, r0)
1455 opset(AVADDUHM, r0)
1456 opset(AVADDUWM, r0)
1457 opset(AVADDUDM, r0)
1458 opset(AVADDUQM, r0)
1459
1460 case AVADDCU:
1461 opset(AVADDCUQ, r0)
1462 opset(AVADDCUW, r0)
1463
1464 case AVADDUS:
1465 opset(AVADDUBS, r0)
1466 opset(AVADDUHS, r0)
1467 opset(AVADDUWS, r0)
1468
1469 case AVADDSS:
1470 opset(AVADDSBS, r0)
1471 opset(AVADDSHS, r0)
1472 opset(AVADDSWS, r0)
1473
1474 case AVADDE:
1475 opset(AVADDEUQM, r0)
1476 opset(AVADDECUQ, r0)
1477
1478 case AVSUBUM:
1479 opset(AVSUBUBM, r0)
1480 opset(AVSUBUHM, r0)
1481 opset(AVSUBUWM, r0)
1482 opset(AVSUBUDM, r0)
1483 opset(AVSUBUQM, r0)
1484
1485 case AVSUBCU:
1486 opset(AVSUBCUQ, r0)
1487 opset(AVSUBCUW, r0)
1488
1489 case AVSUBUS:
1490 opset(AVSUBUBS, r0)
1491 opset(AVSUBUHS, r0)
1492 opset(AVSUBUWS, r0)
1493
1494 case AVSUBSS:
1495 opset(AVSUBSBS, r0)
1496 opset(AVSUBSHS, r0)
1497 opset(AVSUBSWS, r0)
1498
1499 case AVSUBE:
1500 opset(AVSUBEUQM, r0)
1501 opset(AVSUBECUQ, r0)
1502
1503 case AVMULESB:
1504 opset(AVMULOSB, r0)
1505 opset(AVMULEUB, r0)
1506 opset(AVMULOUB, r0)
1507 opset(AVMULESH, r0)
1508 opset(AVMULOSH, r0)
1509 opset(AVMULEUH, r0)
1510 opset(AVMULOUH, r0)
1511 opset(AVMULESW, r0)
1512 opset(AVMULOSW, r0)
1513 opset(AVMULEUW, r0)
1514 opset(AVMULOUW, r0)
1515 opset(AVMULUWM, r0)
1516 case AVPMSUM:
1517 opset(AVPMSUMB, r0)
1518 opset(AVPMSUMH, r0)
1519 opset(AVPMSUMW, r0)
1520 opset(AVPMSUMD, r0)
1521
1522 case AVR:
1523 opset(AVRLB, r0)
1524 opset(AVRLH, r0)
1525 opset(AVRLW, r0)
1526 opset(AVRLD, r0)
1527
1528 case AVS:
1529 opset(AVSLB, r0)
1530 opset(AVSLH, r0)
1531 opset(AVSLW, r0)
1532 opset(AVSL, r0)
1533 opset(AVSLO, r0)
1534 opset(AVSRB, r0)
1535 opset(AVSRH, r0)
1536 opset(AVSRW, r0)
1537 opset(AVSR, r0)
1538 opset(AVSRO, r0)
1539 opset(AVSLD, r0)
1540 opset(AVSRD, r0)
1541
1542 case AVSA:
1543 opset(AVSRAB, r0)
1544 opset(AVSRAH, r0)
1545 opset(AVSRAW, r0)
1546 opset(AVSRAD, r0)
1547
1548 case AVSOI:
1549 opset(AVSLDOI, r0)
1550
1551 case AVCLZ:
1552 opset(AVCLZB, r0)
1553 opset(AVCLZH, r0)
1554 opset(AVCLZW, r0)
1555 opset(AVCLZD, r0)
1556
1557 case AVPOPCNT:
1558 opset(AVPOPCNTB, r0)
1559 opset(AVPOPCNTH, r0)
1560 opset(AVPOPCNTW, r0)
1561 opset(AVPOPCNTD, r0)
1562
1563 case AVCMPEQ:
1564 opset(AVCMPEQUB, r0)
1565 opset(AVCMPEQUBCC, r0)
1566 opset(AVCMPEQUH, r0)
1567 opset(AVCMPEQUHCC, r0)
1568 opset(AVCMPEQUW, r0)
1569 opset(AVCMPEQUWCC, r0)
1570 opset(AVCMPEQUD, r0)
1571 opset(AVCMPEQUDCC, r0)
1572
1573 case AVCMPGT:
1574 opset(AVCMPGTUB, r0)
1575 opset(AVCMPGTUBCC, r0)
1576 opset(AVCMPGTUH, r0)
1577 opset(AVCMPGTUHCC, r0)
1578 opset(AVCMPGTUW, r0)
1579 opset(AVCMPGTUWCC, r0)
1580 opset(AVCMPGTUD, r0)
1581 opset(AVCMPGTUDCC, r0)
1582 opset(AVCMPGTSB, r0)
1583 opset(AVCMPGTSBCC, r0)
1584 opset(AVCMPGTSH, r0)
1585 opset(AVCMPGTSHCC, r0)
1586 opset(AVCMPGTSW, r0)
1587 opset(AVCMPGTSWCC, r0)
1588 opset(AVCMPGTSD, r0)
1589 opset(AVCMPGTSDCC, r0)
1590
1591 case AVCMPNEZB:
1592 opset(AVCMPNEZBCC, r0)
1593 opset(AVCMPNEB, r0)
1594 opset(AVCMPNEBCC, r0)
1595 opset(AVCMPNEH, r0)
1596 opset(AVCMPNEHCC, r0)
1597 opset(AVCMPNEW, r0)
1598 opset(AVCMPNEWCC, r0)
1599
1600 case AVPERM:
1601 opset(AVPERMXOR, r0)
1602 opset(AVPERMR, r0)
1603
1604 case AVBPERMQ:
1605 opset(AVBPERMD, r0)
1606
1607 case AVSEL:
1608 opset(AVSEL, r0)
1609
1610 case AVSPLTB:
1611 opset(AVSPLTH, r0)
1612 opset(AVSPLTW, r0)
1613
1614 case AVSPLTISB:
1615 opset(AVSPLTISH, r0)
1616 opset(AVSPLTISW, r0)
1617
1618 case AVCIPH:
1619 opset(AVCIPHER, r0)
1620 opset(AVCIPHERLAST, r0)
1621
1622 case AVNCIPH:
1623 opset(AVNCIPHER, r0)
1624 opset(AVNCIPHERLAST, r0)
1625
1626 case AVSBOX:
1627 opset(AVSBOX, r0)
1628
1629 case AVSHASIGMA:
1630 opset(AVSHASIGMAW, r0)
1631 opset(AVSHASIGMAD, r0)
1632
1633 case ALXVD2X:
1634 opset(ALXVDSX, r0)
1635 opset(ALXVW4X, r0)
1636 opset(ALXVH8X, r0)
1637 opset(ALXVB16X, r0)
1638
1639 case ALXV:
1640 opset(ALXV, r0)
1641
1642 case ALXVL:
1643 opset(ALXVLL, r0)
1644 opset(ALXVX, r0)
1645
1646 case ASTXVD2X:
1647 opset(ASTXVW4X, r0)
1648 opset(ASTXVH8X, r0)
1649 opset(ASTXVB16X, r0)
1650
1651 case ASTXV:
1652 opset(ASTXV, r0)
1653
1654 case ASTXVL:
1655 opset(ASTXVLL, r0)
1656 opset(ASTXVX, r0)
1657
1658 case ALXSDX:
1659 opset(ALXSDX, r0)
1660
1661 case ASTXSDX:
1662 opset(ASTXSDX, r0)
1663
1664 case ALXSIWAX:
1665 opset(ALXSIWZX, r0)
1666
1667 case ASTXSIWX:
1668 opset(ASTXSIWX, r0)
1669
1670 case AMFVSRD:
1671 opset(AMFFPRD, r0)
1672 opset(AMFVRD, r0)
1673 opset(AMFVSRWZ, r0)
1674 opset(AMFVSRLD, r0)
1675
1676 case AMTVSRD:
1677 opset(AMTFPRD, r0)
1678 opset(AMTVRD, r0)
1679 opset(AMTVSRWA, r0)
1680 opset(AMTVSRWZ, r0)
1681 opset(AMTVSRWS, r0)
1682
1683 case AXXLAND:
1684 opset(AXXLANDC, r0)
1685 opset(AXXLEQV, r0)
1686 opset(AXXLNAND, r0)
1687 opset(AXXLORC, r0)
1688 opset(AXXLNOR, r0)
1689 opset(AXXLORQ, r0)
1690 opset(AXXLXOR, r0)
1691 opset(AXXLOR, r0)
1692 opset(AXSMAXJDP, r0)
1693 opset(AXSMINJDP, r0)
1694
1695 case AXXSEL:
1696 opset(AXXSEL, r0)
1697
1698 case AXXMRGHW:
1699 opset(AXXMRGLW, r0)
1700
1701 case AXXSPLTW:
1702 opset(AXXSPLTW, r0)
1703
1704 case AXXSPLTIB:
1705 opset(AXXSPLTIB, r0)
1706
1707 case AXXPERM:
1708 opset(AXXPERM, r0)
1709
1710 case AXXSLDWI:
1711 opset(AXXPERMDI, r0)
1712 opset(AXXSLDWI, r0)
1713
1714 case AXXBRQ:
1715 opset(AXXBRD, r0)
1716 opset(AXXBRW, r0)
1717 opset(AXXBRH, r0)
1718
1719 case AXSCVDPSP:
1720 opset(AXSCVSPDP, r0)
1721 opset(AXSCVDPSPN, r0)
1722 opset(AXSCVSPDPN, r0)
1723
1724 case AXVCVDPSP:
1725 opset(AXVCVSPDP, r0)
1726
1727 case AXSCVDPSXDS:
1728 opset(AXSCVDPSXWS, r0)
1729 opset(AXSCVDPUXDS, r0)
1730 opset(AXSCVDPUXWS, r0)
1731
1732 case AXSCVSXDDP:
1733 opset(AXSCVUXDDP, r0)
1734 opset(AXSCVSXDSP, r0)
1735 opset(AXSCVUXDSP, r0)
1736
1737 case AXVCVDPSXDS:
1738 opset(AXVCVDPSXDS, r0)
1739 opset(AXVCVDPSXWS, r0)
1740 opset(AXVCVDPUXDS, r0)
1741 opset(AXVCVDPUXWS, r0)
1742 opset(AXVCVSPSXDS, r0)
1743 opset(AXVCVSPSXWS, r0)
1744 opset(AXVCVSPUXDS, r0)
1745 opset(AXVCVSPUXWS, r0)
1746
1747 case AXVCVSXDDP:
1748 opset(AXVCVSXWDP, r0)
1749 opset(AXVCVUXDDP, r0)
1750 opset(AXVCVUXWDP, r0)
1751 opset(AXVCVSXDSP, r0)
1752 opset(AXVCVSXWSP, r0)
1753 opset(AXVCVUXDSP, r0)
1754 opset(AXVCVUXWSP, r0)
1755
1756 case AAND:
1757 opset(AANDN, r0)
1758 opset(AANDNCC, r0)
1759 opset(AEQV, r0)
1760 opset(AEQVCC, r0)
1761 opset(ANAND, r0)
1762 opset(ANANDCC, r0)
1763 opset(ANOR, r0)
1764 opset(ANORCC, r0)
1765 opset(AORCC, r0)
1766 opset(AORN, r0)
1767 opset(AORNCC, r0)
1768 opset(AXORCC, r0)
1769
1770 case AADDME:
1771 opset(AADDMECC, r0)
1772
1773 opset(AADDMEV, r0)
1774 opset(AADDMEVCC, r0)
1775 opset(AADDZE, r0)
1776 opset(AADDZECC, r0)
1777 opset(AADDZEV, r0)
1778 opset(AADDZEVCC, r0)
1779 opset(ASUBME, r0)
1780 opset(ASUBMECC, r0)
1781 opset(ASUBMEV, r0)
1782 opset(ASUBMEVCC, r0)
1783 opset(ASUBZE, r0)
1784 opset(ASUBZECC, r0)
1785 opset(ASUBZEV, r0)
1786 opset(ASUBZEVCC, r0)
1787
1788 case AADDC:
1789 opset(AADDCCC, r0)
1790
1791 case ABEQ:
1792 opset(ABGE, r0)
1793 opset(ABGT, r0)
1794 opset(ABLE, r0)
1795 opset(ABLT, r0)
1796 opset(ABNE, r0)
1797 opset(ABVC, r0)
1798 opset(ABVS, r0)
1799
1800 case ABR:
1801 opset(ABL, r0)
1802
1803 case ABC:
1804 opset(ABCL, r0)
1805
1806 case ABDNZ:
1807 opset(ABDZ, r0)
1808
1809 case AEXTSB:
1810 opset(AEXTSBCC, r0)
1811
1812 opset(AEXTSH, r0)
1813 opset(AEXTSHCC, r0)
1814 opset(ACNTLZW, r0)
1815 opset(ACNTLZWCC, r0)
1816 opset(ACNTLZD, r0)
1817 opset(AEXTSW, r0)
1818 opset(AEXTSWCC, r0)
1819 opset(ACNTLZDCC, r0)
1820
1821 case AFABS:
1822 opset(AFABSCC, r0)
1823
1824 opset(AFNABS, r0)
1825 opset(AFNABSCC, r0)
1826 opset(AFNEG, r0)
1827 opset(AFNEGCC, r0)
1828 opset(AFRSP, r0)
1829 opset(AFRSPCC, r0)
1830 opset(AFCTIW, r0)
1831 opset(AFCTIWCC, r0)
1832 opset(AFCTIWZ, r0)
1833 opset(AFCTIWZCC, r0)
1834 opset(AFCTID, r0)
1835 opset(AFCTIDCC, r0)
1836 opset(AFCTIDZ, r0)
1837 opset(AFCTIDZCC, r0)
1838 opset(AFCFID, r0)
1839 opset(AFCFIDCC, r0)
1840 opset(AFCFIDU, r0)
1841 opset(AFCFIDUCC, r0)
1842 opset(AFCFIDS, r0)
1843 opset(AFCFIDSCC, r0)
1844 opset(AFRES, r0)
1845 opset(AFRESCC, r0)
1846 opset(AFRIM, r0)
1847 opset(AFRIMCC, r0)
1848 opset(AFRIP, r0)
1849 opset(AFRIPCC, r0)
1850 opset(AFRIZ, r0)
1851 opset(AFRIZCC, r0)
1852 opset(AFRIN, r0)
1853 opset(AFRINCC, r0)
1854 opset(AFRSQRTE, r0)
1855 opset(AFRSQRTECC, r0)
1856 opset(AFSQRT, r0)
1857 opset(AFSQRTCC, r0)
1858 opset(AFSQRTS, r0)
1859 opset(AFSQRTSCC, r0)
1860
1861 case AFADD:
1862 opset(AFADDS, r0)
1863 opset(AFADDCC, r0)
1864 opset(AFADDSCC, r0)
1865 opset(AFCPSGN, r0)
1866 opset(AFCPSGNCC, r0)
1867 opset(AFDIV, r0)
1868 opset(AFDIVS, r0)
1869 opset(AFDIVCC, r0)
1870 opset(AFDIVSCC, r0)
1871 opset(AFSUB, r0)
1872 opset(AFSUBS, r0)
1873 opset(AFSUBCC, r0)
1874 opset(AFSUBSCC, r0)
1875 opset(ADADD, r0)
1876 opset(ADDIV, r0)
1877 opset(ADSUB, r0)
1878
1879 case AFMADD:
1880 opset(AFMADDCC, r0)
1881 opset(AFMADDS, r0)
1882 opset(AFMADDSCC, r0)
1883 opset(AFMSUB, r0)
1884 opset(AFMSUBCC, r0)
1885 opset(AFMSUBS, r0)
1886 opset(AFMSUBSCC, r0)
1887 opset(AFNMADD, r0)
1888 opset(AFNMADDCC, r0)
1889 opset(AFNMADDS, r0)
1890 opset(AFNMADDSCC, r0)
1891 opset(AFNMSUB, r0)
1892 opset(AFNMSUBCC, r0)
1893 opset(AFNMSUBS, r0)
1894 opset(AFNMSUBSCC, r0)
1895 opset(AFSEL, r0)
1896 opset(AFSELCC, r0)
1897
1898 case AFMUL:
1899 opset(AFMULS, r0)
1900 opset(AFMULCC, r0)
1901 opset(AFMULSCC, r0)
1902 opset(ADMUL, r0)
1903
1904 case AFCMPO:
1905 opset(AFCMPU, r0)
1906
1907 case AMTFSB0:
1908 opset(AMTFSB0CC, r0)
1909 opset(AMTFSB1, r0)
1910 opset(AMTFSB1CC, r0)
1911
1912 case ANEG:
1913 opset(ANEGCC, r0)
1914
1915 opset(ANEGV, r0)
1916 opset(ANEGVCC, r0)
1917
1918 case AOR:
1919 opset(AXOR, r0)
1920
1921 case AORIS:
1922 opset(AXORIS, r0)
1923
1924 case ASLW:
1925 opset(ASLWCC, r0)
1926 opset(ASRW, r0)
1927 opset(ASRWCC, r0)
1928 opset(AROTLW, r0)
1929
1930 case ASLD:
1931 opset(ASLDCC, r0)
1932 opset(ASRD, r0)
1933 opset(ASRDCC, r0)
1934 opset(AROTL, r0)
1935
1936 case ASRAW:
1937 opset(ASRAWCC, r0)
1938
1939 case AEXTSWSLI:
1940 opset(AEXTSWSLICC, r0)
1941
1942 case ASRAD:
1943 opset(ASRADCC, r0)
1944
1945 case ASUB:
1946 opset(ASUB, r0)
1947
1948 opset(ASUBCC, r0)
1949 opset(ASUBV, r0)
1950 opset(ASUBVCC, r0)
1951 opset(ASUBCCC, r0)
1952 opset(ASUBCV, r0)
1953 opset(ASUBCVCC, r0)
1954 opset(ASUBE, r0)
1955 opset(ASUBECC, r0)
1956 opset(ASUBEV, r0)
1957 opset(ASUBEVCC, r0)
1958
1959 case ASYNC:
1960 opset(AISYNC, r0)
1961 opset(ALWSYNC, r0)
1962 opset(APTESYNC, r0)
1963 opset(ATLBSYNC, r0)
1964
1965 case ARLWNM:
1966 opset(ARLWNMCC, r0)
1967 opset(ARLWMI, r0)
1968 opset(ARLWMICC, r0)
1969
1970 case ARLDMI:
1971 opset(ARLDMICC, r0)
1972 opset(ARLDIMI, r0)
1973 opset(ARLDIMICC, r0)
1974
1975 case ARLDC:
1976 opset(ARLDCCC, r0)
1977
1978 case ARLDCL:
1979 opset(ARLDCR, r0)
1980 opset(ARLDCLCC, r0)
1981 opset(ARLDCRCC, r0)
1982
1983 case ARLDICL:
1984 opset(ARLDICLCC, r0)
1985 opset(ARLDICR, r0)
1986 opset(ARLDICRCC, r0)
1987 opset(ARLDIC, r0)
1988 opset(ARLDICCC, r0)
1989 opset(ACLRLSLDI, r0)
1990
1991 case AFMOVD:
1992 opset(AFMOVDCC, r0)
1993 opset(AFMOVDU, r0)
1994 opset(AFMOVS, r0)
1995 opset(AFMOVSU, r0)
1996
1997 case ALDAR:
1998 opset(ALBAR, r0)
1999 opset(ALHAR, r0)
2000 opset(ALWAR, r0)
2001
2002 case ASYSCALL:
2003 opset(ARFI, r0)
2004
2005 opset(ARFCI, r0)
2006 opset(ARFID, r0)
2007 opset(AHRFID, r0)
2008
2009 case AMOVHBR:
2010 opset(AMOVWBR, r0)
2011 opset(AMOVDBR, r0)
2012
2013 case ASLBMFEE:
2014 opset(ASLBMFEV, r0)
2015
2016 case ATW:
2017 opset(ATD, r0)
2018
2019 case ATLBIE:
2020 opset(ASLBIE, r0)
2021 opset(ATLBIEL, r0)
2022
2023 case AEIEIO:
2024 opset(ASLBIA, r0)
2025
2026 case ACMP:
2027 opset(ACMPW, r0)
2028
2029 case ACMPU:
2030 opset(ACMPWU, r0)
2031
2032 case ACMPB:
2033 opset(ACMPB, r0)
2034
2035 case AFTDIV:
2036 opset(AFTDIV, r0)
2037
2038 case AFTSQRT:
2039 opset(AFTSQRT, r0)
2040
2041 case AMOVW:
2042 opset(AMOVWZ, r0)
2043
2044 case AVCLZLSBB:
2045 opset(AVCTZLSBB, r0)
2046
2047 case AADD,
2048 AADDIS,
2049 AANDCC,
2050 AANDISCC,
2051 AFMOVSX,
2052 AFMOVSZ,
2053 ALSW,
2054 AMOVD,
2055 AMOVB,
2056 AMOVBU,
2057 AMOVFL,
2058
2059 ASUBC,
2060 ASTSW,
2061 ASLBMTE,
2062 AWORD,
2063 ADWORD,
2064 ADARN,
2065 AVMSUMUDM,
2066 AADDEX,
2067 ACMPEQB,
2068 ACLRLSLWI,
2069 AMTVSRDD,
2070 APNOP,
2071 AISEL,
2072 ASETB,
2073 obj.ANOP,
2074 obj.ATEXT,
2075 obj.AUNDEF,
2076 obj.AFUNCDATA,
2077 obj.APCALIGN,
2078 obj.APCDATA,
2079 obj.ADUFFZERO,
2080 obj.ADUFFCOPY:
2081 break
2082 }
2083 }
2084 }
2085
2086 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
2087 return o<<26 | xo<<1 | oe<<11
2088 }
2089
2090 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
2091 return o<<26 | xo<<2 | oe<<11
2092 }
2093
2094 func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32 {
2095 return o<<26 | xo<<2 | oe<<16
2096 }
2097
2098 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
2099 return o<<26 | xo<<3 | oe<<11
2100 }
2101
2102 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
2103 return o<<26 | xo<<4 | oe<<11
2104 }
2105
2106 func OPDQ(o uint32, xo uint32, oe uint32) uint32 {
2107 return o<<26 | xo | oe<<4
2108 }
2109
2110 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2111 return o<<26 | xo | oe<<11 | rc&1
2112 }
2113
2114 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2115 return o<<26 | xo | oe<<11 | (rc&1)<<10
2116 }
2117
2118 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2119 return o<<26 | xo<<1 | oe<<10 | rc&1
2120 }
2121
2122 func OPCC(o uint32, xo uint32, rc uint32) uint32 {
2123 return OPVCC(o, xo, 0, rc)
2124 }
2125
2126
2127 func OPMD(o, xo, rc uint32) uint32 {
2128 return o<<26 | xo<<2 | rc&1
2129 }
2130
2131
2132 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
2133 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
2134 }
2135
2136
2137 func AOP_RR(op uint32, d uint32, a uint32) uint32 {
2138 return op | (d&31)<<21 | (a&31)<<11
2139 }
2140
2141
2142 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2143 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
2144 }
2145
2146 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2147 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
2148 }
2149
2150
2151 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2152 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
2153 }
2154
2155
2156 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
2157 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
2158 }
2159
2160
2161 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
2162 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
2163 }
2164
2165
2166 func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
2167 return op | (d&31)<<21 | (simm&31)<<16
2168 }
2169
2170
2171 func AOP_XX1(op uint32, r uint32, a uint32, b uint32) uint32 {
2172 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
2173 }
2174
2175
2176 func AOP_XX2(op uint32, xt uint32, a uint32, xb uint32) uint32 {
2177 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
2178 }
2179
2180
2181 func AOP_XX3(op uint32, xt uint32, xa uint32, xb uint32) uint32 {
2182 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2183 }
2184
2185
2186 func AOP_XX3I(op uint32, xt uint32, xa uint32, xb uint32, c uint32) uint32 {
2187 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2188 }
2189
2190
2191 func AOP_XX4(op uint32, xt uint32, xa uint32, xb uint32, xc uint32) uint32 {
2192 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2193 }
2194
2195
2196 func AOP_DQ(op uint32, xt uint32, a uint32, b uint32) uint32 {
2197
2198
2199
2200
2201
2202
2203 dq := b >> 4
2204 return op | (xt&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (xt&32)>>2
2205 }
2206
2207
2208 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2209 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<9
2210 }
2211
2212
2213 func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2214 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
2215 }
2216
2217 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
2218 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
2219 }
2220
2221 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
2222 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
2223 }
2224
2225 func OP_BR(op uint32, li uint32, aa uint32) uint32 {
2226 return op | li&0x03FFFFFC | aa<<1
2227 }
2228
2229 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
2230 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
2231 }
2232
2233 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
2234 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
2235 }
2236
2237 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
2238 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
2239 }
2240
2241 func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32 {
2242 return op | (a&31)<<21 | (s&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1
2243 }
2244
2245 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
2246 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
2247 }
2248
2249
2250 func AOP_MD(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
2251 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
2252 }
2253
2254
2255 func AOP_MDS(op, to, from, rsh, m uint32) uint32 {
2256 return AOP_MD(op, to, from, rsh&31, m)
2257 }
2258
2259 func AOP_PFX_00_8LS(r, ie uint32) uint32 {
2260 return 1<<26 | 0<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
2261 }
2262 func AOP_PFX_10_MLS(r, ie uint32) uint32 {
2263 return 1<<26 | 2<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
2264 }
2265
2266 const (
2267
2268 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
2269 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
2270 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
2271 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0
2272 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0
2273 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0
2274 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0
2275 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0
2276 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0
2277 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0
2278 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
2279 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
2280 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
2281 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
2282 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
2283 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
2284 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
2285 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
2286 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
2287 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
2288 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
2289 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
2290 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0
2291 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0
2292 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0
2293 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0
2294 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0
2295 OP_XORI = 26<<26 | 0<<1 | 0<<10 | 0
2296 OP_XORIS = 27<<26 | 0<<1 | 0<<10 | 0
2297 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
2298 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0
2299 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0
2300 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0
2301 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
2302 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
2303 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0
2304 OP_EXTSWSLI = 31<<26 | 445<<2
2305 OP_SETB = 31<<26 | 128<<1
2306 )
2307
2308 func pfxadd(rt, ra int16, r uint32, imm32 int64) (uint32, uint32) {
2309 return AOP_PFX_10_MLS(r, uint32(imm32>>16)), AOP_IRR(14<<26, uint32(rt), uint32(ra), uint32(imm32))
2310 }
2311
2312 func pfxload(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
2313 switch a {
2314 case AMOVH:
2315 return AOP_PFX_10_MLS(r, 0), AOP_IRR(42<<26, uint32(reg), uint32(base), 0)
2316 case AMOVW:
2317 return AOP_PFX_00_8LS(r, 0), AOP_IRR(41<<26, uint32(reg), uint32(base), 0)
2318 case AMOVD:
2319 return AOP_PFX_00_8LS(r, 0), AOP_IRR(57<<26, uint32(reg), uint32(base), 0)
2320 case AMOVBZ, AMOVB:
2321 return AOP_PFX_10_MLS(r, 0), AOP_IRR(34<<26, uint32(reg), uint32(base), 0)
2322 case AMOVHZ:
2323 return AOP_PFX_10_MLS(r, 0), AOP_IRR(40<<26, uint32(reg), uint32(base), 0)
2324 case AMOVWZ:
2325 return AOP_PFX_10_MLS(r, 0), AOP_IRR(32<<26, uint32(reg), uint32(base), 0)
2326 case AFMOVS:
2327 return AOP_PFX_10_MLS(r, 0), AOP_IRR(48<<26, uint32(reg), uint32(base), 0)
2328 case AFMOVD:
2329 return AOP_PFX_10_MLS(r, 0), AOP_IRR(50<<26, uint32(reg), uint32(base), 0)
2330 }
2331 log.Fatalf("Error no pfxload for %v\n", a)
2332 return 0, 0
2333 }
2334
2335 func pfxstore(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
2336 switch a {
2337 case AMOVD:
2338 return AOP_PFX_00_8LS(r, 0), AOP_IRR(61<<26, uint32(reg), uint32(base), 0)
2339 case AMOVBZ, AMOVB:
2340 return AOP_PFX_10_MLS(r, 0), AOP_IRR(38<<26, uint32(reg), uint32(base), 0)
2341 case AMOVHZ, AMOVH:
2342 return AOP_PFX_10_MLS(r, 0), AOP_IRR(44<<26, uint32(reg), uint32(base), 0)
2343 case AMOVWZ, AMOVW:
2344 return AOP_PFX_10_MLS(r, 0), AOP_IRR(36<<26, uint32(reg), uint32(base), 0)
2345 case AFMOVS:
2346 return AOP_PFX_10_MLS(r, 0), AOP_IRR(52<<26, uint32(reg), uint32(base), 0)
2347 case AFMOVD:
2348 return AOP_PFX_10_MLS(r, 0), AOP_IRR(54<<26, uint32(reg), uint32(base), 0)
2349 }
2350 log.Fatalf("Error no pfxstore for %v\n", a)
2351 return 0, 0
2352 }
2353
2354 func oclass(a *obj.Addr) int {
2355 return int(a.Class) - 1
2356 }
2357
2358 const (
2359 D_FORM = iota
2360 DS_FORM
2361 )
2362
2363
2364
2365
2366
2367
2368
2369
2370 func (c *ctxt9) opform(insn uint32) int {
2371 switch insn {
2372 default:
2373 c.ctxt.Diag("bad insn in loadform: %x", insn)
2374 case OPVCC(58, 0, 0, 0),
2375 OPVCC(58, 0, 0, 1),
2376 OPVCC(58, 0, 0, 0) | 1<<1,
2377 OPVCC(62, 0, 0, 0),
2378 OPVCC(62, 0, 0, 1):
2379 return DS_FORM
2380 case OP_ADDI,
2381 OPVCC(32, 0, 0, 0),
2382 OPVCC(33, 0, 0, 0),
2383 OPVCC(34, 0, 0, 0),
2384 OPVCC(35, 0, 0, 0),
2385 OPVCC(40, 0, 0, 0),
2386 OPVCC(41, 0, 0, 0),
2387 OPVCC(42, 0, 0, 0),
2388 OPVCC(43, 0, 0, 0),
2389 OPVCC(46, 0, 0, 0),
2390 OPVCC(48, 0, 0, 0),
2391 OPVCC(49, 0, 0, 0),
2392 OPVCC(50, 0, 0, 0),
2393 OPVCC(51, 0, 0, 0),
2394 OPVCC(36, 0, 0, 0),
2395 OPVCC(37, 0, 0, 0),
2396 OPVCC(38, 0, 0, 0),
2397 OPVCC(39, 0, 0, 0),
2398 OPVCC(44, 0, 0, 0),
2399 OPVCC(45, 0, 0, 0),
2400 OPVCC(47, 0, 0, 0),
2401 OPVCC(52, 0, 0, 0),
2402 OPVCC(53, 0, 0, 0),
2403 OPVCC(54, 0, 0, 0),
2404 OPVCC(55, 0, 0, 0):
2405 return D_FORM
2406 }
2407 return 0
2408 }
2409
2410
2411
2412
2413 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32, reuse bool) (o1, o2 uint32, rel obj.Reloc) {
2414 if c.ctxt.Headtype == objabi.Haix {
2415
2416 c.ctxt.Diag("symbolAccess called for %s", s.Name)
2417 }
2418 var base uint32
2419 form := c.opform(op)
2420 if c.ctxt.Flag_shared {
2421 base = REG_R2
2422 } else {
2423 base = REG_R0
2424 }
2425
2426
2427 if !reuse {
2428 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
2429 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
2430 } else {
2431 o1 = AOP_IRR(OP_ADDIS, uint32(reg), base, 0)
2432 o2 = AOP_IRR(op, uint32(reg), uint32(reg), 0)
2433 }
2434 var typ objabi.RelocType
2435 if c.ctxt.Flag_shared {
2436 switch form {
2437 case D_FORM:
2438 typ = objabi.R_ADDRPOWER_TOCREL
2439 case DS_FORM:
2440 typ = objabi.R_ADDRPOWER_TOCREL_DS
2441 }
2442 } else {
2443 switch form {
2444 case D_FORM:
2445 typ = objabi.R_ADDRPOWER
2446 case DS_FORM:
2447 typ = objabi.R_ADDRPOWER_DS
2448 }
2449 }
2450 rel = obj.Reloc{
2451 Type: typ,
2452 Off: int32(c.pc),
2453 Siz: 8,
2454 Sym: s,
2455 Add: d,
2456 }
2457 return
2458 }
2459
2460
2461
2462
2463
2464
2465 func decodeMask32(mask uint32) (mb, me uint32, valid bool) {
2466 mb = uint32(bits.LeadingZeros32(mask))
2467 me = uint32(32 - bits.TrailingZeros32(mask))
2468 mbn := uint32(bits.LeadingZeros32(^mask))
2469 men := uint32(32 - bits.TrailingZeros32(^mask))
2470
2471 if mb == 0 && me == 32 {
2472
2473 mb, me = men, mbn
2474 }
2475
2476
2477
2478 v := mask
2479 vp := (v & -v) + v
2480
2481 vn := ^v
2482 vpn := (vn & -vn) + vn
2483 return mb, (me - 1) & 31, (v&vp == 0 || vn&vpn == 0) && v != 0
2484 }
2485
2486
2487
2488
2489
2490
2491
2492
2493 func decodeMask64(mask int64) (mb, me uint32, valid bool) {
2494 m := uint64(mask)
2495 mb = uint32(bits.LeadingZeros64(m))
2496 me = uint32(64 - bits.TrailingZeros64(m))
2497 valid = ((m&-m)+m)&m == 0 && m != 0
2498 return mb, (me - 1) & 63, valid
2499 }
2500
2501
2502 func loadl16(r int, d int64) uint32 {
2503 v := uint16(d)
2504 if v == 0 {
2505
2506
2507 return NOP
2508 }
2509 return LOP_IRR(OP_ORI, uint32(r), uint32(r), uint32(v))
2510 }
2511
2512
2513 func loadu32(r int, d int64) uint32 {
2514 v := int32(d >> 16)
2515 if isuint32(uint64(d)) {
2516 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
2517 }
2518 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
2519 }
2520
2521 func high16adjusted(d int32) uint16 {
2522 if d&0x8000 != 0 {
2523 return uint16((d >> 16) + 1)
2524 }
2525 return uint16(d >> 16)
2526 }
2527
2528 func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
2529 o1 := uint32(0)
2530 o2 := uint32(0)
2531 o3 := uint32(0)
2532 o4 := uint32(0)
2533 o5 := uint32(0)
2534
2535
2536 switch o.type_ {
2537 default:
2538 c.ctxt.Diag("unknown type %d", o.type_)
2539 prasm(p)
2540
2541 case 0:
2542 break
2543
2544 case 2:
2545 r := int(p.Reg)
2546
2547 if r == 0 {
2548 r = int(p.To.Reg)
2549 }
2550 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2551
2552 case 3:
2553 d := c.vregoff(&p.From)
2554
2555 v := int32(d)
2556 r := int(p.From.Reg)
2557
2558 if r0iszero != 0 && p.To.Reg == 0 && (r != 0 || v != 0) {
2559 c.ctxt.Diag("literal operation on R0\n%v", p)
2560 }
2561 if int64(int16(d)) == d {
2562
2563 o1 = AOP_IRR(uint32(OP_ADDI), uint32(p.To.Reg), uint32(r), uint32(v))
2564 } else {
2565
2566 if int64(uint16(d)) != d || (r != 0 && r != REGZERO) {
2567 c.ctxt.Diag("Rule expects a uint16 constant load. got:\n%v", p)
2568 }
2569 o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
2570 }
2571
2572 case 4:
2573 v := c.regoff(&p.From)
2574
2575 r := int(p.Reg)
2576 if r == 0 {
2577 r = int(p.To.Reg)
2578 }
2579 if r0iszero != 0 && p.To.Reg == 0 {
2580 c.ctxt.Diag("literal operation on R0\n%v", p)
2581 }
2582 if int32(int16(v)) != v {
2583 log.Fatalf("mishandled instruction %v", p)
2584 }
2585 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2586
2587 case 5:
2588 o1 = c.oprrr(p.As)
2589
2590 case 6:
2591 r := int(p.Reg)
2592
2593 if r == 0 {
2594 r = int(p.To.Reg)
2595 }
2596
2597 switch p.As {
2598 case AROTL:
2599 o1 = AOP_MD(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
2600 case AROTLW:
2601 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
2602 default:
2603 if p.As == AOR && p.From.Type == obj.TYPE_CONST && p.From.Offset == 0 {
2604
2605
2606 o1 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(r), 0)
2607 } else {
2608 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2609 }
2610 }
2611
2612 case 7:
2613 r := int(p.To.Reg)
2614 v := c.regoff(&p.To)
2615 if int32(int16(v)) != v {
2616 log.Fatalf("mishandled instruction %v", p)
2617 }
2618
2619 inst := c.opstore(p.As)
2620 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2621 log.Fatalf("invalid offset for DS form load/store %v", p)
2622 }
2623 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
2624
2625 case 8:
2626 r := int(p.From.Reg)
2627 v := c.regoff(&p.From)
2628 if int32(int16(v)) != v {
2629 log.Fatalf("mishandled instruction %v", p)
2630 }
2631
2632 inst := c.opload(p.As)
2633 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2634 log.Fatalf("invalid offset for DS form load/store %v", p)
2635 }
2636 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
2637
2638
2639 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
2640
2641 case 9:
2642 sh := uint32(p.RestArgs[0].Addr.Offset) & 0x3F
2643 mb := uint32(p.RestArgs[1].Addr.Offset) & 0x3F
2644 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), (uint32(sh) & 0x1F))
2645 o1 |= (sh & 0x20) >> 4
2646 o1 |= (mb & 0x1F) << 6
2647 o1 |= (mb & 0x20)
2648
2649 case 10:
2650 r := int(p.Reg)
2651
2652 if r == 0 {
2653 r = int(p.To.Reg)
2654 }
2655 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
2656
2657 case 11:
2658 v := int32(0)
2659
2660 if p.To.Target() != nil {
2661 v = int32(p.To.Target().Pc - p.Pc)
2662 if v&03 != 0 {
2663 c.ctxt.Diag("odd branch target address\n%v", p)
2664 v &^= 03
2665 }
2666
2667 if v < -(1<<25) || v >= 1<<24 {
2668 c.ctxt.Diag("branch too far\n%v", p)
2669 }
2670 }
2671
2672 o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
2673 if p.To.Sym != nil {
2674 v += int32(p.To.Offset)
2675 if v&03 != 0 {
2676 c.ctxt.Diag("odd branch target address\n%v", p)
2677 v &^= 03
2678 }
2679 c.cursym.AddRel(c.ctxt, obj.Reloc{
2680 Type: objabi.R_CALLPOWER,
2681 Off: int32(c.pc),
2682 Siz: 4,
2683 Sym: p.To.Sym,
2684 Add: int64(v),
2685 })
2686 }
2687 o2 = NOP
2688
2689 case 13:
2690
2691
2692
2693 if p.From.Type == obj.TYPE_CONST {
2694 o1 = LOP_IRR(OP_ADDI, REGZERO, uint32(p.To.Reg), 0)
2695 break
2696 }
2697 if p.To.Type == obj.TYPE_CONST {
2698 c.ctxt.Diag("cannot move into constant 0\n%v", p)
2699 }
2700
2701 switch p.As {
2702 case AMOVB:
2703 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2704 case AMOVBZ:
2705 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
2706 case AMOVH:
2707 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2708 case AMOVHZ:
2709 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
2710 case AMOVW:
2711 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2712 case AMOVWZ:
2713 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5
2714 case AMOVD:
2715 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
2716 default:
2717 c.ctxt.Diag("internal: bad register move/truncation\n%v", p)
2718 }
2719
2720 case 14:
2721 r := uint32(p.Reg)
2722
2723 if r == 0 {
2724 r = uint32(p.To.Reg)
2725 }
2726 d := c.vregoff(p.GetFrom3())
2727 switch p.As {
2728
2729
2730
2731
2732 case ARLDCL, ARLDCLCC:
2733 mb, me, valid := decodeMask64(d)
2734 if me != 63 || !valid {
2735 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
2736 }
2737 o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), mb)
2738
2739 case ARLDCR, ARLDCRCC:
2740 mb, me, valid := decodeMask64(d)
2741 if mb != 0 || !valid {
2742 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p)
2743 }
2744 o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), me)
2745
2746
2747 case ARLDICR, ARLDICRCC:
2748 me := uint32(d)
2749 sh := c.regoff(&p.From)
2750 if me < 0 || me > 63 || sh > 63 {
2751 c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh, p)
2752 }
2753 o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), me)
2754
2755 case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
2756 mb := uint32(d)
2757 sh := c.regoff(&p.From)
2758 if mb < 0 || mb > 63 || sh > 63 {
2759 c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh, p)
2760 }
2761 o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), mb)
2762
2763 case ACLRLSLDI:
2764
2765
2766
2767
2768 n := int32(d)
2769 b := c.regoff(&p.From)
2770 if n > b || b > 63 {
2771 c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b, p)
2772 }
2773 o1 = AOP_MD(OP_RLDIC, uint32(p.To.Reg), uint32(r), uint32(n), uint32(b)-uint32(n))
2774
2775 default:
2776 c.ctxt.Diag("unexpected op in rldc case\n%v", p)
2777 }
2778
2779 case 16:
2780 a := 0
2781
2782 r := int(p.Reg)
2783
2784 if p.From.Type == obj.TYPE_CONST {
2785 a = int(c.regoff(&p.From))
2786 } else if p.From.Type == obj.TYPE_REG {
2787 if r != 0 {
2788 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
2789 }
2790
2791 switch p.From.Reg {
2792 case REG_CR0:
2793 r = BI_CR0
2794 case REG_CR1:
2795 r = BI_CR1
2796 case REG_CR2:
2797 r = BI_CR2
2798 case REG_CR3:
2799 r = BI_CR3
2800 case REG_CR4:
2801 r = BI_CR4
2802 case REG_CR5:
2803 r = BI_CR5
2804 case REG_CR6:
2805 r = BI_CR6
2806 case REG_CR7:
2807 r = BI_CR7
2808 default:
2809 c.ctxt.Diag("unrecognized register: expecting CR\n")
2810 }
2811 }
2812 v := int32(0)
2813 if p.To.Target() != nil {
2814 v = int32(p.To.Target().Pc - p.Pc)
2815 }
2816 if v&03 != 0 {
2817 c.ctxt.Diag("odd branch target address\n%v", p)
2818 v &^= 03
2819 }
2820
2821 if v < -(1<<16) || v >= 1<<15 {
2822 c.ctxt.Diag("branch too far\n%v", p)
2823 }
2824 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
2825
2826 case 17:
2827 var bo int32
2828 bi := int(p.Reg)
2829
2830 if p.From.Reg == REG_CR {
2831 c.ctxt.Diag("unrecognized register: expected CR0-CR7\n")
2832 }
2833 bi = int(p.From.Reg&0x7) * 4
2834
2835 bo = BO_BCR
2836
2837 switch p.As {
2838 case ABLT:
2839 bi += BI_LT
2840 case ABGT:
2841 bi += BI_GT
2842 case ABEQ:
2843 bi += BI_EQ
2844 case ABNE:
2845 bo = BO_NOTBCR
2846 bi += BI_EQ
2847 case ABLE:
2848 bo = BO_NOTBCR
2849 bi += BI_GT
2850 case ABGE:
2851 bo = BO_NOTBCR
2852 bi += BI_LT
2853 case ABVS:
2854 bi += BI_FU
2855 case ABVC:
2856 bo = BO_NOTBCR
2857 bi += BI_FU
2858 default:
2859 c.ctxt.Diag("unexpected instruction: expecting BGT, BEQ, BNE, BLE, BGE, BVS, BVC \n%v", p)
2860
2861 }
2862 if oclass(&p.To) == C_LR {
2863 o1 = OPVCC(19, 16, 0, 0)
2864 } else {
2865 c.ctxt.Diag("bad optab entry (17): %d\n%v", p.To.Class, p)
2866 }
2867
2868 o1 = OP_BCR(o1, uint32(bo), uint32(bi))
2869
2870 case 18:
2871 var v int32
2872 var bh uint32 = 0
2873 if p.As == ABC || p.As == ABCL {
2874 v = c.regoff(&p.From) & 31
2875 } else {
2876 v = 20
2877 }
2878 r := int(p.Reg)
2879 if r == 0 {
2880 r = 0
2881 }
2882 switch oclass(&p.To) {
2883 case C_CTR:
2884 o1 = OPVCC(19, 528, 0, 0)
2885
2886 case C_LR:
2887 o1 = OPVCC(19, 16, 0, 0)
2888
2889 default:
2890 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
2891 v = 0
2892 }
2893
2894
2895 if p.From3Type() != obj.TYPE_NONE {
2896 bh = uint32(p.GetFrom3().Offset)
2897 if bh == 2 || bh > 3 {
2898 log.Fatalf("BH must be 0,1,3 for %v", p)
2899 }
2900 o1 |= bh << 11
2901 }
2902
2903 if p.As == ABL || p.As == ABCL {
2904 o1 |= 1
2905 }
2906 o1 = OP_BCR(o1, uint32(v), uint32(r))
2907
2908 case 19:
2909 d := c.vregoff(&p.From)
2910 if o.ispfx {
2911 o1, o2 = pfxadd(p.To.Reg, REG_R0, PFX_R_ABS, d)
2912 } else {
2913 o1 = loadu32(int(p.To.Reg), d)
2914 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
2915 }
2916
2917 case 20:
2918 v := c.regoff(&p.From)
2919
2920 r := int(p.Reg)
2921 if r == 0 {
2922 r = int(p.To.Reg)
2923 }
2924 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2925
2926 case 21:
2927 var opu, opl uint32
2928 r := uint32(p.Reg)
2929 if r == 0 {
2930 r = uint32(p.To.Reg)
2931 }
2932 switch p.As {
2933 case AOR:
2934 opu, opl = OP_ORIS, OP_ORI
2935 case AXOR:
2936 opu, opl = OP_XORIS, OP_XORI
2937 default:
2938 c.ctxt.Diag("unhandled opcode.\n%v", p)
2939 }
2940 o1 = LOP_IRR(opu, uint32(p.To.Reg), r, uint32(p.From.Offset>>16))
2941 o2 = LOP_IRR(opl, uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.From.Offset)&0xFFFF)
2942
2943 case 22:
2944 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2945 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2946 }
2947 d := c.vregoff(&p.From)
2948 r := int(p.Reg)
2949 if r == 0 {
2950 r = int(p.To.Reg)
2951 }
2952 if p.From.Sym != nil {
2953 c.ctxt.Diag("%v is not supported", p)
2954 }
2955 if o.ispfx {
2956 o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, d)
2957 } else if o.size == 8 {
2958 o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))
2959 o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2960 } else if o.size == 12 {
2961
2962 o1 = loadu32(REGTMP, d)
2963 o2 = loadl16(REGTMP, d)
2964 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2965 } else {
2966
2967 o1 = LOP_IRR(OP_ADDIS, REGZERO, REGTMP, uint32(d>>32))
2968 o2 = loadl16(REGTMP, int64(d>>16))
2969 o3 = AOP_MD(OP_RLDICR, REGTMP, REGTMP, 16, 63-16)
2970 o4 = loadl16(REGTMP, int64(uint16(d)))
2971 o5 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2972 }
2973
2974 case 23:
2975 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2976 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2977 }
2978 d := c.vregoff(&p.From)
2979 r := int(p.Reg)
2980 if r == 0 {
2981 r = int(p.To.Reg)
2982 }
2983
2984
2985
2986 if o.size == 8 {
2987 o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
2988 o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2989 } else {
2990 o1 = loadu32(REGTMP, d)
2991 o2 = loadl16(REGTMP, d)
2992 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2993 }
2994 if p.From.Sym != nil {
2995 c.ctxt.Diag("%v is not supported", p)
2996 }
2997
2998 case 24:
2999 o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
3000
3001 if o.size == 8 {
3002 o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
3003 }
3004
3005 case 25:
3006
3007 v := c.regoff(&p.From)
3008
3009 if v < 0 {
3010 v = 0
3011 } else if v > 63 {
3012 v = 63
3013 }
3014 r := int(p.Reg)
3015 if r == 0 {
3016 r = int(p.To.Reg)
3017 }
3018 var a int
3019 op := uint32(0)
3020 switch p.As {
3021 case ASLD, ASLDCC:
3022 a = int(63 - v)
3023 op = OP_RLDICR
3024
3025 case ASRD, ASRDCC:
3026 a = int(v)
3027 v = 64 - v
3028 op = OP_RLDICL
3029 case AROTL:
3030 a = int(0)
3031 op = OP_RLDICL
3032 case AEXTSWSLI, AEXTSWSLICC:
3033 a = int(v)
3034 default:
3035 c.ctxt.Diag("unexpected op in sldi case\n%v", p)
3036 a = 0
3037 o1 = 0
3038 }
3039
3040 if p.As == AEXTSWSLI || p.As == AEXTSWSLICC {
3041 o1 = AOP_EXTSWSLI(OP_EXTSWSLI, uint32(r), uint32(p.To.Reg), uint32(v))
3042
3043 } else {
3044 o1 = AOP_MD(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
3045 }
3046 if p.As == ASLDCC || p.As == ASRDCC || p.As == AEXTSWSLICC {
3047 o1 |= 1
3048 }
3049
3050 case 26:
3051 v := c.vregoff(&p.From)
3052 r := int(p.From.Reg)
3053 var rel *obj.Reloc
3054
3055 switch p.From.Name {
3056 case obj.NAME_EXTERN, obj.NAME_STATIC:
3057
3058 var rel1 obj.Reloc
3059 o1, o2, rel1 = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI, true)
3060 rel = &rel1
3061 default:
3062
3063 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(int32(v))))
3064 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3065 }
3066
3067 if o.ispfx {
3068 if rel == nil {
3069 o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, v)
3070 } else {
3071 o1, o2 = pfxadd(int16(p.To.Reg), REG_R0, PFX_R_PCREL, 0)
3072 rel.Type = objabi.R_ADDRPOWER_PCREL34
3073 }
3074 }
3075 if rel != nil {
3076 c.cursym.AddRel(c.ctxt, *rel)
3077 }
3078
3079 case 27:
3080 v := c.regoff(p.GetFrom3())
3081
3082 r := int(p.From.Reg)
3083 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3084
3085 case 28:
3086 if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
3087 c.ctxt.Diag("can't synthesize large constant\n%v", p)
3088 }
3089 v := c.vregoff(p.GetFrom3())
3090 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
3091 o2 = loadl16(REGTMP, v)
3092 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
3093 if p.From.Sym != nil {
3094 c.ctxt.Diag("%v is not supported", p)
3095 }
3096
3097 case 29:
3098 sh := uint32(c.regoff(&p.From))
3099 d := c.vregoff(p.GetFrom3())
3100 mb, me, valid := decodeMask64(d)
3101 var a uint32
3102 switch p.As {
3103 case ARLDC, ARLDCCC:
3104 a = mb
3105 if me != (63-sh) || !valid {
3106 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3107 }
3108
3109 case ARLDCL, ARLDCLCC:
3110 a = mb
3111 if mb != 63 || !valid {
3112 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3113 }
3114
3115 case ARLDCR, ARLDCRCC:
3116 a = me
3117 if mb != 0 || !valid {
3118 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3119 }
3120
3121 default:
3122 c.ctxt.Diag("unexpected op in rldic case\n%v", p)
3123 }
3124 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, a)
3125
3126 case 30:
3127 sh := uint32(c.regoff(&p.From))
3128 d := c.vregoff(p.GetFrom3())
3129
3130
3131
3132 switch p.As {
3133 case ARLDMI, ARLDMICC:
3134 mb, me, valid := decodeMask64(d)
3135 if me != (63-sh) || !valid {
3136 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), me, sh, p)
3137 }
3138 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, mb)
3139
3140
3141 case ARLDIMI, ARLDIMICC:
3142 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, uint32(d))
3143 }
3144
3145 case 31:
3146 d := c.vregoff(&p.From)
3147
3148 if c.ctxt.Arch.ByteOrder == binary.BigEndian {
3149 o1 = uint32(d >> 32)
3150 o2 = uint32(d)
3151 } else {
3152 o1 = uint32(d)
3153 o2 = uint32(d >> 32)
3154 }
3155
3156 if p.From.Sym != nil {
3157 c.cursym.AddRel(c.ctxt, obj.Reloc{
3158 Type: objabi.R_ADDR,
3159 Off: int32(c.pc),
3160 Siz: 8,
3161 Sym: p.From.Sym,
3162 Add: p.From.Offset,
3163 })
3164 o2 = 0
3165 o1 = o2
3166 }
3167
3168 case 32:
3169 r := int(p.Reg)
3170
3171 if r == 0 {
3172 r = int(p.To.Reg)
3173 }
3174 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
3175
3176 case 33:
3177 r := int(p.From.Reg)
3178
3179 if oclass(&p.From) == C_NONE {
3180 r = int(p.To.Reg)
3181 }
3182 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
3183
3184 case 34:
3185 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
3186
3187 case 35:
3188 v := c.regoff(&p.To)
3189 r := int(p.To.Reg)
3190
3191 if o.ispfx {
3192 o1, o2 = pfxstore(p.As, p.From.Reg, int16(r), PFX_R_ABS)
3193 o1 |= uint32((v >> 16) & 0x3FFFF)
3194 o2 |= uint32(v & 0xFFFF)
3195 } else {
3196 inst := c.opstore(p.As)
3197 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3198 log.Fatalf("invalid offset for DS form load/store %v", p)
3199 }
3200 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
3201 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
3202 }
3203
3204 case 36:
3205 v := c.regoff(&p.From)
3206 r := int(p.From.Reg)
3207
3208 if o.ispfx {
3209 o1, o2 = pfxload(p.As, p.To.Reg, int16(r), PFX_R_ABS)
3210 o1 |= uint32((v >> 16) & 0x3FFFF)
3211 o2 |= uint32(v & 0xFFFF)
3212 } else {
3213 if o.a6 == C_REG {
3214
3215
3216 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
3217 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3218 } else {
3219 o1 = AOP_IRR(OP_ADDIS, uint32(REGTMP), uint32(r), uint32(high16adjusted(v)))
3220 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(REGTMP), uint32(v))
3221 }
3222 }
3223
3224
3225 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3226
3227 case 40:
3228 o1 = uint32(c.regoff(&p.From))
3229
3230 case 41:
3231 if p.To.Type == obj.TYPE_MEM && p.To.Index == 0 && p.To.Offset != 0 {
3232 c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
3233 }
3234
3235 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3236
3237 case 42:
3238 if p.From.Type == obj.TYPE_MEM && p.From.Index == 0 && p.From.Offset != 0 {
3239 c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
3240 }
3241 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3242
3243 case 43:
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254 if p.To.Type == obj.TYPE_NONE {
3255 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
3256 } else {
3257 th := c.regoff(&p.To)
3258 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
3259 }
3260
3261 case 44:
3262 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3263
3264 case 45:
3265 switch p.As {
3266
3267
3268
3269
3270 case ALBAR, ALHAR, ALWAR, ALDAR:
3271 if p.From3Type() != obj.TYPE_NONE {
3272 eh := int(c.regoff(p.GetFrom3()))
3273 if eh > 1 {
3274 c.ctxt.Diag("illegal EH field\n%v", p)
3275 }
3276 o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
3277 } else {
3278 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3279 }
3280 default:
3281 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3282 }
3283 case 46:
3284 o1 = c.oprrr(p.As)
3285
3286 case 47:
3287 r := int(p.From.Reg)
3288
3289 if r == 0 {
3290 r = int(p.To.Reg)
3291 }
3292 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3293
3294 case 48:
3295 r := int(p.From.Reg)
3296
3297 if r == 0 {
3298 r = int(p.To.Reg)
3299 }
3300 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3301
3302 case 49:
3303 if p.From.Type != obj.TYPE_REG {
3304 v := c.regoff(&p.From) & 1
3305 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
3306 } else {
3307 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
3308 }
3309
3310 case 50:
3311 r := int(p.Reg)
3312
3313 if r == 0 {
3314 r = int(p.To.Reg)
3315 }
3316 v := c.oprrr(p.As)
3317 t := v & (1<<10 | 1)
3318 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3319 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
3320 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3321 if p.As == AREMU {
3322 o4 = o3
3323
3324
3325 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
3326 }
3327
3328 case 51:
3329 r := int(p.Reg)
3330
3331 if r == 0 {
3332 r = int(p.To.Reg)
3333 }
3334 v := c.oprrr(p.As)
3335 t := v & (1<<10 | 1)
3336 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3337 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
3338 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3339
3340
3341
3342
3343 case 52:
3344 v := c.regoff(&p.From) & 31
3345
3346 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
3347
3348 case 53:
3349 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
3350
3351 case 55:
3352 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
3353
3354 case 56:
3355 v := c.regoff(&p.From)
3356
3357 r := int(p.Reg)
3358 if r == 0 {
3359 r = int(p.To.Reg)
3360 }
3361 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
3362 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
3363 o1 |= 1 << 1
3364 }
3365
3366 case 57:
3367 v := c.regoff(&p.From)
3368
3369 r := int(p.Reg)
3370 if r == 0 {
3371 r = int(p.To.Reg)
3372 }
3373
3374
3381 if v < 0 {
3382 v = 0
3383 } else if v > 32 {
3384 v = 32
3385 }
3386 var mask [2]uint8
3387 switch p.As {
3388 case AROTLW:
3389 mask[0], mask[1] = 0, 31
3390 case ASRW, ASRWCC:
3391 mask[0], mask[1] = uint8(v), 31
3392 v = 32 - v
3393 default:
3394 mask[0], mask[1] = 0, uint8(31-v)
3395 }
3396 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
3397 if p.As == ASLWCC || p.As == ASRWCC {
3398 o1 |= 1
3399 }
3400
3401 case 58:
3402 v := c.regoff(&p.From)
3403
3404 r := int(p.Reg)
3405 if r == 0 {
3406 r = int(p.To.Reg)
3407 }
3408 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3409
3410 case 60:
3411 r := int(c.regoff(&p.From) & 31)
3412
3413 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
3414
3415 case 61:
3416 r := int(c.regoff(&p.From) & 31)
3417
3418 v := c.regoff(&p.To)
3419 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
3420
3421 case 62:
3422 v := c.regoff(&p.From)
3423 n := c.regoff(p.GetFrom3())
3424
3425
3426
3427 if n > v || v >= 32 {
3428 c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, n, p)
3429 }
3430
3431 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(n), uint32(v-n), uint32(31-n))
3432
3433 case 63:
3434 var mb, me uint32
3435 if len(p.RestArgs) == 1 {
3436 var valid bool
3437
3438 mb, me, valid = decodeMask32(uint32(p.RestArgs[0].Addr.Offset))
3439 if !valid {
3440 c.ctxt.Diag("cannot generate mask #%x\n%v", uint64(p.RestArgs[0].Addr.Offset), p)
3441 }
3442 } else {
3443 mb, me = uint32(p.RestArgs[0].Addr.Offset), uint32(p.RestArgs[1].Addr.Offset)
3444 }
3445 if p.From.Type == obj.TYPE_CONST {
3446 o1 = OP_RLW(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Offset), mb, me)
3447 } else {
3448 o1 = OP_RLW(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), mb, me)
3449 }
3450
3451 case 64:
3452 var v int32
3453 if p.From3Type() != obj.TYPE_NONE {
3454 v = c.regoff(p.GetFrom3()) & 255
3455 } else {
3456 v = 255
3457 }
3458 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
3459
3460 case 65:
3461 if p.To.Reg == 0 {
3462 c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
3463 }
3464 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
3465
3466 case 66:
3467 var r int
3468 var v int32
3469 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
3470 r = int(p.From.Reg)
3471 v = int32(p.To.Reg)
3472 o1 = OPVCC(31, 467, 0, 0)
3473 } else {
3474 r = int(p.To.Reg)
3475 v = int32(p.From.Reg)
3476 o1 = OPVCC(31, 339, 0, 0)
3477 }
3478
3479 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3480
3481 case 67:
3482 if p.From.Reg == REG_CR || p.To.Reg == REG_CR {
3483 c.ctxt.Diag("CR argument must be a conditional register field (CR0-CR7)\n%v", p)
3484 }
3485 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
3486
3487 case 68:
3488 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0)
3489 if p.From.Reg != REG_CR {
3490 v := uint32(1) << uint(7-(p.From.Reg&7))
3491 o1 |= 1<<20 | v<<12
3492 }
3493
3494 case 69:
3495 var v uint32
3496 if p.To.Reg == REG_CR {
3497 v = 0xff
3498 } else if p.To.Offset != 0 {
3499 v = uint32(p.To.Offset)
3500 } else {
3501 v = 1 << uint(7-(p.To.Reg&7))
3502 }
3503
3504 if bits.OnesCount32(v) == 1 {
3505 v |= 1 << 8
3506 }
3507
3508 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12
3509
3510 case 70:
3511 r := uint32(p.Reg&7) << 2
3512 if p.To.Type == obj.TYPE_CONST {
3513 o1 = AOP_IRR(c.opirr(p.As), r, uint32(p.From.Reg), uint32(uint16(p.To.Offset)))
3514 } else {
3515 o1 = AOP_RRR(c.oprrr(p.As), r, uint32(p.From.Reg), uint32(p.To.Reg))
3516 }
3517
3518 case 72:
3519 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
3520
3521 case 73:
3522 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
3523 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
3524 }
3525 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
3526
3527 case 77:
3528 if p.From.Type == obj.TYPE_CONST {
3529 if p.From.Offset > BIG || p.From.Offset < -BIG {
3530 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
3531 }
3532 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
3533 } else if p.From.Type == obj.TYPE_REG {
3534 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
3535 } else {
3536 c.ctxt.Diag("illegal syscall: %v", p)
3537 o1 = 0x7fe00008
3538 }
3539
3540 o2 = c.oprrr(p.As)
3541 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO)
3542
3543 case 78:
3544 o1 = 0
3546
3547
3548 case 74:
3549 v := c.vregoff(&p.To)
3550
3551 inst := c.opstore(p.As)
3552
3553
3554 var rel obj.Reloc
3555 o1, o2, rel = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst, false)
3556
3557
3558 if o.ispfx {
3559 o1, o2 = pfxstore(p.As, p.From.Reg, REG_R0, PFX_R_PCREL)
3560 rel.Type = objabi.R_ADDRPOWER_PCREL34
3561 } else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3562 log.Fatalf("invalid offset for DS form load/store %v", p)
3563 }
3564 c.cursym.AddRel(c.ctxt, rel)
3565
3566 case 75:
3567 v := p.From.Offset
3568
3569
3570 inst := c.opload(p.As)
3571 var rel obj.Reloc
3572 switch p.From.Name {
3573 case obj.NAME_GOTREF, obj.NAME_TOCREF:
3574 if v != 0 {
3575 c.ctxt.Diag("invalid offset for GOT/TOC access %v", p)
3576 }
3577 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3578 o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3579 rel.Off = int32(c.pc)
3580 rel.Siz = 8
3581 rel.Sym = p.From.Sym
3582 switch p.From.Name {
3583 case obj.NAME_GOTREF:
3584 rel.Type = objabi.R_ADDRPOWER_GOT
3585 case obj.NAME_TOCREF:
3586 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
3587 }
3588 default:
3589 reuseBaseReg := o.a6 == C_REG
3590
3591 o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
3592 }
3593
3594
3595 if o.ispfx {
3596 switch rel.Type {
3597 case objabi.R_ADDRPOWER, objabi.R_ADDRPOWER_DS,
3598 objabi.R_ADDRPOWER_TOCREL, objabi.R_ADDRPOWER_TOCREL_DS:
3599 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3600 rel.Type = objabi.R_ADDRPOWER_PCREL34
3601 case objabi.R_POWER_TLS_IE:
3602 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3603 rel.Type = objabi.R_POWER_TLS_IE_PCREL34
3604 case objabi.R_ADDRPOWER_GOT:
3605 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3606 rel.Type = objabi.R_ADDRPOWER_GOT_PCREL34
3607 default:
3608
3609 log.Fatalf("Unable convert TOC-relative relocation %v to PC-relative", rel.Type)
3610 }
3611 } else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3612 log.Fatalf("invalid offset for DS form load/store %v", p)
3613 }
3614 c.cursym.AddRel(c.ctxt, rel)
3615
3616 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3617
3618 case 79:
3619 if p.From.Offset != 0 {
3620 c.ctxt.Diag("invalid offset against tls var %v", p)
3621 }
3622 var typ objabi.RelocType
3623 if !o.ispfx {
3624 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R13, 0)
3625 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3626 typ = objabi.R_POWER_TLS_LE
3627 } else {
3628 o1, o2 = pfxadd(p.To.Reg, REG_R13, PFX_R_ABS, 0)
3629 typ = objabi.R_POWER_TLS_LE_TPREL34
3630 }
3631 c.cursym.AddRel(c.ctxt, obj.Reloc{
3632 Type: typ,
3633 Off: int32(c.pc),
3634 Siz: 8,
3635 Sym: p.From.Sym,
3636 })
3637
3638 case 80:
3639 if p.From.Offset != 0 {
3640 c.ctxt.Diag("invalid offset against tls var %v", p)
3641 }
3642 typ := objabi.R_POWER_TLS_IE
3643 if !o.ispfx {
3644 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3645 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
3646 } else {
3647 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3648 typ = objabi.R_POWER_TLS_IE_PCREL34
3649 }
3650 c.cursym.AddRel(c.ctxt, obj.Reloc{
3651 Type: typ,
3652 Off: int32(c.pc),
3653 Siz: 8,
3654 Sym: p.From.Sym,
3655 })
3656 o3 = AOP_RRR(OP_ADD, uint32(p.To.Reg), uint32(p.To.Reg), REG_R13)
3657 c.cursym.AddRel(c.ctxt, obj.Reloc{
3658 Type: objabi.R_POWER_TLS,
3659 Off: int32(c.pc) + 8,
3660 Siz: 4,
3661 Sym: p.From.Sym,
3662 })
3663
3664 case 82:
3665 if p.From.Type == obj.TYPE_REG {
3666
3667
3668
3669 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3670 } else if p.From3Type() == obj.TYPE_CONST {
3671
3672
3673 six := int(c.regoff(&p.From))
3674 st := int(c.regoff(p.GetFrom3()))
3675 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
3676 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
3677
3678
3679 uim := int(c.regoff(&p.From))
3680 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
3681 } else {
3682
3683
3684 sim := int(c.regoff(&p.From))
3685 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
3686 }
3687
3688 case 83:
3689 if p.From.Type == obj.TYPE_REG {
3690
3691
3692 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3693 } else if p.From.Type == obj.TYPE_CONST {
3694
3695
3696 shb := int(c.regoff(&p.From))
3697 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
3698 }
3699
3700 case 84:
3701 bc := c.vregoff(&p.From)
3702 if o.a1 == C_CRBIT {
3703
3704 bc = int64(p.From.Reg)
3705 }
3706
3707
3708 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
3709
3710 case 85:
3711
3712
3713 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
3714
3715 case 86:
3716
3717
3718 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3719
3720 case 87:
3721
3722
3723 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3724
3725 case 88:
3726 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3727
3728 case 89:
3729
3730
3731 uim := int(c.regoff(p.GetFrom3()))
3732 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
3733
3734 case 90:
3735 if p.From3Type() == obj.TYPE_NONE {
3736
3737
3738 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3739 } else if p.From3Type() == obj.TYPE_CONST {
3740
3741
3742 dm := int(c.regoff(p.GetFrom3()))
3743 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
3744 }
3745
3746 case 91:
3747
3748
3749 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3750
3751 case 92:
3752 if p.To.Type == obj.TYPE_CONST {
3753
3754 xf := int32(p.From.Reg)
3755 if REG_F0 <= xf && xf <= REG_F31 {
3756
3757 bf := int(c.regoff(&p.To)) << 2
3758 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3759 } else {
3760
3761 l := int(c.regoff(&p.To))
3762 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
3763 }
3764 } else if p.From3Type() == obj.TYPE_CONST {
3765
3766
3767 l := int(c.regoff(p.GetFrom3()))
3768 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
3769 } else if p.To.Type == obj.TYPE_REG {
3770 cr := int32(p.To.Reg)
3771 if REG_CR0 <= cr && cr <= REG_CR7 {
3772
3773
3774 bf := (int(p.To.Reg) & 7) << 2
3775 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3776 } else if p.From.Type == obj.TYPE_CONST {
3777
3778
3779 l := int(c.regoff(&p.From))
3780 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
3781 } else {
3782 switch p.As {
3783 case ACOPY, APASTECC:
3784 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
3785 default:
3786
3787
3788 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3789 }
3790 }
3791 }
3792
3793 case 93:
3794 if p.To.Type == obj.TYPE_CONST {
3795
3796
3797 bf := int(c.regoff(&p.To)) << 2
3798 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
3799 } else if p.Reg == 0 {
3800
3801
3802 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3803 }
3804
3805 case 94:
3806
3807
3808 cy := int(c.regoff(p.GetFrom3()))
3809 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
3810
3811 case 96:
3812
3813
3814 dq := int16(c.regoff(&p.From))
3815 if (dq & 15) != 0 {
3816 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3817 }
3818 o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq))
3819
3820 case 97:
3821
3822
3823 dq := int16(c.regoff(&p.To))
3824 if (dq & 15) != 0 {
3825 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3826 }
3827 o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq))
3828 case 98:
3829
3830 o1 = AOP_XX1(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3831 case 99:
3832
3833 o1 = AOP_XX1(c.opstore(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
3834 case 100:
3835 if p.From.Type == obj.TYPE_CONST {
3836
3837 uim := int(c.regoff(&p.From))
3838
3839
3840 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(uim))
3841 } else {
3842 c.ctxt.Diag("invalid ops for %v", p.As)
3843 }
3844 case 101:
3845 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg))
3846
3847 case 104:
3848 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3849
3850 case 106:
3851 v := int32(p.From.Reg)
3852 o1 = OPVCC(31, 339, 0, 0)
3853 o1 = AOP_RRR(o1, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3854 so := c.regoff(&p.To)
3855 o2 = AOP_IRR(c.opstore(AMOVD), uint32(REGTMP), uint32(p.To.Reg), uint32(so))
3856 if so&0x3 != 0 {
3857 log.Fatalf("invalid offset for DS form load/store %v", p)
3858 }
3859 if p.To.Reg == REGTMP {
3860 log.Fatalf("SPR move to memory will clobber R31 %v", p)
3861 }
3862
3863 case 107:
3864 v := int32(p.From.Reg)
3865 so := c.regoff(&p.From)
3866 o1 = AOP_IRR(c.opload(AMOVD), uint32(REGTMP), uint32(v), uint32(so))
3867 o2 = OPVCC(31, 467, 0, 0)
3868 v = int32(p.To.Reg)
3869 o2 = AOP_RRR(o2, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3870 if so&0x3 != 0 {
3871 log.Fatalf("invalid offset for DS form load/store %v", p)
3872 }
3873
3874 case 108:
3875 r := int(p.To.Reg)
3876 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
3877
3878 case 109:
3879 r := int(p.From.Reg)
3880
3881 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
3882
3883 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3884
3885 case 110:
3886 bfa := uint32(p.From.Reg) << 2
3887 rt := uint32(p.To.Reg)
3888 o1 = LOP_RRR(OP_SETB, bfa, rt, 0)
3889 }
3890
3891 out[0] = o1
3892 out[1] = o2
3893 out[2] = o3
3894 out[3] = o4
3895 out[4] = o5
3896 }
3897
3898 func (c *ctxt9) vregoff(a *obj.Addr) int64 {
3899 c.instoffset = 0
3900 if a != nil {
3901 c.aclass(a)
3902 }
3903 return c.instoffset
3904 }
3905
3906 func (c *ctxt9) regoff(a *obj.Addr) int32 {
3907 return int32(c.vregoff(a))
3908 }
3909
3910 func (c *ctxt9) oprrr(a obj.As) uint32 {
3911 switch a {
3912 case AADD:
3913 return OPVCC(31, 266, 0, 0)
3914 case AADDCC:
3915 return OPVCC(31, 266, 0, 1)
3916 case AADDV:
3917 return OPVCC(31, 266, 1, 0)
3918 case AADDVCC:
3919 return OPVCC(31, 266, 1, 1)
3920 case AADDC:
3921 return OPVCC(31, 10, 0, 0)
3922 case AADDCCC:
3923 return OPVCC(31, 10, 0, 1)
3924 case AADDCV:
3925 return OPVCC(31, 10, 1, 0)
3926 case AADDCVCC:
3927 return OPVCC(31, 10, 1, 1)
3928 case AADDE:
3929 return OPVCC(31, 138, 0, 0)
3930 case AADDECC:
3931 return OPVCC(31, 138, 0, 1)
3932 case AADDEV:
3933 return OPVCC(31, 138, 1, 0)
3934 case AADDEVCC:
3935 return OPVCC(31, 138, 1, 1)
3936 case AADDME:
3937 return OPVCC(31, 234, 0, 0)
3938 case AADDMECC:
3939 return OPVCC(31, 234, 0, 1)
3940 case AADDMEV:
3941 return OPVCC(31, 234, 1, 0)
3942 case AADDMEVCC:
3943 return OPVCC(31, 234, 1, 1)
3944 case AADDZE:
3945 return OPVCC(31, 202, 0, 0)
3946 case AADDZECC:
3947 return OPVCC(31, 202, 0, 1)
3948 case AADDZEV:
3949 return OPVCC(31, 202, 1, 0)
3950 case AADDZEVCC:
3951 return OPVCC(31, 202, 1, 1)
3952 case AADDEX:
3953 return OPVCC(31, 170, 0, 0)
3954
3955 case AAND:
3956 return OPVCC(31, 28, 0, 0)
3957 case AANDCC:
3958 return OPVCC(31, 28, 0, 1)
3959 case AANDN:
3960 return OPVCC(31, 60, 0, 0)
3961 case AANDNCC:
3962 return OPVCC(31, 60, 0, 1)
3963
3964 case ACMP:
3965 return OPVCC(31, 0, 0, 0) | 1<<21
3966 case ACMPU:
3967 return OPVCC(31, 32, 0, 0) | 1<<21
3968 case ACMPW:
3969 return OPVCC(31, 0, 0, 0)
3970 case ACMPWU:
3971 return OPVCC(31, 32, 0, 0)
3972 case ACMPB:
3973 return OPVCC(31, 508, 0, 0)
3974 case ACMPEQB:
3975 return OPVCC(31, 224, 0, 0)
3976
3977 case ACNTLZW:
3978 return OPVCC(31, 26, 0, 0)
3979 case ACNTLZWCC:
3980 return OPVCC(31, 26, 0, 1)
3981 case ACNTLZD:
3982 return OPVCC(31, 58, 0, 0)
3983 case ACNTLZDCC:
3984 return OPVCC(31, 58, 0, 1)
3985
3986 case ACRAND:
3987 return OPVCC(19, 257, 0, 0)
3988 case ACRANDN:
3989 return OPVCC(19, 129, 0, 0)
3990 case ACREQV:
3991 return OPVCC(19, 289, 0, 0)
3992 case ACRNAND:
3993 return OPVCC(19, 225, 0, 0)
3994 case ACRNOR:
3995 return OPVCC(19, 33, 0, 0)
3996 case ACROR:
3997 return OPVCC(19, 449, 0, 0)
3998 case ACRORN:
3999 return OPVCC(19, 417, 0, 0)
4000 case ACRXOR:
4001 return OPVCC(19, 193, 0, 0)
4002
4003 case ADADD:
4004 return OPVCC(59, 2, 0, 0)
4005 case ADDIV:
4006 return OPVCC(59, 546, 0, 0)
4007 case ADMUL:
4008 return OPVCC(59, 34, 0, 0)
4009 case ADSUB:
4010 return OPVCC(59, 514, 0, 0)
4011
4012 case ADCBF:
4013 return OPVCC(31, 86, 0, 0)
4014 case ADCBI:
4015 return OPVCC(31, 470, 0, 0)
4016 case ADCBST:
4017 return OPVCC(31, 54, 0, 0)
4018 case ADCBT:
4019 return OPVCC(31, 278, 0, 0)
4020 case ADCBTST:
4021 return OPVCC(31, 246, 0, 0)
4022 case ADCBZ:
4023 return OPVCC(31, 1014, 0, 0)
4024
4025 case AMODUD:
4026 return OPVCC(31, 265, 0, 0)
4027 case AMODUW:
4028 return OPVCC(31, 267, 0, 0)
4029 case AMODSD:
4030 return OPVCC(31, 777, 0, 0)
4031 case AMODSW:
4032 return OPVCC(31, 779, 0, 0)
4033
4034 case ADIVW, AREM:
4035 return OPVCC(31, 491, 0, 0)
4036
4037 case ADIVWCC:
4038 return OPVCC(31, 491, 0, 1)
4039
4040 case ADIVWV:
4041 return OPVCC(31, 491, 1, 0)
4042
4043 case ADIVWVCC:
4044 return OPVCC(31, 491, 1, 1)
4045
4046 case ADIVWU, AREMU:
4047 return OPVCC(31, 459, 0, 0)
4048
4049 case ADIVWUCC:
4050 return OPVCC(31, 459, 0, 1)
4051
4052 case ADIVWUV:
4053 return OPVCC(31, 459, 1, 0)
4054
4055 case ADIVWUVCC:
4056 return OPVCC(31, 459, 1, 1)
4057
4058 case ADIVD, AREMD:
4059 return OPVCC(31, 489, 0, 0)
4060
4061 case ADIVDCC:
4062 return OPVCC(31, 489, 0, 1)
4063
4064 case ADIVDE:
4065 return OPVCC(31, 425, 0, 0)
4066
4067 case ADIVDECC:
4068 return OPVCC(31, 425, 0, 1)
4069
4070 case ADIVDEU:
4071 return OPVCC(31, 393, 0, 0)
4072
4073 case ADIVDEUCC:
4074 return OPVCC(31, 393, 0, 1)
4075
4076 case ADIVDV:
4077 return OPVCC(31, 489, 1, 0)
4078
4079 case ADIVDVCC:
4080 return OPVCC(31, 489, 1, 1)
4081
4082 case ADIVDU, AREMDU:
4083 return OPVCC(31, 457, 0, 0)
4084
4085 case ADIVDUCC:
4086 return OPVCC(31, 457, 0, 1)
4087
4088 case ADIVDUV:
4089 return OPVCC(31, 457, 1, 0)
4090
4091 case ADIVDUVCC:
4092 return OPVCC(31, 457, 1, 1)
4093
4094 case AEIEIO:
4095 return OPVCC(31, 854, 0, 0)
4096
4097 case AEQV:
4098 return OPVCC(31, 284, 0, 0)
4099 case AEQVCC:
4100 return OPVCC(31, 284, 0, 1)
4101
4102 case AEXTSB:
4103 return OPVCC(31, 954, 0, 0)
4104 case AEXTSBCC:
4105 return OPVCC(31, 954, 0, 1)
4106 case AEXTSH:
4107 return OPVCC(31, 922, 0, 0)
4108 case AEXTSHCC:
4109 return OPVCC(31, 922, 0, 1)
4110 case AEXTSW:
4111 return OPVCC(31, 986, 0, 0)
4112 case AEXTSWCC:
4113 return OPVCC(31, 986, 0, 1)
4114
4115 case AFABS:
4116 return OPVCC(63, 264, 0, 0)
4117 case AFABSCC:
4118 return OPVCC(63, 264, 0, 1)
4119 case AFADD:
4120 return OPVCC(63, 21, 0, 0)
4121 case AFADDCC:
4122 return OPVCC(63, 21, 0, 1)
4123 case AFADDS:
4124 return OPVCC(59, 21, 0, 0)
4125 case AFADDSCC:
4126 return OPVCC(59, 21, 0, 1)
4127 case AFCMPO:
4128 return OPVCC(63, 32, 0, 0)
4129 case AFCMPU:
4130 return OPVCC(63, 0, 0, 0)
4131 case AFCFID:
4132 return OPVCC(63, 846, 0, 0)
4133 case AFCFIDCC:
4134 return OPVCC(63, 846, 0, 1)
4135 case AFCFIDU:
4136 return OPVCC(63, 974, 0, 0)
4137 case AFCFIDUCC:
4138 return OPVCC(63, 974, 0, 1)
4139 case AFCFIDS:
4140 return OPVCC(59, 846, 0, 0)
4141 case AFCFIDSCC:
4142 return OPVCC(59, 846, 0, 1)
4143 case AFCTIW:
4144 return OPVCC(63, 14, 0, 0)
4145 case AFCTIWCC:
4146 return OPVCC(63, 14, 0, 1)
4147 case AFCTIWZ:
4148 return OPVCC(63, 15, 0, 0)
4149 case AFCTIWZCC:
4150 return OPVCC(63, 15, 0, 1)
4151 case AFCTID:
4152 return OPVCC(63, 814, 0, 0)
4153 case AFCTIDCC:
4154 return OPVCC(63, 814, 0, 1)
4155 case AFCTIDZ:
4156 return OPVCC(63, 815, 0, 0)
4157 case AFCTIDZCC:
4158 return OPVCC(63, 815, 0, 1)
4159 case AFDIV:
4160 return OPVCC(63, 18, 0, 0)
4161 case AFDIVCC:
4162 return OPVCC(63, 18, 0, 1)
4163 case AFDIVS:
4164 return OPVCC(59, 18, 0, 0)
4165 case AFDIVSCC:
4166 return OPVCC(59, 18, 0, 1)
4167 case AFMADD:
4168 return OPVCC(63, 29, 0, 0)
4169 case AFMADDCC:
4170 return OPVCC(63, 29, 0, 1)
4171 case AFMADDS:
4172 return OPVCC(59, 29, 0, 0)
4173 case AFMADDSCC:
4174 return OPVCC(59, 29, 0, 1)
4175
4176 case AFMOVS, AFMOVD:
4177 return OPVCC(63, 72, 0, 0)
4178 case AFMOVDCC:
4179 return OPVCC(63, 72, 0, 1)
4180 case AFMSUB:
4181 return OPVCC(63, 28, 0, 0)
4182 case AFMSUBCC:
4183 return OPVCC(63, 28, 0, 1)
4184 case AFMSUBS:
4185 return OPVCC(59, 28, 0, 0)
4186 case AFMSUBSCC:
4187 return OPVCC(59, 28, 0, 1)
4188 case AFMUL:
4189 return OPVCC(63, 25, 0, 0)
4190 case AFMULCC:
4191 return OPVCC(63, 25, 0, 1)
4192 case AFMULS:
4193 return OPVCC(59, 25, 0, 0)
4194 case AFMULSCC:
4195 return OPVCC(59, 25, 0, 1)
4196 case AFNABS:
4197 return OPVCC(63, 136, 0, 0)
4198 case AFNABSCC:
4199 return OPVCC(63, 136, 0, 1)
4200 case AFNEG:
4201 return OPVCC(63, 40, 0, 0)
4202 case AFNEGCC:
4203 return OPVCC(63, 40, 0, 1)
4204 case AFNMADD:
4205 return OPVCC(63, 31, 0, 0)
4206 case AFNMADDCC:
4207 return OPVCC(63, 31, 0, 1)
4208 case AFNMADDS:
4209 return OPVCC(59, 31, 0, 0)
4210 case AFNMADDSCC:
4211 return OPVCC(59, 31, 0, 1)
4212 case AFNMSUB:
4213 return OPVCC(63, 30, 0, 0)
4214 case AFNMSUBCC:
4215 return OPVCC(63, 30, 0, 1)
4216 case AFNMSUBS:
4217 return OPVCC(59, 30, 0, 0)
4218 case AFNMSUBSCC:
4219 return OPVCC(59, 30, 0, 1)
4220 case AFCPSGN:
4221 return OPVCC(63, 8, 0, 0)
4222 case AFCPSGNCC:
4223 return OPVCC(63, 8, 0, 1)
4224 case AFRES:
4225 return OPVCC(59, 24, 0, 0)
4226 case AFRESCC:
4227 return OPVCC(59, 24, 0, 1)
4228 case AFRIM:
4229 return OPVCC(63, 488, 0, 0)
4230 case AFRIMCC:
4231 return OPVCC(63, 488, 0, 1)
4232 case AFRIP:
4233 return OPVCC(63, 456, 0, 0)
4234 case AFRIPCC:
4235 return OPVCC(63, 456, 0, 1)
4236 case AFRIZ:
4237 return OPVCC(63, 424, 0, 0)
4238 case AFRIZCC:
4239 return OPVCC(63, 424, 0, 1)
4240 case AFRIN:
4241 return OPVCC(63, 392, 0, 0)
4242 case AFRINCC:
4243 return OPVCC(63, 392, 0, 1)
4244 case AFRSP:
4245 return OPVCC(63, 12, 0, 0)
4246 case AFRSPCC:
4247 return OPVCC(63, 12, 0, 1)
4248 case AFRSQRTE:
4249 return OPVCC(63, 26, 0, 0)
4250 case AFRSQRTECC:
4251 return OPVCC(63, 26, 0, 1)
4252 case AFSEL:
4253 return OPVCC(63, 23, 0, 0)
4254 case AFSELCC:
4255 return OPVCC(63, 23, 0, 1)
4256 case AFSQRT:
4257 return OPVCC(63, 22, 0, 0)
4258 case AFSQRTCC:
4259 return OPVCC(63, 22, 0, 1)
4260 case AFSQRTS:
4261 return OPVCC(59, 22, 0, 0)
4262 case AFSQRTSCC:
4263 return OPVCC(59, 22, 0, 1)
4264 case AFSUB:
4265 return OPVCC(63, 20, 0, 0)
4266 case AFSUBCC:
4267 return OPVCC(63, 20, 0, 1)
4268 case AFSUBS:
4269 return OPVCC(59, 20, 0, 0)
4270 case AFSUBSCC:
4271 return OPVCC(59, 20, 0, 1)
4272
4273 case AICBI:
4274 return OPVCC(31, 982, 0, 0)
4275 case AISYNC:
4276 return OPVCC(19, 150, 0, 0)
4277
4278 case AMTFSB0:
4279 return OPVCC(63, 70, 0, 0)
4280 case AMTFSB0CC:
4281 return OPVCC(63, 70, 0, 1)
4282 case AMTFSB1:
4283 return OPVCC(63, 38, 0, 0)
4284 case AMTFSB1CC:
4285 return OPVCC(63, 38, 0, 1)
4286
4287 case AMULHW:
4288 return OPVCC(31, 75, 0, 0)
4289 case AMULHWCC:
4290 return OPVCC(31, 75, 0, 1)
4291 case AMULHWU:
4292 return OPVCC(31, 11, 0, 0)
4293 case AMULHWUCC:
4294 return OPVCC(31, 11, 0, 1)
4295 case AMULLW:
4296 return OPVCC(31, 235, 0, 0)
4297 case AMULLWCC:
4298 return OPVCC(31, 235, 0, 1)
4299 case AMULLWV:
4300 return OPVCC(31, 235, 1, 0)
4301 case AMULLWVCC:
4302 return OPVCC(31, 235, 1, 1)
4303
4304 case AMULHD:
4305 return OPVCC(31, 73, 0, 0)
4306 case AMULHDCC:
4307 return OPVCC(31, 73, 0, 1)
4308 case AMULHDU:
4309 return OPVCC(31, 9, 0, 0)
4310 case AMULHDUCC:
4311 return OPVCC(31, 9, 0, 1)
4312 case AMULLD:
4313 return OPVCC(31, 233, 0, 0)
4314 case AMULLDCC:
4315 return OPVCC(31, 233, 0, 1)
4316 case AMULLDV:
4317 return OPVCC(31, 233, 1, 0)
4318 case AMULLDVCC:
4319 return OPVCC(31, 233, 1, 1)
4320
4321 case ANAND:
4322 return OPVCC(31, 476, 0, 0)
4323 case ANANDCC:
4324 return OPVCC(31, 476, 0, 1)
4325 case ANEG:
4326 return OPVCC(31, 104, 0, 0)
4327 case ANEGCC:
4328 return OPVCC(31, 104, 0, 1)
4329 case ANEGV:
4330 return OPVCC(31, 104, 1, 0)
4331 case ANEGVCC:
4332 return OPVCC(31, 104, 1, 1)
4333 case ANOR:
4334 return OPVCC(31, 124, 0, 0)
4335 case ANORCC:
4336 return OPVCC(31, 124, 0, 1)
4337 case AOR:
4338 return OPVCC(31, 444, 0, 0)
4339 case AORCC:
4340 return OPVCC(31, 444, 0, 1)
4341 case AORN:
4342 return OPVCC(31, 412, 0, 0)
4343 case AORNCC:
4344 return OPVCC(31, 412, 0, 1)
4345
4346 case APOPCNTD:
4347 return OPVCC(31, 506, 0, 0)
4348 case APOPCNTW:
4349 return OPVCC(31, 378, 0, 0)
4350 case APOPCNTB:
4351 return OPVCC(31, 122, 0, 0)
4352 case ACNTTZW:
4353 return OPVCC(31, 538, 0, 0)
4354 case ACNTTZWCC:
4355 return OPVCC(31, 538, 0, 1)
4356 case ACNTTZD:
4357 return OPVCC(31, 570, 0, 0)
4358 case ACNTTZDCC:
4359 return OPVCC(31, 570, 0, 1)
4360
4361 case ARFI:
4362 return OPVCC(19, 50, 0, 0)
4363 case ARFCI:
4364 return OPVCC(19, 51, 0, 0)
4365 case ARFID:
4366 return OPVCC(19, 18, 0, 0)
4367 case AHRFID:
4368 return OPVCC(19, 274, 0, 0)
4369
4370 case ARLWNM:
4371 return OPVCC(23, 0, 0, 0)
4372 case ARLWNMCC:
4373 return OPVCC(23, 0, 0, 1)
4374
4375 case ARLDCL:
4376 return OPVCC(30, 8, 0, 0)
4377 case ARLDCLCC:
4378 return OPVCC(30, 0, 0, 1)
4379
4380 case ARLDCR:
4381 return OPVCC(30, 9, 0, 0)
4382 case ARLDCRCC:
4383 return OPVCC(30, 9, 0, 1)
4384
4385 case ARLDICL:
4386 return OPVCC(30, 0, 0, 0)
4387 case ARLDICLCC:
4388 return OPVCC(30, 0, 0, 1)
4389 case ARLDICR:
4390 return OPMD(30, 1, 0)
4391 case ARLDICRCC:
4392 return OPMD(30, 1, 1)
4393
4394 case ARLDIC:
4395 return OPMD(30, 2, 0)
4396 case ARLDICCC:
4397 return OPMD(30, 2, 1)
4398
4399 case ASYSCALL:
4400 return OPVCC(17, 1, 0, 0)
4401
4402 case ASLW:
4403 return OPVCC(31, 24, 0, 0)
4404 case ASLWCC:
4405 return OPVCC(31, 24, 0, 1)
4406 case ASLD:
4407 return OPVCC(31, 27, 0, 0)
4408 case ASLDCC:
4409 return OPVCC(31, 27, 0, 1)
4410
4411 case ASRAW:
4412 return OPVCC(31, 792, 0, 0)
4413 case ASRAWCC:
4414 return OPVCC(31, 792, 0, 1)
4415 case ASRAD:
4416 return OPVCC(31, 794, 0, 0)
4417 case ASRADCC:
4418 return OPVCC(31, 794, 0, 1)
4419
4420 case AEXTSWSLI:
4421 return OPVCC(31, 445, 0, 0)
4422 case AEXTSWSLICC:
4423 return OPVCC(31, 445, 0, 1)
4424
4425 case ASRW:
4426 return OPVCC(31, 536, 0, 0)
4427 case ASRWCC:
4428 return OPVCC(31, 536, 0, 1)
4429 case ASRD:
4430 return OPVCC(31, 539, 0, 0)
4431 case ASRDCC:
4432 return OPVCC(31, 539, 0, 1)
4433
4434 case ASUB:
4435 return OPVCC(31, 40, 0, 0)
4436 case ASUBCC:
4437 return OPVCC(31, 40, 0, 1)
4438 case ASUBV:
4439 return OPVCC(31, 40, 1, 0)
4440 case ASUBVCC:
4441 return OPVCC(31, 40, 1, 1)
4442 case ASUBC:
4443 return OPVCC(31, 8, 0, 0)
4444 case ASUBCCC:
4445 return OPVCC(31, 8, 0, 1)
4446 case ASUBCV:
4447 return OPVCC(31, 8, 1, 0)
4448 case ASUBCVCC:
4449 return OPVCC(31, 8, 1, 1)
4450 case ASUBE:
4451 return OPVCC(31, 136, 0, 0)
4452 case ASUBECC:
4453 return OPVCC(31, 136, 0, 1)
4454 case ASUBEV:
4455 return OPVCC(31, 136, 1, 0)
4456 case ASUBEVCC:
4457 return OPVCC(31, 136, 1, 1)
4458 case ASUBME:
4459 return OPVCC(31, 232, 0, 0)
4460 case ASUBMECC:
4461 return OPVCC(31, 232, 0, 1)
4462 case ASUBMEV:
4463 return OPVCC(31, 232, 1, 0)
4464 case ASUBMEVCC:
4465 return OPVCC(31, 232, 1, 1)
4466 case ASUBZE:
4467 return OPVCC(31, 200, 0, 0)
4468 case ASUBZECC:
4469 return OPVCC(31, 200, 0, 1)
4470 case ASUBZEV:
4471 return OPVCC(31, 200, 1, 0)
4472 case ASUBZEVCC:
4473 return OPVCC(31, 200, 1, 1)
4474
4475 case ASYNC:
4476 return OPVCC(31, 598, 0, 0)
4477 case ALWSYNC:
4478 return OPVCC(31, 598, 0, 0) | 1<<21
4479
4480 case APTESYNC:
4481 return OPVCC(31, 598, 0, 0) | 2<<21
4482
4483 case ATLBIE:
4484 return OPVCC(31, 306, 0, 0)
4485 case ATLBIEL:
4486 return OPVCC(31, 274, 0, 0)
4487 case ATLBSYNC:
4488 return OPVCC(31, 566, 0, 0)
4489 case ASLBIA:
4490 return OPVCC(31, 498, 0, 0)
4491 case ASLBIE:
4492 return OPVCC(31, 434, 0, 0)
4493 case ASLBMFEE:
4494 return OPVCC(31, 915, 0, 0)
4495 case ASLBMFEV:
4496 return OPVCC(31, 851, 0, 0)
4497 case ASLBMTE:
4498 return OPVCC(31, 402, 0, 0)
4499
4500 case ATW:
4501 return OPVCC(31, 4, 0, 0)
4502 case ATD:
4503 return OPVCC(31, 68, 0, 0)
4504
4505
4506
4507
4508 case AVAND:
4509 return OPVX(4, 1028, 0, 0)
4510 case AVANDC:
4511 return OPVX(4, 1092, 0, 0)
4512 case AVNAND:
4513 return OPVX(4, 1412, 0, 0)
4514
4515 case AVOR:
4516 return OPVX(4, 1156, 0, 0)
4517 case AVORC:
4518 return OPVX(4, 1348, 0, 0)
4519 case AVNOR:
4520 return OPVX(4, 1284, 0, 0)
4521 case AVXOR:
4522 return OPVX(4, 1220, 0, 0)
4523 case AVEQV:
4524 return OPVX(4, 1668, 0, 0)
4525
4526 case AVADDUBM:
4527 return OPVX(4, 0, 0, 0)
4528 case AVADDUHM:
4529 return OPVX(4, 64, 0, 0)
4530 case AVADDUWM:
4531 return OPVX(4, 128, 0, 0)
4532 case AVADDUDM:
4533 return OPVX(4, 192, 0, 0)
4534 case AVADDUQM:
4535 return OPVX(4, 256, 0, 0)
4536
4537 case AVADDCUQ:
4538 return OPVX(4, 320, 0, 0)
4539 case AVADDCUW:
4540 return OPVX(4, 384, 0, 0)
4541
4542 case AVADDUBS:
4543 return OPVX(4, 512, 0, 0)
4544 case AVADDUHS:
4545 return OPVX(4, 576, 0, 0)
4546 case AVADDUWS:
4547 return OPVX(4, 640, 0, 0)
4548
4549 case AVADDSBS:
4550 return OPVX(4, 768, 0, 0)
4551 case AVADDSHS:
4552 return OPVX(4, 832, 0, 0)
4553 case AVADDSWS:
4554 return OPVX(4, 896, 0, 0)
4555
4556 case AVADDEUQM:
4557 return OPVX(4, 60, 0, 0)
4558 case AVADDECUQ:
4559 return OPVX(4, 61, 0, 0)
4560
4561 case AVMULESB:
4562 return OPVX(4, 776, 0, 0)
4563 case AVMULOSB:
4564 return OPVX(4, 264, 0, 0)
4565 case AVMULEUB:
4566 return OPVX(4, 520, 0, 0)
4567 case AVMULOUB:
4568 return OPVX(4, 8, 0, 0)
4569 case AVMULESH:
4570 return OPVX(4, 840, 0, 0)
4571 case AVMULOSH:
4572 return OPVX(4, 328, 0, 0)
4573 case AVMULEUH:
4574 return OPVX(4, 584, 0, 0)
4575 case AVMULOUH:
4576 return OPVX(4, 72, 0, 0)
4577 case AVMULESW:
4578 return OPVX(4, 904, 0, 0)
4579 case AVMULOSW:
4580 return OPVX(4, 392, 0, 0)
4581 case AVMULEUW:
4582 return OPVX(4, 648, 0, 0)
4583 case AVMULOUW:
4584 return OPVX(4, 136, 0, 0)
4585 case AVMULUWM:
4586 return OPVX(4, 137, 0, 0)
4587
4588 case AVPMSUMB:
4589 return OPVX(4, 1032, 0, 0)
4590 case AVPMSUMH:
4591 return OPVX(4, 1096, 0, 0)
4592 case AVPMSUMW:
4593 return OPVX(4, 1160, 0, 0)
4594 case AVPMSUMD:
4595 return OPVX(4, 1224, 0, 0)
4596
4597 case AVMSUMUDM:
4598 return OPVX(4, 35, 0, 0)
4599
4600 case AVSUBUBM:
4601 return OPVX(4, 1024, 0, 0)
4602 case AVSUBUHM:
4603 return OPVX(4, 1088, 0, 0)
4604 case AVSUBUWM:
4605 return OPVX(4, 1152, 0, 0)
4606 case AVSUBUDM:
4607 return OPVX(4, 1216, 0, 0)
4608 case AVSUBUQM:
4609 return OPVX(4, 1280, 0, 0)
4610
4611 case AVSUBCUQ:
4612 return OPVX(4, 1344, 0, 0)
4613 case AVSUBCUW:
4614 return OPVX(4, 1408, 0, 0)
4615
4616 case AVSUBUBS:
4617 return OPVX(4, 1536, 0, 0)
4618 case AVSUBUHS:
4619 return OPVX(4, 1600, 0, 0)
4620 case AVSUBUWS:
4621 return OPVX(4, 1664, 0, 0)
4622
4623 case AVSUBSBS:
4624 return OPVX(4, 1792, 0, 0)
4625 case AVSUBSHS:
4626 return OPVX(4, 1856, 0, 0)
4627 case AVSUBSWS:
4628 return OPVX(4, 1920, 0, 0)
4629
4630 case AVSUBEUQM:
4631 return OPVX(4, 62, 0, 0)
4632 case AVSUBECUQ:
4633 return OPVX(4, 63, 0, 0)
4634
4635 case AVRLB:
4636 return OPVX(4, 4, 0, 0)
4637 case AVRLH:
4638 return OPVX(4, 68, 0, 0)
4639 case AVRLW:
4640 return OPVX(4, 132, 0, 0)
4641 case AVRLD:
4642 return OPVX(4, 196, 0, 0)
4643
4644 case AVMRGOW:
4645 return OPVX(4, 1676, 0, 0)
4646 case AVMRGEW:
4647 return OPVX(4, 1932, 0, 0)
4648
4649 case AVSLB:
4650 return OPVX(4, 260, 0, 0)
4651 case AVSLH:
4652 return OPVX(4, 324, 0, 0)
4653 case AVSLW:
4654 return OPVX(4, 388, 0, 0)
4655 case AVSL:
4656 return OPVX(4, 452, 0, 0)
4657 case AVSLO:
4658 return OPVX(4, 1036, 0, 0)
4659 case AVSRB:
4660 return OPVX(4, 516, 0, 0)
4661 case AVSRH:
4662 return OPVX(4, 580, 0, 0)
4663 case AVSRW:
4664 return OPVX(4, 644, 0, 0)
4665 case AVSR:
4666 return OPVX(4, 708, 0, 0)
4667 case AVSRO:
4668 return OPVX(4, 1100, 0, 0)
4669 case AVSLD:
4670 return OPVX(4, 1476, 0, 0)
4671 case AVSRD:
4672 return OPVX(4, 1732, 0, 0)
4673
4674 case AVSRAB:
4675 return OPVX(4, 772, 0, 0)
4676 case AVSRAH:
4677 return OPVX(4, 836, 0, 0)
4678 case AVSRAW:
4679 return OPVX(4, 900, 0, 0)
4680 case AVSRAD:
4681 return OPVX(4, 964, 0, 0)
4682
4683 case AVBPERMQ:
4684 return OPVC(4, 1356, 0, 0)
4685 case AVBPERMD:
4686 return OPVC(4, 1484, 0, 0)
4687
4688 case AVCLZB:
4689 return OPVX(4, 1794, 0, 0)
4690 case AVCLZH:
4691 return OPVX(4, 1858, 0, 0)
4692 case AVCLZW:
4693 return OPVX(4, 1922, 0, 0)
4694 case AVCLZD:
4695 return OPVX(4, 1986, 0, 0)
4696
4697 case AVCLZLSBB:
4698 return OPVX(4, 1538, 0, 0)
4699 case AVCTZLSBB:
4700 return OPVX(4, 1538, 0, 0) | 1<<16
4701
4702 case AVPOPCNTB:
4703 return OPVX(4, 1795, 0, 0)
4704 case AVPOPCNTH:
4705 return OPVX(4, 1859, 0, 0)
4706 case AVPOPCNTW:
4707 return OPVX(4, 1923, 0, 0)
4708 case AVPOPCNTD:
4709 return OPVX(4, 1987, 0, 0)
4710
4711 case AVCMPEQUB:
4712 return OPVC(4, 6, 0, 0)
4713 case AVCMPEQUBCC:
4714 return OPVC(4, 6, 0, 1)
4715 case AVCMPEQUH:
4716 return OPVC(4, 70, 0, 0)
4717 case AVCMPEQUHCC:
4718 return OPVC(4, 70, 0, 1)
4719 case AVCMPEQUW:
4720 return OPVC(4, 134, 0, 0)
4721 case AVCMPEQUWCC:
4722 return OPVC(4, 134, 0, 1)
4723 case AVCMPEQUD:
4724 return OPVC(4, 199, 0, 0)
4725 case AVCMPEQUDCC:
4726 return OPVC(4, 199, 0, 1)
4727
4728 case AVCMPGTUB:
4729 return OPVC(4, 518, 0, 0)
4730 case AVCMPGTUBCC:
4731 return OPVC(4, 518, 0, 1)
4732 case AVCMPGTUH:
4733 return OPVC(4, 582, 0, 0)
4734 case AVCMPGTUHCC:
4735 return OPVC(4, 582, 0, 1)
4736 case AVCMPGTUW:
4737 return OPVC(4, 646, 0, 0)
4738 case AVCMPGTUWCC:
4739 return OPVC(4, 646, 0, 1)
4740 case AVCMPGTUD:
4741 return OPVC(4, 711, 0, 0)
4742 case AVCMPGTUDCC:
4743 return OPVC(4, 711, 0, 1)
4744 case AVCMPGTSB:
4745 return OPVC(4, 774, 0, 0)
4746 case AVCMPGTSBCC:
4747 return OPVC(4, 774, 0, 1)
4748 case AVCMPGTSH:
4749 return OPVC(4, 838, 0, 0)
4750 case AVCMPGTSHCC:
4751 return OPVC(4, 838, 0, 1)
4752 case AVCMPGTSW:
4753 return OPVC(4, 902, 0, 0)
4754 case AVCMPGTSWCC:
4755 return OPVC(4, 902, 0, 1)
4756 case AVCMPGTSD:
4757 return OPVC(4, 967, 0, 0)
4758 case AVCMPGTSDCC:
4759 return OPVC(4, 967, 0, 1)
4760
4761 case AVCMPNEZB:
4762 return OPVC(4, 263, 0, 0)
4763 case AVCMPNEZBCC:
4764 return OPVC(4, 263, 0, 1)
4765 case AVCMPNEB:
4766 return OPVC(4, 7, 0, 0)
4767 case AVCMPNEBCC:
4768 return OPVC(4, 7, 0, 1)
4769 case AVCMPNEH:
4770 return OPVC(4, 71, 0, 0)
4771 case AVCMPNEHCC:
4772 return OPVC(4, 71, 0, 1)
4773 case AVCMPNEW:
4774 return OPVC(4, 135, 0, 0)
4775 case AVCMPNEWCC:
4776 return OPVC(4, 135, 0, 1)
4777
4778 case AVPERM:
4779 return OPVX(4, 43, 0, 0)
4780 case AVPERMXOR:
4781 return OPVX(4, 45, 0, 0)
4782 case AVPERMR:
4783 return OPVX(4, 59, 0, 0)
4784
4785 case AVSEL:
4786 return OPVX(4, 42, 0, 0)
4787
4788 case AVCIPHER:
4789 return OPVX(4, 1288, 0, 0)
4790 case AVCIPHERLAST:
4791 return OPVX(4, 1289, 0, 0)
4792 case AVNCIPHER:
4793 return OPVX(4, 1352, 0, 0)
4794 case AVNCIPHERLAST:
4795 return OPVX(4, 1353, 0, 0)
4796 case AVSBOX:
4797 return OPVX(4, 1480, 0, 0)
4798
4799
4800
4801
4802 case AMFVSRD, AMFVRD, AMFFPRD:
4803 return OPVXX1(31, 51, 0)
4804 case AMFVSRWZ:
4805 return OPVXX1(31, 115, 0)
4806 case AMFVSRLD:
4807 return OPVXX1(31, 307, 0)
4808
4809 case AMTVSRD, AMTFPRD, AMTVRD:
4810 return OPVXX1(31, 179, 0)
4811 case AMTVSRWA:
4812 return OPVXX1(31, 211, 0)
4813 case AMTVSRWZ:
4814 return OPVXX1(31, 243, 0)
4815 case AMTVSRDD:
4816 return OPVXX1(31, 435, 0)
4817 case AMTVSRWS:
4818 return OPVXX1(31, 403, 0)
4819
4820 case AXXLAND:
4821 return OPVXX3(60, 130, 0)
4822 case AXXLANDC:
4823 return OPVXX3(60, 138, 0)
4824 case AXXLEQV:
4825 return OPVXX3(60, 186, 0)
4826 case AXXLNAND:
4827 return OPVXX3(60, 178, 0)
4828
4829 case AXXLORC:
4830 return OPVXX3(60, 170, 0)
4831 case AXXLNOR:
4832 return OPVXX3(60, 162, 0)
4833 case AXXLOR, AXXLORQ:
4834 return OPVXX3(60, 146, 0)
4835 case AXXLXOR:
4836 return OPVXX3(60, 154, 0)
4837 case AXSMINJDP:
4838 return OPVXX3(60, 152, 0)
4839 case AXSMAXJDP:
4840 return OPVXX3(60, 144, 0)
4841
4842 case AXXSEL:
4843 return OPVXX4(60, 3, 0)
4844
4845 case AXXMRGHW:
4846 return OPVXX3(60, 18, 0)
4847 case AXXMRGLW:
4848 return OPVXX3(60, 50, 0)
4849
4850 case AXXSPLTW:
4851 return OPVXX2(60, 164, 0)
4852
4853 case AXXSPLTIB:
4854 return OPVCC(60, 360, 0, 0)
4855
4856 case AXXPERM:
4857 return OPVXX3(60, 26, 0)
4858 case AXXPERMDI:
4859 return OPVXX3(60, 10, 0)
4860
4861 case AXXSLDWI:
4862 return OPVXX3(60, 2, 0)
4863
4864 case AXXBRQ:
4865 return OPVXX2VA(60, 475, 31)
4866 case AXXBRD:
4867 return OPVXX2VA(60, 475, 23)
4868 case AXXBRW:
4869 return OPVXX2VA(60, 475, 15)
4870 case AXXBRH:
4871 return OPVXX2VA(60, 475, 7)
4872
4873 case AXSCVDPSP:
4874 return OPVXX2(60, 265, 0)
4875 case AXSCVSPDP:
4876 return OPVXX2(60, 329, 0)
4877 case AXSCVDPSPN:
4878 return OPVXX2(60, 267, 0)
4879 case AXSCVSPDPN:
4880 return OPVXX2(60, 331, 0)
4881
4882 case AXVCVDPSP:
4883 return OPVXX2(60, 393, 0)
4884 case AXVCVSPDP:
4885 return OPVXX2(60, 457, 0)
4886
4887 case AXSCVDPSXDS:
4888 return OPVXX2(60, 344, 0)
4889 case AXSCVDPSXWS:
4890 return OPVXX2(60, 88, 0)
4891 case AXSCVDPUXDS:
4892 return OPVXX2(60, 328, 0)
4893 case AXSCVDPUXWS:
4894 return OPVXX2(60, 72, 0)
4895
4896 case AXSCVSXDDP:
4897 return OPVXX2(60, 376, 0)
4898 case AXSCVUXDDP:
4899 return OPVXX2(60, 360, 0)
4900 case AXSCVSXDSP:
4901 return OPVXX2(60, 312, 0)
4902 case AXSCVUXDSP:
4903 return OPVXX2(60, 296, 0)
4904
4905 case AXVCVDPSXDS:
4906 return OPVXX2(60, 472, 0)
4907 case AXVCVDPSXWS:
4908 return OPVXX2(60, 216, 0)
4909 case AXVCVDPUXDS:
4910 return OPVXX2(60, 456, 0)
4911 case AXVCVDPUXWS:
4912 return OPVXX2(60, 200, 0)
4913 case AXVCVSPSXDS:
4914 return OPVXX2(60, 408, 0)
4915 case AXVCVSPSXWS:
4916 return OPVXX2(60, 152, 0)
4917 case AXVCVSPUXDS:
4918 return OPVXX2(60, 392, 0)
4919 case AXVCVSPUXWS:
4920 return OPVXX2(60, 136, 0)
4921
4922 case AXVCVSXDDP:
4923 return OPVXX2(60, 504, 0)
4924 case AXVCVSXWDP:
4925 return OPVXX2(60, 248, 0)
4926 case AXVCVUXDDP:
4927 return OPVXX2(60, 488, 0)
4928 case AXVCVUXWDP:
4929 return OPVXX2(60, 232, 0)
4930 case AXVCVSXDSP:
4931 return OPVXX2(60, 440, 0)
4932 case AXVCVSXWSP:
4933 return OPVXX2(60, 184, 0)
4934 case AXVCVUXDSP:
4935 return OPVXX2(60, 424, 0)
4936 case AXVCVUXWSP:
4937 return OPVXX2(60, 168, 0)
4938
4939
4940 case AMADDHD:
4941 return OPVX(4, 48, 0, 0)
4942 case AMADDHDU:
4943 return OPVX(4, 49, 0, 0)
4944 case AMADDLD:
4945 return OPVX(4, 51, 0, 0)
4946
4947 case AXOR:
4948 return OPVCC(31, 316, 0, 0)
4949 case AXORCC:
4950 return OPVCC(31, 316, 0, 1)
4951 }
4952
4953 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
4954 return 0
4955 }
4956
4957 func (c *ctxt9) opirrr(a obj.As) uint32 {
4958 switch a {
4959
4960
4961
4962 case AVSLDOI:
4963 return OPVX(4, 44, 0, 0)
4964 }
4965
4966 c.ctxt.Diag("bad i/r/r/r opcode %v", a)
4967 return 0
4968 }
4969
4970 func (c *ctxt9) opiirr(a obj.As) uint32 {
4971 switch a {
4972
4973
4974 case AVSHASIGMAW:
4975 return OPVX(4, 1666, 0, 0)
4976 case AVSHASIGMAD:
4977 return OPVX(4, 1730, 0, 0)
4978 }
4979
4980 c.ctxt.Diag("bad i/i/r/r opcode %v", a)
4981 return 0
4982 }
4983
4984 func (c *ctxt9) opirr(a obj.As) uint32 {
4985 switch a {
4986 case AADD:
4987 return OPVCC(14, 0, 0, 0)
4988 case AADDC:
4989 return OPVCC(12, 0, 0, 0)
4990 case AADDCCC:
4991 return OPVCC(13, 0, 0, 0)
4992 case AADDIS:
4993 return OPVCC(15, 0, 0, 0)
4994
4995 case AANDCC:
4996 return OPVCC(28, 0, 0, 0)
4997 case AANDISCC:
4998 return OPVCC(29, 0, 0, 0)
4999
5000 case ABR:
5001 return OPVCC(18, 0, 0, 0)
5002 case ABL:
5003 return OPVCC(18, 0, 0, 0) | 1
5004 case obj.ADUFFZERO:
5005 return OPVCC(18, 0, 0, 0) | 1
5006 case obj.ADUFFCOPY:
5007 return OPVCC(18, 0, 0, 0) | 1
5008 case ABC:
5009 return OPVCC(16, 0, 0, 0)
5010 case ABCL:
5011 return OPVCC(16, 0, 0, 0) | 1
5012
5013 case ABEQ:
5014 return AOP_RRR(16<<26, BO_BCR, BI_EQ, 0)
5015 case ABGE:
5016 return AOP_RRR(16<<26, BO_NOTBCR, BI_LT, 0)
5017 case ABGT:
5018 return AOP_RRR(16<<26, BO_BCR, BI_GT, 0)
5019 case ABLE:
5020 return AOP_RRR(16<<26, BO_NOTBCR, BI_GT, 0)
5021 case ABLT:
5022 return AOP_RRR(16<<26, BO_BCR, BI_LT, 0)
5023 case ABNE:
5024 return AOP_RRR(16<<26, BO_NOTBCR, BI_EQ, 0)
5025 case ABVC:
5026 return AOP_RRR(16<<26, BO_NOTBCR, BI_FU, 0)
5027 case ABVS:
5028 return AOP_RRR(16<<26, BO_BCR, BI_FU, 0)
5029 case ABDZ:
5030 return AOP_RRR(16<<26, BO_NOTBCTR, 0, 0)
5031 case ABDNZ:
5032 return AOP_RRR(16<<26, BO_BCTR, 0, 0)
5033
5034 case ACMP:
5035 return OPVCC(11, 0, 0, 0) | 1<<21
5036 case ACMPU:
5037 return OPVCC(10, 0, 0, 0) | 1<<21
5038 case ACMPW:
5039 return OPVCC(11, 0, 0, 0)
5040 case ACMPWU:
5041 return OPVCC(10, 0, 0, 0)
5042 case ACMPEQB:
5043 return OPVCC(31, 224, 0, 0)
5044
5045 case ALSW:
5046 return OPVCC(31, 597, 0, 0)
5047
5048 case ACOPY:
5049 return OPVCC(31, 774, 0, 0)
5050 case APASTECC:
5051 return OPVCC(31, 902, 0, 1)
5052 case ADARN:
5053 return OPVCC(31, 755, 0, 0)
5054
5055 case AMULLW, AMULLD:
5056 return OPVCC(7, 0, 0, 0)
5057
5058 case AOR:
5059 return OPVCC(24, 0, 0, 0)
5060 case AORIS:
5061 return OPVCC(25, 0, 0, 0)
5062
5063 case ARLWMI:
5064 return OPVCC(20, 0, 0, 0)
5065 case ARLWMICC:
5066 return OPVCC(20, 0, 0, 1)
5067 case ARLDMI:
5068 return OPMD(30, 3, 0)
5069 case ARLDMICC:
5070 return OPMD(30, 3, 1)
5071 case ARLDIMI:
5072 return OPMD(30, 3, 0)
5073 case ARLDIMICC:
5074 return OPMD(30, 3, 1)
5075 case ARLWNM:
5076 return OPVCC(21, 0, 0, 0)
5077 case ARLWNMCC:
5078 return OPVCC(21, 0, 0, 1)
5079
5080 case ARLDCL:
5081 return OPMD(30, 0, 0)
5082 case ARLDCLCC:
5083 return OPMD(30, 0, 1)
5084 case ARLDCR:
5085 return OPMD(30, 1, 0)
5086 case ARLDCRCC:
5087 return OPMD(30, 1, 1)
5088 case ARLDC:
5089 return OPMD(30, 2, 0)
5090 case ARLDCCC:
5091 return OPMD(30, 2, 1)
5092
5093 case ASRAW:
5094 return OPVCC(31, 824, 0, 0)
5095 case ASRAWCC:
5096 return OPVCC(31, 824, 0, 1)
5097 case ASRAD:
5098 return OPVCC(31, (413 << 1), 0, 0)
5099 case ASRADCC:
5100 return OPVCC(31, (413 << 1), 0, 1)
5101 case AEXTSWSLI:
5102 return OPVCC(31, 445, 0, 0)
5103 case AEXTSWSLICC:
5104 return OPVCC(31, 445, 0, 1)
5105
5106 case ASTSW:
5107 return OPVCC(31, 725, 0, 0)
5108
5109 case ASUBC:
5110 return OPVCC(8, 0, 0, 0)
5111
5112 case ATW:
5113 return OPVCC(3, 0, 0, 0)
5114 case ATD:
5115 return OPVCC(2, 0, 0, 0)
5116
5117
5118
5119
5120 case AVSPLTB:
5121 return OPVX(4, 524, 0, 0)
5122 case AVSPLTH:
5123 return OPVX(4, 588, 0, 0)
5124 case AVSPLTW:
5125 return OPVX(4, 652, 0, 0)
5126
5127 case AVSPLTISB:
5128 return OPVX(4, 780, 0, 0)
5129 case AVSPLTISH:
5130 return OPVX(4, 844, 0, 0)
5131 case AVSPLTISW:
5132 return OPVX(4, 908, 0, 0)
5133
5134
5135 case AFTDIV:
5136 return OPVCC(63, 128, 0, 0)
5137 case AFTSQRT:
5138 return OPVCC(63, 160, 0, 0)
5139
5140 case AXOR:
5141 return OPVCC(26, 0, 0, 0)
5142 case AXORIS:
5143 return OPVCC(27, 0, 0, 0)
5144 }
5145
5146 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
5147 return 0
5148 }
5149
5150
5153 func (c *ctxt9) opload(a obj.As) uint32 {
5154 switch a {
5155 case AMOVD:
5156 return OPVCC(58, 0, 0, 0)
5157 case AMOVDU:
5158 return OPVCC(58, 0, 0, 1)
5159 case AMOVWZ:
5160 return OPVCC(32, 0, 0, 0)
5161 case AMOVWZU:
5162 return OPVCC(33, 0, 0, 0)
5163 case AMOVW:
5164 return OPVCC(58, 0, 0, 0) | 1<<1
5165 case ALXV:
5166 return OPDQ(61, 1, 0)
5167 case ALXVL:
5168 return OPVXX1(31, 269, 0)
5169 case ALXVLL:
5170 return OPVXX1(31, 301, 0)
5171 case ALXVX:
5172 return OPVXX1(31, 268, 0)
5173
5174
5175 case AMOVB, AMOVBZ:
5176 return OPVCC(34, 0, 0, 0)
5177
5178
5179 case AMOVBU, AMOVBZU:
5180 return OPVCC(35, 0, 0, 0)
5181 case AFMOVD:
5182 return OPVCC(50, 0, 0, 0)
5183 case AFMOVDU:
5184 return OPVCC(51, 0, 0, 0)
5185 case AFMOVS:
5186 return OPVCC(48, 0, 0, 0)
5187 case AFMOVSU:
5188 return OPVCC(49, 0, 0, 0)
5189 case AMOVH:
5190 return OPVCC(42, 0, 0, 0)
5191 case AMOVHU:
5192 return OPVCC(43, 0, 0, 0)
5193 case AMOVHZ:
5194 return OPVCC(40, 0, 0, 0)
5195 case AMOVHZU:
5196 return OPVCC(41, 0, 0, 0)
5197 case AMOVMW:
5198 return OPVCC(46, 0, 0, 0)
5199 }
5200
5201 c.ctxt.Diag("bad load opcode %v", a)
5202 return 0
5203 }
5204
5205
5208 func (c *ctxt9) oploadx(a obj.As) uint32 {
5209 switch a {
5210 case AMOVWZ:
5211 return OPVCC(31, 23, 0, 0)
5212 case AMOVWZU:
5213 return OPVCC(31, 55, 0, 0)
5214 case AMOVW:
5215 return OPVCC(31, 341, 0, 0)
5216 case AMOVWU:
5217 return OPVCC(31, 373, 0, 0)
5218
5219 case AMOVB, AMOVBZ:
5220 return OPVCC(31, 87, 0, 0)
5221
5222 case AMOVBU, AMOVBZU:
5223 return OPVCC(31, 119, 0, 0)
5224 case AFMOVD:
5225 return OPVCC(31, 599, 0, 0)
5226 case AFMOVDU:
5227 return OPVCC(31, 631, 0, 0)
5228 case AFMOVS:
5229 return OPVCC(31, 535, 0, 0)
5230 case AFMOVSU:
5231 return OPVCC(31, 567, 0, 0)
5232 case AFMOVSX:
5233 return OPVCC(31, 855, 0, 0)
5234 case AFMOVSZ:
5235 return OPVCC(31, 887, 0, 0)
5236 case AMOVH:
5237 return OPVCC(31, 343, 0, 0)
5238 case AMOVHU:
5239 return OPVCC(31, 375, 0, 0)
5240 case AMOVHBR:
5241 return OPVCC(31, 790, 0, 0)
5242 case AMOVWBR:
5243 return OPVCC(31, 534, 0, 0)
5244 case AMOVDBR:
5245 return OPVCC(31, 532, 0, 0)
5246 case AMOVHZ:
5247 return OPVCC(31, 279, 0, 0)
5248 case AMOVHZU:
5249 return OPVCC(31, 311, 0, 0)
5250 case ALBAR:
5251 return OPVCC(31, 52, 0, 0)
5252 case ALHAR:
5253 return OPVCC(31, 116, 0, 0)
5254 case ALWAR:
5255 return OPVCC(31, 20, 0, 0)
5256 case ALDAR:
5257 return OPVCC(31, 84, 0, 0)
5258 case ALSW:
5259 return OPVCC(31, 533, 0, 0)
5260 case AMOVD:
5261 return OPVCC(31, 21, 0, 0)
5262 case AMOVDU:
5263 return OPVCC(31, 53, 0, 0)
5264
5265
5266 case ALVEBX:
5267 return OPVCC(31, 7, 0, 0)
5268 case ALVEHX:
5269 return OPVCC(31, 39, 0, 0)
5270 case ALVEWX:
5271 return OPVCC(31, 71, 0, 0)
5272 case ALVX:
5273 return OPVCC(31, 103, 0, 0)
5274 case ALVXL:
5275 return OPVCC(31, 359, 0, 0)
5276 case ALVSL:
5277 return OPVCC(31, 6, 0, 0)
5278 case ALVSR:
5279 return OPVCC(31, 38, 0, 0)
5280
5281
5282
5283 case ALXVX:
5284 return OPVXX1(31, 268, 0)
5285 case ALXVD2X:
5286 return OPVXX1(31, 844, 0)
5287 case ALXVW4X:
5288 return OPVXX1(31, 780, 0)
5289 case ALXVH8X:
5290 return OPVXX1(31, 812, 0)
5291 case ALXVB16X:
5292 return OPVXX1(31, 876, 0)
5293 case ALXVDSX:
5294 return OPVXX1(31, 332, 0)
5295 case ALXSDX:
5296 return OPVXX1(31, 588, 0)
5297 case ALXSIWAX:
5298 return OPVXX1(31, 76, 0)
5299 case ALXSIWZX:
5300 return OPVXX1(31, 12, 0)
5301 }
5302
5303 c.ctxt.Diag("bad loadx opcode %v", a)
5304 return 0
5305 }
5306
5307
5310 func (c *ctxt9) opstore(a obj.As) uint32 {
5311 switch a {
5312 case AMOVB, AMOVBZ:
5313 return OPVCC(38, 0, 0, 0)
5314
5315 case AMOVBU, AMOVBZU:
5316 return OPVCC(39, 0, 0, 0)
5317 case AFMOVD:
5318 return OPVCC(54, 0, 0, 0)
5319 case AFMOVDU:
5320 return OPVCC(55, 0, 0, 0)
5321 case AFMOVS:
5322 return OPVCC(52, 0, 0, 0)
5323 case AFMOVSU:
5324 return OPVCC(53, 0, 0, 0)
5325
5326 case AMOVHZ, AMOVH:
5327 return OPVCC(44, 0, 0, 0)
5328
5329 case AMOVHZU, AMOVHU:
5330 return OPVCC(45, 0, 0, 0)
5331 case AMOVMW:
5332 return OPVCC(47, 0, 0, 0)
5333 case ASTSW:
5334 return OPVCC(31, 725, 0, 0)
5335
5336 case AMOVWZ, AMOVW:
5337 return OPVCC(36, 0, 0, 0)
5338
5339 case AMOVWZU, AMOVWU:
5340 return OPVCC(37, 0, 0, 0)
5341 case AMOVD:
5342 return OPVCC(62, 0, 0, 0)
5343 case AMOVDU:
5344 return OPVCC(62, 0, 0, 1)
5345 case ASTXV:
5346 return OPDQ(61, 5, 0)
5347 case ASTXVL:
5348 return OPVXX1(31, 397, 0)
5349 case ASTXVLL:
5350 return OPVXX1(31, 429, 0)
5351 case ASTXVX:
5352 return OPVXX1(31, 396, 0)
5353
5354 }
5355
5356 c.ctxt.Diag("unknown store opcode %v", a)
5357 return 0
5358 }
5359
5360
5363 func (c *ctxt9) opstorex(a obj.As) uint32 {
5364 switch a {
5365 case AMOVB, AMOVBZ:
5366 return OPVCC(31, 215, 0, 0)
5367
5368 case AMOVBU, AMOVBZU:
5369 return OPVCC(31, 247, 0, 0)
5370 case AFMOVD:
5371 return OPVCC(31, 727, 0, 0)
5372 case AFMOVDU:
5373 return OPVCC(31, 759, 0, 0)
5374 case AFMOVS:
5375 return OPVCC(31, 663, 0, 0)
5376 case AFMOVSU:
5377 return OPVCC(31, 695, 0, 0)
5378 case AFMOVSX:
5379 return OPVCC(31, 983, 0, 0)
5380
5381 case AMOVHZ, AMOVH:
5382 return OPVCC(31, 407, 0, 0)
5383 case AMOVHBR:
5384 return OPVCC(31, 918, 0, 0)
5385
5386 case AMOVHZU, AMOVHU:
5387 return OPVCC(31, 439, 0, 0)
5388
5389 case AMOVWZ, AMOVW:
5390 return OPVCC(31, 151, 0, 0)
5391
5392 case AMOVWZU, AMOVWU:
5393 return OPVCC(31, 183, 0, 0)
5394 case ASTSW:
5395 return OPVCC(31, 661, 0, 0)
5396 case AMOVWBR:
5397 return OPVCC(31, 662, 0, 0)
5398 case AMOVDBR:
5399 return OPVCC(31, 660, 0, 0)
5400 case ASTBCCC:
5401 return OPVCC(31, 694, 0, 1)
5402 case ASTHCCC:
5403 return OPVCC(31, 726, 0, 1)
5404 case ASTWCCC:
5405 return OPVCC(31, 150, 0, 1)
5406 case ASTDCCC:
5407 return OPVCC(31, 214, 0, 1)
5408 case AMOVD:
5409 return OPVCC(31, 149, 0, 0)
5410 case AMOVDU:
5411 return OPVCC(31, 181, 0, 0)
5412
5413
5414 case ASTVEBX:
5415 return OPVCC(31, 135, 0, 0)
5416 case ASTVEHX:
5417 return OPVCC(31, 167, 0, 0)
5418 case ASTVEWX:
5419 return OPVCC(31, 199, 0, 0)
5420 case ASTVX:
5421 return OPVCC(31, 231, 0, 0)
5422 case ASTVXL:
5423 return OPVCC(31, 487, 0, 0)
5424
5425
5426
5427 case ASTXVX:
5428 return OPVXX1(31, 396, 0)
5429 case ASTXVD2X:
5430 return OPVXX1(31, 972, 0)
5431 case ASTXVW4X:
5432 return OPVXX1(31, 908, 0)
5433 case ASTXVH8X:
5434 return OPVXX1(31, 940, 0)
5435 case ASTXVB16X:
5436 return OPVXX1(31, 1004, 0)
5437
5438 case ASTXSDX:
5439 return OPVXX1(31, 716, 0)
5440
5441 case ASTXSIWX:
5442 return OPVXX1(31, 140, 0)
5443
5444
5445
5446 }
5447
5448 c.ctxt.Diag("unknown storex opcode %v", a)
5449 return 0
5450 }
5451
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