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30 package ppc64
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "encoding/binary"
36 "fmt"
37 "internal/buildcfg"
38 "log"
39 "math"
40 "math/bits"
41 "sort"
42 )
43
44
45
46
47 type ctxt9 struct {
48 ctxt *obj.Link
49 newprog obj.ProgAlloc
50 cursym *obj.LSym
51 autosize int32
52 instoffset int64
53 pc int64
54 }
55
56
57
58 const (
59 r0iszero = 1
60 )
61
62 const (
63
64 PFX_R_ABS = 0
65 PFX_R_PCREL = 1
66 )
67
68 const (
69
70 NOP = 0x60000000
71 )
72
73 type Optab struct {
74 as obj.As
75 a1 uint8
76 a2 uint8
77 a3 uint8
78 a4 uint8
79 a5 uint8
80 a6 uint8
81 type_ int8
82 size int8
83
84
85
86
87
88 ispfx bool
89
90 asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32)
91 }
92
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107
108
109 var optab []Optab
110
111 var optabBase = []Optab{
112 {as: obj.ATEXT, a1: C_LOREG, a6: C_TEXTSIZE, type_: 0, size: 0},
113 {as: obj.ATEXT, a1: C_LOREG, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
114 {as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE, type_: 0, size: 0},
115 {as: obj.ATEXT, a1: C_ADDR, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0},
116
117 {as: AADD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
118 {as: AADD, a1: C_REG, a6: C_REG, type_: 2, size: 4},
119 {as: AADD, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
120 {as: AADD, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
121 {as: AADD, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 22, size: 8},
122 {as: AADD, a1: C_U16CON, a6: C_REG, type_: 22, size: 8},
123 {as: AADDIS, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 20, size: 4},
124 {as: AADDIS, a1: C_S16CON, a6: C_REG, type_: 20, size: 4},
125 {as: AADDC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
126 {as: AADDC, a1: C_REG, a6: C_REG, type_: 2, size: 4},
127 {as: AADDC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
128 {as: AADDC, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
129 {as: AADDC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
130 {as: AADDC, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
131 {as: AAND, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
132 {as: AAND, a1: C_REG, a6: C_REG, type_: 6, size: 4},
133 {as: AANDCC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
134 {as: AANDCC, a1: C_REG, a6: C_REG, type_: 6, size: 4},
135 {as: AANDCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
136 {as: AANDCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
137 {as: AANDCC, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
138 {as: AANDCC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
139 {as: AANDCC, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
140 {as: AANDCC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
141 {as: AANDISCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
142 {as: AANDISCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
143 {as: AMULLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
144 {as: AMULLW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
145 {as: AMULLW, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
146 {as: AMULLW, a1: C_S16CON, a6: C_REG, type_: 4, size: 4},
147 {as: AMULLW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
148 {as: AMULLW, a1: C_32CON, a6: C_REG, type_: 22, size: 12},
149 {as: ASUBC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
150 {as: ASUBC, a1: C_REG, a6: C_REG, type_: 10, size: 4},
151 {as: ASUBC, a1: C_REG, a3: C_S16CON, a6: C_REG, type_: 27, size: 4},
152 {as: ASUBC, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 28, size: 12},
153 {as: AOR, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
154 {as: AOR, a1: C_REG, a6: C_REG, type_: 6, size: 4},
155 {as: AOR, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
156 {as: AOR, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
157 {as: AOR, a1: C_S16CON, a6: C_REG, type_: 23, size: 8},
158 {as: AOR, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
159 {as: AOR, a1: C_U32CON, a2: C_REG, a6: C_REG, type_: 21, size: 8},
160 {as: AOR, a1: C_U32CON, a6: C_REG, type_: 21, size: 8},
161 {as: AOR, a1: C_32CON, a6: C_REG, type_: 23, size: 12},
162 {as: AOR, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
163 {as: AORIS, a1: C_U16CON, a6: C_REG, type_: 58, size: 4},
164 {as: AORIS, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
165 {as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
166 {as: ADIVW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
167 {as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
168 {as: ASUB, a1: C_REG, a6: C_REG, type_: 10, size: 4},
169 {as: ASLW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
170 {as: ASLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
171 {as: ASLD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
172 {as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
173 {as: ASLD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
174 {as: ASLD, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
175 {as: AEXTSWSLI, a1: C_U15CON, a6: C_REG, type_: 25, size: 4},
176 {as: AEXTSWSLI, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
177 {as: ASLW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 57, size: 4},
178 {as: ASLW, a1: C_U15CON, a6: C_REG, type_: 57, size: 4},
179 {as: ASRAW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
180 {as: ASRAW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
181 {as: ASRAW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
182 {as: ASRAW, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
183 {as: ASRAD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
184 {as: ASRAD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
185 {as: ASRAD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
186 {as: ASRAD, a1: C_U15CON, a6: C_REG, type_: 56, size: 4},
187 {as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
188 {as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
189 {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4},
190 {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4},
191 {as: ACLRLSLWI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 62, size: 4},
192 {as: ARLDMI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 30, size: 4},
193 {as: ARLDC, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
194 {as: ARLDC, a1: C_REG, a3: C_U8CON, a4: C_U8CON, a6: C_REG, type_: 9, size: 4},
195 {as: ARLDCL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4},
196 {as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
197 {as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
198 {as: ARLDICL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
199 {as: ARLDCL, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4},
200 {as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4},
201 {as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4},
202 {as: ADADDQ, a1: C_FREGP, a6: C_FREGP, type_: 2, size: 4},
203 {as: ADADDQ, a1: C_FREGP, a2: C_FREGP, a6: C_FREGP, type_: 2, size: 4},
204 {as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
205 {as: AFABS, a6: C_FREG, type_: 33, size: 4},
206 {as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4},
207 {as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4},
208 {as: AFMUL, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 32, size: 4},
209 {as: ADMULQ, a1: C_FREGP, a6: C_FREGP, type_: 32, size: 4},
210 {as: ADMULQ, a1: C_FREGP, a2: C_FREGP, a6: C_FREGP, type_: 32, size: 4},
211
212 {as: AMOVBU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
213 {as: AMOVBU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
214 {as: AMOVBU, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
215 {as: AMOVBU, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
216
217 {as: AMOVBZU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
218 {as: AMOVBZU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
219 {as: AMOVBZU, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
220 {as: AMOVBZU, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
221
222 {as: AMOVHBR, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
223 {as: AMOVHBR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
224
225 {as: AMOVB, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
226 {as: AMOVB, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
227 {as: AMOVB, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
228 {as: AMOVB, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
229 {as: AMOVB, a1: C_REG, a6: C_REG, type_: 13, size: 4},
230
231 {as: AMOVBZ, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
232 {as: AMOVBZ, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
233 {as: AMOVBZ, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
234 {as: AMOVBZ, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
235 {as: AMOVBZ, a1: C_REG, a6: C_REG, type_: 13, size: 4},
236
237 {as: AMOVD, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
238 {as: AMOVD, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
239 {as: AMOVD, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
240 {as: AMOVD, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
241 {as: AMOVD, a1: C_SOREG, a6: C_SPR, type_: 107, size: 8},
242 {as: AMOVD, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
243 {as: AMOVD, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
244 {as: AMOVD, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
245 {as: AMOVD, a1: C_SPR, a6: C_SOREG, type_: 106, size: 8},
246 {as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
247 {as: AMOVD, a1: C_REG, a6: C_REG, type_: 13, size: 4},
248
249 {as: AMOVW, a1: C_16CON, a6: C_REG, type_: 3, size: 4},
250 {as: AMOVW, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
251 {as: AMOVW, a1: C_CREG, a6: C_REG, type_: 68, size: 4},
252 {as: AMOVW, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
253 {as: AMOVW, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
254 {as: AMOVW, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
255 {as: AMOVW, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
256 {as: AMOVW, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
257 {as: AMOVW, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
258 {as: AMOVW, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
259 {as: AMOVW, a1: C_REG, a6: C_REG, type_: 13, size: 4},
260
261 {as: AFMOVD, a1: C_S16CON, a6: C_FREG, type_: 24, size: 8},
262 {as: AFMOVD, a1: C_SOREG, a6: C_FREG, type_: 8, size: 4},
263 {as: AFMOVD, a1: C_XOREG, a6: C_FREG, type_: 109, size: 4},
264 {as: AFMOVD, a1: C_ZCON, a6: C_FREG, type_: 24, size: 4},
265 {as: AFMOVD, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
266 {as: AFMOVD, a1: C_FREG, a6: C_SOREG, type_: 7, size: 4},
267 {as: AFMOVD, a1: C_FREG, a6: C_XOREG, type_: 108, size: 4},
268
269 {as: AFMOVSX, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
270 {as: AFMOVSX, a1: C_FREG, a6: C_XOREG, type_: 44, size: 4},
271
272 {as: AFMOVSZ, a1: C_ZOREG, a6: C_FREG, type_: 45, size: 4},
273 {as: AFMOVSZ, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
274
275 {as: AMOVFL, a1: C_CREG, a6: C_CREG, type_: 67, size: 4},
276 {as: AMOVFL, a1: C_FPSCR, a6: C_CREG, type_: 73, size: 4},
277 {as: AMOVFL, a1: C_FPSCR, a6: C_FREG, type_: 53, size: 4},
278 {as: AMOVFL, a1: C_FREG, a3: C_32CON, a6: C_FPSCR, type_: 64, size: 4},
279 {as: AMOVFL, a1: C_FREG, a6: C_FPSCR, type_: 64, size: 4},
280 {as: AMOVFL, a1: C_32CON, a6: C_FPSCR, type_: 65, size: 4},
281 {as: AMOVFL, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
282 {as: AMOVFL, a1: C_REG, a6: C_32CON, type_: 69, size: 4},
283
284 {as: ASYSCALL, type_: 5, size: 4},
285 {as: ASYSCALL, a1: C_REG, type_: 77, size: 12},
286 {as: ASYSCALL, a1: C_U15CON, type_: 77, size: 12},
287 {as: ABEQ, a6: C_BRA, type_: 16, size: 4},
288 {as: ABEQ, a1: C_CREG, a6: C_BRA, type_: 16, size: 4},
289 {as: ABEQ, a1: C_CREG, a6: C_LR, type_: 17, size: 4},
290 {as: ABR, a6: C_BRA, type_: 11, size: 4},
291 {as: ABR, a6: C_BRAPIC, type_: 11, size: 8},
292 {as: ABR, a6: C_LR, type_: 18, size: 4},
293 {as: ABR, a6: C_CTR, type_: 18, size: 4},
294 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_BRA, type_: 16, size: 4},
295 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_LR, type_: 18, size: 4},
296 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a3: C_U15CON, a6: C_LR, type_: 18, size: 4},
297 {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_CTR, type_: 18, size: 4},
298 {as: ABDNZ, a6: C_BRA, type_: 16, size: 4},
299 {as: ASYNC, type_: 46, size: 4},
300 {as: AWORD, a1: C_32CON, type_: 40, size: 4},
301 {as: ADWORD, a1: C_64CON, type_: 31, size: 8},
302 {as: ADWORD, a1: C_LACON, type_: 31, size: 8},
303 {as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4},
304 {as: AEXTSB, a1: C_REG, a6: C_REG, type_: 48, size: 4},
305 {as: AEXTSB, a6: C_REG, type_: 48, size: 4},
306 {as: AISEL, a1: C_U5CON, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
307 {as: AISEL, a1: C_CRBIT, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
308 {as: ANEG, a1: C_REG, a6: C_REG, type_: 47, size: 4},
309 {as: ANEG, a6: C_REG, type_: 47, size: 4},
310 {as: AREM, a1: C_REG, a6: C_REG, type_: 50, size: 12},
311 {as: AREM, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 12},
312 {as: AREMU, a1: C_REG, a6: C_REG, type_: 50, size: 16},
313 {as: AREMU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 16},
314 {as: AREMD, a1: C_REG, a6: C_REG, type_: 51, size: 12},
315 {as: AREMD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 51, size: 12},
316 {as: AMTFSB0, a1: C_U15CON, type_: 52, size: 4},
317
318 {as: APOPCNTD, a1: C_REG, a6: C_REG, type_: 93, size: 4},
319 {as: ACMPB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 92, size: 4},
320 {as: ACMPEQB, a1: C_REG, a2: C_REG, a6: C_CREG, type_: 92, size: 4},
321 {as: ACMPEQB, a1: C_REG, a6: C_REG, type_: 70, size: 4},
322 {as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_U15CON, type_: 92, size: 4},
323 {as: AFTSQRT, a1: C_FREG, a6: C_U15CON, type_: 93, size: 4},
324 {as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4},
325 {as: ADARN, a1: C_U15CON, a6: C_REG, type_: 92, size: 4},
326 {as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4},
327 {as: AADDEX, a1: C_REG, a2: C_REG, a3: C_U15CON, a6: C_REG, type_: 94, size: 4},
328 {as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4},
329
330
331 {as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4},
332 {as: AVCLZLSBB, a1: C_VREG, a6: C_REG, type_: 85, size: 4},
333
334
335
336
337 {as: ALVEBX, a1: C_XOREG, a6: C_VREG, type_: 45, size: 4},
338
339
340 {as: ASTVEBX, a1: C_VREG, a6: C_XOREG, type_: 44, size: 4},
341
342
343 {as: AVAND, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
344 {as: AVOR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
345
346
347 {as: AVADDUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
348 {as: AVADDCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
349 {as: AVADDUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
350 {as: AVADDSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
351 {as: AVADDE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
352
353
354 {as: AVSUBUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
355 {as: AVSUBCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
356 {as: AVSUBUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
357 {as: AVSUBSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
358 {as: AVSUBE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
359
360
361 {as: AVMULESB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
362 {as: AVPMSUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
363 {as: AVMSUMUDM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
364
365
366 {as: AVR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
367
368
369 {as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
370 {as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
371 {as: AVSOI, a1: C_U16CON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
372
373
374 {as: AVCLZ, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
375 {as: AVPOPCNT, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
376
377
378 {as: AVCMPEQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
379 {as: AVCMPGT, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
380 {as: AVCMPNEZB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
381
382
383 {as: AVMRGOW, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
384
385
386 {as: AVPERM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
387
388
389 {as: AVBPERMQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
390
391
392 {as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
393
394
395 {as: AVSPLTB, a1: C_S16CON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
396 {as: AVSPLTISB, a1: C_S16CON, a6: C_VREG, type_: 82, size: 4},
397
398
399 {as: AVCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
400 {as: AVNCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
401 {as: AVSBOX, a1: C_VREG, a6: C_VREG, type_: 82, size: 4},
402
403
404 {as: AVSHASIGMA, a1: C_U16CON, a2: C_VREG, a3: C_U16CON, a6: C_VREG, type_: 82, size: 4},
405
406
407 {as: ALXVD2X, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
408 {as: ALXV, a1: C_SOREG, a6: C_VSREG, type_: 96, size: 4},
409 {as: ALXVL, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 98, size: 4},
410
411
412 {as: ASTXVD2X, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
413 {as: ASTXV, a1: C_VSREG, a6: C_SOREG, type_: 97, size: 4},
414 {as: ASTXVL, a1: C_VSREG, a2: C_REG, a6: C_REG, type_: 99, size: 4},
415
416
417 {as: ALXSDX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
418
419
420 {as: ASTXSDX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
421
422
423 {as: ALXSIWAX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
424
425
426 {as: ASTXSIWX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
427
428
429 {as: AMFVSRD, a1: C_VSREG, a6: C_REG, type_: 88, size: 4},
430 {as: AMFVSRD, a1: C_FREG, a6: C_REG, type_: 88, size: 4},
431
432
433 {as: AMTVSRD, a1: C_REG, a6: C_VSREG, type_: 104, size: 4},
434 {as: AMTVSRD, a1: C_REG, a6: C_FREG, type_: 104, size: 4},
435 {as: AMTVSRDD, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 104, size: 4},
436
437
438 {as: AXXLAND, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 90, size: 4},
439 {as: AXXLAND, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
440
441
442 {as: AXXSEL, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a6: C_VSREG, type_: 91, size: 4},
443
444
445 {as: AXXSPLTW, a1: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 89, size: 4},
446 {as: AXXSPLTIB, a1: C_U15CON, a6: C_VSREG, type_: 100, size: 4},
447
448
449 {as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 90, size: 4},
450
451
452 {as: AXXBRQ, a1: C_VSREG, a6: C_VSREG, type_: 101, size: 4},
453
454
455 {as: AXSCVDPSP, a1: C_FREG, a6: C_FREG, type_: 89, size: 4},
456 {as: AXSCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
457
458 {as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4},
459 {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
460 {as: ACMP, a1: C_REG, a6: C_S16CON, type_: 70, size: 4},
461 {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_S16CON, type_: 70, size: 4},
462 {as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4},
463 {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
464 {as: ACMPU, a1: C_REG, a6: C_U16CON, type_: 70, size: 4},
465 {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_U16CON, type_: 70, size: 4},
466 {as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4},
467 {as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4},
468 {as: ADCMPOQ, a1: C_FREGP, a6: C_FREGP, type_: 70, size: 4},
469 {as: ADCMPOQ, a1: C_FREGP, a2: C_CREG, a6: C_FREGP, type_: 70, size: 4},
470 {as: ATW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 60, size: 4},
471 {as: ATW, a1: C_32CON, a2: C_REG, a6: C_S16CON, type_: 61, size: 4},
472 {as: ADCBF, a1: C_SOREG, type_: 43, size: 4},
473 {as: ADCBF, a1: C_XOREG, type_: 43, size: 4},
474 {as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_U15CON, type_: 43, size: 4},
475 {as: ADCBF, a1: C_SOREG, a6: C_U15CON, type_: 43, size: 4},
476 {as: ADCBF, a1: C_XOREG, a6: C_U15CON, type_: 43, size: 4},
477 {as: ASTDCCC, a1: C_REG, a2: C_REG, a6: C_XOREG, type_: 44, size: 4},
478 {as: ASTDCCC, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
479 {as: ALDAR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
480 {as: ALDAR, a1: C_XOREG, a3: C_U16CON, a6: C_REG, type_: 45, size: 4},
481 {as: AEIEIO, type_: 46, size: 4},
482 {as: ATLBIE, a1: C_REG, type_: 49, size: 4},
483 {as: ATLBIE, a1: C_U15CON, a6: C_REG, type_: 49, size: 4},
484 {as: ASLBMFEE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
485 {as: ASLBMTE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
486 {as: ASTSW, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
487 {as: ASTSW, a1: C_REG, a3: C_32CON, a6: C_ZOREG, type_: 41, size: 4},
488 {as: ALSW, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
489 {as: ALSW, a1: C_ZOREG, a3: C_32CON, a6: C_REG, type_: 42, size: 4},
490
491 {as: obj.AUNDEF, type_: 78, size: 4},
492 {as: obj.APCDATA, a1: C_32CON, a6: C_32CON, type_: 0, size: 0},
493 {as: obj.AFUNCDATA, a1: C_U15CON, a6: C_ADDR, type_: 0, size: 0},
494 {as: obj.ANOP, type_: 0, size: 0},
495 {as: obj.ANOP, a1: C_32CON, type_: 0, size: 0},
496 {as: obj.ANOP, a1: C_REG, type_: 0, size: 0},
497 {as: obj.ANOP, a1: C_FREG, type_: 0, size: 0},
498 {as: obj.ADUFFZERO, a6: C_BRA, type_: 11, size: 4},
499 {as: obj.ADUFFCOPY, a6: C_BRA, type_: 11, size: 4},
500 {as: obj.APCALIGN, a1: C_32CON, type_: 0, size: 0},
501 }
502
503
504
505 type PrefixableOptab struct {
506 Optab
507 minGOPPC64 int
508 pfxsize int8
509 }
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525 var prefixableOptab = []PrefixableOptab{
526 {Optab: Optab{as: AMOVD, a1: C_S34CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
527 {Optab: Optab{as: AMOVD, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
528 {Optab: Optab{as: AMOVD, a1: C_TLS_LE, a6: C_REG, type_: 79, size: 8}, minGOPPC64: 10, pfxsize: 8},
529 {Optab: Optab{as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 12}, minGOPPC64: 10, pfxsize: 12},
530 {Optab: Optab{as: AMOVD, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
531 {Optab: Optab{as: AMOVD, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
532 {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
533 {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
534
535 {Optab: Optab{as: AMOVW, a1: C_32CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
536 {Optab: Optab{as: AMOVW, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
537 {Optab: Optab{as: AMOVW, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
538 {Optab: Optab{as: AMOVW, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
539 {Optab: Optab{as: AMOVW, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
540 {Optab: Optab{as: AMOVW, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
541
542 {Optab: Optab{as: AMOVB, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
543 {Optab: Optab{as: AMOVB, a1: C_LOREG, a6: C_REG, type_: 36, size: 12}, minGOPPC64: 10, pfxsize: 12},
544 {Optab: Optab{as: AMOVB, a1: C_ADDR, a6: C_REG, type_: 75, size: 12}, minGOPPC64: 10, pfxsize: 12},
545 {Optab: Optab{as: AMOVB, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
546
547 {Optab: Optab{as: AMOVBZ, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
548 {Optab: Optab{as: AMOVBZ, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
549 {Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
550 {Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
551
552 {Optab: Optab{as: AFMOVD, a1: C_LOREG, a6: C_FREG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
553 {Optab: Optab{as: AFMOVD, a1: C_ADDR, a6: C_FREG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
554 {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
555 {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
556
557 {Optab: Optab{as: AADD, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
558 {Optab: Optab{as: AADD, a1: C_32CON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
559 {Optab: Optab{as: AADD, a1: C_S34CON, a2: C_REG, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
560 {Optab: Optab{as: AADD, a1: C_S34CON, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
561 }
562
563 var oprange [ALAST & obj.AMask][]Optab
564
565 var xcmp [C_NCLASS][C_NCLASS]bool
566
567 var pfxEnabled = false
568 var buildOpCfg = ""
569
570
571 func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
572 switch a {
573 case 8, 16, 32, 64:
574
575
576
577
578 if ctxt.Headtype != objabi.Haix && cursym.Align < int16(a) {
579 cursym.Align = int16(a)
580 }
581 if pc&(a-1) != 0 {
582 return int(a - (pc & (a - 1)))
583 }
584 default:
585 ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
586 }
587 return 0
588 }
589
590 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
591 p := cursym.Func().Text
592 if p == nil || p.Link == nil {
593 return
594 }
595
596 if oprange[AANDN&obj.AMask] == nil {
597 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
598 }
599
600 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
601
602 pc := int64(0)
603 p.Pc = pc
604
605 var m int
606 var o *Optab
607 for p = p.Link; p != nil; p = p.Link {
608 p.Pc = pc
609 o = c.oplook(p)
610 m = int(o.size)
611 if m == 0 {
612 if p.As == obj.APCALIGN {
613 a := c.vregoff(&p.From)
614 m = addpad(pc, a, ctxt, cursym)
615 } else {
616 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
617 ctxt.Diag("zero-width instruction\n%v", p)
618 }
619 continue
620 }
621 }
622 pc += int64(m)
623 }
624
625 c.cursym.Size = pc
626
627
633 bflag := 1
634
635 var otxt int64
636 var q *obj.Prog
637 var out [5]uint32
638 var falign int32
639 for bflag != 0 {
640 bflag = 0
641 pc = 0
642 falign = 0
643 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
644 p.Pc = pc
645 o = c.oplook(p)
646
647
648 if (o.type_ == 16 || o.type_ == 17) && p.To.Target() != nil {
649 otxt = p.To.Target().Pc - pc
650 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
651
652
653
654 tgt := p.To.Target()
655 p.To.SetTarget(p.Link)
656 o.asmout(&c, p, o, &out)
657 p.To.SetTarget(tgt)
658
659 bo := int64(out[0]>>21) & 31
660 bi := int16((out[0] >> 16) & 31)
661 invertible := false
662
663 if bo&0x14 == 0x14 {
664
665 } else if bo&0x10 == 0x10 {
666
667 bo ^= 0x2
668 invertible = true
669 } else if bo&0x04 == 0x04 {
670
671 bo ^= 0x8
672 invertible = true
673 }
674
675 if invertible {
676
677
678
679
680
681
682
683
684 p.As = ABC
685 p.From = obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: bo}
686 q = c.newprog()
687 q.As = ABR
688 q.To.Type = obj.TYPE_BRANCH
689 q.To.SetTarget(p.To.Target())
690 q.Link = p.Link
691 p.To.SetTarget(p.Link)
692 p.Link = q
693 p.Reg = REG_CRBIT0 + bi
694 } else {
695
696
697
698
699
700
701
702
703
704
705 q = c.newprog()
706 q.Link = p.Link
707 p.Link = q
708 q.As = ABR
709 q.To.Type = obj.TYPE_BRANCH
710 q.To.SetTarget(p.To.Target())
711 p.To.SetTarget(q)
712 q = c.newprog()
713 q.Link = p.Link
714 p.Link = q
715 q.As = ABR
716 q.To.Type = obj.TYPE_BRANCH
717 q.To.SetTarget(q.Link.Link)
718 }
719 bflag = 1
720 }
721 }
722
723 m = int(o.size)
724 if m == 0 {
725 if p.As == obj.APCALIGN {
726 a := c.vregoff(&p.From)
727 m = addpad(pc, a, ctxt, cursym)
728 } else {
729 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
730 ctxt.Diag("zero-width instruction\n%v", p)
731 }
732 continue
733 }
734 }
735
736
737
738
739 if o.ispfx {
740 mark := p.Mark &^ PFX_X64B
741 if pc&63 == 60 {
742 p.Pc += 4
743 m += 4
744 mark |= PFX_X64B
745 }
746
747
748
749
750
751
752 if mark != p.Mark {
753 bflag = 1
754 p.Mark = mark
755 }
756
757
758
759
760
761
762 switch p.Pc & 31 {
763 case 28:
764 falign = 64
765 case 12:
766 if falign < 64 {
767 falign = 32
768 }
769 }
770 }
771
772 pc += int64(m)
773 }
774
775 c.cursym.Size = pc
776 }
777
778 c.cursym.Size = pc
779 c.cursym.Align = int16(falign)
780 c.cursym.Grow(c.cursym.Size)
781
782
783
784 bp := c.cursym.P
785 var i int32
786 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
787 c.pc = p.Pc
788 o = c.oplook(p)
789 if int(o.size) > 4*len(out) {
790 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
791 }
792
793 if o.type_ == 0 && p.As == obj.APCALIGN {
794 aln := c.vregoff(&p.From)
795 v := addpad(p.Pc, aln, c.ctxt, c.cursym)
796 if v > 0 {
797
798 for i = 0; i < int32(v/4); i++ {
799 c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
800 bp = bp[4:]
801 }
802 }
803 } else {
804 if p.Mark&PFX_X64B != 0 {
805 c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
806 bp = bp[4:]
807 }
808 o.asmout(&c, p, o, &out)
809 for i = 0; i < int32(o.size/4); i++ {
810 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
811 bp = bp[4:]
812 }
813 }
814 }
815 }
816
817 func isint32(v int64) bool {
818 return int64(int32(v)) == v
819 }
820
821 func isuint32(v uint64) bool {
822 return uint64(uint32(v)) == v
823 }
824
825 func (c *ctxt9) aclassreg(reg int16) int {
826 if REG_R0 <= reg && reg <= REG_R31 {
827 return C_REGP + int(reg&1)
828 }
829 if REG_F0 <= reg && reg <= REG_F31 {
830 return C_FREGP + int(reg&1)
831 }
832 if REG_V0 <= reg && reg <= REG_V31 {
833 return C_VREG
834 }
835 if REG_VS0 <= reg && reg <= REG_VS63 {
836 return C_VSREGP + int(reg&1)
837 }
838 if REG_CR0 <= reg && reg <= REG_CR7 || reg == REG_CR {
839 return C_CREG
840 }
841 if REG_CR0LT <= reg && reg <= REG_CR7SO {
842 return C_CRBIT
843 }
844 if REG_SPR0 <= reg && reg <= REG_SPR0+1023 {
845 switch reg {
846 case REG_LR:
847 return C_LR
848
849 case REG_CTR:
850 return C_CTR
851 }
852
853 return C_SPR
854 }
855 if REG_A0 <= reg && reg <= REG_A7 {
856 return C_AREG
857 }
858 if reg == REG_FPSCR {
859 return C_FPSCR
860 }
861 return C_GOK
862 }
863
864 func (c *ctxt9) aclass(a *obj.Addr) int {
865 switch a.Type {
866 case obj.TYPE_NONE:
867 return C_NONE
868
869 case obj.TYPE_REG:
870 return c.aclassreg(a.Reg)
871
872 case obj.TYPE_MEM:
873 if a.Index != 0 {
874 if a.Name != obj.NAME_NONE || a.Offset != 0 {
875 c.ctxt.Logf("Unexpected Instruction operand index %d offset %d class %d \n", a.Index, a.Offset, a.Class)
876
877 }
878 return C_XOREG
879 }
880 switch a.Name {
881 case obj.NAME_GOTREF, obj.NAME_TOCREF:
882 return C_ADDR
883
884 case obj.NAME_EXTERN,
885 obj.NAME_STATIC:
886 c.instoffset = a.Offset
887 if a.Sym == nil {
888 break
889 } else if a.Sym.Type == objabi.STLSBSS {
890
891 if c.ctxt.Flag_shared {
892 return C_TLS_IE
893 }
894
895 return C_TLS_LE
896 } else {
897 return C_ADDR
898 }
899
900 case obj.NAME_AUTO:
901 a.Reg = REGSP
902 c.instoffset = int64(c.autosize) + a.Offset
903 if c.instoffset >= -BIG && c.instoffset < BIG {
904 return C_SOREG
905 }
906 return C_LOREG
907
908 case obj.NAME_PARAM:
909 a.Reg = REGSP
910 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
911 if c.instoffset >= -BIG && c.instoffset < BIG {
912 return C_SOREG
913 }
914 return C_LOREG
915
916 case obj.NAME_NONE:
917 c.instoffset = a.Offset
918 if a.Offset == 0 && a.Index == 0 {
919 return C_ZOREG
920 } else if c.instoffset >= -BIG && c.instoffset < BIG {
921 return C_SOREG
922 } else {
923 return C_LOREG
924 }
925 }
926
927 return C_GOK
928
929 case obj.TYPE_TEXTSIZE:
930 return C_TEXTSIZE
931
932 case obj.TYPE_FCONST:
933
934
935 f64 := a.Val.(float64)
936 if f64 == 0 {
937 if math.Signbit(f64) {
938 return C_S16CON
939 }
940 return C_ZCON
941 }
942 log.Fatalf("Unexpected nonzero FCONST operand %v", a)
943
944 case obj.TYPE_CONST,
945 obj.TYPE_ADDR:
946 switch a.Name {
947 case obj.NAME_NONE:
948 c.instoffset = a.Offset
949 if a.Reg != 0 {
950 if -BIG <= c.instoffset && c.instoffset < BIG {
951 return C_SACON
952 }
953 if isint32(c.instoffset) {
954 return C_LACON
955 }
956 return C_DACON
957 }
958
959 case obj.NAME_EXTERN,
960 obj.NAME_STATIC:
961 s := a.Sym
962 if s == nil {
963 return C_GOK
964 }
965 c.instoffset = a.Offset
966 return C_LACON
967
968 case obj.NAME_AUTO:
969 a.Reg = REGSP
970 c.instoffset = int64(c.autosize) + a.Offset
971 if c.instoffset >= -BIG && c.instoffset < BIG {
972 return C_SACON
973 }
974 return C_LACON
975
976 case obj.NAME_PARAM:
977 a.Reg = REGSP
978 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
979 if c.instoffset >= -BIG && c.instoffset < BIG {
980 return C_SACON
981 }
982 return C_LACON
983
984 default:
985 return C_GOK
986 }
987
988 if c.instoffset >= 0 {
989 sbits := bits.Len64(uint64(c.instoffset))
990 switch {
991 case sbits <= 5:
992 return C_ZCON + sbits
993 case sbits <= 8:
994 return C_U8CON
995 case sbits <= 15:
996 return C_U15CON
997 case sbits <= 16:
998 return C_U16CON
999 case sbits <= 31:
1000 return C_U31CON
1001 case sbits <= 32:
1002 return C_U32CON
1003 case sbits <= 33:
1004 return C_S34CON
1005 default:
1006 return C_64CON
1007 }
1008 } else {
1009 sbits := bits.Len64(uint64(^c.instoffset))
1010 switch {
1011 case sbits <= 15:
1012 return C_S16CON
1013 case sbits <= 31:
1014 return C_S32CON
1015 case sbits <= 33:
1016 return C_S34CON
1017 default:
1018 return C_64CON
1019 }
1020 }
1021
1022 case obj.TYPE_BRANCH:
1023 if a.Sym != nil && c.ctxt.Flag_dynlink && !pfxEnabled {
1024 return C_BRAPIC
1025 }
1026 return C_BRA
1027 }
1028
1029 return C_GOK
1030 }
1031
1032 func prasm(p *obj.Prog) {
1033 fmt.Printf("%v\n", p)
1034 }
1035
1036 func (c *ctxt9) oplook(p *obj.Prog) *Optab {
1037 a1 := int(p.Optab)
1038 if a1 != 0 {
1039 return &optab[a1-1]
1040 }
1041 a1 = int(p.From.Class)
1042 if a1 == 0 {
1043 a1 = c.aclass(&p.From) + 1
1044 p.From.Class = int8(a1)
1045 }
1046 a1--
1047
1048 argsv := [3]int{C_NONE + 1, C_NONE + 1, C_NONE + 1}
1049 for i, ap := range p.RestArgs {
1050 argsv[i] = int(ap.Addr.Class)
1051 if argsv[i] == 0 {
1052 argsv[i] = c.aclass(&ap.Addr) + 1
1053 ap.Addr.Class = int8(argsv[i])
1054 }
1055
1056 }
1057 a3 := argsv[0] - 1
1058 a4 := argsv[1] - 1
1059 a5 := argsv[2] - 1
1060
1061 a6 := int(p.To.Class)
1062 if a6 == 0 {
1063 a6 = c.aclass(&p.To) + 1
1064 p.To.Class = int8(a6)
1065 }
1066 a6--
1067
1068 a2 := C_NONE
1069 if p.Reg != 0 {
1070 a2 = c.aclassreg(p.Reg)
1071 }
1072
1073
1074 ops := oprange[p.As&obj.AMask]
1075 c1 := &xcmp[a1]
1076 c2 := &xcmp[a2]
1077 c3 := &xcmp[a3]
1078 c4 := &xcmp[a4]
1079 c5 := &xcmp[a5]
1080 c6 := &xcmp[a6]
1081 for i := range ops {
1082 op := &ops[i]
1083 if c1[op.a1] && c2[op.a2] && c3[op.a3] && c4[op.a4] && c5[op.a5] && c6[op.a6] {
1084 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1085 return op
1086 }
1087 }
1088
1089 c.ctxt.Diag("illegal combination %v %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5), DRconv(a6))
1090 prasm(p)
1091 if ops == nil {
1092 ops = optab
1093 }
1094 return &ops[0]
1095 }
1096
1097
1098
1099
1100
1101
1102
1103 func cmp(a int, b int) bool {
1104 if a == b {
1105 return true
1106 }
1107 switch a {
1108
1109 case C_SPR:
1110 if b == C_LR || b == C_CTR {
1111 return true
1112 }
1113
1114 case C_U1CON:
1115 return cmp(C_ZCON, b)
1116 case C_U2CON:
1117 return cmp(C_U1CON, b)
1118 case C_U3CON:
1119 return cmp(C_U2CON, b)
1120 case C_U4CON:
1121 return cmp(C_U3CON, b)
1122 case C_U5CON:
1123 return cmp(C_U4CON, b)
1124 case C_U8CON:
1125 return cmp(C_U5CON, b)
1126 case C_U15CON:
1127 return cmp(C_U8CON, b)
1128 case C_S16CON:
1129 return cmp(C_U15CON, b)
1130 case C_U16CON:
1131 return cmp(C_U15CON, b)
1132 case C_16CON:
1133 return cmp(C_S16CON, b) || cmp(C_U16CON, b)
1134 case C_U31CON:
1135 return cmp(C_U16CON, b)
1136 case C_U32CON:
1137 return cmp(C_U31CON, b)
1138 case C_S32CON:
1139 return cmp(C_U31CON, b) || cmp(C_S16CON, b)
1140 case C_32CON:
1141 return cmp(C_S32CON, b) || cmp(C_U32CON, b)
1142 case C_S34CON:
1143 return cmp(C_32CON, b)
1144 case C_64CON:
1145 return cmp(C_S34CON, b)
1146
1147 case C_LACON:
1148 return cmp(C_SACON, b)
1149
1150 case C_SOREG:
1151 return cmp(C_ZOREG, b)
1152
1153 case C_LOREG:
1154 return cmp(C_SOREG, b)
1155
1156 case C_XOREG:
1157 return cmp(C_REG, b) || cmp(C_ZOREG, b)
1158
1159
1160 case C_REG:
1161 return cmp(C_REGP, b) || (b == C_ZCON && r0iszero != 0)
1162 case C_FREG:
1163 return cmp(C_FREGP, b)
1164 case C_VSREG:
1165
1166 return cmp(C_VSREGP, b) || cmp(C_VREG, b)
1167
1168 case C_ANY:
1169 return true
1170 }
1171
1172 return false
1173 }
1174
1175
1176
1177
1178 func optabLess(i, j int) bool {
1179 p1 := &optab[i]
1180 p2 := &optab[j]
1181 n := int(p1.as) - int(p2.as)
1182
1183 if n != 0 {
1184 return n < 0
1185 }
1186
1187
1188 n = int(p1.size) - int(p2.size)
1189 if n != 0 {
1190 return n < 0
1191 }
1192
1193
1194 n = int(p1.a1) - int(p2.a1)
1195 if n != 0 {
1196 return n < 0
1197 }
1198 n = int(p1.a2) - int(p2.a2)
1199 if n != 0 {
1200 return n < 0
1201 }
1202 n = int(p1.a3) - int(p2.a3)
1203 if n != 0 {
1204 return n < 0
1205 }
1206 n = int(p1.a4) - int(p2.a4)
1207 if n != 0 {
1208 return n < 0
1209 }
1210 n = int(p1.a5) - int(p2.a5)
1211 if n != 0 {
1212 return n < 0
1213 }
1214 n = int(p1.a6) - int(p2.a6)
1215 if n != 0 {
1216 return n < 0
1217 }
1218 return false
1219 }
1220
1221
1222
1223
1224 func opset(a, b0 obj.As) {
1225 oprange[a&obj.AMask] = oprange[b0]
1226 }
1227
1228
1229
1230 func NeedTOCpointer(ctxt *obj.Link) bool {
1231 return !pfxEnabled && ctxt.Flag_shared
1232 }
1233
1234
1235 func buildop(ctxt *obj.Link) {
1236
1237 pfxEnabled = buildcfg.GOPPC64 >= 10 && buildcfg.GOOS == "linux"
1238 cfg := fmt.Sprintf("power%d/%s/%s", buildcfg.GOPPC64, buildcfg.GOARCH, buildcfg.GOOS)
1239 if cfg == buildOpCfg {
1240
1241
1242
1243 return
1244 }
1245 buildOpCfg = cfg
1246
1247
1248 prefixOptab := make([]Optab, 0, len(prefixableOptab))
1249 for _, entry := range prefixableOptab {
1250 entry := entry
1251 if pfxEnabled && buildcfg.GOPPC64 >= entry.minGOPPC64 {
1252
1253 entry.ispfx = true
1254 entry.size = entry.pfxsize
1255 }
1256 prefixOptab = append(prefixOptab, entry.Optab)
1257
1258 }
1259
1260 for i := 0; i < C_NCLASS; i++ {
1261 for n := 0; n < C_NCLASS; n++ {
1262 if cmp(n, i) {
1263 xcmp[i][n] = true
1264 }
1265 }
1266 }
1267
1268
1269 optab = make([]Optab, 0, len(optabBase)+len(optabGen)+len(prefixOptab))
1270 optab = append(optab, optabBase...)
1271 optab = append(optab, optabGen...)
1272 optab = append(optab, prefixOptab...)
1273 sort.Slice(optab, optabLess)
1274
1275 for i := range optab {
1276
1277 if optab[i].asmout == nil {
1278 optab[i].asmout = asmout
1279 }
1280 }
1281
1282 for i := 0; i < len(optab); {
1283 r := optab[i].as
1284 r0 := r & obj.AMask
1285 start := i
1286 for i < len(optab) && optab[i].as == r {
1287 i++
1288 }
1289 oprange[r0] = optab[start:i]
1290
1291 switch r {
1292 default:
1293 if !opsetGen(r) {
1294 ctxt.Diag("unknown op in build: %v", r)
1295 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
1296 }
1297
1298 case ADCBF:
1299 opset(ADCBI, r0)
1300
1301 opset(ADCBST, r0)
1302 opset(ADCBT, r0)
1303 opset(ADCBTST, r0)
1304 opset(ADCBZ, r0)
1305 opset(AICBI, r0)
1306
1307 case ASTDCCC:
1308 opset(ASTWCCC, r0)
1309 opset(ASTHCCC, r0)
1310 opset(ASTBCCC, r0)
1311
1312 case AREM:
1313 opset(AREM, r0)
1314
1315 case AREMU:
1316 opset(AREMU, r0)
1317
1318 case AREMD:
1319 opset(AREMDU, r0)
1320
1321 case AMULLW:
1322 opset(AMULLD, r0)
1323
1324 case ADIVW:
1325 opset(AMULHW, r0)
1326
1327 opset(AMULHWCC, r0)
1328 opset(AMULHWU, r0)
1329 opset(AMULHWUCC, r0)
1330 opset(AMULLWCC, r0)
1331 opset(AMULLWVCC, r0)
1332 opset(AMULLWV, r0)
1333 opset(ADIVWCC, r0)
1334 opset(ADIVWV, r0)
1335 opset(ADIVWVCC, r0)
1336 opset(ADIVWU, r0)
1337 opset(ADIVWUCC, r0)
1338 opset(ADIVWUV, r0)
1339 opset(ADIVWUVCC, r0)
1340 opset(AMODUD, r0)
1341 opset(AMODUW, r0)
1342 opset(AMODSD, r0)
1343 opset(AMODSW, r0)
1344 opset(AADDCC, r0)
1345 opset(AADDCV, r0)
1346 opset(AADDCVCC, r0)
1347 opset(AADDV, r0)
1348 opset(AADDVCC, r0)
1349 opset(AADDE, r0)
1350 opset(AADDECC, r0)
1351 opset(AADDEV, r0)
1352 opset(AADDEVCC, r0)
1353 opset(AMULHD, r0)
1354 opset(AMULHDCC, r0)
1355 opset(AMULHDU, r0)
1356 opset(AMULHDUCC, r0)
1357 opset(AMULLDCC, r0)
1358 opset(AMULLDVCC, r0)
1359 opset(AMULLDV, r0)
1360 opset(ADIVD, r0)
1361 opset(ADIVDCC, r0)
1362 opset(ADIVDE, r0)
1363 opset(ADIVDEU, r0)
1364 opset(ADIVDECC, r0)
1365 opset(ADIVDEUCC, r0)
1366 opset(ADIVDVCC, r0)
1367 opset(ADIVDV, r0)
1368 opset(ADIVDU, r0)
1369 opset(ADIVDUV, r0)
1370 opset(ADIVDUVCC, r0)
1371 opset(ADIVDUCC, r0)
1372
1373 case ACRAND:
1374 opset(ACRANDN, r0)
1375 opset(ACREQV, r0)
1376 opset(ACRNAND, r0)
1377 opset(ACRNOR, r0)
1378 opset(ACROR, r0)
1379 opset(ACRORN, r0)
1380 opset(ACRXOR, r0)
1381
1382 case APOPCNTD:
1383 opset(APOPCNTW, r0)
1384 opset(APOPCNTB, r0)
1385 opset(ACNTTZW, r0)
1386 opset(ACNTTZWCC, r0)
1387 opset(ACNTTZD, r0)
1388 opset(ACNTTZDCC, r0)
1389
1390 case ACOPY:
1391 opset(APASTECC, r0)
1392
1393 case AMADDHD:
1394 opset(AMADDHDU, r0)
1395 opset(AMADDLD, r0)
1396
1397 case AMOVBZ:
1398 opset(AMOVH, r0)
1399 opset(AMOVHZ, r0)
1400
1401 case AMOVBZU:
1402 opset(AMOVHU, r0)
1403
1404 opset(AMOVHZU, r0)
1405 opset(AMOVWU, r0)
1406 opset(AMOVWZU, r0)
1407 opset(AMOVDU, r0)
1408 opset(AMOVMW, r0)
1409
1410 case ALVEBX:
1411 opset(ALVEHX, r0)
1412 opset(ALVEWX, r0)
1413 opset(ALVX, r0)
1414 opset(ALVXL, r0)
1415 opset(ALVSL, r0)
1416 opset(ALVSR, r0)
1417
1418 case ASTVEBX:
1419 opset(ASTVEHX, r0)
1420 opset(ASTVEWX, r0)
1421 opset(ASTVX, r0)
1422 opset(ASTVXL, r0)
1423
1424 case AVAND:
1425 opset(AVAND, r0)
1426 opset(AVANDC, r0)
1427 opset(AVNAND, r0)
1428
1429 case AVMRGOW:
1430 opset(AVMRGEW, r0)
1431
1432 case AVOR:
1433 opset(AVOR, r0)
1434 opset(AVORC, r0)
1435 opset(AVXOR, r0)
1436 opset(AVNOR, r0)
1437 opset(AVEQV, r0)
1438
1439 case AVADDUM:
1440 opset(AVADDUBM, r0)
1441 opset(AVADDUHM, r0)
1442 opset(AVADDUWM, r0)
1443 opset(AVADDUDM, r0)
1444 opset(AVADDUQM, r0)
1445
1446 case AVADDCU:
1447 opset(AVADDCUQ, r0)
1448 opset(AVADDCUW, r0)
1449
1450 case AVADDUS:
1451 opset(AVADDUBS, r0)
1452 opset(AVADDUHS, r0)
1453 opset(AVADDUWS, r0)
1454
1455 case AVADDSS:
1456 opset(AVADDSBS, r0)
1457 opset(AVADDSHS, r0)
1458 opset(AVADDSWS, r0)
1459
1460 case AVADDE:
1461 opset(AVADDEUQM, r0)
1462 opset(AVADDECUQ, r0)
1463
1464 case AVSUBUM:
1465 opset(AVSUBUBM, r0)
1466 opset(AVSUBUHM, r0)
1467 opset(AVSUBUWM, r0)
1468 opset(AVSUBUDM, r0)
1469 opset(AVSUBUQM, r0)
1470
1471 case AVSUBCU:
1472 opset(AVSUBCUQ, r0)
1473 opset(AVSUBCUW, r0)
1474
1475 case AVSUBUS:
1476 opset(AVSUBUBS, r0)
1477 opset(AVSUBUHS, r0)
1478 opset(AVSUBUWS, r0)
1479
1480 case AVSUBSS:
1481 opset(AVSUBSBS, r0)
1482 opset(AVSUBSHS, r0)
1483 opset(AVSUBSWS, r0)
1484
1485 case AVSUBE:
1486 opset(AVSUBEUQM, r0)
1487 opset(AVSUBECUQ, r0)
1488
1489 case AVMULESB:
1490 opset(AVMULOSB, r0)
1491 opset(AVMULEUB, r0)
1492 opset(AVMULOUB, r0)
1493 opset(AVMULESH, r0)
1494 opset(AVMULOSH, r0)
1495 opset(AVMULEUH, r0)
1496 opset(AVMULOUH, r0)
1497 opset(AVMULESW, r0)
1498 opset(AVMULOSW, r0)
1499 opset(AVMULEUW, r0)
1500 opset(AVMULOUW, r0)
1501 opset(AVMULUWM, r0)
1502 case AVPMSUM:
1503 opset(AVPMSUMB, r0)
1504 opset(AVPMSUMH, r0)
1505 opset(AVPMSUMW, r0)
1506 opset(AVPMSUMD, r0)
1507
1508 case AVR:
1509 opset(AVRLB, r0)
1510 opset(AVRLH, r0)
1511 opset(AVRLW, r0)
1512 opset(AVRLD, r0)
1513
1514 case AVS:
1515 opset(AVSLB, r0)
1516 opset(AVSLH, r0)
1517 opset(AVSLW, r0)
1518 opset(AVSL, r0)
1519 opset(AVSLO, r0)
1520 opset(AVSRB, r0)
1521 opset(AVSRH, r0)
1522 opset(AVSRW, r0)
1523 opset(AVSR, r0)
1524 opset(AVSRO, r0)
1525 opset(AVSLD, r0)
1526 opset(AVSRD, r0)
1527
1528 case AVSA:
1529 opset(AVSRAB, r0)
1530 opset(AVSRAH, r0)
1531 opset(AVSRAW, r0)
1532 opset(AVSRAD, r0)
1533
1534 case AVSOI:
1535 opset(AVSLDOI, r0)
1536
1537 case AVCLZ:
1538 opset(AVCLZB, r0)
1539 opset(AVCLZH, r0)
1540 opset(AVCLZW, r0)
1541 opset(AVCLZD, r0)
1542
1543 case AVPOPCNT:
1544 opset(AVPOPCNTB, r0)
1545 opset(AVPOPCNTH, r0)
1546 opset(AVPOPCNTW, r0)
1547 opset(AVPOPCNTD, r0)
1548
1549 case AVCMPEQ:
1550 opset(AVCMPEQUB, r0)
1551 opset(AVCMPEQUBCC, r0)
1552 opset(AVCMPEQUH, r0)
1553 opset(AVCMPEQUHCC, r0)
1554 opset(AVCMPEQUW, r0)
1555 opset(AVCMPEQUWCC, r0)
1556 opset(AVCMPEQUD, r0)
1557 opset(AVCMPEQUDCC, r0)
1558
1559 case AVCMPGT:
1560 opset(AVCMPGTUB, r0)
1561 opset(AVCMPGTUBCC, r0)
1562 opset(AVCMPGTUH, r0)
1563 opset(AVCMPGTUHCC, r0)
1564 opset(AVCMPGTUW, r0)
1565 opset(AVCMPGTUWCC, r0)
1566 opset(AVCMPGTUD, r0)
1567 opset(AVCMPGTUDCC, r0)
1568 opset(AVCMPGTSB, r0)
1569 opset(AVCMPGTSBCC, r0)
1570 opset(AVCMPGTSH, r0)
1571 opset(AVCMPGTSHCC, r0)
1572 opset(AVCMPGTSW, r0)
1573 opset(AVCMPGTSWCC, r0)
1574 opset(AVCMPGTSD, r0)
1575 opset(AVCMPGTSDCC, r0)
1576
1577 case AVCMPNEZB:
1578 opset(AVCMPNEZBCC, r0)
1579 opset(AVCMPNEB, r0)
1580 opset(AVCMPNEBCC, r0)
1581 opset(AVCMPNEH, r0)
1582 opset(AVCMPNEHCC, r0)
1583 opset(AVCMPNEW, r0)
1584 opset(AVCMPNEWCC, r0)
1585
1586 case AVPERM:
1587 opset(AVPERMXOR, r0)
1588 opset(AVPERMR, r0)
1589
1590 case AVBPERMQ:
1591 opset(AVBPERMD, r0)
1592
1593 case AVSEL:
1594 opset(AVSEL, r0)
1595
1596 case AVSPLTB:
1597 opset(AVSPLTH, r0)
1598 opset(AVSPLTW, r0)
1599
1600 case AVSPLTISB:
1601 opset(AVSPLTISH, r0)
1602 opset(AVSPLTISW, r0)
1603
1604 case AVCIPH:
1605 opset(AVCIPHER, r0)
1606 opset(AVCIPHERLAST, r0)
1607
1608 case AVNCIPH:
1609 opset(AVNCIPHER, r0)
1610 opset(AVNCIPHERLAST, r0)
1611
1612 case AVSBOX:
1613 opset(AVSBOX, r0)
1614
1615 case AVSHASIGMA:
1616 opset(AVSHASIGMAW, r0)
1617 opset(AVSHASIGMAD, r0)
1618
1619 case ALXVD2X:
1620 opset(ALXVDSX, r0)
1621 opset(ALXVW4X, r0)
1622 opset(ALXVH8X, r0)
1623 opset(ALXVB16X, r0)
1624
1625 case ALXV:
1626 opset(ALXV, r0)
1627
1628 case ALXVL:
1629 opset(ALXVLL, r0)
1630 opset(ALXVX, r0)
1631
1632 case ASTXVD2X:
1633 opset(ASTXVW4X, r0)
1634 opset(ASTXVH8X, r0)
1635 opset(ASTXVB16X, r0)
1636
1637 case ASTXV:
1638 opset(ASTXV, r0)
1639
1640 case ASTXVL:
1641 opset(ASTXVLL, r0)
1642 opset(ASTXVX, r0)
1643
1644 case ALXSDX:
1645 opset(ALXSDX, r0)
1646
1647 case ASTXSDX:
1648 opset(ASTXSDX, r0)
1649
1650 case ALXSIWAX:
1651 opset(ALXSIWZX, r0)
1652
1653 case ASTXSIWX:
1654 opset(ASTXSIWX, r0)
1655
1656 case AMFVSRD:
1657 opset(AMFFPRD, r0)
1658 opset(AMFVRD, r0)
1659 opset(AMFVSRWZ, r0)
1660 opset(AMFVSRLD, r0)
1661
1662 case AMTVSRD:
1663 opset(AMTFPRD, r0)
1664 opset(AMTVRD, r0)
1665 opset(AMTVSRWA, r0)
1666 opset(AMTVSRWZ, r0)
1667 opset(AMTVSRWS, r0)
1668
1669 case AXXLAND:
1670 opset(AXXLANDC, r0)
1671 opset(AXXLEQV, r0)
1672 opset(AXXLNAND, r0)
1673 opset(AXXLORC, r0)
1674 opset(AXXLNOR, r0)
1675 opset(AXXLORQ, r0)
1676 opset(AXXLXOR, r0)
1677 opset(AXXLOR, r0)
1678 opset(AXSMAXJDP, r0)
1679 opset(AXSMINJDP, r0)
1680 opset(AXXMRGHW, r0)
1681 opset(AXXMRGLW, r0)
1682 opset(AXXPERM, r0)
1683 opset(AXVADDDP, r0)
1684 opset(AXVSUBDP, r0)
1685 opset(AXVMULDP, r0)
1686 opset(AXVDIVDP, r0)
1687 opset(AXVMADDADP, r0)
1688 opset(AXVMAXDP, r0)
1689 opset(AXVMINDP, r0)
1690 opset(AXVADDSP, r0)
1691 opset(AXVSUBSP, r0)
1692 opset(AXVMULSP, r0)
1693 opset(AXVDIVSP, r0)
1694 opset(AXVMADDASP, r0)
1695 opset(AXVMAXSP, r0)
1696 opset(AXVMINSP, r0)
1697
1698 case AXXSEL:
1699 opset(AXXSEL, r0)
1700
1701 case AXXSPLTW:
1702 opset(AXXSPLTW, r0)
1703
1704 case AXXSPLTIB:
1705 opset(AXXSPLTIB, r0)
1706
1707 case AXXSLDWI:
1708 opset(AXXPERMDI, r0)
1709 opset(AXXSLDWI, r0)
1710
1711 case AXXBRQ:
1712 opset(AXXBRD, r0)
1713 opset(AXXBRW, r0)
1714 opset(AXXBRH, r0)
1715
1716 case AXSCVDPSP:
1717 opset(AXSCVSPDP, r0)
1718 opset(AXSCVDPSPN, r0)
1719 opset(AXSCVSPDPN, r0)
1720 opset(AXVCVDPSP, r0)
1721 opset(AXVCVSPDP, r0)
1722 opset(AXSCVDPSXDS, r0)
1723 opset(AXSCVDPSXWS, r0)
1724 opset(AXSCVDPUXDS, r0)
1725 opset(AXSCVDPUXWS, r0)
1726 opset(AXSCVSXDDP, r0)
1727 opset(AXSCVUXDDP, r0)
1728 opset(AXSCVSXDSP, r0)
1729 opset(AXSCVUXDSP, r0)
1730 opset(AXVCVDPSXDS, r0)
1731 opset(AXVCVDPSXWS, r0)
1732 opset(AXVCVDPUXDS, r0)
1733 opset(AXVCVDPUXWS, r0)
1734 opset(AXVCVSPSXDS, r0)
1735 opset(AXVCVSPSXWS, r0)
1736 opset(AXVCVSPUXDS, r0)
1737 opset(AXVCVSPUXWS, r0)
1738 opset(AXVCVSXDDP, r0)
1739 opset(AXVCVSXWDP, r0)
1740 opset(AXVCVUXDDP, r0)
1741 opset(AXVCVUXWDP, r0)
1742 opset(AXVCVSXDSP, r0)
1743 opset(AXVCVSXWSP, r0)
1744 opset(AXVCVUXDSP, r0)
1745 opset(AXVCVUXWSP, r0)
1746 opset(AXVSQRTDP, r0)
1747 opset(AXVSQRTSP, r0)
1748
1749 case AAND:
1750 opset(AANDN, r0)
1751 opset(AANDNCC, r0)
1752 opset(AEQV, r0)
1753 opset(AEQVCC, r0)
1754 opset(ANAND, r0)
1755 opset(ANANDCC, r0)
1756 opset(ANOR, r0)
1757 opset(ANORCC, r0)
1758 opset(AORCC, r0)
1759 opset(AORN, r0)
1760 opset(AORNCC, r0)
1761 opset(AXORCC, r0)
1762
1763 case AADDME:
1764 opset(AADDMECC, r0)
1765
1766 opset(AADDMEV, r0)
1767 opset(AADDMEVCC, r0)
1768 opset(AADDZE, r0)
1769 opset(AADDZECC, r0)
1770 opset(AADDZEV, r0)
1771 opset(AADDZEVCC, r0)
1772 opset(ASUBME, r0)
1773 opset(ASUBMECC, r0)
1774 opset(ASUBMEV, r0)
1775 opset(ASUBMEVCC, r0)
1776 opset(ASUBZE, r0)
1777 opset(ASUBZECC, r0)
1778 opset(ASUBZEV, r0)
1779 opset(ASUBZEVCC, r0)
1780
1781 case AADDC:
1782 opset(AADDCCC, r0)
1783
1784 case ABEQ:
1785 opset(ABGE, r0)
1786 opset(ABGT, r0)
1787 opset(ABLE, r0)
1788 opset(ABLT, r0)
1789 opset(ABNE, r0)
1790 opset(ABVC, r0)
1791 opset(ABVS, r0)
1792
1793 case ABR:
1794 opset(ABL, r0)
1795
1796 case ABC:
1797 opset(ABCL, r0)
1798
1799 case ABDNZ:
1800 opset(ABDZ, r0)
1801
1802 case AEXTSB:
1803 opset(AEXTSBCC, r0)
1804
1805 opset(AEXTSH, r0)
1806 opset(AEXTSHCC, r0)
1807 opset(ACNTLZW, r0)
1808 opset(ACNTLZWCC, r0)
1809 opset(ACNTLZD, r0)
1810 opset(AEXTSW, r0)
1811 opset(AEXTSWCC, r0)
1812 opset(ACNTLZDCC, r0)
1813
1814 case AFABS:
1815 opset(AFABSCC, r0)
1816
1817 opset(AFNABS, r0)
1818 opset(AFNABSCC, r0)
1819 opset(AFNEG, r0)
1820 opset(AFNEGCC, r0)
1821 opset(AFRSP, r0)
1822 opset(AFRSPCC, r0)
1823 opset(AFCTIW, r0)
1824 opset(AFCTIWCC, r0)
1825 opset(AFCTIWZ, r0)
1826 opset(AFCTIWZCC, r0)
1827 opset(AFCTID, r0)
1828 opset(AFCTIDCC, r0)
1829 opset(AFCTIDZ, r0)
1830 opset(AFCTIDZCC, r0)
1831 opset(AFCFID, r0)
1832 opset(AFCFIDCC, r0)
1833 opset(AFCFIDU, r0)
1834 opset(AFCFIDUCC, r0)
1835 opset(AFCFIDS, r0)
1836 opset(AFCFIDSCC, r0)
1837 opset(AFRES, r0)
1838 opset(AFRESCC, r0)
1839 opset(AFRIM, r0)
1840 opset(AFRIMCC, r0)
1841 opset(AFRIP, r0)
1842 opset(AFRIPCC, r0)
1843 opset(AFRIZ, r0)
1844 opset(AFRIZCC, r0)
1845 opset(AFRIN, r0)
1846 opset(AFRINCC, r0)
1847 opset(AFRSQRTE, r0)
1848 opset(AFRSQRTECC, r0)
1849 opset(AFSQRT, r0)
1850 opset(AFSQRTCC, r0)
1851 opset(AFSQRTS, r0)
1852 opset(AFSQRTSCC, r0)
1853
1854 case AFADD:
1855 opset(AFADDS, r0)
1856 opset(AFADDCC, r0)
1857 opset(AFADDSCC, r0)
1858 opset(AFCPSGN, r0)
1859 opset(AFCPSGNCC, r0)
1860 opset(AFDIV, r0)
1861 opset(AFDIVS, r0)
1862 opset(AFDIVCC, r0)
1863 opset(AFDIVSCC, r0)
1864 opset(AFSUB, r0)
1865 opset(AFSUBS, r0)
1866 opset(AFSUBCC, r0)
1867 opset(AFSUBSCC, r0)
1868 opset(ADADD, r0)
1869 opset(ADDIV, r0)
1870 opset(ADSUB, r0)
1871
1872 case ADADDQ:
1873 opset(ADDIVQ, r0)
1874 opset(ADSUBQ, r0)
1875
1876 case AFMADD:
1877 opset(AFMADDCC, r0)
1878 opset(AFMADDS, r0)
1879 opset(AFMADDSCC, r0)
1880 opset(AFMSUB, r0)
1881 opset(AFMSUBCC, r0)
1882 opset(AFMSUBS, r0)
1883 opset(AFMSUBSCC, r0)
1884 opset(AFNMADD, r0)
1885 opset(AFNMADDCC, r0)
1886 opset(AFNMADDS, r0)
1887 opset(AFNMADDSCC, r0)
1888 opset(AFNMSUB, r0)
1889 opset(AFNMSUBCC, r0)
1890 opset(AFNMSUBS, r0)
1891 opset(AFNMSUBSCC, r0)
1892 opset(AFSEL, r0)
1893 opset(AFSELCC, r0)
1894
1895 case AFMUL:
1896 opset(AFMULS, r0)
1897 opset(AFMULCC, r0)
1898 opset(AFMULSCC, r0)
1899 opset(ADMUL, r0)
1900
1901 case ADMULQ:
1902 opset(ADMULQ, r0)
1903
1904 case AFCMPO:
1905 opset(AFCMPU, r0)
1906 opset(ADCMPU, r0)
1907 opset(ADCMPO, r0)
1908
1909 case ADCMPOQ:
1910 opset(ADCMPUQ, r0)
1911
1912 case AMTFSB0:
1913 opset(AMTFSB0CC, r0)
1914 opset(AMTFSB1, r0)
1915 opset(AMTFSB1CC, r0)
1916
1917 case ANEG:
1918 opset(ANEGCC, r0)
1919
1920 opset(ANEGV, r0)
1921 opset(ANEGVCC, r0)
1922
1923 case AOR:
1924 opset(AXOR, r0)
1925
1926 case AORIS:
1927 opset(AXORIS, r0)
1928
1929 case ASLW:
1930 opset(ASLWCC, r0)
1931 opset(ASRW, r0)
1932 opset(ASRWCC, r0)
1933 opset(AROTLW, r0)
1934
1935 case ASLD:
1936 opset(ASLDCC, r0)
1937 opset(ASRD, r0)
1938 opset(ASRDCC, r0)
1939 opset(AROTL, r0)
1940
1941 case ASRAW:
1942 opset(ASRAWCC, r0)
1943
1944 case AEXTSWSLI:
1945 opset(AEXTSWSLICC, r0)
1946
1947 case ASRAD:
1948 opset(ASRADCC, r0)
1949
1950 case ASUB:
1951 opset(ASUB, r0)
1952
1953 opset(ASUBCC, r0)
1954 opset(ASUBV, r0)
1955 opset(ASUBVCC, r0)
1956 opset(ASUBCCC, r0)
1957 opset(ASUBCV, r0)
1958 opset(ASUBCVCC, r0)
1959 opset(ASUBE, r0)
1960 opset(ASUBECC, r0)
1961 opset(ASUBEV, r0)
1962 opset(ASUBEVCC, r0)
1963
1964 case ASYNC:
1965 opset(AISYNC, r0)
1966 opset(ALWSYNC, r0)
1967 opset(APTESYNC, r0)
1968 opset(ATLBSYNC, r0)
1969
1970 case ARLWNM:
1971 opset(ARLWNMCC, r0)
1972 opset(ARLWMI, r0)
1973 opset(ARLWMICC, r0)
1974
1975 case ARLDMI:
1976 opset(ARLDMICC, r0)
1977 opset(ARLDIMI, r0)
1978 opset(ARLDIMICC, r0)
1979
1980 case ARLDC:
1981 opset(ARLDCCC, r0)
1982
1983 case ARLDCL:
1984 opset(ARLDCR, r0)
1985 opset(ARLDCLCC, r0)
1986 opset(ARLDCRCC, r0)
1987
1988 case ARLDICL:
1989 opset(ARLDICLCC, r0)
1990 opset(ARLDICR, r0)
1991 opset(ARLDICRCC, r0)
1992 opset(ARLDIC, r0)
1993 opset(ARLDICCC, r0)
1994 opset(ACLRLSLDI, r0)
1995
1996 case AFMOVD:
1997 opset(AFMOVDCC, r0)
1998 opset(AFMOVDU, r0)
1999 opset(AFMOVS, r0)
2000 opset(AFMOVSU, r0)
2001
2002 case ALDAR:
2003 opset(ALBAR, r0)
2004 opset(ALHAR, r0)
2005 opset(ALWAR, r0)
2006
2007 case ASYSCALL:
2008 opset(ARFI, r0)
2009
2010 opset(ARFCI, r0)
2011 opset(ARFID, r0)
2012 opset(AHRFID, r0)
2013
2014 case AMOVHBR:
2015 opset(AMOVWBR, r0)
2016 opset(AMOVDBR, r0)
2017
2018 case ASLBMFEE:
2019 opset(ASLBMFEV, r0)
2020
2021 case ATW:
2022 opset(ATD, r0)
2023
2024 case ATLBIE:
2025 opset(ASLBIE, r0)
2026 opset(ATLBIEL, r0)
2027
2028 case AEIEIO:
2029 opset(ASLBIA, r0)
2030
2031 case ACMP:
2032 opset(ACMPW, r0)
2033
2034 case ACMPU:
2035 opset(ACMPWU, r0)
2036
2037 case ACMPB:
2038 opset(ACMPB, r0)
2039
2040 case AFTDIV:
2041 opset(AFTDIV, r0)
2042
2043 case AFTSQRT:
2044 opset(AFTSQRT, r0)
2045
2046 case AMOVW:
2047 opset(AMOVWZ, r0)
2048
2049 case AVCLZLSBB:
2050 opset(AVCTZLSBB, r0)
2051
2052 case AADD,
2053 AADDIS,
2054 AANDCC,
2055 AANDISCC,
2056 AFMOVSX,
2057 AFMOVSZ,
2058 ALSW,
2059 AMOVD,
2060 AMOVB,
2061 AMOVBU,
2062 AMOVFL,
2063
2064 ASUBC,
2065 ASTSW,
2066 ASLBMTE,
2067 AWORD,
2068 ADWORD,
2069 ADARN,
2070 AVMSUMUDM,
2071 AADDEX,
2072 ACMPEQB,
2073 ACLRLSLWI,
2074 AMTVSRDD,
2075 APNOP,
2076 AISEL,
2077 ASETB,
2078 obj.ANOP,
2079 obj.ATEXT,
2080 obj.AUNDEF,
2081 obj.AFUNCDATA,
2082 obj.APCALIGN,
2083 obj.APCDATA,
2084 obj.ADUFFZERO,
2085 obj.ADUFFCOPY:
2086 break
2087 }
2088 }
2089 }
2090
2091 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
2092 return o<<26 | xo<<1 | oe<<11
2093 }
2094
2095 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
2096 return o<<26 | xo<<2 | oe<<11
2097 }
2098
2099 func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32 {
2100 return o<<26 | xo<<2 | oe<<16
2101 }
2102
2103 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
2104 return o<<26 | xo<<3 | oe<<11
2105 }
2106
2107 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
2108 return o<<26 | xo<<4 | oe<<11
2109 }
2110
2111 func OPDQ(o uint32, xo uint32, oe uint32) uint32 {
2112 return o<<26 | xo | oe<<4
2113 }
2114
2115 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2116 return o<<26 | xo | oe<<11 | rc&1
2117 }
2118
2119 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2120 return o<<26 | xo | oe<<11 | (rc&1)<<10
2121 }
2122
2123 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2124 return o<<26 | xo<<1 | oe<<10 | rc&1
2125 }
2126
2127
2128 func OPMD(o, xo, rc uint32) uint32 {
2129 return o<<26 | xo<<2 | rc&1
2130 }
2131
2132
2133 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
2134 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
2135 }
2136
2137
2138 func AOP_RR(op uint32, d uint32, a uint32) uint32 {
2139 return op | (d&31)<<21 | (a&31)<<11
2140 }
2141
2142
2143 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2144 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
2145 }
2146
2147 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2148 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
2149 }
2150
2151
2152 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2153 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
2154 }
2155
2156
2157 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
2158 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
2159 }
2160
2161
2162 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
2163 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
2164 }
2165
2166
2167 func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
2168 return op | (d&31)<<21 | (simm&31)<<16
2169 }
2170
2171
2172 func AOP_XX1(op uint32, r uint32, a uint32, b uint32) uint32 {
2173 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
2174 }
2175
2176
2177 func AOP_XX2(op uint32, xt uint32, a uint32, xb uint32) uint32 {
2178 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
2179 }
2180
2181
2182 func AOP_XX3(op uint32, xt uint32, xa uint32, xb uint32) uint32 {
2183 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2184 }
2185
2186
2187 func AOP_XX3I(op uint32, xt uint32, xa uint32, xb uint32, c uint32) uint32 {
2188 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2189 }
2190
2191
2192 func AOP_XX4(op uint32, xt uint32, xa uint32, xb uint32, xc uint32) uint32 {
2193 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2194 }
2195
2196
2197 func AOP_DQ(op uint32, xt uint32, a uint32, b uint32) uint32 {
2198
2199
2200
2201
2202
2203
2204 dq := b >> 4
2205 return op | (xt&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (xt&32)>>2
2206 }
2207
2208
2209 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2210 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<9
2211 }
2212
2213
2214 func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2215 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
2216 }
2217
2218 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
2219 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
2220 }
2221
2222 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
2223 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
2224 }
2225
2226 func OP_BR(op uint32, li uint32, aa uint32) uint32 {
2227 return op | li&0x03FFFFFC | aa<<1
2228 }
2229
2230 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
2231 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
2232 }
2233
2234 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
2235 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
2236 }
2237
2238 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
2239 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
2240 }
2241
2242 func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32 {
2243 return op | (a&31)<<21 | (s&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1
2244 }
2245
2246 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
2247 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
2248 }
2249
2250
2251 func AOP_MD(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
2252 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
2253 }
2254
2255
2256 func AOP_MDS(op, to, from, rsh, m uint32) uint32 {
2257 return AOP_MD(op, to, from, rsh&31, m)
2258 }
2259
2260 func AOP_PFX_00_8LS(r, ie uint32) uint32 {
2261 return 1<<26 | 0<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
2262 }
2263 func AOP_PFX_10_MLS(r, ie uint32) uint32 {
2264 return 1<<26 | 2<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
2265 }
2266
2267 const (
2268
2269 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
2270 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
2271 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
2272 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0
2273 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0
2274 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0
2275 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0
2276 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0
2277 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0
2278 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0
2279 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
2280 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
2281 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
2282 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
2283 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
2284 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
2285 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
2286 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
2287 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
2288 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
2289 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
2290 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
2291 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0
2292 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0
2293 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0
2294 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0
2295 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0
2296 OP_XORI = 26<<26 | 0<<1 | 0<<10 | 0
2297 OP_XORIS = 27<<26 | 0<<1 | 0<<10 | 0
2298 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
2299 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0
2300 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0
2301 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0
2302 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
2303 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
2304 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0
2305 OP_EXTSWSLI = 31<<26 | 445<<2
2306 OP_SETB = 31<<26 | 128<<1
2307 )
2308
2309 func pfxadd(rt, ra int16, r uint32, imm32 int64) (uint32, uint32) {
2310 return AOP_PFX_10_MLS(r, uint32(imm32>>16)), AOP_IRR(14<<26, uint32(rt), uint32(ra), uint32(imm32))
2311 }
2312
2313 func pfxload(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
2314 switch a {
2315 case AMOVH:
2316 return AOP_PFX_10_MLS(r, 0), AOP_IRR(42<<26, uint32(reg), uint32(base), 0)
2317 case AMOVW:
2318 return AOP_PFX_00_8LS(r, 0), AOP_IRR(41<<26, uint32(reg), uint32(base), 0)
2319 case AMOVD:
2320 return AOP_PFX_00_8LS(r, 0), AOP_IRR(57<<26, uint32(reg), uint32(base), 0)
2321 case AMOVBZ, AMOVB:
2322 return AOP_PFX_10_MLS(r, 0), AOP_IRR(34<<26, uint32(reg), uint32(base), 0)
2323 case AMOVHZ:
2324 return AOP_PFX_10_MLS(r, 0), AOP_IRR(40<<26, uint32(reg), uint32(base), 0)
2325 case AMOVWZ:
2326 return AOP_PFX_10_MLS(r, 0), AOP_IRR(32<<26, uint32(reg), uint32(base), 0)
2327 case AFMOVS:
2328 return AOP_PFX_10_MLS(r, 0), AOP_IRR(48<<26, uint32(reg), uint32(base), 0)
2329 case AFMOVD:
2330 return AOP_PFX_10_MLS(r, 0), AOP_IRR(50<<26, uint32(reg), uint32(base), 0)
2331 }
2332 log.Fatalf("Error no pfxload for %v\n", a)
2333 return 0, 0
2334 }
2335
2336 func pfxstore(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
2337 switch a {
2338 case AMOVD:
2339 return AOP_PFX_00_8LS(r, 0), AOP_IRR(61<<26, uint32(reg), uint32(base), 0)
2340 case AMOVBZ, AMOVB:
2341 return AOP_PFX_10_MLS(r, 0), AOP_IRR(38<<26, uint32(reg), uint32(base), 0)
2342 case AMOVHZ, AMOVH:
2343 return AOP_PFX_10_MLS(r, 0), AOP_IRR(44<<26, uint32(reg), uint32(base), 0)
2344 case AMOVWZ, AMOVW:
2345 return AOP_PFX_10_MLS(r, 0), AOP_IRR(36<<26, uint32(reg), uint32(base), 0)
2346 case AFMOVS:
2347 return AOP_PFX_10_MLS(r, 0), AOP_IRR(52<<26, uint32(reg), uint32(base), 0)
2348 case AFMOVD:
2349 return AOP_PFX_10_MLS(r, 0), AOP_IRR(54<<26, uint32(reg), uint32(base), 0)
2350 }
2351 log.Fatalf("Error no pfxstore for %v\n", a)
2352 return 0, 0
2353 }
2354
2355 func oclass(a *obj.Addr) int {
2356 return int(a.Class) - 1
2357 }
2358
2359 const (
2360 D_FORM = iota
2361 DS_FORM
2362 )
2363
2364
2365
2366
2367
2368
2369
2370
2371 func (c *ctxt9) opform(insn uint32) int {
2372 switch insn {
2373 default:
2374 c.ctxt.Diag("bad insn in loadform: %x", insn)
2375 case OPVCC(58, 0, 0, 0),
2376 OPVCC(58, 0, 0, 1),
2377 OPVCC(58, 0, 0, 0) | 1<<1,
2378 OPVCC(62, 0, 0, 0),
2379 OPVCC(62, 0, 0, 1):
2380 return DS_FORM
2381 case OP_ADDI,
2382 OPVCC(32, 0, 0, 0),
2383 OPVCC(33, 0, 0, 0),
2384 OPVCC(34, 0, 0, 0),
2385 OPVCC(35, 0, 0, 0),
2386 OPVCC(40, 0, 0, 0),
2387 OPVCC(41, 0, 0, 0),
2388 OPVCC(42, 0, 0, 0),
2389 OPVCC(43, 0, 0, 0),
2390 OPVCC(46, 0, 0, 0),
2391 OPVCC(48, 0, 0, 0),
2392 OPVCC(49, 0, 0, 0),
2393 OPVCC(50, 0, 0, 0),
2394 OPVCC(51, 0, 0, 0),
2395 OPVCC(36, 0, 0, 0),
2396 OPVCC(37, 0, 0, 0),
2397 OPVCC(38, 0, 0, 0),
2398 OPVCC(39, 0, 0, 0),
2399 OPVCC(44, 0, 0, 0),
2400 OPVCC(45, 0, 0, 0),
2401 OPVCC(47, 0, 0, 0),
2402 OPVCC(52, 0, 0, 0),
2403 OPVCC(53, 0, 0, 0),
2404 OPVCC(54, 0, 0, 0),
2405 OPVCC(55, 0, 0, 0):
2406 return D_FORM
2407 }
2408 return 0
2409 }
2410
2411
2412
2413
2414 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32, reuse bool) (o1, o2 uint32, rel obj.Reloc) {
2415 if c.ctxt.Headtype == objabi.Haix {
2416
2417 c.ctxt.Diag("symbolAccess called for %s", s.Name)
2418 }
2419 var base uint32
2420 form := c.opform(op)
2421 if c.ctxt.Flag_shared {
2422 base = REG_R2
2423 } else {
2424 base = REG_R0
2425 }
2426
2427
2428 if !reuse {
2429 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
2430 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
2431 } else {
2432 o1 = AOP_IRR(OP_ADDIS, uint32(reg), base, 0)
2433 o2 = AOP_IRR(op, uint32(reg), uint32(reg), 0)
2434 }
2435 var typ objabi.RelocType
2436 if c.ctxt.Flag_shared {
2437 switch form {
2438 case D_FORM:
2439 typ = objabi.R_ADDRPOWER_TOCREL
2440 case DS_FORM:
2441 typ = objabi.R_ADDRPOWER_TOCREL_DS
2442 }
2443 } else {
2444 switch form {
2445 case D_FORM:
2446 typ = objabi.R_ADDRPOWER
2447 case DS_FORM:
2448 typ = objabi.R_ADDRPOWER_DS
2449 }
2450 }
2451 rel = obj.Reloc{
2452 Type: typ,
2453 Off: int32(c.pc),
2454 Siz: 8,
2455 Sym: s,
2456 Add: d,
2457 }
2458 return
2459 }
2460
2461
2462
2463
2464
2465
2466 func decodeMask32(mask uint32) (mb, me uint32, valid bool) {
2467 mb = uint32(bits.LeadingZeros32(mask))
2468 me = uint32(32 - bits.TrailingZeros32(mask))
2469 mbn := uint32(bits.LeadingZeros32(^mask))
2470 men := uint32(32 - bits.TrailingZeros32(^mask))
2471
2472 if mb == 0 && me == 32 {
2473
2474 mb, me = men, mbn
2475 }
2476
2477
2478
2479 v := mask
2480 vp := (v & -v) + v
2481
2482 vn := ^v
2483 vpn := (vn & -vn) + vn
2484 return mb, (me - 1) & 31, (v&vp == 0 || vn&vpn == 0) && v != 0
2485 }
2486
2487
2488
2489
2490
2491
2492
2493
2494 func decodeMask64(mask int64) (mb, me uint32, valid bool) {
2495 m := uint64(mask)
2496 mb = uint32(bits.LeadingZeros64(m))
2497 me = uint32(64 - bits.TrailingZeros64(m))
2498 valid = ((m&-m)+m)&m == 0 && m != 0
2499 return mb, (me - 1) & 63, valid
2500 }
2501
2502
2503 func loadl16(r int, d int64) uint32 {
2504 v := uint16(d)
2505 if v == 0 {
2506
2507
2508 return NOP
2509 }
2510 return LOP_IRR(OP_ORI, uint32(r), uint32(r), uint32(v))
2511 }
2512
2513
2514 func loadu32(r int, d int64) uint32 {
2515 v := int32(d >> 16)
2516 if isuint32(uint64(d)) {
2517 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
2518 }
2519 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
2520 }
2521
2522 func high16adjusted(d int32) uint16 {
2523 if d&0x8000 != 0 {
2524 return uint16((d >> 16) + 1)
2525 }
2526 return uint16(d >> 16)
2527 }
2528
2529 func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
2530 o1 := uint32(0)
2531 o2 := uint32(0)
2532 o3 := uint32(0)
2533 o4 := uint32(0)
2534 o5 := uint32(0)
2535
2536
2537 switch o.type_ {
2538 default:
2539 c.ctxt.Diag("unknown type %d", o.type_)
2540 prasm(p)
2541
2542 case 0:
2543 break
2544
2545 case 2:
2546 r := int(p.Reg)
2547
2548 if r == 0 {
2549 r = int(p.To.Reg)
2550 }
2551 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2552
2553 case 3:
2554 d := c.vregoff(&p.From)
2555
2556 v := int32(d)
2557 r := int(p.From.Reg)
2558
2559 if r0iszero != 0 && p.To.Reg == 0 && (r != 0 || v != 0) {
2560 c.ctxt.Diag("literal operation on R0\n%v", p)
2561 }
2562 if int64(int16(d)) == d {
2563
2564 o1 = AOP_IRR(uint32(OP_ADDI), uint32(p.To.Reg), uint32(r), uint32(v))
2565 } else {
2566
2567 if int64(uint16(d)) != d || (r != 0 && r != REGZERO) {
2568 c.ctxt.Diag("Rule expects a uint16 constant load. got:\n%v", p)
2569 }
2570 o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
2571 }
2572
2573 case 4:
2574 v := c.regoff(&p.From)
2575
2576 r := int(p.Reg)
2577 if r == 0 {
2578 r = int(p.To.Reg)
2579 }
2580 if r0iszero != 0 && p.To.Reg == 0 {
2581 c.ctxt.Diag("literal operation on R0\n%v", p)
2582 }
2583 if int32(int16(v)) != v {
2584 log.Fatalf("mishandled instruction %v", p)
2585 }
2586 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2587
2588 case 5:
2589 o1 = c.oprrr(p.As)
2590
2591 case 6:
2592 r := int(p.Reg)
2593
2594 if r == 0 {
2595 r = int(p.To.Reg)
2596 }
2597
2598 switch p.As {
2599 case AROTL:
2600 o1 = AOP_MD(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
2601 case AROTLW:
2602 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
2603 default:
2604 if p.As == AOR && p.From.Type == obj.TYPE_CONST && p.From.Offset == 0 {
2605
2606
2607 o1 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(r), 0)
2608 } else {
2609 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2610 }
2611 }
2612
2613 case 7:
2614 r := int(p.To.Reg)
2615 v := c.regoff(&p.To)
2616 if int32(int16(v)) != v {
2617 log.Fatalf("mishandled instruction %v", p)
2618 }
2619
2620 inst := c.opstore(p.As)
2621 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2622 log.Fatalf("invalid offset for DS form load/store %v", p)
2623 }
2624 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
2625
2626 case 8:
2627 r := int(p.From.Reg)
2628 v := c.regoff(&p.From)
2629 if int32(int16(v)) != v {
2630 log.Fatalf("mishandled instruction %v", p)
2631 }
2632
2633 inst := c.opload(p.As)
2634 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2635 log.Fatalf("invalid offset for DS form load/store %v", p)
2636 }
2637 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
2638
2639
2640 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
2641
2642 case 9:
2643 sh := uint32(p.RestArgs[0].Addr.Offset) & 0x3F
2644 mb := uint32(p.RestArgs[1].Addr.Offset) & 0x3F
2645 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), (sh & 0x1F))
2646 o1 |= (sh & 0x20) >> 4
2647 o1 |= (mb & 0x1F) << 6
2648 o1 |= (mb & 0x20)
2649
2650 case 10:
2651 r := int(p.Reg)
2652
2653 if r == 0 {
2654 r = int(p.To.Reg)
2655 }
2656 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
2657
2658 case 11:
2659 v := int32(0)
2660
2661 if p.To.Target() != nil {
2662 v = int32(p.To.Target().Pc - p.Pc)
2663 if v&03 != 0 {
2664 c.ctxt.Diag("odd branch target address\n%v", p)
2665 v &^= 03
2666 }
2667
2668 if v < -(1<<25) || v >= 1<<24 {
2669 c.ctxt.Diag("branch too far\n%v", p)
2670 }
2671 }
2672
2673 o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
2674 if p.To.Sym != nil {
2675 v += int32(p.To.Offset)
2676 if v&03 != 0 {
2677 c.ctxt.Diag("odd branch target address\n%v", p)
2678 v &^= 03
2679 }
2680 c.cursym.AddRel(c.ctxt, obj.Reloc{
2681 Type: objabi.R_CALLPOWER,
2682 Off: int32(c.pc),
2683 Siz: 4,
2684 Sym: p.To.Sym,
2685 Add: int64(v),
2686 })
2687 }
2688 o2 = NOP
2689
2690 case 13:
2691
2692
2693
2694 if p.From.Type == obj.TYPE_CONST {
2695 o1 = LOP_IRR(OP_ADDI, REGZERO, uint32(p.To.Reg), 0)
2696 break
2697 }
2698 if p.To.Type == obj.TYPE_CONST {
2699 c.ctxt.Diag("cannot move into constant 0\n%v", p)
2700 }
2701
2702 switch p.As {
2703 case AMOVB:
2704 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2705 case AMOVBZ:
2706 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
2707 case AMOVH:
2708 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2709 case AMOVHZ:
2710 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
2711 case AMOVW:
2712 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2713 case AMOVWZ:
2714 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5
2715 case AMOVD:
2716 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
2717 default:
2718 c.ctxt.Diag("internal: bad register move/truncation\n%v", p)
2719 }
2720
2721 case 14:
2722 r := uint32(p.Reg)
2723
2724 if r == 0 {
2725 r = uint32(p.To.Reg)
2726 }
2727 d := c.vregoff(p.GetFrom3())
2728 switch p.As {
2729
2730
2731
2732
2733 case ARLDCL, ARLDCLCC:
2734 mb, me, valid := decodeMask64(d)
2735 if me != 63 || !valid {
2736 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
2737 }
2738 o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), mb)
2739
2740 case ARLDCR, ARLDCRCC:
2741 mb, me, valid := decodeMask64(d)
2742 if mb != 0 || !valid {
2743 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p)
2744 }
2745 o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), me)
2746
2747
2748 case ARLDICR, ARLDICRCC:
2749 me := uint32(d)
2750 sh := c.regoff(&p.From)
2751 if me < 0 || me > 63 || sh > 63 {
2752 c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh, p)
2753 }
2754 o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), me)
2755
2756 case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
2757 mb := uint32(d)
2758 sh := c.regoff(&p.From)
2759 if mb < 0 || mb > 63 || sh > 63 {
2760 c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh, p)
2761 }
2762 o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), mb)
2763
2764 case ACLRLSLDI:
2765
2766
2767
2768
2769 n := int32(d)
2770 b := c.regoff(&p.From)
2771 if n > b || b > 63 {
2772 c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b, p)
2773 }
2774 o1 = AOP_MD(OP_RLDIC, uint32(p.To.Reg), r, uint32(n), uint32(b)-uint32(n))
2775
2776 default:
2777 c.ctxt.Diag("unexpected op in rldc case\n%v", p)
2778 }
2779
2780 case 16:
2781 a := 0
2782
2783 r := int(p.Reg)
2784
2785 if p.From.Type == obj.TYPE_CONST {
2786 a = int(c.regoff(&p.From))
2787 } else if p.From.Type == obj.TYPE_REG {
2788 if r != 0 {
2789 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
2790 }
2791
2792 switch p.From.Reg {
2793 case REG_CR0:
2794 r = BI_CR0
2795 case REG_CR1:
2796 r = BI_CR1
2797 case REG_CR2:
2798 r = BI_CR2
2799 case REG_CR3:
2800 r = BI_CR3
2801 case REG_CR4:
2802 r = BI_CR4
2803 case REG_CR5:
2804 r = BI_CR5
2805 case REG_CR6:
2806 r = BI_CR6
2807 case REG_CR7:
2808 r = BI_CR7
2809 default:
2810 c.ctxt.Diag("unrecognized register: expecting CR\n")
2811 }
2812 }
2813 v := int32(0)
2814 if p.To.Target() != nil {
2815 v = int32(p.To.Target().Pc - p.Pc)
2816 }
2817 if v&03 != 0 {
2818 c.ctxt.Diag("odd branch target address\n%v", p)
2819 v &^= 03
2820 }
2821
2822 if v < -(1<<16) || v >= 1<<15 {
2823 c.ctxt.Diag("branch too far\n%v", p)
2824 }
2825 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
2826
2827 case 17:
2828 var bo int32
2829 bi := int(p.Reg)
2830
2831 if p.From.Reg == REG_CR {
2832 c.ctxt.Diag("unrecognized register: expected CR0-CR7\n")
2833 }
2834 bi = int(p.From.Reg&0x7) * 4
2835
2836 bo = BO_BCR
2837
2838 switch p.As {
2839 case ABLT:
2840 bi += BI_LT
2841 case ABGT:
2842 bi += BI_GT
2843 case ABEQ:
2844 bi += BI_EQ
2845 case ABNE:
2846 bo = BO_NOTBCR
2847 bi += BI_EQ
2848 case ABLE:
2849 bo = BO_NOTBCR
2850 bi += BI_GT
2851 case ABGE:
2852 bo = BO_NOTBCR
2853 bi += BI_LT
2854 case ABVS:
2855 bi += BI_FU
2856 case ABVC:
2857 bo = BO_NOTBCR
2858 bi += BI_FU
2859 default:
2860 c.ctxt.Diag("unexpected instruction: expecting BGT, BEQ, BNE, BLE, BGE, BVS, BVC \n%v", p)
2861
2862 }
2863 if oclass(&p.To) == C_LR {
2864 o1 = OPVCC(19, 16, 0, 0)
2865 } else {
2866 c.ctxt.Diag("bad optab entry (17): %d\n%v", p.To.Class, p)
2867 }
2868
2869 o1 = OP_BCR(o1, uint32(bo), uint32(bi))
2870
2871 case 18:
2872 var v int32
2873 var bh uint32 = 0
2874 if p.As == ABC || p.As == ABCL {
2875 v = c.regoff(&p.From) & 31
2876 } else {
2877 v = 20
2878 }
2879 r := int(p.Reg)
2880 if r == 0 {
2881 r = 0
2882 }
2883 switch oclass(&p.To) {
2884 case C_CTR:
2885 o1 = OPVCC(19, 528, 0, 0)
2886
2887 case C_LR:
2888 o1 = OPVCC(19, 16, 0, 0)
2889
2890 default:
2891 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
2892 v = 0
2893 }
2894
2895
2896 if p.From3Type() != obj.TYPE_NONE {
2897 bh = uint32(p.GetFrom3().Offset)
2898 if bh == 2 || bh > 3 {
2899 log.Fatalf("BH must be 0,1,3 for %v", p)
2900 }
2901 o1 |= bh << 11
2902 }
2903
2904 if p.As == ABL || p.As == ABCL {
2905 o1 |= 1
2906 }
2907 o1 = OP_BCR(o1, uint32(v), uint32(r))
2908
2909 case 19:
2910 d := c.vregoff(&p.From)
2911 if o.ispfx {
2912 o1, o2 = pfxadd(p.To.Reg, REG_R0, PFX_R_ABS, d)
2913 } else {
2914 o1 = loadu32(int(p.To.Reg), d)
2915 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
2916 }
2917
2918 case 20:
2919 v := c.regoff(&p.From)
2920
2921 r := int(p.Reg)
2922 if r == 0 {
2923 r = int(p.To.Reg)
2924 }
2925 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2926
2927 case 21:
2928 var opu, opl uint32
2929 r := uint32(p.Reg)
2930 if r == 0 {
2931 r = uint32(p.To.Reg)
2932 }
2933 switch p.As {
2934 case AOR:
2935 opu, opl = OP_ORIS, OP_ORI
2936 case AXOR:
2937 opu, opl = OP_XORIS, OP_XORI
2938 default:
2939 c.ctxt.Diag("unhandled opcode.\n%v", p)
2940 }
2941 o1 = LOP_IRR(opu, uint32(p.To.Reg), r, uint32(p.From.Offset>>16))
2942 o2 = LOP_IRR(opl, uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.From.Offset)&0xFFFF)
2943
2944 case 22:
2945 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2946 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2947 }
2948 d := c.vregoff(&p.From)
2949 r := int(p.Reg)
2950 if r == 0 {
2951 r = int(p.To.Reg)
2952 }
2953 if p.From.Sym != nil {
2954 c.ctxt.Diag("%v is not supported", p)
2955 }
2956 if o.ispfx {
2957 o1, o2 = pfxadd(p.To.Reg, int16(r), PFX_R_ABS, d)
2958 } else if o.size == 8 {
2959 o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))
2960 o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2961 } else if o.size == 12 {
2962
2963 o1 = loadu32(REGTMP, d)
2964 o2 = loadl16(REGTMP, d)
2965 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2966 } else {
2967
2968 o1 = LOP_IRR(OP_ADDIS, REGZERO, REGTMP, uint32(d>>32))
2969 o2 = loadl16(REGTMP, d>>16)
2970 o3 = AOP_MD(OP_RLDICR, REGTMP, REGTMP, 16, 63-16)
2971 o4 = loadl16(REGTMP, int64(uint16(d)))
2972 o5 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2973 }
2974
2975 case 23:
2976 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2977 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2978 }
2979 d := c.vregoff(&p.From)
2980 r := int(p.Reg)
2981 if r == 0 {
2982 r = int(p.To.Reg)
2983 }
2984
2985
2986
2987 if o.size == 8 {
2988 o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
2989 o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2990 } else {
2991 o1 = loadu32(REGTMP, d)
2992 o2 = loadl16(REGTMP, d)
2993 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2994 }
2995 if p.From.Sym != nil {
2996 c.ctxt.Diag("%v is not supported", p)
2997 }
2998
2999 case 24:
3000 o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
3001
3002 if o.size == 8 {
3003 o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
3004 }
3005
3006 case 25:
3007
3008 v := c.regoff(&p.From)
3009
3010 if v < 0 {
3011 v = 0
3012 } else if v > 63 {
3013 v = 63
3014 }
3015 r := int(p.Reg)
3016 if r == 0 {
3017 r = int(p.To.Reg)
3018 }
3019 var a int
3020 op := uint32(0)
3021 switch p.As {
3022 case ASLD, ASLDCC:
3023 a = int(63 - v)
3024 op = OP_RLDICR
3025
3026 case ASRD, ASRDCC:
3027 a = int(v)
3028 v = 64 - v
3029 op = OP_RLDICL
3030 case AROTL:
3031 a = int(0)
3032 op = OP_RLDICL
3033 case AEXTSWSLI, AEXTSWSLICC:
3034 a = int(v)
3035 default:
3036 c.ctxt.Diag("unexpected op in sldi case\n%v", p)
3037 a = 0
3038 o1 = 0
3039 }
3040
3041 if p.As == AEXTSWSLI || p.As == AEXTSWSLICC {
3042 o1 = AOP_EXTSWSLI(OP_EXTSWSLI, uint32(r), uint32(p.To.Reg), uint32(v))
3043
3044 } else {
3045 o1 = AOP_MD(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
3046 }
3047 if p.As == ASLDCC || p.As == ASRDCC || p.As == AEXTSWSLICC {
3048 o1 |= 1
3049 }
3050
3051 case 26:
3052 v := c.vregoff(&p.From)
3053 r := int(p.From.Reg)
3054 var rel *obj.Reloc
3055
3056 switch p.From.Name {
3057 case obj.NAME_EXTERN, obj.NAME_STATIC:
3058
3059 var rel1 obj.Reloc
3060 o1, o2, rel1 = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI, true)
3061 rel = &rel1
3062 default:
3063
3064 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(int32(v))))
3065 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3066 }
3067
3068 if o.ispfx {
3069 if rel == nil {
3070 o1, o2 = pfxadd(p.To.Reg, int16(r), PFX_R_ABS, v)
3071 } else {
3072 o1, o2 = pfxadd(p.To.Reg, REG_R0, PFX_R_PCREL, 0)
3073 rel.Type = objabi.R_ADDRPOWER_PCREL34
3074 }
3075 }
3076 if rel != nil {
3077 c.cursym.AddRel(c.ctxt, *rel)
3078 }
3079
3080 case 27:
3081 v := c.regoff(p.GetFrom3())
3082
3083 r := int(p.From.Reg)
3084 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3085
3086 case 28:
3087 if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
3088 c.ctxt.Diag("can't synthesize large constant\n%v", p)
3089 }
3090 v := c.vregoff(p.GetFrom3())
3091 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
3092 o2 = loadl16(REGTMP, v)
3093 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
3094 if p.From.Sym != nil {
3095 c.ctxt.Diag("%v is not supported", p)
3096 }
3097
3098 case 29:
3099 sh := uint32(c.regoff(&p.From))
3100 d := c.vregoff(p.GetFrom3())
3101 mb, me, valid := decodeMask64(d)
3102 var a uint32
3103 switch p.As {
3104 case ARLDC, ARLDCCC:
3105 a = mb
3106 if me != (63-sh) || !valid {
3107 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3108 }
3109
3110 case ARLDCL, ARLDCLCC:
3111 a = mb
3112 if mb != 63 || !valid {
3113 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3114 }
3115
3116 case ARLDCR, ARLDCRCC:
3117 a = me
3118 if mb != 0 || !valid {
3119 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3120 }
3121
3122 default:
3123 c.ctxt.Diag("unexpected op in rldic case\n%v", p)
3124 }
3125 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, a)
3126
3127 case 30:
3128 sh := uint32(c.regoff(&p.From))
3129 d := c.vregoff(p.GetFrom3())
3130
3131
3132
3133 switch p.As {
3134 case ARLDMI, ARLDMICC:
3135 mb, me, valid := decodeMask64(d)
3136 if me != (63-sh) || !valid {
3137 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), me, sh, p)
3138 }
3139 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, mb)
3140
3141
3142 case ARLDIMI, ARLDIMICC:
3143 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, uint32(d))
3144 }
3145
3146 case 31:
3147 d := c.vregoff(&p.From)
3148
3149 if c.ctxt.Arch.ByteOrder == binary.BigEndian {
3150 o1 = uint32(d >> 32)
3151 o2 = uint32(d)
3152 } else {
3153 o1 = uint32(d)
3154 o2 = uint32(d >> 32)
3155 }
3156
3157 if p.From.Sym != nil {
3158 c.cursym.AddRel(c.ctxt, obj.Reloc{
3159 Type: objabi.R_ADDR,
3160 Off: int32(c.pc),
3161 Siz: 8,
3162 Sym: p.From.Sym,
3163 Add: p.From.Offset,
3164 })
3165 o2 = 0
3166 o1 = o2
3167 }
3168
3169 case 32:
3170 r := int(p.Reg)
3171
3172 if r == 0 {
3173 r = int(p.To.Reg)
3174 }
3175 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
3176
3177 case 33:
3178 r := int(p.From.Reg)
3179
3180 if oclass(&p.From) == C_NONE {
3181 r = int(p.To.Reg)
3182 }
3183 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
3184
3185 case 34:
3186 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
3187
3188 case 35:
3189 v := c.regoff(&p.To)
3190 r := int(p.To.Reg)
3191
3192 if o.ispfx {
3193 o1, o2 = pfxstore(p.As, p.From.Reg, int16(r), PFX_R_ABS)
3194 o1 |= uint32((v >> 16) & 0x3FFFF)
3195 o2 |= uint32(v & 0xFFFF)
3196 } else {
3197 inst := c.opstore(p.As)
3198 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3199 log.Fatalf("invalid offset for DS form load/store %v", p)
3200 }
3201 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
3202 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
3203 }
3204
3205 case 36:
3206 v := c.regoff(&p.From)
3207 r := int(p.From.Reg)
3208
3209 if o.ispfx {
3210 o1, o2 = pfxload(p.As, p.To.Reg, int16(r), PFX_R_ABS)
3211 o1 |= uint32((v >> 16) & 0x3FFFF)
3212 o2 |= uint32(v & 0xFFFF)
3213 } else {
3214 if o.a6 == C_REG {
3215
3216
3217 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
3218 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3219 } else {
3220 o1 = AOP_IRR(OP_ADDIS, uint32(REGTMP), uint32(r), uint32(high16adjusted(v)))
3221 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(REGTMP), uint32(v))
3222 }
3223 }
3224
3225
3226 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3227
3228 case 40:
3229 o1 = uint32(c.regoff(&p.From))
3230
3231 case 41:
3232 if p.To.Type == obj.TYPE_MEM && p.To.Index == 0 && p.To.Offset != 0 {
3233 c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
3234 }
3235
3236 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3237
3238 case 42:
3239 if p.From.Type == obj.TYPE_MEM && p.From.Index == 0 && p.From.Offset != 0 {
3240 c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
3241 }
3242 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3243
3244 case 43:
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255 if p.To.Type == obj.TYPE_NONE {
3256 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
3257 } else {
3258 th := c.regoff(&p.To)
3259 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
3260 }
3261
3262 case 44:
3263 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3264
3265 case 45:
3266 switch p.As {
3267
3268
3269
3270
3271 case ALBAR, ALHAR, ALWAR, ALDAR:
3272 if p.From3Type() != obj.TYPE_NONE {
3273 eh := int(c.regoff(p.GetFrom3()))
3274 if eh > 1 {
3275 c.ctxt.Diag("illegal EH field\n%v", p)
3276 }
3277 o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
3278 } else {
3279 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3280 }
3281 default:
3282 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3283 }
3284 case 46:
3285 o1 = c.oprrr(p.As)
3286
3287 case 47:
3288 r := int(p.From.Reg)
3289
3290 if r == 0 {
3291 r = int(p.To.Reg)
3292 }
3293 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3294
3295 case 48:
3296 r := int(p.From.Reg)
3297
3298 if r == 0 {
3299 r = int(p.To.Reg)
3300 }
3301 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3302
3303 case 49:
3304 if p.From.Type != obj.TYPE_REG {
3305 v := c.regoff(&p.From) & 1
3306 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
3307 } else {
3308 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
3309 }
3310
3311 case 50:
3312 r := int(p.Reg)
3313
3314 if r == 0 {
3315 r = int(p.To.Reg)
3316 }
3317 v := c.oprrr(p.As)
3318 t := v & (1<<10 | 1)
3319 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3320 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
3321 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3322 if p.As == AREMU {
3323 o4 = o3
3324
3325
3326 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
3327 }
3328
3329 case 51:
3330 r := int(p.Reg)
3331
3332 if r == 0 {
3333 r = int(p.To.Reg)
3334 }
3335 v := c.oprrr(p.As)
3336 t := v & (1<<10 | 1)
3337 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3338 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
3339 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3340
3341
3342
3343
3344 case 52:
3345 v := c.regoff(&p.From) & 31
3346
3347 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
3348
3349 case 53:
3350 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
3351
3352 case 55:
3353 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
3354
3355 case 56:
3356 v := c.regoff(&p.From)
3357
3358 r := int(p.Reg)
3359 if r == 0 {
3360 r = int(p.To.Reg)
3361 }
3362 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
3363 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
3364 o1 |= 1 << 1
3365 }
3366
3367 case 57:
3368 v := c.regoff(&p.From)
3369
3370 r := int(p.Reg)
3371 if r == 0 {
3372 r = int(p.To.Reg)
3373 }
3374
3375
3382 if v < 0 {
3383 v = 0
3384 } else if v > 32 {
3385 v = 32
3386 }
3387 var mask [2]uint8
3388 switch p.As {
3389 case AROTLW:
3390 mask[0], mask[1] = 0, 31
3391 case ASRW, ASRWCC:
3392 mask[0], mask[1] = uint8(v), 31
3393 v = 32 - v
3394 default:
3395 mask[0], mask[1] = 0, uint8(31-v)
3396 }
3397 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
3398 if p.As == ASLWCC || p.As == ASRWCC {
3399 o1 |= 1
3400 }
3401
3402 case 58:
3403 v := c.regoff(&p.From)
3404
3405 r := int(p.Reg)
3406 if r == 0 {
3407 r = int(p.To.Reg)
3408 }
3409 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3410
3411 case 60:
3412 r := int(c.regoff(&p.From) & 31)
3413
3414 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
3415
3416 case 61:
3417 r := int(c.regoff(&p.From) & 31)
3418
3419 v := c.regoff(&p.To)
3420 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
3421
3422 case 62:
3423 v := c.regoff(&p.From)
3424 n := c.regoff(p.GetFrom3())
3425
3426
3427
3428 if n > v || v >= 32 {
3429 c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, n, p)
3430 }
3431
3432 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(n), uint32(v-n), uint32(31-n))
3433
3434 case 63:
3435 var mb, me uint32
3436 if len(p.RestArgs) == 1 {
3437 var valid bool
3438
3439 mb, me, valid = decodeMask32(uint32(p.RestArgs[0].Addr.Offset))
3440 if !valid {
3441 c.ctxt.Diag("cannot generate mask #%x\n%v", uint64(p.RestArgs[0].Addr.Offset), p)
3442 }
3443 } else {
3444 mb, me = uint32(p.RestArgs[0].Addr.Offset), uint32(p.RestArgs[1].Addr.Offset)
3445 }
3446 if p.From.Type == obj.TYPE_CONST {
3447 o1 = OP_RLW(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Offset), mb, me)
3448 } else {
3449 o1 = OP_RLW(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), mb, me)
3450 }
3451
3452 case 64:
3453 var v int32
3454 if p.From3Type() != obj.TYPE_NONE {
3455 v = c.regoff(p.GetFrom3()) & 255
3456 } else {
3457 v = 255
3458 }
3459 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
3460
3461 case 65:
3462 if p.To.Reg == 0 {
3463 c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
3464 }
3465 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
3466
3467 case 66:
3468 var r int
3469 var v int32
3470 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
3471 r = int(p.From.Reg)
3472 v = int32(p.To.Reg)
3473 o1 = OPVCC(31, 467, 0, 0)
3474 } else {
3475 r = int(p.To.Reg)
3476 v = int32(p.From.Reg)
3477 o1 = OPVCC(31, 339, 0, 0)
3478 }
3479
3480 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3481
3482 case 67:
3483 if p.From.Reg == REG_CR || p.To.Reg == REG_CR {
3484 c.ctxt.Diag("CR argument must be a conditional register field (CR0-CR7)\n%v", p)
3485 }
3486 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
3487
3488 case 68:
3489 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0)
3490 if p.From.Reg != REG_CR {
3491 v := uint32(1) << uint(7-(p.From.Reg&7))
3492 o1 |= 1<<20 | v<<12
3493 }
3494
3495 case 69:
3496 var v uint32
3497 if p.To.Reg == REG_CR {
3498 v = 0xff
3499 } else if p.To.Offset != 0 {
3500 v = uint32(p.To.Offset)
3501 } else {
3502 v = 1 << uint(7-(p.To.Reg&7))
3503 }
3504
3505 if bits.OnesCount32(v) == 1 {
3506 v |= 1 << 8
3507 }
3508
3509 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | v<<12
3510
3511 case 70:
3512 r := uint32(p.Reg&7) << 2
3513 if p.To.Type == obj.TYPE_CONST {
3514 o1 = AOP_IRR(c.opirr(p.As), r, uint32(p.From.Reg), uint32(uint16(p.To.Offset)))
3515 } else {
3516 o1 = AOP_RRR(c.oprrr(p.As), r, uint32(p.From.Reg), uint32(p.To.Reg))
3517 }
3518
3519 case 72:
3520 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
3521
3522 case 73:
3523 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
3524 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
3525 }
3526 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
3527
3528 case 77:
3529 if p.From.Type == obj.TYPE_CONST {
3530 if p.From.Offset > BIG || p.From.Offset < -BIG {
3531 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
3532 }
3533 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
3534 } else if p.From.Type == obj.TYPE_REG {
3535 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
3536 } else {
3537 c.ctxt.Diag("illegal syscall: %v", p)
3538 o1 = 0x7fe00008
3539 }
3540
3541 o2 = c.oprrr(p.As)
3542 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO)
3543
3544 case 78:
3545 o1 = 0
3547
3548
3549 case 74:
3550 v := c.vregoff(&p.To)
3551
3552 inst := c.opstore(p.As)
3553
3554
3555 var rel obj.Reloc
3556 o1, o2, rel = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst, false)
3557
3558
3559 if o.ispfx {
3560 o1, o2 = pfxstore(p.As, p.From.Reg, REG_R0, PFX_R_PCREL)
3561 rel.Type = objabi.R_ADDRPOWER_PCREL34
3562 } else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3563 log.Fatalf("invalid offset for DS form load/store %v", p)
3564 }
3565 c.cursym.AddRel(c.ctxt, rel)
3566
3567 case 75:
3568 v := p.From.Offset
3569
3570
3571 inst := c.opload(p.As)
3572 var rel obj.Reloc
3573 switch p.From.Name {
3574 case obj.NAME_GOTREF, obj.NAME_TOCREF:
3575 if v != 0 {
3576 c.ctxt.Diag("invalid offset for GOT/TOC access %v", p)
3577 }
3578 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3579 o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3580 rel.Off = int32(c.pc)
3581 rel.Siz = 8
3582 rel.Sym = p.From.Sym
3583 switch p.From.Name {
3584 case obj.NAME_GOTREF:
3585 rel.Type = objabi.R_ADDRPOWER_GOT
3586 case obj.NAME_TOCREF:
3587 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
3588 }
3589 default:
3590 reuseBaseReg := o.a6 == C_REG
3591
3592 o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
3593 }
3594
3595
3596 if o.ispfx {
3597 switch rel.Type {
3598 case objabi.R_ADDRPOWER, objabi.R_ADDRPOWER_DS,
3599 objabi.R_ADDRPOWER_TOCREL, objabi.R_ADDRPOWER_TOCREL_DS:
3600 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3601 rel.Type = objabi.R_ADDRPOWER_PCREL34
3602 case objabi.R_POWER_TLS_IE:
3603 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3604 rel.Type = objabi.R_POWER_TLS_IE_PCREL34
3605 case objabi.R_ADDRPOWER_GOT:
3606 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3607 rel.Type = objabi.R_ADDRPOWER_GOT_PCREL34
3608 default:
3609
3610 log.Fatalf("Unable convert TOC-relative relocation %v to PC-relative", rel.Type)
3611 }
3612 } else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3613 log.Fatalf("invalid offset for DS form load/store %v", p)
3614 }
3615 c.cursym.AddRel(c.ctxt, rel)
3616
3617 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3618
3619 case 79:
3620 if p.From.Offset != 0 {
3621 c.ctxt.Diag("invalid offset against tls var %v", p)
3622 }
3623 var typ objabi.RelocType
3624 if !o.ispfx {
3625 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R13, 0)
3626 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3627 typ = objabi.R_POWER_TLS_LE
3628 } else {
3629 o1, o2 = pfxadd(p.To.Reg, REG_R13, PFX_R_ABS, 0)
3630 typ = objabi.R_POWER_TLS_LE_TPREL34
3631 }
3632 c.cursym.AddRel(c.ctxt, obj.Reloc{
3633 Type: typ,
3634 Off: int32(c.pc),
3635 Siz: 8,
3636 Sym: p.From.Sym,
3637 })
3638
3639 case 80:
3640 if p.From.Offset != 0 {
3641 c.ctxt.Diag("invalid offset against tls var %v", p)
3642 }
3643 typ := objabi.R_POWER_TLS_IE
3644 if !o.ispfx {
3645 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3646 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
3647 } else {
3648 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3649 typ = objabi.R_POWER_TLS_IE_PCREL34
3650 }
3651 c.cursym.AddRel(c.ctxt, obj.Reloc{
3652 Type: typ,
3653 Off: int32(c.pc),
3654 Siz: 8,
3655 Sym: p.From.Sym,
3656 })
3657 o3 = AOP_RRR(OP_ADD, uint32(p.To.Reg), uint32(p.To.Reg), REG_R13)
3658 c.cursym.AddRel(c.ctxt, obj.Reloc{
3659 Type: objabi.R_POWER_TLS,
3660 Off: int32(c.pc) + 8,
3661 Siz: 4,
3662 Sym: p.From.Sym,
3663 })
3664
3665 case 82:
3666 if p.From.Type == obj.TYPE_REG {
3667
3668
3669
3670 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3671 } else if p.From3Type() == obj.TYPE_CONST {
3672
3673
3674 six := int(c.regoff(&p.From))
3675 st := int(c.regoff(p.GetFrom3()))
3676 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
3677 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
3678
3679
3680 uim := int(c.regoff(&p.From))
3681 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
3682 } else {
3683
3684
3685 sim := int(c.regoff(&p.From))
3686 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
3687 }
3688
3689 case 83:
3690 if p.From.Type == obj.TYPE_REG {
3691
3692
3693 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3694 } else if p.From.Type == obj.TYPE_CONST {
3695
3696
3697 shb := int(c.regoff(&p.From))
3698 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
3699 }
3700
3701 case 84:
3702 bc := c.vregoff(&p.From)
3703 if o.a1 == C_CRBIT {
3704
3705 bc = int64(p.From.Reg)
3706 }
3707
3708
3709 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
3710
3711 case 85:
3712
3713
3714 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
3715
3716 case 86:
3717
3718
3719 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3720
3721 case 87:
3722
3723
3724 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3725
3726 case 88:
3727 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3728
3729 case 89:
3730
3731
3732 uim := int(c.regoff(p.GetFrom3()))
3733 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
3734
3735 case 90:
3736 if p.From3Type() == obj.TYPE_NONE {
3737
3738
3739 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3740 } else if p.From3Type() == obj.TYPE_CONST {
3741
3742
3743 dm := int(c.regoff(p.GetFrom3()))
3744 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
3745 }
3746
3747 case 91:
3748
3749
3750 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3751
3752 case 92:
3753 if p.To.Type == obj.TYPE_CONST {
3754
3755 xf := int32(p.From.Reg)
3756 if REG_F0 <= xf && xf <= REG_F31 {
3757
3758 bf := int(c.regoff(&p.To)) << 2
3759 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3760 } else {
3761
3762 l := int(c.regoff(&p.To))
3763 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
3764 }
3765 } else if p.From3Type() == obj.TYPE_CONST {
3766
3767
3768 l := int(c.regoff(p.GetFrom3()))
3769 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
3770 } else if p.To.Type == obj.TYPE_REG {
3771 cr := int32(p.To.Reg)
3772 if REG_CR0 <= cr && cr <= REG_CR7 {
3773
3774
3775 bf := (int(p.To.Reg) & 7) << 2
3776 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3777 } else if p.From.Type == obj.TYPE_CONST {
3778
3779
3780 l := int(c.regoff(&p.From))
3781 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
3782 } else {
3783 switch p.As {
3784 case ACOPY, APASTECC:
3785 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
3786 default:
3787
3788
3789 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3790 }
3791 }
3792 }
3793
3794 case 93:
3795 if p.To.Type == obj.TYPE_CONST {
3796
3797
3798 bf := int(c.regoff(&p.To)) << 2
3799 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
3800 } else if p.Reg == 0 {
3801
3802
3803 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3804 }
3805
3806 case 94:
3807
3808
3809 cy := int(c.regoff(p.GetFrom3()))
3810 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
3811
3812 case 96:
3813
3814
3815 dq := int16(c.regoff(&p.From))
3816 if (dq & 15) != 0 {
3817 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3818 }
3819 o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq))
3820
3821 case 97:
3822
3823
3824 dq := int16(c.regoff(&p.To))
3825 if (dq & 15) != 0 {
3826 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3827 }
3828 o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq))
3829 case 98:
3830
3831 o1 = AOP_XX1(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3832 case 99:
3833
3834 o1 = AOP_XX1(c.opstore(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
3835 case 100:
3836 if p.From.Type == obj.TYPE_CONST {
3837
3838 uim := int(c.regoff(&p.From))
3839
3840
3841 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(uim))
3842 } else {
3843 c.ctxt.Diag("invalid ops for %v", p.As)
3844 }
3845 case 101:
3846 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg))
3847
3848 case 104:
3849 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3850
3851 case 106:
3852 v := int32(p.From.Reg)
3853 o1 = OPVCC(31, 339, 0, 0)
3854 o1 = AOP_RRR(o1, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3855 so := c.regoff(&p.To)
3856 o2 = AOP_IRR(c.opstore(AMOVD), uint32(REGTMP), uint32(p.To.Reg), uint32(so))
3857 if so&0x3 != 0 {
3858 log.Fatalf("invalid offset for DS form load/store %v", p)
3859 }
3860 if p.To.Reg == REGTMP {
3861 log.Fatalf("SPR move to memory will clobber R31 %v", p)
3862 }
3863
3864 case 107:
3865 v := int32(p.From.Reg)
3866 so := c.regoff(&p.From)
3867 o1 = AOP_IRR(c.opload(AMOVD), uint32(REGTMP), uint32(v), uint32(so))
3868 o2 = OPVCC(31, 467, 0, 0)
3869 v = int32(p.To.Reg)
3870 o2 = AOP_RRR(o2, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3871 if so&0x3 != 0 {
3872 log.Fatalf("invalid offset for DS form load/store %v", p)
3873 }
3874
3875 case 108:
3876 r := int(p.To.Reg)
3877 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
3878
3879 case 109:
3880 r := int(p.From.Reg)
3881
3882 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
3883
3884 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3885
3886 case 110:
3887 bfa := uint32(p.From.Reg) << 2
3888 rt := uint32(p.To.Reg)
3889 o1 = LOP_RRR(OP_SETB, bfa, rt, 0)
3890 }
3891
3892 out[0] = o1
3893 out[1] = o2
3894 out[2] = o3
3895 out[3] = o4
3896 out[4] = o5
3897 }
3898
3899 func (c *ctxt9) vregoff(a *obj.Addr) int64 {
3900 c.instoffset = 0
3901 if a != nil {
3902 c.aclass(a)
3903 }
3904 return c.instoffset
3905 }
3906
3907 func (c *ctxt9) regoff(a *obj.Addr) int32 {
3908 return int32(c.vregoff(a))
3909 }
3910
3911 func (c *ctxt9) oprrr(a obj.As) uint32 {
3912 switch a {
3913 case AADD:
3914 return OPVCC(31, 266, 0, 0)
3915 case AADDCC:
3916 return OPVCC(31, 266, 0, 1)
3917 case AADDV:
3918 return OPVCC(31, 266, 1, 0)
3919 case AADDVCC:
3920 return OPVCC(31, 266, 1, 1)
3921 case AADDC:
3922 return OPVCC(31, 10, 0, 0)
3923 case AADDCCC:
3924 return OPVCC(31, 10, 0, 1)
3925 case AADDCV:
3926 return OPVCC(31, 10, 1, 0)
3927 case AADDCVCC:
3928 return OPVCC(31, 10, 1, 1)
3929 case AADDE:
3930 return OPVCC(31, 138, 0, 0)
3931 case AADDECC:
3932 return OPVCC(31, 138, 0, 1)
3933 case AADDEV:
3934 return OPVCC(31, 138, 1, 0)
3935 case AADDEVCC:
3936 return OPVCC(31, 138, 1, 1)
3937 case AADDME:
3938 return OPVCC(31, 234, 0, 0)
3939 case AADDMECC:
3940 return OPVCC(31, 234, 0, 1)
3941 case AADDMEV:
3942 return OPVCC(31, 234, 1, 0)
3943 case AADDMEVCC:
3944 return OPVCC(31, 234, 1, 1)
3945 case AADDZE:
3946 return OPVCC(31, 202, 0, 0)
3947 case AADDZECC:
3948 return OPVCC(31, 202, 0, 1)
3949 case AADDZEV:
3950 return OPVCC(31, 202, 1, 0)
3951 case AADDZEVCC:
3952 return OPVCC(31, 202, 1, 1)
3953 case AADDEX:
3954 return OPVCC(31, 170, 0, 0)
3955
3956 case AAND:
3957 return OPVCC(31, 28, 0, 0)
3958 case AANDCC:
3959 return OPVCC(31, 28, 0, 1)
3960 case AANDN:
3961 return OPVCC(31, 60, 0, 0)
3962 case AANDNCC:
3963 return OPVCC(31, 60, 0, 1)
3964
3965 case ACMP:
3966 return OPVCC(31, 0, 0, 0) | 1<<21
3967 case ACMPU:
3968 return OPVCC(31, 32, 0, 0) | 1<<21
3969 case ACMPW:
3970 return OPVCC(31, 0, 0, 0)
3971 case ACMPWU:
3972 return OPVCC(31, 32, 0, 0)
3973 case ACMPB:
3974 return OPVCC(31, 508, 0, 0)
3975 case ACMPEQB:
3976 return OPVCC(31, 224, 0, 0)
3977
3978 case ACNTLZW:
3979 return OPVCC(31, 26, 0, 0)
3980 case ACNTLZWCC:
3981 return OPVCC(31, 26, 0, 1)
3982 case ACNTLZD:
3983 return OPVCC(31, 58, 0, 0)
3984 case ACNTLZDCC:
3985 return OPVCC(31, 58, 0, 1)
3986
3987 case ACRAND:
3988 return OPVCC(19, 257, 0, 0)
3989 case ACRANDN:
3990 return OPVCC(19, 129, 0, 0)
3991 case ACREQV:
3992 return OPVCC(19, 289, 0, 0)
3993 case ACRNAND:
3994 return OPVCC(19, 225, 0, 0)
3995 case ACRNOR:
3996 return OPVCC(19, 33, 0, 0)
3997 case ACROR:
3998 return OPVCC(19, 449, 0, 0)
3999 case ACRORN:
4000 return OPVCC(19, 417, 0, 0)
4001 case ACRXOR:
4002 return OPVCC(19, 193, 0, 0)
4003
4004 case ADADD:
4005 return OPVCC(59, 2, 0, 0)
4006 case ADDIV:
4007 return OPVCC(59, 546, 0, 0)
4008 case ADMUL:
4009 return OPVCC(59, 34, 0, 0)
4010 case ADSUB:
4011 return OPVCC(59, 514, 0, 0)
4012 case ADADDQ:
4013 return OPVCC(63, 2, 0, 0)
4014 case ADDIVQ:
4015 return OPVCC(63, 546, 0, 0)
4016 case ADMULQ:
4017 return OPVCC(63, 34, 0, 0)
4018 case ADSUBQ:
4019 return OPVCC(63, 514, 0, 0)
4020 case ADCMPU:
4021 return OPVCC(59, 642, 0, 0)
4022 case ADCMPUQ:
4023 return OPVCC(63, 642, 0, 0)
4024 case ADCMPO:
4025 return OPVCC(59, 130, 0, 0)
4026 case ADCMPOQ:
4027 return OPVCC(63, 130, 0, 0)
4028
4029 case ADCBF:
4030 return OPVCC(31, 86, 0, 0)
4031 case ADCBI:
4032 return OPVCC(31, 470, 0, 0)
4033 case ADCBST:
4034 return OPVCC(31, 54, 0, 0)
4035 case ADCBT:
4036 return OPVCC(31, 278, 0, 0)
4037 case ADCBTST:
4038 return OPVCC(31, 246, 0, 0)
4039 case ADCBZ:
4040 return OPVCC(31, 1014, 0, 0)
4041
4042 case AMODUD:
4043 return OPVCC(31, 265, 0, 0)
4044 case AMODUW:
4045 return OPVCC(31, 267, 0, 0)
4046 case AMODSD:
4047 return OPVCC(31, 777, 0, 0)
4048 case AMODSW:
4049 return OPVCC(31, 779, 0, 0)
4050
4051 case ADIVW, AREM:
4052 return OPVCC(31, 491, 0, 0)
4053
4054 case ADIVWCC:
4055 return OPVCC(31, 491, 0, 1)
4056
4057 case ADIVWV:
4058 return OPVCC(31, 491, 1, 0)
4059
4060 case ADIVWVCC:
4061 return OPVCC(31, 491, 1, 1)
4062
4063 case ADIVWU, AREMU:
4064 return OPVCC(31, 459, 0, 0)
4065
4066 case ADIVWUCC:
4067 return OPVCC(31, 459, 0, 1)
4068
4069 case ADIVWUV:
4070 return OPVCC(31, 459, 1, 0)
4071
4072 case ADIVWUVCC:
4073 return OPVCC(31, 459, 1, 1)
4074
4075 case ADIVD, AREMD:
4076 return OPVCC(31, 489, 0, 0)
4077
4078 case ADIVDCC:
4079 return OPVCC(31, 489, 0, 1)
4080
4081 case ADIVDE:
4082 return OPVCC(31, 425, 0, 0)
4083
4084 case ADIVDECC:
4085 return OPVCC(31, 425, 0, 1)
4086
4087 case ADIVDEU:
4088 return OPVCC(31, 393, 0, 0)
4089
4090 case ADIVDEUCC:
4091 return OPVCC(31, 393, 0, 1)
4092
4093 case ADIVDV:
4094 return OPVCC(31, 489, 1, 0)
4095
4096 case ADIVDVCC:
4097 return OPVCC(31, 489, 1, 1)
4098
4099 case ADIVDU, AREMDU:
4100 return OPVCC(31, 457, 0, 0)
4101
4102 case ADIVDUCC:
4103 return OPVCC(31, 457, 0, 1)
4104
4105 case ADIVDUV:
4106 return OPVCC(31, 457, 1, 0)
4107
4108 case ADIVDUVCC:
4109 return OPVCC(31, 457, 1, 1)
4110
4111 case AEIEIO:
4112 return OPVCC(31, 854, 0, 0)
4113
4114 case AEQV:
4115 return OPVCC(31, 284, 0, 0)
4116 case AEQVCC:
4117 return OPVCC(31, 284, 0, 1)
4118
4119 case AEXTSB:
4120 return OPVCC(31, 954, 0, 0)
4121 case AEXTSBCC:
4122 return OPVCC(31, 954, 0, 1)
4123 case AEXTSH:
4124 return OPVCC(31, 922, 0, 0)
4125 case AEXTSHCC:
4126 return OPVCC(31, 922, 0, 1)
4127 case AEXTSW:
4128 return OPVCC(31, 986, 0, 0)
4129 case AEXTSWCC:
4130 return OPVCC(31, 986, 0, 1)
4131
4132 case AFABS:
4133 return OPVCC(63, 264, 0, 0)
4134 case AFABSCC:
4135 return OPVCC(63, 264, 0, 1)
4136 case AFADD:
4137 return OPVCC(63, 21, 0, 0)
4138 case AFADDCC:
4139 return OPVCC(63, 21, 0, 1)
4140 case AFADDS:
4141 return OPVCC(59, 21, 0, 0)
4142 case AFADDSCC:
4143 return OPVCC(59, 21, 0, 1)
4144 case AFCMPO:
4145 return OPVCC(63, 32, 0, 0)
4146 case AFCMPU:
4147 return OPVCC(63, 0, 0, 0)
4148 case AFCFID:
4149 return OPVCC(63, 846, 0, 0)
4150 case AFCFIDCC:
4151 return OPVCC(63, 846, 0, 1)
4152 case AFCFIDU:
4153 return OPVCC(63, 974, 0, 0)
4154 case AFCFIDUCC:
4155 return OPVCC(63, 974, 0, 1)
4156 case AFCFIDS:
4157 return OPVCC(59, 846, 0, 0)
4158 case AFCFIDSCC:
4159 return OPVCC(59, 846, 0, 1)
4160 case AFCTIW:
4161 return OPVCC(63, 14, 0, 0)
4162 case AFCTIWCC:
4163 return OPVCC(63, 14, 0, 1)
4164 case AFCTIWZ:
4165 return OPVCC(63, 15, 0, 0)
4166 case AFCTIWZCC:
4167 return OPVCC(63, 15, 0, 1)
4168 case AFCTID:
4169 return OPVCC(63, 814, 0, 0)
4170 case AFCTIDCC:
4171 return OPVCC(63, 814, 0, 1)
4172 case AFCTIDZ:
4173 return OPVCC(63, 815, 0, 0)
4174 case AFCTIDZCC:
4175 return OPVCC(63, 815, 0, 1)
4176 case AFDIV:
4177 return OPVCC(63, 18, 0, 0)
4178 case AFDIVCC:
4179 return OPVCC(63, 18, 0, 1)
4180 case AFDIVS:
4181 return OPVCC(59, 18, 0, 0)
4182 case AFDIVSCC:
4183 return OPVCC(59, 18, 0, 1)
4184 case AFMADD:
4185 return OPVCC(63, 29, 0, 0)
4186 case AFMADDCC:
4187 return OPVCC(63, 29, 0, 1)
4188 case AFMADDS:
4189 return OPVCC(59, 29, 0, 0)
4190 case AFMADDSCC:
4191 return OPVCC(59, 29, 0, 1)
4192
4193 case AFMOVS, AFMOVD:
4194 return OPVCC(63, 72, 0, 0)
4195 case AFMOVDCC:
4196 return OPVCC(63, 72, 0, 1)
4197 case AFMSUB:
4198 return OPVCC(63, 28, 0, 0)
4199 case AFMSUBCC:
4200 return OPVCC(63, 28, 0, 1)
4201 case AFMSUBS:
4202 return OPVCC(59, 28, 0, 0)
4203 case AFMSUBSCC:
4204 return OPVCC(59, 28, 0, 1)
4205 case AFMUL:
4206 return OPVCC(63, 25, 0, 0)
4207 case AFMULCC:
4208 return OPVCC(63, 25, 0, 1)
4209 case AFMULS:
4210 return OPVCC(59, 25, 0, 0)
4211 case AFMULSCC:
4212 return OPVCC(59, 25, 0, 1)
4213 case AFNABS:
4214 return OPVCC(63, 136, 0, 0)
4215 case AFNABSCC:
4216 return OPVCC(63, 136, 0, 1)
4217 case AFNEG:
4218 return OPVCC(63, 40, 0, 0)
4219 case AFNEGCC:
4220 return OPVCC(63, 40, 0, 1)
4221 case AFNMADD:
4222 return OPVCC(63, 31, 0, 0)
4223 case AFNMADDCC:
4224 return OPVCC(63, 31, 0, 1)
4225 case AFNMADDS:
4226 return OPVCC(59, 31, 0, 0)
4227 case AFNMADDSCC:
4228 return OPVCC(59, 31, 0, 1)
4229 case AFNMSUB:
4230 return OPVCC(63, 30, 0, 0)
4231 case AFNMSUBCC:
4232 return OPVCC(63, 30, 0, 1)
4233 case AFNMSUBS:
4234 return OPVCC(59, 30, 0, 0)
4235 case AFNMSUBSCC:
4236 return OPVCC(59, 30, 0, 1)
4237 case AFCPSGN:
4238 return OPVCC(63, 8, 0, 0)
4239 case AFCPSGNCC:
4240 return OPVCC(63, 8, 0, 1)
4241 case AFRES:
4242 return OPVCC(59, 24, 0, 0)
4243 case AFRESCC:
4244 return OPVCC(59, 24, 0, 1)
4245 case AFRIM:
4246 return OPVCC(63, 488, 0, 0)
4247 case AFRIMCC:
4248 return OPVCC(63, 488, 0, 1)
4249 case AFRIP:
4250 return OPVCC(63, 456, 0, 0)
4251 case AFRIPCC:
4252 return OPVCC(63, 456, 0, 1)
4253 case AFRIZ:
4254 return OPVCC(63, 424, 0, 0)
4255 case AFRIZCC:
4256 return OPVCC(63, 424, 0, 1)
4257 case AFRIN:
4258 return OPVCC(63, 392, 0, 0)
4259 case AFRINCC:
4260 return OPVCC(63, 392, 0, 1)
4261 case AFRSP:
4262 return OPVCC(63, 12, 0, 0)
4263 case AFRSPCC:
4264 return OPVCC(63, 12, 0, 1)
4265 case AFRSQRTE:
4266 return OPVCC(63, 26, 0, 0)
4267 case AFRSQRTECC:
4268 return OPVCC(63, 26, 0, 1)
4269 case AFSEL:
4270 return OPVCC(63, 23, 0, 0)
4271 case AFSELCC:
4272 return OPVCC(63, 23, 0, 1)
4273 case AFSQRT:
4274 return OPVCC(63, 22, 0, 0)
4275 case AFSQRTCC:
4276 return OPVCC(63, 22, 0, 1)
4277 case AFSQRTS:
4278 return OPVCC(59, 22, 0, 0)
4279 case AFSQRTSCC:
4280 return OPVCC(59, 22, 0, 1)
4281 case AFSUB:
4282 return OPVCC(63, 20, 0, 0)
4283 case AFSUBCC:
4284 return OPVCC(63, 20, 0, 1)
4285 case AFSUBS:
4286 return OPVCC(59, 20, 0, 0)
4287 case AFSUBSCC:
4288 return OPVCC(59, 20, 0, 1)
4289
4290 case AICBI:
4291 return OPVCC(31, 982, 0, 0)
4292 case AISYNC:
4293 return OPVCC(19, 150, 0, 0)
4294
4295 case AMTFSB0:
4296 return OPVCC(63, 70, 0, 0)
4297 case AMTFSB0CC:
4298 return OPVCC(63, 70, 0, 1)
4299 case AMTFSB1:
4300 return OPVCC(63, 38, 0, 0)
4301 case AMTFSB1CC:
4302 return OPVCC(63, 38, 0, 1)
4303
4304 case AMULHW:
4305 return OPVCC(31, 75, 0, 0)
4306 case AMULHWCC:
4307 return OPVCC(31, 75, 0, 1)
4308 case AMULHWU:
4309 return OPVCC(31, 11, 0, 0)
4310 case AMULHWUCC:
4311 return OPVCC(31, 11, 0, 1)
4312 case AMULLW:
4313 return OPVCC(31, 235, 0, 0)
4314 case AMULLWCC:
4315 return OPVCC(31, 235, 0, 1)
4316 case AMULLWV:
4317 return OPVCC(31, 235, 1, 0)
4318 case AMULLWVCC:
4319 return OPVCC(31, 235, 1, 1)
4320
4321 case AMULHD:
4322 return OPVCC(31, 73, 0, 0)
4323 case AMULHDCC:
4324 return OPVCC(31, 73, 0, 1)
4325 case AMULHDU:
4326 return OPVCC(31, 9, 0, 0)
4327 case AMULHDUCC:
4328 return OPVCC(31, 9, 0, 1)
4329 case AMULLD:
4330 return OPVCC(31, 233, 0, 0)
4331 case AMULLDCC:
4332 return OPVCC(31, 233, 0, 1)
4333 case AMULLDV:
4334 return OPVCC(31, 233, 1, 0)
4335 case AMULLDVCC:
4336 return OPVCC(31, 233, 1, 1)
4337
4338 case ANAND:
4339 return OPVCC(31, 476, 0, 0)
4340 case ANANDCC:
4341 return OPVCC(31, 476, 0, 1)
4342 case ANEG:
4343 return OPVCC(31, 104, 0, 0)
4344 case ANEGCC:
4345 return OPVCC(31, 104, 0, 1)
4346 case ANEGV:
4347 return OPVCC(31, 104, 1, 0)
4348 case ANEGVCC:
4349 return OPVCC(31, 104, 1, 1)
4350 case ANOR:
4351 return OPVCC(31, 124, 0, 0)
4352 case ANORCC:
4353 return OPVCC(31, 124, 0, 1)
4354 case AOR:
4355 return OPVCC(31, 444, 0, 0)
4356 case AORCC:
4357 return OPVCC(31, 444, 0, 1)
4358 case AORN:
4359 return OPVCC(31, 412, 0, 0)
4360 case AORNCC:
4361 return OPVCC(31, 412, 0, 1)
4362
4363 case APOPCNTD:
4364 return OPVCC(31, 506, 0, 0)
4365 case APOPCNTW:
4366 return OPVCC(31, 378, 0, 0)
4367 case APOPCNTB:
4368 return OPVCC(31, 122, 0, 0)
4369 case ACNTTZW:
4370 return OPVCC(31, 538, 0, 0)
4371 case ACNTTZWCC:
4372 return OPVCC(31, 538, 0, 1)
4373 case ACNTTZD:
4374 return OPVCC(31, 570, 0, 0)
4375 case ACNTTZDCC:
4376 return OPVCC(31, 570, 0, 1)
4377
4378 case ARFI:
4379 return OPVCC(19, 50, 0, 0)
4380 case ARFCI:
4381 return OPVCC(19, 51, 0, 0)
4382 case ARFID:
4383 return OPVCC(19, 18, 0, 0)
4384 case AHRFID:
4385 return OPVCC(19, 274, 0, 0)
4386
4387 case ARLWNM:
4388 return OPVCC(23, 0, 0, 0)
4389 case ARLWNMCC:
4390 return OPVCC(23, 0, 0, 1)
4391
4392 case ARLDCL:
4393 return OPVCC(30, 8, 0, 0)
4394 case ARLDCLCC:
4395 return OPVCC(30, 0, 0, 1)
4396
4397 case ARLDCR:
4398 return OPVCC(30, 9, 0, 0)
4399 case ARLDCRCC:
4400 return OPVCC(30, 9, 0, 1)
4401
4402 case ARLDICL:
4403 return OPVCC(30, 0, 0, 0)
4404 case ARLDICLCC:
4405 return OPVCC(30, 0, 0, 1)
4406 case ARLDICR:
4407 return OPMD(30, 1, 0)
4408 case ARLDICRCC:
4409 return OPMD(30, 1, 1)
4410
4411 case ARLDIC:
4412 return OPMD(30, 2, 0)
4413 case ARLDICCC:
4414 return OPMD(30, 2, 1)
4415
4416 case ASYSCALL:
4417 return OPVCC(17, 1, 0, 0)
4418
4419 case ASLW:
4420 return OPVCC(31, 24, 0, 0)
4421 case ASLWCC:
4422 return OPVCC(31, 24, 0, 1)
4423 case ASLD:
4424 return OPVCC(31, 27, 0, 0)
4425 case ASLDCC:
4426 return OPVCC(31, 27, 0, 1)
4427
4428 case ASRAW:
4429 return OPVCC(31, 792, 0, 0)
4430 case ASRAWCC:
4431 return OPVCC(31, 792, 0, 1)
4432 case ASRAD:
4433 return OPVCC(31, 794, 0, 0)
4434 case ASRADCC:
4435 return OPVCC(31, 794, 0, 1)
4436
4437 case AEXTSWSLI:
4438 return OPVCC(31, 445, 0, 0)
4439 case AEXTSWSLICC:
4440 return OPVCC(31, 445, 0, 1)
4441
4442 case ASRW:
4443 return OPVCC(31, 536, 0, 0)
4444 case ASRWCC:
4445 return OPVCC(31, 536, 0, 1)
4446 case ASRD:
4447 return OPVCC(31, 539, 0, 0)
4448 case ASRDCC:
4449 return OPVCC(31, 539, 0, 1)
4450
4451 case ASUB:
4452 return OPVCC(31, 40, 0, 0)
4453 case ASUBCC:
4454 return OPVCC(31, 40, 0, 1)
4455 case ASUBV:
4456 return OPVCC(31, 40, 1, 0)
4457 case ASUBVCC:
4458 return OPVCC(31, 40, 1, 1)
4459 case ASUBC:
4460 return OPVCC(31, 8, 0, 0)
4461 case ASUBCCC:
4462 return OPVCC(31, 8, 0, 1)
4463 case ASUBCV:
4464 return OPVCC(31, 8, 1, 0)
4465 case ASUBCVCC:
4466 return OPVCC(31, 8, 1, 1)
4467 case ASUBE:
4468 return OPVCC(31, 136, 0, 0)
4469 case ASUBECC:
4470 return OPVCC(31, 136, 0, 1)
4471 case ASUBEV:
4472 return OPVCC(31, 136, 1, 0)
4473 case ASUBEVCC:
4474 return OPVCC(31, 136, 1, 1)
4475 case ASUBME:
4476 return OPVCC(31, 232, 0, 0)
4477 case ASUBMECC:
4478 return OPVCC(31, 232, 0, 1)
4479 case ASUBMEV:
4480 return OPVCC(31, 232, 1, 0)
4481 case ASUBMEVCC:
4482 return OPVCC(31, 232, 1, 1)
4483 case ASUBZE:
4484 return OPVCC(31, 200, 0, 0)
4485 case ASUBZECC:
4486 return OPVCC(31, 200, 0, 1)
4487 case ASUBZEV:
4488 return OPVCC(31, 200, 1, 0)
4489 case ASUBZEVCC:
4490 return OPVCC(31, 200, 1, 1)
4491
4492 case ASYNC:
4493 return OPVCC(31, 598, 0, 0)
4494 case ALWSYNC:
4495 return OPVCC(31, 598, 0, 0) | 1<<21
4496
4497 case APTESYNC:
4498 return OPVCC(31, 598, 0, 0) | 2<<21
4499
4500 case ATLBIE:
4501 return OPVCC(31, 306, 0, 0)
4502 case ATLBIEL:
4503 return OPVCC(31, 274, 0, 0)
4504 case ATLBSYNC:
4505 return OPVCC(31, 566, 0, 0)
4506 case ASLBIA:
4507 return OPVCC(31, 498, 0, 0)
4508 case ASLBIE:
4509 return OPVCC(31, 434, 0, 0)
4510 case ASLBMFEE:
4511 return OPVCC(31, 915, 0, 0)
4512 case ASLBMFEV:
4513 return OPVCC(31, 851, 0, 0)
4514 case ASLBMTE:
4515 return OPVCC(31, 402, 0, 0)
4516
4517 case ATW:
4518 return OPVCC(31, 4, 0, 0)
4519 case ATD:
4520 return OPVCC(31, 68, 0, 0)
4521
4522
4523
4524
4525 case AVAND:
4526 return OPVX(4, 1028, 0, 0)
4527 case AVANDC:
4528 return OPVX(4, 1092, 0, 0)
4529 case AVNAND:
4530 return OPVX(4, 1412, 0, 0)
4531
4532 case AVOR:
4533 return OPVX(4, 1156, 0, 0)
4534 case AVORC:
4535 return OPVX(4, 1348, 0, 0)
4536 case AVNOR:
4537 return OPVX(4, 1284, 0, 0)
4538 case AVXOR:
4539 return OPVX(4, 1220, 0, 0)
4540 case AVEQV:
4541 return OPVX(4, 1668, 0, 0)
4542
4543 case AVADDUBM:
4544 return OPVX(4, 0, 0, 0)
4545 case AVADDUHM:
4546 return OPVX(4, 64, 0, 0)
4547 case AVADDUWM:
4548 return OPVX(4, 128, 0, 0)
4549 case AVADDUDM:
4550 return OPVX(4, 192, 0, 0)
4551 case AVADDUQM:
4552 return OPVX(4, 256, 0, 0)
4553
4554 case AVADDCUQ:
4555 return OPVX(4, 320, 0, 0)
4556 case AVADDCUW:
4557 return OPVX(4, 384, 0, 0)
4558
4559 case AVADDUBS:
4560 return OPVX(4, 512, 0, 0)
4561 case AVADDUHS:
4562 return OPVX(4, 576, 0, 0)
4563 case AVADDUWS:
4564 return OPVX(4, 640, 0, 0)
4565
4566 case AVADDSBS:
4567 return OPVX(4, 768, 0, 0)
4568 case AVADDSHS:
4569 return OPVX(4, 832, 0, 0)
4570 case AVADDSWS:
4571 return OPVX(4, 896, 0, 0)
4572
4573 case AVADDEUQM:
4574 return OPVX(4, 60, 0, 0)
4575 case AVADDECUQ:
4576 return OPVX(4, 61, 0, 0)
4577
4578 case AVMULESB:
4579 return OPVX(4, 776, 0, 0)
4580 case AVMULOSB:
4581 return OPVX(4, 264, 0, 0)
4582 case AVMULEUB:
4583 return OPVX(4, 520, 0, 0)
4584 case AVMULOUB:
4585 return OPVX(4, 8, 0, 0)
4586 case AVMULESH:
4587 return OPVX(4, 840, 0, 0)
4588 case AVMULOSH:
4589 return OPVX(4, 328, 0, 0)
4590 case AVMULEUH:
4591 return OPVX(4, 584, 0, 0)
4592 case AVMULOUH:
4593 return OPVX(4, 72, 0, 0)
4594 case AVMULESW:
4595 return OPVX(4, 904, 0, 0)
4596 case AVMULOSW:
4597 return OPVX(4, 392, 0, 0)
4598 case AVMULEUW:
4599 return OPVX(4, 648, 0, 0)
4600 case AVMULOUW:
4601 return OPVX(4, 136, 0, 0)
4602 case AVMULUWM:
4603 return OPVX(4, 137, 0, 0)
4604
4605 case AVPMSUMB:
4606 return OPVX(4, 1032, 0, 0)
4607 case AVPMSUMH:
4608 return OPVX(4, 1096, 0, 0)
4609 case AVPMSUMW:
4610 return OPVX(4, 1160, 0, 0)
4611 case AVPMSUMD:
4612 return OPVX(4, 1224, 0, 0)
4613
4614 case AVMSUMUDM:
4615 return OPVX(4, 35, 0, 0)
4616
4617 case AVSUBUBM:
4618 return OPVX(4, 1024, 0, 0)
4619 case AVSUBUHM:
4620 return OPVX(4, 1088, 0, 0)
4621 case AVSUBUWM:
4622 return OPVX(4, 1152, 0, 0)
4623 case AVSUBUDM:
4624 return OPVX(4, 1216, 0, 0)
4625 case AVSUBUQM:
4626 return OPVX(4, 1280, 0, 0)
4627
4628 case AVSUBCUQ:
4629 return OPVX(4, 1344, 0, 0)
4630 case AVSUBCUW:
4631 return OPVX(4, 1408, 0, 0)
4632
4633 case AVSUBUBS:
4634 return OPVX(4, 1536, 0, 0)
4635 case AVSUBUHS:
4636 return OPVX(4, 1600, 0, 0)
4637 case AVSUBUWS:
4638 return OPVX(4, 1664, 0, 0)
4639
4640 case AVSUBSBS:
4641 return OPVX(4, 1792, 0, 0)
4642 case AVSUBSHS:
4643 return OPVX(4, 1856, 0, 0)
4644 case AVSUBSWS:
4645 return OPVX(4, 1920, 0, 0)
4646
4647 case AVSUBEUQM:
4648 return OPVX(4, 62, 0, 0)
4649 case AVSUBECUQ:
4650 return OPVX(4, 63, 0, 0)
4651
4652 case AVRLB:
4653 return OPVX(4, 4, 0, 0)
4654 case AVRLH:
4655 return OPVX(4, 68, 0, 0)
4656 case AVRLW:
4657 return OPVX(4, 132, 0, 0)
4658 case AVRLD:
4659 return OPVX(4, 196, 0, 0)
4660
4661 case AVMRGOW:
4662 return OPVX(4, 1676, 0, 0)
4663 case AVMRGEW:
4664 return OPVX(4, 1932, 0, 0)
4665
4666 case AVSLB:
4667 return OPVX(4, 260, 0, 0)
4668 case AVSLH:
4669 return OPVX(4, 324, 0, 0)
4670 case AVSLW:
4671 return OPVX(4, 388, 0, 0)
4672 case AVSL:
4673 return OPVX(4, 452, 0, 0)
4674 case AVSLO:
4675 return OPVX(4, 1036, 0, 0)
4676 case AVSRB:
4677 return OPVX(4, 516, 0, 0)
4678 case AVSRH:
4679 return OPVX(4, 580, 0, 0)
4680 case AVSRW:
4681 return OPVX(4, 644, 0, 0)
4682 case AVSR:
4683 return OPVX(4, 708, 0, 0)
4684 case AVSRO:
4685 return OPVX(4, 1100, 0, 0)
4686 case AVSLD:
4687 return OPVX(4, 1476, 0, 0)
4688 case AVSRD:
4689 return OPVX(4, 1732, 0, 0)
4690
4691 case AVSRAB:
4692 return OPVX(4, 772, 0, 0)
4693 case AVSRAH:
4694 return OPVX(4, 836, 0, 0)
4695 case AVSRAW:
4696 return OPVX(4, 900, 0, 0)
4697 case AVSRAD:
4698 return OPVX(4, 964, 0, 0)
4699
4700 case AVBPERMQ:
4701 return OPVC(4, 1356, 0, 0)
4702 case AVBPERMD:
4703 return OPVC(4, 1484, 0, 0)
4704
4705 case AVCLZB:
4706 return OPVX(4, 1794, 0, 0)
4707 case AVCLZH:
4708 return OPVX(4, 1858, 0, 0)
4709 case AVCLZW:
4710 return OPVX(4, 1922, 0, 0)
4711 case AVCLZD:
4712 return OPVX(4, 1986, 0, 0)
4713
4714 case AVCLZLSBB:
4715 return OPVX(4, 1538, 0, 0)
4716 case AVCTZLSBB:
4717 return OPVX(4, 1538, 0, 0) | 1<<16
4718
4719 case AVPOPCNTB:
4720 return OPVX(4, 1795, 0, 0)
4721 case AVPOPCNTH:
4722 return OPVX(4, 1859, 0, 0)
4723 case AVPOPCNTW:
4724 return OPVX(4, 1923, 0, 0)
4725 case AVPOPCNTD:
4726 return OPVX(4, 1987, 0, 0)
4727
4728 case AVCMPEQUB:
4729 return OPVC(4, 6, 0, 0)
4730 case AVCMPEQUBCC:
4731 return OPVC(4, 6, 0, 1)
4732 case AVCMPEQUH:
4733 return OPVC(4, 70, 0, 0)
4734 case AVCMPEQUHCC:
4735 return OPVC(4, 70, 0, 1)
4736 case AVCMPEQUW:
4737 return OPVC(4, 134, 0, 0)
4738 case AVCMPEQUWCC:
4739 return OPVC(4, 134, 0, 1)
4740 case AVCMPEQUD:
4741 return OPVC(4, 199, 0, 0)
4742 case AVCMPEQUDCC:
4743 return OPVC(4, 199, 0, 1)
4744
4745 case AVCMPGTUB:
4746 return OPVC(4, 518, 0, 0)
4747 case AVCMPGTUBCC:
4748 return OPVC(4, 518, 0, 1)
4749 case AVCMPGTUH:
4750 return OPVC(4, 582, 0, 0)
4751 case AVCMPGTUHCC:
4752 return OPVC(4, 582, 0, 1)
4753 case AVCMPGTUW:
4754 return OPVC(4, 646, 0, 0)
4755 case AVCMPGTUWCC:
4756 return OPVC(4, 646, 0, 1)
4757 case AVCMPGTUD:
4758 return OPVC(4, 711, 0, 0)
4759 case AVCMPGTUDCC:
4760 return OPVC(4, 711, 0, 1)
4761 case AVCMPGTSB:
4762 return OPVC(4, 774, 0, 0)
4763 case AVCMPGTSBCC:
4764 return OPVC(4, 774, 0, 1)
4765 case AVCMPGTSH:
4766 return OPVC(4, 838, 0, 0)
4767 case AVCMPGTSHCC:
4768 return OPVC(4, 838, 0, 1)
4769 case AVCMPGTSW:
4770 return OPVC(4, 902, 0, 0)
4771 case AVCMPGTSWCC:
4772 return OPVC(4, 902, 0, 1)
4773 case AVCMPGTSD:
4774 return OPVC(4, 967, 0, 0)
4775 case AVCMPGTSDCC:
4776 return OPVC(4, 967, 0, 1)
4777
4778 case AVCMPNEZB:
4779 return OPVC(4, 263, 0, 0)
4780 case AVCMPNEZBCC:
4781 return OPVC(4, 263, 0, 1)
4782 case AVCMPNEB:
4783 return OPVC(4, 7, 0, 0)
4784 case AVCMPNEBCC:
4785 return OPVC(4, 7, 0, 1)
4786 case AVCMPNEH:
4787 return OPVC(4, 71, 0, 0)
4788 case AVCMPNEHCC:
4789 return OPVC(4, 71, 0, 1)
4790 case AVCMPNEW:
4791 return OPVC(4, 135, 0, 0)
4792 case AVCMPNEWCC:
4793 return OPVC(4, 135, 0, 1)
4794
4795 case AVPERM:
4796 return OPVX(4, 43, 0, 0)
4797 case AVPERMXOR:
4798 return OPVX(4, 45, 0, 0)
4799 case AVPERMR:
4800 return OPVX(4, 59, 0, 0)
4801
4802 case AVSEL:
4803 return OPVX(4, 42, 0, 0)
4804
4805 case AVCIPHER:
4806 return OPVX(4, 1288, 0, 0)
4807 case AVCIPHERLAST:
4808 return OPVX(4, 1289, 0, 0)
4809 case AVNCIPHER:
4810 return OPVX(4, 1352, 0, 0)
4811 case AVNCIPHERLAST:
4812 return OPVX(4, 1353, 0, 0)
4813 case AVSBOX:
4814 return OPVX(4, 1480, 0, 0)
4815
4816
4817
4818
4819 case AMFVSRD, AMFVRD, AMFFPRD:
4820 return OPVXX1(31, 51, 0)
4821 case AMFVSRWZ:
4822 return OPVXX1(31, 115, 0)
4823 case AMFVSRLD:
4824 return OPVXX1(31, 307, 0)
4825
4826 case AMTVSRD, AMTFPRD, AMTVRD:
4827 return OPVXX1(31, 179, 0)
4828 case AMTVSRWA:
4829 return OPVXX1(31, 211, 0)
4830 case AMTVSRWZ:
4831 return OPVXX1(31, 243, 0)
4832 case AMTVSRDD:
4833 return OPVXX1(31, 435, 0)
4834 case AMTVSRWS:
4835 return OPVXX1(31, 403, 0)
4836
4837 case AXXLAND:
4838 return OPVXX3(60, 130, 0)
4839 case AXXLANDC:
4840 return OPVXX3(60, 138, 0)
4841 case AXXLEQV:
4842 return OPVXX3(60, 186, 0)
4843 case AXXLNAND:
4844 return OPVXX3(60, 178, 0)
4845
4846 case AXXLORC:
4847 return OPVXX3(60, 170, 0)
4848 case AXXLNOR:
4849 return OPVXX3(60, 162, 0)
4850 case AXXLOR, AXXLORQ:
4851 return OPVXX3(60, 146, 0)
4852 case AXXLXOR:
4853 return OPVXX3(60, 154, 0)
4854 case AXSMINJDP:
4855 return OPVXX3(60, 152, 0)
4856 case AXSMAXJDP:
4857 return OPVXX3(60, 144, 0)
4858
4859 case AXXSEL:
4860 return OPVXX4(60, 3, 0)
4861
4862 case AXXMRGHW:
4863 return OPVXX3(60, 18, 0)
4864 case AXXMRGLW:
4865 return OPVXX3(60, 50, 0)
4866
4867 case AXXSPLTW:
4868 return OPVXX2(60, 164, 0)
4869
4870 case AXXSPLTIB:
4871 return OPVCC(60, 360, 0, 0)
4872
4873 case AXXPERM:
4874 return OPVXX3(60, 26, 0)
4875 case AXXPERMDI:
4876 return OPVXX3(60, 10, 0)
4877
4878 case AXXSLDWI:
4879 return OPVXX3(60, 2, 0)
4880
4881 case AXXBRQ:
4882 return OPVXX2VA(60, 475, 31)
4883 case AXXBRD:
4884 return OPVXX2VA(60, 475, 23)
4885 case AXXBRW:
4886 return OPVXX2VA(60, 475, 15)
4887 case AXXBRH:
4888 return OPVXX2VA(60, 475, 7)
4889
4890 case AXSCVDPSP:
4891 return OPVXX2(60, 265, 0)
4892 case AXSCVSPDP:
4893 return OPVXX2(60, 329, 0)
4894 case AXSCVDPSPN:
4895 return OPVXX2(60, 267, 0)
4896 case AXSCVSPDPN:
4897 return OPVXX2(60, 331, 0)
4898
4899 case AXVCVDPSP:
4900 return OPVXX2(60, 393, 0)
4901 case AXVCVSPDP:
4902 return OPVXX2(60, 457, 0)
4903
4904 case AXSCVDPSXDS:
4905 return OPVXX2(60, 344, 0)
4906 case AXSCVDPSXWS:
4907 return OPVXX2(60, 88, 0)
4908 case AXSCVDPUXDS:
4909 return OPVXX2(60, 328, 0)
4910 case AXSCVDPUXWS:
4911 return OPVXX2(60, 72, 0)
4912
4913 case AXSCVSXDDP:
4914 return OPVXX2(60, 376, 0)
4915 case AXSCVUXDDP:
4916 return OPVXX2(60, 360, 0)
4917 case AXSCVSXDSP:
4918 return OPVXX2(60, 312, 0)
4919 case AXSCVUXDSP:
4920 return OPVXX2(60, 296, 0)
4921
4922 case AXVCVDPSXDS:
4923 return OPVXX2(60, 472, 0)
4924 case AXVCVDPSXWS:
4925 return OPVXX2(60, 216, 0)
4926 case AXVCVDPUXDS:
4927 return OPVXX2(60, 456, 0)
4928 case AXVCVDPUXWS:
4929 return OPVXX2(60, 200, 0)
4930 case AXVCVSPSXDS:
4931 return OPVXX2(60, 408, 0)
4932 case AXVCVSPSXWS:
4933 return OPVXX2(60, 152, 0)
4934 case AXVCVSPUXDS:
4935 return OPVXX2(60, 392, 0)
4936 case AXVCVSPUXWS:
4937 return OPVXX2(60, 136, 0)
4938
4939 case AXVCVSXDDP:
4940 return OPVXX2(60, 504, 0)
4941 case AXVCVSXWDP:
4942 return OPVXX2(60, 248, 0)
4943 case AXVCVUXDDP:
4944 return OPVXX2(60, 488, 0)
4945 case AXVCVUXWDP:
4946 return OPVXX2(60, 232, 0)
4947 case AXVCVSXDSP:
4948 return OPVXX2(60, 440, 0)
4949 case AXVCVSXWSP:
4950 return OPVXX2(60, 184, 0)
4951 case AXVCVUXDSP:
4952 return OPVXX2(60, 424, 0)
4953 case AXVCVUXWSP:
4954 return OPVXX2(60, 168, 0)
4955
4956 case AXVADDDP:
4957 return OPVXX3(60, 96, 0)
4958 case AXVSUBDP:
4959 return OPVXX3(60, 104, 0)
4960 case AXVMULDP:
4961 return OPVXX3(60, 112, 0)
4962 case AXVDIVDP:
4963 return OPVXX3(60, 120, 0)
4964 case AXVMADDADP:
4965 return OPVXX3(60, 97, 0)
4966 case AXVMAXDP:
4967 return OPVXX3(60, 224, 0)
4968 case AXVMINDP:
4969 return OPVXX3(60, 232, 0)
4970 case AXVSQRTDP:
4971 return OPVXX2(60, 203, 0)
4972 case AXVADDSP:
4973 return OPVXX3(60, 64, 0)
4974 case AXVSUBSP:
4975 return OPVXX3(60, 72, 0)
4976 case AXVMULSP:
4977 return OPVXX3(60, 80, 0)
4978 case AXVDIVSP:
4979 return OPVXX3(60, 88, 0)
4980 case AXVMADDASP:
4981 return OPVXX3(60, 65, 0)
4982 case AXVMAXSP:
4983 return OPVXX3(60, 192, 0)
4984 case AXVMINSP:
4985 return OPVXX3(60, 200, 0)
4986 case AXVSQRTSP:
4987 return OPVXX2(60, 139, 0)
4988
4989
4990 case AMADDHD:
4991 return OPVX(4, 48, 0, 0)
4992 case AMADDHDU:
4993 return OPVX(4, 49, 0, 0)
4994 case AMADDLD:
4995 return OPVX(4, 51, 0, 0)
4996
4997 case AXOR:
4998 return OPVCC(31, 316, 0, 0)
4999 case AXORCC:
5000 return OPVCC(31, 316, 0, 1)
5001 }
5002
5003 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
5004 return 0
5005 }
5006
5007 func (c *ctxt9) opirrr(a obj.As) uint32 {
5008 switch a {
5009
5010
5011
5012 case AVSLDOI:
5013 return OPVX(4, 44, 0, 0)
5014 }
5015
5016 c.ctxt.Diag("bad i/r/r/r opcode %v", a)
5017 return 0
5018 }
5019
5020 func (c *ctxt9) opiirr(a obj.As) uint32 {
5021 switch a {
5022
5023
5024 case AVSHASIGMAW:
5025 return OPVX(4, 1666, 0, 0)
5026 case AVSHASIGMAD:
5027 return OPVX(4, 1730, 0, 0)
5028 }
5029
5030 c.ctxt.Diag("bad i/i/r/r opcode %v", a)
5031 return 0
5032 }
5033
5034 func (c *ctxt9) opirr(a obj.As) uint32 {
5035 switch a {
5036 case AADD:
5037 return OPVCC(14, 0, 0, 0)
5038 case AADDC:
5039 return OPVCC(12, 0, 0, 0)
5040 case AADDCCC:
5041 return OPVCC(13, 0, 0, 0)
5042 case AADDIS:
5043 return OPVCC(15, 0, 0, 0)
5044
5045 case AANDCC:
5046 return OPVCC(28, 0, 0, 0)
5047 case AANDISCC:
5048 return OPVCC(29, 0, 0, 0)
5049
5050 case ABR:
5051 return OPVCC(18, 0, 0, 0)
5052 case ABL:
5053 return OPVCC(18, 0, 0, 0) | 1
5054 case obj.ADUFFZERO:
5055 return OPVCC(18, 0, 0, 0) | 1
5056 case obj.ADUFFCOPY:
5057 return OPVCC(18, 0, 0, 0) | 1
5058 case ABC:
5059 return OPVCC(16, 0, 0, 0)
5060 case ABCL:
5061 return OPVCC(16, 0, 0, 0) | 1
5062
5063 case ABEQ:
5064 return AOP_RRR(16<<26, BO_BCR, BI_EQ, 0)
5065 case ABGE:
5066 return AOP_RRR(16<<26, BO_NOTBCR, BI_LT, 0)
5067 case ABGT:
5068 return AOP_RRR(16<<26, BO_BCR, BI_GT, 0)
5069 case ABLE:
5070 return AOP_RRR(16<<26, BO_NOTBCR, BI_GT, 0)
5071 case ABLT:
5072 return AOP_RRR(16<<26, BO_BCR, BI_LT, 0)
5073 case ABNE:
5074 return AOP_RRR(16<<26, BO_NOTBCR, BI_EQ, 0)
5075 case ABVC:
5076 return AOP_RRR(16<<26, BO_NOTBCR, BI_FU, 0)
5077 case ABVS:
5078 return AOP_RRR(16<<26, BO_BCR, BI_FU, 0)
5079 case ABDZ:
5080 return AOP_RRR(16<<26, BO_NOTBCTR, 0, 0)
5081 case ABDNZ:
5082 return AOP_RRR(16<<26, BO_BCTR, 0, 0)
5083
5084 case ACMP:
5085 return OPVCC(11, 0, 0, 0) | 1<<21
5086 case ACMPU:
5087 return OPVCC(10, 0, 0, 0) | 1<<21
5088 case ACMPW:
5089 return OPVCC(11, 0, 0, 0)
5090 case ACMPWU:
5091 return OPVCC(10, 0, 0, 0)
5092 case ACMPEQB:
5093 return OPVCC(31, 224, 0, 0)
5094
5095 case ALSW:
5096 return OPVCC(31, 597, 0, 0)
5097
5098 case ACOPY:
5099 return OPVCC(31, 774, 0, 0)
5100 case APASTECC:
5101 return OPVCC(31, 902, 0, 1)
5102 case ADARN:
5103 return OPVCC(31, 755, 0, 0)
5104
5105 case AMULLW, AMULLD:
5106 return OPVCC(7, 0, 0, 0)
5107
5108 case AOR:
5109 return OPVCC(24, 0, 0, 0)
5110 case AORIS:
5111 return OPVCC(25, 0, 0, 0)
5112
5113 case ARLWMI:
5114 return OPVCC(20, 0, 0, 0)
5115 case ARLWMICC:
5116 return OPVCC(20, 0, 0, 1)
5117 case ARLDMI:
5118 return OPMD(30, 3, 0)
5119 case ARLDMICC:
5120 return OPMD(30, 3, 1)
5121 case ARLDIMI:
5122 return OPMD(30, 3, 0)
5123 case ARLDIMICC:
5124 return OPMD(30, 3, 1)
5125 case ARLWNM:
5126 return OPVCC(21, 0, 0, 0)
5127 case ARLWNMCC:
5128 return OPVCC(21, 0, 0, 1)
5129
5130 case ARLDCL:
5131 return OPMD(30, 0, 0)
5132 case ARLDCLCC:
5133 return OPMD(30, 0, 1)
5134 case ARLDCR:
5135 return OPMD(30, 1, 0)
5136 case ARLDCRCC:
5137 return OPMD(30, 1, 1)
5138 case ARLDC:
5139 return OPMD(30, 2, 0)
5140 case ARLDCCC:
5141 return OPMD(30, 2, 1)
5142
5143 case ASRAW:
5144 return OPVCC(31, 824, 0, 0)
5145 case ASRAWCC:
5146 return OPVCC(31, 824, 0, 1)
5147 case ASRAD:
5148 return OPVCC(31, (413 << 1), 0, 0)
5149 case ASRADCC:
5150 return OPVCC(31, (413 << 1), 0, 1)
5151 case AEXTSWSLI:
5152 return OPVCC(31, 445, 0, 0)
5153 case AEXTSWSLICC:
5154 return OPVCC(31, 445, 0, 1)
5155
5156 case ASTSW:
5157 return OPVCC(31, 725, 0, 0)
5158
5159 case ASUBC:
5160 return OPVCC(8, 0, 0, 0)
5161
5162 case ATW:
5163 return OPVCC(3, 0, 0, 0)
5164 case ATD:
5165 return OPVCC(2, 0, 0, 0)
5166
5167
5168
5169
5170 case AVSPLTB:
5171 return OPVX(4, 524, 0, 0)
5172 case AVSPLTH:
5173 return OPVX(4, 588, 0, 0)
5174 case AVSPLTW:
5175 return OPVX(4, 652, 0, 0)
5176
5177 case AVSPLTISB:
5178 return OPVX(4, 780, 0, 0)
5179 case AVSPLTISH:
5180 return OPVX(4, 844, 0, 0)
5181 case AVSPLTISW:
5182 return OPVX(4, 908, 0, 0)
5183
5184
5185 case AFTDIV:
5186 return OPVCC(63, 128, 0, 0)
5187 case AFTSQRT:
5188 return OPVCC(63, 160, 0, 0)
5189
5190 case AXOR:
5191 return OPVCC(26, 0, 0, 0)
5192 case AXORIS:
5193 return OPVCC(27, 0, 0, 0)
5194 }
5195
5196 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
5197 return 0
5198 }
5199
5200
5203 func (c *ctxt9) opload(a obj.As) uint32 {
5204 switch a {
5205 case AMOVD:
5206 return OPVCC(58, 0, 0, 0)
5207 case AMOVDU:
5208 return OPVCC(58, 0, 0, 1)
5209 case AMOVWZ:
5210 return OPVCC(32, 0, 0, 0)
5211 case AMOVWZU:
5212 return OPVCC(33, 0, 0, 0)
5213 case AMOVW:
5214 return OPVCC(58, 0, 0, 0) | 1<<1
5215 case ALXV:
5216 return OPDQ(61, 1, 0)
5217 case ALXVL:
5218 return OPVXX1(31, 269, 0)
5219 case ALXVLL:
5220 return OPVXX1(31, 301, 0)
5221 case ALXVX:
5222 return OPVXX1(31, 268, 0)
5223
5224
5225 case AMOVB, AMOVBZ:
5226 return OPVCC(34, 0, 0, 0)
5227
5228
5229 case AMOVBU, AMOVBZU:
5230 return OPVCC(35, 0, 0, 0)
5231 case AFMOVD:
5232 return OPVCC(50, 0, 0, 0)
5233 case AFMOVDU:
5234 return OPVCC(51, 0, 0, 0)
5235 case AFMOVS:
5236 return OPVCC(48, 0, 0, 0)
5237 case AFMOVSU:
5238 return OPVCC(49, 0, 0, 0)
5239 case AMOVH:
5240 return OPVCC(42, 0, 0, 0)
5241 case AMOVHU:
5242 return OPVCC(43, 0, 0, 0)
5243 case AMOVHZ:
5244 return OPVCC(40, 0, 0, 0)
5245 case AMOVHZU:
5246 return OPVCC(41, 0, 0, 0)
5247 case AMOVMW:
5248 return OPVCC(46, 0, 0, 0)
5249 }
5250
5251 c.ctxt.Diag("bad load opcode %v", a)
5252 return 0
5253 }
5254
5255
5258 func (c *ctxt9) oploadx(a obj.As) uint32 {
5259 switch a {
5260 case AMOVWZ:
5261 return OPVCC(31, 23, 0, 0)
5262 case AMOVWZU:
5263 return OPVCC(31, 55, 0, 0)
5264 case AMOVW:
5265 return OPVCC(31, 341, 0, 0)
5266 case AMOVWU:
5267 return OPVCC(31, 373, 0, 0)
5268
5269 case AMOVB, AMOVBZ:
5270 return OPVCC(31, 87, 0, 0)
5271
5272 case AMOVBU, AMOVBZU:
5273 return OPVCC(31, 119, 0, 0)
5274 case AFMOVD:
5275 return OPVCC(31, 599, 0, 0)
5276 case AFMOVDU:
5277 return OPVCC(31, 631, 0, 0)
5278 case AFMOVS:
5279 return OPVCC(31, 535, 0, 0)
5280 case AFMOVSU:
5281 return OPVCC(31, 567, 0, 0)
5282 case AFMOVSX:
5283 return OPVCC(31, 855, 0, 0)
5284 case AFMOVSZ:
5285 return OPVCC(31, 887, 0, 0)
5286 case AMOVH:
5287 return OPVCC(31, 343, 0, 0)
5288 case AMOVHU:
5289 return OPVCC(31, 375, 0, 0)
5290 case AMOVHBR:
5291 return OPVCC(31, 790, 0, 0)
5292 case AMOVWBR:
5293 return OPVCC(31, 534, 0, 0)
5294 case AMOVDBR:
5295 return OPVCC(31, 532, 0, 0)
5296 case AMOVHZ:
5297 return OPVCC(31, 279, 0, 0)
5298 case AMOVHZU:
5299 return OPVCC(31, 311, 0, 0)
5300 case ALBAR:
5301 return OPVCC(31, 52, 0, 0)
5302 case ALHAR:
5303 return OPVCC(31, 116, 0, 0)
5304 case ALWAR:
5305 return OPVCC(31, 20, 0, 0)
5306 case ALDAR:
5307 return OPVCC(31, 84, 0, 0)
5308 case ALSW:
5309 return OPVCC(31, 533, 0, 0)
5310 case AMOVD:
5311 return OPVCC(31, 21, 0, 0)
5312 case AMOVDU:
5313 return OPVCC(31, 53, 0, 0)
5314
5315
5316 case ALVEBX:
5317 return OPVCC(31, 7, 0, 0)
5318 case ALVEHX:
5319 return OPVCC(31, 39, 0, 0)
5320 case ALVEWX:
5321 return OPVCC(31, 71, 0, 0)
5322 case ALVX:
5323 return OPVCC(31, 103, 0, 0)
5324 case ALVXL:
5325 return OPVCC(31, 359, 0, 0)
5326 case ALVSL:
5327 return OPVCC(31, 6, 0, 0)
5328 case ALVSR:
5329 return OPVCC(31, 38, 0, 0)
5330
5331
5332
5333 case ALXVX:
5334 return OPVXX1(31, 268, 0)
5335 case ALXVD2X:
5336 return OPVXX1(31, 844, 0)
5337 case ALXVW4X:
5338 return OPVXX1(31, 780, 0)
5339 case ALXVH8X:
5340 return OPVXX1(31, 812, 0)
5341 case ALXVB16X:
5342 return OPVXX1(31, 876, 0)
5343 case ALXVDSX:
5344 return OPVXX1(31, 332, 0)
5345 case ALXSDX:
5346 return OPVXX1(31, 588, 0)
5347 case ALXSIWAX:
5348 return OPVXX1(31, 76, 0)
5349 case ALXSIWZX:
5350 return OPVXX1(31, 12, 0)
5351 }
5352
5353 c.ctxt.Diag("bad loadx opcode %v", a)
5354 return 0
5355 }
5356
5357
5360 func (c *ctxt9) opstore(a obj.As) uint32 {
5361 switch a {
5362 case AMOVB, AMOVBZ:
5363 return OPVCC(38, 0, 0, 0)
5364
5365 case AMOVBU, AMOVBZU:
5366 return OPVCC(39, 0, 0, 0)
5367 case AFMOVD:
5368 return OPVCC(54, 0, 0, 0)
5369 case AFMOVDU:
5370 return OPVCC(55, 0, 0, 0)
5371 case AFMOVS:
5372 return OPVCC(52, 0, 0, 0)
5373 case AFMOVSU:
5374 return OPVCC(53, 0, 0, 0)
5375
5376 case AMOVHZ, AMOVH:
5377 return OPVCC(44, 0, 0, 0)
5378
5379 case AMOVHZU, AMOVHU:
5380 return OPVCC(45, 0, 0, 0)
5381 case AMOVMW:
5382 return OPVCC(47, 0, 0, 0)
5383 case ASTSW:
5384 return OPVCC(31, 725, 0, 0)
5385
5386 case AMOVWZ, AMOVW:
5387 return OPVCC(36, 0, 0, 0)
5388
5389 case AMOVWZU, AMOVWU:
5390 return OPVCC(37, 0, 0, 0)
5391 case AMOVD:
5392 return OPVCC(62, 0, 0, 0)
5393 case AMOVDU:
5394 return OPVCC(62, 0, 0, 1)
5395 case ASTXV:
5396 return OPDQ(61, 5, 0)
5397 case ASTXVL:
5398 return OPVXX1(31, 397, 0)
5399 case ASTXVLL:
5400 return OPVXX1(31, 429, 0)
5401 case ASTXVX:
5402 return OPVXX1(31, 396, 0)
5403
5404 }
5405
5406 c.ctxt.Diag("unknown store opcode %v", a)
5407 return 0
5408 }
5409
5410
5413 func (c *ctxt9) opstorex(a obj.As) uint32 {
5414 switch a {
5415 case AMOVB, AMOVBZ:
5416 return OPVCC(31, 215, 0, 0)
5417
5418 case AMOVBU, AMOVBZU:
5419 return OPVCC(31, 247, 0, 0)
5420 case AFMOVD:
5421 return OPVCC(31, 727, 0, 0)
5422 case AFMOVDU:
5423 return OPVCC(31, 759, 0, 0)
5424 case AFMOVS:
5425 return OPVCC(31, 663, 0, 0)
5426 case AFMOVSU:
5427 return OPVCC(31, 695, 0, 0)
5428 case AFMOVSX:
5429 return OPVCC(31, 983, 0, 0)
5430
5431 case AMOVHZ, AMOVH:
5432 return OPVCC(31, 407, 0, 0)
5433 case AMOVHBR:
5434 return OPVCC(31, 918, 0, 0)
5435
5436 case AMOVHZU, AMOVHU:
5437 return OPVCC(31, 439, 0, 0)
5438
5439 case AMOVWZ, AMOVW:
5440 return OPVCC(31, 151, 0, 0)
5441
5442 case AMOVWZU, AMOVWU:
5443 return OPVCC(31, 183, 0, 0)
5444 case ASTSW:
5445 return OPVCC(31, 661, 0, 0)
5446 case AMOVWBR:
5447 return OPVCC(31, 662, 0, 0)
5448 case AMOVDBR:
5449 return OPVCC(31, 660, 0, 0)
5450 case ASTBCCC:
5451 return OPVCC(31, 694, 0, 1)
5452 case ASTHCCC:
5453 return OPVCC(31, 726, 0, 1)
5454 case ASTWCCC:
5455 return OPVCC(31, 150, 0, 1)
5456 case ASTDCCC:
5457 return OPVCC(31, 214, 0, 1)
5458 case AMOVD:
5459 return OPVCC(31, 149, 0, 0)
5460 case AMOVDU:
5461 return OPVCC(31, 181, 0, 0)
5462
5463
5464 case ASTVEBX:
5465 return OPVCC(31, 135, 0, 0)
5466 case ASTVEHX:
5467 return OPVCC(31, 167, 0, 0)
5468 case ASTVEWX:
5469 return OPVCC(31, 199, 0, 0)
5470 case ASTVX:
5471 return OPVCC(31, 231, 0, 0)
5472 case ASTVXL:
5473 return OPVCC(31, 487, 0, 0)
5474
5475
5476
5477 case ASTXVX:
5478 return OPVXX1(31, 396, 0)
5479 case ASTXVD2X:
5480 return OPVXX1(31, 972, 0)
5481 case ASTXVW4X:
5482 return OPVXX1(31, 908, 0)
5483 case ASTXVH8X:
5484 return OPVXX1(31, 940, 0)
5485 case ASTXVB16X:
5486 return OPVXX1(31, 1004, 0)
5487
5488 case ASTXSDX:
5489 return OPVXX1(31, 716, 0)
5490
5491 case ASTXSIWX:
5492 return OPVXX1(31, 140, 0)
5493
5494
5495
5496 }
5497
5498 c.ctxt.Diag("unknown storex opcode %v", a)
5499 return 0
5500 }
5501
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