Source file src/cmd/internal/obj/riscv/cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  var CSRs map[uint16]string = csrs
    39  
    40  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    41  
    42  const (
    43  	// Base register numberings.
    44  	REG_X0 = obj.RBaseRISCV + iota
    45  	REG_X1
    46  	REG_X2
    47  	REG_X3
    48  	REG_X4
    49  	REG_X5
    50  	REG_X6
    51  	REG_X7
    52  	REG_X8
    53  	REG_X9
    54  	REG_X10
    55  	REG_X11
    56  	REG_X12
    57  	REG_X13
    58  	REG_X14
    59  	REG_X15
    60  	REG_X16
    61  	REG_X17
    62  	REG_X18
    63  	REG_X19
    64  	REG_X20
    65  	REG_X21
    66  	REG_X22
    67  	REG_X23
    68  	REG_X24
    69  	REG_X25
    70  	REG_X26
    71  	REG_X27
    72  	REG_X28
    73  	REG_X29
    74  	REG_X30
    75  	REG_X31
    76  
    77  	// Floating Point register numberings.
    78  	REG_F0
    79  	REG_F1
    80  	REG_F2
    81  	REG_F3
    82  	REG_F4
    83  	REG_F5
    84  	REG_F6
    85  	REG_F7
    86  	REG_F8
    87  	REG_F9
    88  	REG_F10
    89  	REG_F11
    90  	REG_F12
    91  	REG_F13
    92  	REG_F14
    93  	REG_F15
    94  	REG_F16
    95  	REG_F17
    96  	REG_F18
    97  	REG_F19
    98  	REG_F20
    99  	REG_F21
   100  	REG_F22
   101  	REG_F23
   102  	REG_F24
   103  	REG_F25
   104  	REG_F26
   105  	REG_F27
   106  	REG_F28
   107  	REG_F29
   108  	REG_F30
   109  	REG_F31
   110  
   111  	// Vector register numberings.
   112  	REG_V0
   113  	REG_V1
   114  	REG_V2
   115  	REG_V3
   116  	REG_V4
   117  	REG_V5
   118  	REG_V6
   119  	REG_V7
   120  	REG_V8
   121  	REG_V9
   122  	REG_V10
   123  	REG_V11
   124  	REG_V12
   125  	REG_V13
   126  	REG_V14
   127  	REG_V15
   128  	REG_V16
   129  	REG_V17
   130  	REG_V18
   131  	REG_V19
   132  	REG_V20
   133  	REG_V21
   134  	REG_V22
   135  	REG_V23
   136  	REG_V24
   137  	REG_V25
   138  	REG_V26
   139  	REG_V27
   140  	REG_V28
   141  	REG_V29
   142  	REG_V30
   143  	REG_V31
   144  
   145  	// This marks the end of the register numbering.
   146  	REG_END
   147  
   148  	// General registers reassigned to ABI names.
   149  	REG_ZERO = REG_X0
   150  	REG_RA   = REG_X1 // aka REG_LR
   151  	REG_SP   = REG_X2
   152  	REG_GP   = REG_X3 // aka REG_SB
   153  	REG_TP   = REG_X4
   154  	REG_T0   = REG_X5
   155  	REG_T1   = REG_X6
   156  	REG_T2   = REG_X7
   157  	REG_S0   = REG_X8
   158  	REG_S1   = REG_X9
   159  	REG_A0   = REG_X10
   160  	REG_A1   = REG_X11
   161  	REG_A2   = REG_X12
   162  	REG_A3   = REG_X13
   163  	REG_A4   = REG_X14
   164  	REG_A5   = REG_X15
   165  	REG_A6   = REG_X16
   166  	REG_A7   = REG_X17
   167  	REG_S2   = REG_X18
   168  	REG_S3   = REG_X19
   169  	REG_S4   = REG_X20
   170  	REG_S5   = REG_X21
   171  	REG_S6   = REG_X22
   172  	REG_S7   = REG_X23
   173  	REG_S8   = REG_X24
   174  	REG_S9   = REG_X25
   175  	REG_S10  = REG_X26 // aka REG_CTXT
   176  	REG_S11  = REG_X27 // aka REG_G
   177  	REG_T3   = REG_X28
   178  	REG_T4   = REG_X29
   179  	REG_T5   = REG_X30
   180  	REG_T6   = REG_X31 // aka REG_TMP
   181  
   182  	// Go runtime register names.
   183  	REG_CTXT = REG_S10 // Context for closures.
   184  	REG_G    = REG_S11 // G pointer.
   185  	REG_LR   = REG_RA  // Link register.
   186  	REG_TMP  = REG_T6  // Reserved for assembler use.
   187  
   188  	// ABI names for floating point registers.
   189  	REG_FT0  = REG_F0
   190  	REG_FT1  = REG_F1
   191  	REG_FT2  = REG_F2
   192  	REG_FT3  = REG_F3
   193  	REG_FT4  = REG_F4
   194  	REG_FT5  = REG_F5
   195  	REG_FT6  = REG_F6
   196  	REG_FT7  = REG_F7
   197  	REG_FS0  = REG_F8
   198  	REG_FS1  = REG_F9
   199  	REG_FA0  = REG_F10
   200  	REG_FA1  = REG_F11
   201  	REG_FA2  = REG_F12
   202  	REG_FA3  = REG_F13
   203  	REG_FA4  = REG_F14
   204  	REG_FA5  = REG_F15
   205  	REG_FA6  = REG_F16
   206  	REG_FA7  = REG_F17
   207  	REG_FS2  = REG_F18
   208  	REG_FS3  = REG_F19
   209  	REG_FS4  = REG_F20
   210  	REG_FS5  = REG_F21
   211  	REG_FS6  = REG_F22
   212  	REG_FS7  = REG_F23
   213  	REG_FS8  = REG_F24
   214  	REG_FS9  = REG_F25
   215  	REG_FS10 = REG_F26
   216  	REG_FS11 = REG_F27
   217  	REG_FT8  = REG_F28
   218  	REG_FT9  = REG_F29
   219  	REG_FT10 = REG_F30
   220  	REG_FT11 = REG_F31
   221  
   222  	// Names generated by the SSA compiler.
   223  	REGSP = REG_SP
   224  	REGG  = REG_G
   225  )
   226  
   227  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   228  var RISCV64DWARFRegisters = map[int16]int16{
   229  	// Integer Registers.
   230  	REG_X0:  0,
   231  	REG_X1:  1,
   232  	REG_X2:  2,
   233  	REG_X3:  3,
   234  	REG_X4:  4,
   235  	REG_X5:  5,
   236  	REG_X6:  6,
   237  	REG_X7:  7,
   238  	REG_X8:  8,
   239  	REG_X9:  9,
   240  	REG_X10: 10,
   241  	REG_X11: 11,
   242  	REG_X12: 12,
   243  	REG_X13: 13,
   244  	REG_X14: 14,
   245  	REG_X15: 15,
   246  	REG_X16: 16,
   247  	REG_X17: 17,
   248  	REG_X18: 18,
   249  	REG_X19: 19,
   250  	REG_X20: 20,
   251  	REG_X21: 21,
   252  	REG_X22: 22,
   253  	REG_X23: 23,
   254  	REG_X24: 24,
   255  	REG_X25: 25,
   256  	REG_X26: 26,
   257  	REG_X27: 27,
   258  	REG_X28: 28,
   259  	REG_X29: 29,
   260  	REG_X30: 30,
   261  	REG_X31: 31,
   262  
   263  	// Floating-Point Registers.
   264  	REG_F0:  32,
   265  	REG_F1:  33,
   266  	REG_F2:  34,
   267  	REG_F3:  35,
   268  	REG_F4:  36,
   269  	REG_F5:  37,
   270  	REG_F6:  38,
   271  	REG_F7:  39,
   272  	REG_F8:  40,
   273  	REG_F9:  41,
   274  	REG_F10: 42,
   275  	REG_F11: 43,
   276  	REG_F12: 44,
   277  	REG_F13: 45,
   278  	REG_F14: 46,
   279  	REG_F15: 47,
   280  	REG_F16: 48,
   281  	REG_F17: 49,
   282  	REG_F18: 50,
   283  	REG_F19: 51,
   284  	REG_F20: 52,
   285  	REG_F21: 53,
   286  	REG_F22: 54,
   287  	REG_F23: 55,
   288  	REG_F24: 56,
   289  	REG_F25: 57,
   290  	REG_F26: 58,
   291  	REG_F27: 59,
   292  	REG_F28: 60,
   293  	REG_F29: 61,
   294  	REG_F30: 62,
   295  	REG_F31: 63,
   296  }
   297  
   298  // Prog.Mark flags.
   299  const (
   300  	// USES_REG_TMP indicates that a machine instruction generated from the
   301  	// corresponding *obj.Prog uses the temporary register.
   302  	USES_REG_TMP = 1 << iota
   303  
   304  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   305  	// R_RISCV_JAL relocation is needed.
   306  	NEED_JAL_RELOC
   307  
   308  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   309  	// is the first instruction in an AUIPC + JAL pair that needs a
   310  	// R_RISCV_CALL relocation.
   311  	NEED_CALL_RELOC
   312  
   313  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   314  	// it is the first instruction in an AUIPC + I-type pair that needs a
   315  	// R_RISCV_PCREL_ITYPE relocation.
   316  	NEED_PCREL_ITYPE_RELOC
   317  
   318  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   319  	// it is the first instruction in an AUIPC + S-type pair that needs a
   320  	// R_RISCV_PCREL_STYPE relocation.
   321  	NEED_PCREL_STYPE_RELOC
   322  
   323  	// NEED_GOT_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   324  	// it is the first instruction in an AUIPC + I-type pair that needs a
   325  	// R_RISCV_GOT_PCREL_ITYPE relocation.
   326  	NEED_GOT_PCREL_ITYPE_RELOC
   327  )
   328  
   329  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   330  // at https://github.com/riscv/riscv-opcodes.
   331  //
   332  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   333  //
   334  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
   335  //
   336  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   337  const (
   338  	//
   339  	// Unprivileged ISA (version 20240411)
   340  	//
   341  
   342  	// 2.4: Integer Computational Instructions
   343  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   344  	ASLTI
   345  	ASLTIU
   346  	AANDI
   347  	AORI
   348  	AXORI
   349  	ASLLI
   350  	ASRLI
   351  	ASRAI
   352  	ALUI
   353  	AAUIPC
   354  	AADD
   355  	ASLT
   356  	ASLTU
   357  	AAND
   358  	AOR
   359  	AXOR
   360  	ASLL
   361  	ASRL
   362  	ASUB
   363  	ASRA
   364  
   365  	// 2.5: Control Transfer Instructions
   366  	AJAL
   367  	AJALR
   368  	ABEQ
   369  	ABNE
   370  	ABLT
   371  	ABLTU
   372  	ABGE
   373  	ABGEU
   374  
   375  	// 2.6: Load and Store Instructions
   376  	ALW
   377  	ALWU
   378  	ALH
   379  	ALHU
   380  	ALB
   381  	ALBU
   382  	ASW
   383  	ASH
   384  	ASB
   385  
   386  	// 2.7: Memory Ordering Instructions
   387  	AFENCE
   388  
   389  	// 4.2: Integer Computational Instructions (RV64I)
   390  	AADDIW
   391  	ASLLIW
   392  	ASRLIW
   393  	ASRAIW
   394  	AADDW
   395  	ASLLW
   396  	ASRLW
   397  	ASUBW
   398  	ASRAW
   399  
   400  	// 4.3: Load and Store Instructions (RV64I)
   401  	ALD
   402  	ASD
   403  
   404  	// 7.1: CSR Instructions (Zicsr)
   405  	ACSRRW
   406  	ACSRRS
   407  	ACSRRC
   408  	ACSRRWI
   409  	ACSRRSI
   410  	ACSRRCI
   411  
   412  	// 13.1: Multiplication Operations
   413  	AMUL
   414  	AMULH
   415  	AMULHU
   416  	AMULHSU
   417  	AMULW
   418  
   419  	// 13.2: Division Operations
   420  	ADIV
   421  	ADIVU
   422  	AREM
   423  	AREMU
   424  	ADIVW
   425  	ADIVUW
   426  	AREMW
   427  	AREMUW
   428  
   429  	// 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
   430  	ALRD
   431  	ASCD
   432  	ALRW
   433  	ASCW
   434  
   435  	// 14.4: Atomic Memory Operations (Zaamo)
   436  	AAMOSWAPD
   437  	AAMOADDD
   438  	AAMOANDD
   439  	AAMOORD
   440  	AAMOXORD
   441  	AAMOMAXD
   442  	AAMOMAXUD
   443  	AAMOMIND
   444  	AAMOMINUD
   445  	AAMOSWAPW
   446  	AAMOADDW
   447  	AAMOANDW
   448  	AAMOORW
   449  	AAMOXORW
   450  	AAMOMAXW
   451  	AAMOMAXUW
   452  	AAMOMINW
   453  	AAMOMINUW
   454  
   455  	// 20.5: Single-Precision Load and Store Instructions
   456  	AFLW
   457  	AFSW
   458  
   459  	// 20.6: Single-Precision Floating-Point Computational Instructions
   460  	AFADDS
   461  	AFSUBS
   462  	AFMULS
   463  	AFDIVS
   464  	AFMINS
   465  	AFMAXS
   466  	AFSQRTS
   467  	AFMADDS
   468  	AFMSUBS
   469  	AFNMADDS
   470  	AFNMSUBS
   471  
   472  	// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
   473  	AFCVTWS
   474  	AFCVTLS
   475  	AFCVTSW
   476  	AFCVTSL
   477  	AFCVTWUS
   478  	AFCVTLUS
   479  	AFCVTSWU
   480  	AFCVTSLU
   481  	AFSGNJS
   482  	AFSGNJNS
   483  	AFSGNJXS
   484  	AFMVXS
   485  	AFMVSX
   486  	AFMVXW
   487  	AFMVWX
   488  
   489  	// 20.8: Single-Precision Floating-Point Compare Instructions
   490  	AFEQS
   491  	AFLTS
   492  	AFLES
   493  
   494  	// 20.9: Single-Precision Floating-Point Classify Instruction
   495  	AFCLASSS
   496  
   497  	// 21.3: Double-Precision Load and Store Instructions
   498  	AFLD
   499  	AFSD
   500  
   501  	// 21.4: Double-Precision Floating-Point Computational Instructions
   502  	AFADDD
   503  	AFSUBD
   504  	AFMULD
   505  	AFDIVD
   506  	AFMIND
   507  	AFMAXD
   508  	AFSQRTD
   509  	AFMADDD
   510  	AFMSUBD
   511  	AFNMADDD
   512  	AFNMSUBD
   513  
   514  	// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
   515  	AFCVTWD
   516  	AFCVTLD
   517  	AFCVTDW
   518  	AFCVTDL
   519  	AFCVTWUD
   520  	AFCVTLUD
   521  	AFCVTDWU
   522  	AFCVTDLU
   523  	AFCVTSD
   524  	AFCVTDS
   525  	AFSGNJD
   526  	AFSGNJND
   527  	AFSGNJXD
   528  	AFMVXD
   529  	AFMVDX
   530  
   531  	// 21.6: Double-Precision Floating-Point Compare Instructions
   532  	AFEQD
   533  	AFLTD
   534  	AFLED
   535  
   536  	// 21.7: Double-Precision Floating-Point Classify Instruction
   537  	AFCLASSD
   538  
   539  	// 22.1 Quad-Precision Load and Store Instructions
   540  	AFLQ
   541  	AFSQ
   542  
   543  	// 22.2: Quad-Precision Computational Instructions
   544  	AFADDQ
   545  	AFSUBQ
   546  	AFMULQ
   547  	AFDIVQ
   548  	AFMINQ
   549  	AFMAXQ
   550  	AFSQRTQ
   551  	AFMADDQ
   552  	AFMSUBQ
   553  	AFNMADDQ
   554  	AFNMSUBQ
   555  
   556  	// 22.3: Quad-Precision Convert and Move Instructions
   557  	AFCVTWQ
   558  	AFCVTLQ
   559  	AFCVTSQ
   560  	AFCVTDQ
   561  	AFCVTQW
   562  	AFCVTQL
   563  	AFCVTQS
   564  	AFCVTQD
   565  	AFCVTWUQ
   566  	AFCVTLUQ
   567  	AFCVTQWU
   568  	AFCVTQLU
   569  	AFSGNJQ
   570  	AFSGNJNQ
   571  	AFSGNJXQ
   572  
   573  	// 22.4: Quad-Precision Floating-Point Compare Instructions
   574  	AFEQQ
   575  	AFLEQ
   576  	AFLTQ
   577  
   578  	// 22.5: Quad-Precision Floating-Point Classify Instruction
   579  	AFCLASSQ
   580  
   581  	//
   582  	// "C" Extension for Compressed Instructions
   583  	//
   584  
   585  	// 26.3.1: Compressed Stack-Pointer-Based Loads and Stores
   586  	ACLWSP
   587  	ACFLWSP
   588  	ACLDSP
   589  	ACFLDSP
   590  	ACSWSP
   591  	ACSDSP
   592  	ACFSWSP
   593  	ACFSDSP
   594  
   595  	// 26.3.2: Compressed Register-Based Loads and Stores
   596  	ACLW
   597  	ACLD
   598  	ACFLW
   599  	ACFLD
   600  	ACSW
   601  	ACSD
   602  	ACFSW
   603  	ACFSD
   604  
   605  	// 26.4: Compressed Control Transfer Instructions
   606  	ACJ
   607  	ACJR
   608  	ACJALR
   609  	ACBEQZ
   610  	ACBNEZ
   611  
   612  	// 26.5.1: Compressed Integer Constant-Generation Instructions
   613  	ACLI
   614  	ACLUI
   615  	ACADDI
   616  	ACADDIW
   617  	ACADDI16SP
   618  	ACADDI4SPN
   619  	ACSLLI
   620  	ACSRLI
   621  	ACSRAI
   622  	ACANDI
   623  
   624  	// 26.5.3: Compressed Integer Register-Register Operations
   625  	ACMV
   626  	ACADD
   627  	ACAND
   628  	ACOR
   629  	ACXOR
   630  	ACSUB
   631  	ACADDW
   632  	ACSUBW
   633  
   634  	// 26.5.5: Compressed NOP Instruction
   635  	ACNOP
   636  
   637  	// 26.5.6: Compressed Breakpoint Instruction
   638  	ACEBREAK
   639  
   640  	//
   641  	// "B" Extension for Bit Manipulation, Version 1.0.0
   642  	//
   643  
   644  	// 28.4.1: Address Generation Instructions (Zba)
   645  	AADDUW
   646  	ASH1ADD
   647  	ASH1ADDUW
   648  	ASH2ADD
   649  	ASH2ADDUW
   650  	ASH3ADD
   651  	ASH3ADDUW
   652  	ASLLIUW
   653  
   654  	// 28.4.2: Basic Bit Manipulation (Zbb)
   655  	AANDN
   656  	AORN
   657  	AXNOR
   658  	ACLZ
   659  	ACLZW
   660  	ACTZ
   661  	ACTZW
   662  	ACPOP
   663  	ACPOPW
   664  	AMAX
   665  	AMAXU
   666  	AMIN
   667  	AMINU
   668  	ASEXTB
   669  	ASEXTH
   670  	AZEXTH
   671  
   672  	// 28.4.3: Bitwise Rotation (Zbb)
   673  	AROL
   674  	AROLW
   675  	AROR
   676  	ARORI
   677  	ARORIW
   678  	ARORW
   679  	AORCB
   680  	AREV8
   681  
   682  	// 28.4.4: Single-bit Instructions (Zbs)
   683  	ABCLR
   684  	ABCLRI
   685  	ABEXT
   686  	ABEXTI
   687  	ABINV
   688  	ABINVI
   689  	ABSET
   690  	ABSETI
   691  
   692  	//
   693  	// "V" Standard Extension for Vector Operations, Version 1.0
   694  	//
   695  
   696  	// 31.6: Configuration-Setting Instructions
   697  	AVSETVLI
   698  	AVSETIVLI
   699  	AVSETVL
   700  
   701  	// 31.7.4: Vector Unit-Stride Instructions
   702  	AVLE8V
   703  	AVLE16V
   704  	AVLE32V
   705  	AVLE64V
   706  	AVSE8V
   707  	AVSE16V
   708  	AVSE32V
   709  	AVSE64V
   710  	AVLMV
   711  	AVSMV
   712  
   713  	// 31.7.5: Vector Strided Instructions
   714  	AVLSE8V
   715  	AVLSE16V
   716  	AVLSE32V
   717  	AVLSE64V
   718  	AVSSE8V
   719  	AVSSE16V
   720  	AVSSE32V
   721  	AVSSE64V
   722  
   723  	// 31.7.6: Vector Indexed Instructions
   724  	AVLUXEI8V
   725  	AVLUXEI16V
   726  	AVLUXEI32V
   727  	AVLUXEI64V
   728  	AVLOXEI8V
   729  	AVLOXEI16V
   730  	AVLOXEI32V
   731  	AVLOXEI64V
   732  	AVSUXEI8V
   733  	AVSUXEI16V
   734  	AVSUXEI32V
   735  	AVSUXEI64V
   736  	AVSOXEI8V
   737  	AVSOXEI16V
   738  	AVSOXEI32V
   739  	AVSOXEI64V
   740  
   741  	// 31.7.7: Unit-stride Fault-Only-First Loads
   742  	AVLE8FFV
   743  	AVLE16FFV
   744  	AVLE32FFV
   745  	AVLE64FFV
   746  
   747  	// 31.7.9: Vector Load/Store Whole Register Instructions
   748  	AVL1RE8V
   749  	AVL1RE16V
   750  	AVL1RE32V
   751  	AVL1RE64V
   752  	AVL2RE8V
   753  	AVL2RE16V
   754  	AVL2RE32V
   755  	AVL2RE64V
   756  	AVL4RE8V
   757  	AVL4RE16V
   758  	AVL4RE32V
   759  	AVL4RE64V
   760  	AVL8RE8V
   761  	AVL8RE16V
   762  	AVL8RE32V
   763  	AVL8RE64V
   764  	AVS1RV
   765  	AVS2RV
   766  	AVS4RV
   767  	AVS8RV
   768  
   769  	// 31.11.1: Vector Single-Width Integer Add and Subtract
   770  	AVADDVV
   771  	AVADDVX
   772  	AVADDVI
   773  	AVSUBVV
   774  	AVSUBVX
   775  	AVRSUBVX
   776  	AVRSUBVI
   777  
   778  	// 31.11.2: Vector Widening Integer Add/Subtract
   779  	AVWADDUVV
   780  	AVWADDUVX
   781  	AVWSUBUVV
   782  	AVWSUBUVX
   783  	AVWADDVV
   784  	AVWADDVX
   785  	AVWSUBVV
   786  	AVWSUBVX
   787  	AVWADDUWV
   788  	AVWADDUWX
   789  	AVWSUBUWV
   790  	AVWSUBUWX
   791  	AVWADDWV
   792  	AVWADDWX
   793  	AVWSUBWV
   794  	AVWSUBWX
   795  
   796  	// 31.11.3: Vector Integer Extension
   797  	AVZEXTVF2
   798  	AVSEXTVF2
   799  	AVZEXTVF4
   800  	AVSEXTVF4
   801  	AVZEXTVF8
   802  	AVSEXTVF8
   803  
   804  	// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
   805  	AVADCVVM
   806  	AVADCVXM
   807  	AVADCVIM
   808  	AVMADCVVM
   809  	AVMADCVXM
   810  	AVMADCVIM
   811  	AVMADCVV
   812  	AVMADCVX
   813  	AVMADCVI
   814  	AVSBCVVM
   815  	AVSBCVXM
   816  	AVMSBCVVM
   817  	AVMSBCVXM
   818  	AVMSBCVV
   819  	AVMSBCVX
   820  
   821  	// 31.11.5: Vector Bitwise Logical Instructions
   822  	AVANDVV
   823  	AVANDVX
   824  	AVANDVI
   825  	AVORVV
   826  	AVORVX
   827  	AVORVI
   828  	AVXORVV
   829  	AVXORVX
   830  	AVXORVI
   831  
   832  	// 31.11.6: Vector Single-Width Shift Instructions
   833  	AVSLLVV
   834  	AVSLLVX
   835  	AVSLLVI
   836  	AVSRLVV
   837  	AVSRLVX
   838  	AVSRLVI
   839  	AVSRAVV
   840  	AVSRAVX
   841  	AVSRAVI
   842  
   843  	// 31.11.7: Vector Narrowing Integer Right Shift Instructions
   844  	AVNSRLWV
   845  	AVNSRLWX
   846  	AVNSRLWI
   847  	AVNSRAWV
   848  	AVNSRAWX
   849  	AVNSRAWI
   850  
   851  	// 31.11.8: Vector Integer Compare Instructions
   852  	AVMSEQVV
   853  	AVMSEQVX
   854  	AVMSEQVI
   855  	AVMSNEVV
   856  	AVMSNEVX
   857  	AVMSNEVI
   858  	AVMSLTUVV
   859  	AVMSLTUVX
   860  	AVMSLTVV
   861  	AVMSLTVX
   862  	AVMSLEUVV
   863  	AVMSLEUVX
   864  	AVMSLEUVI
   865  	AVMSLEVV
   866  	AVMSLEVX
   867  	AVMSLEVI
   868  	AVMSGTUVX
   869  	AVMSGTUVI
   870  	AVMSGTVX
   871  	AVMSGTVI
   872  
   873  	// 31.11.9: Vector Integer Min/Max Instructions
   874  	AVMINUVV
   875  	AVMINUVX
   876  	AVMINVV
   877  	AVMINVX
   878  	AVMAXUVV
   879  	AVMAXUVX
   880  	AVMAXVV
   881  	AVMAXVX
   882  
   883  	// 31.11.10: Vector Single-Width Integer Multiply Instructions
   884  	AVMULVV
   885  	AVMULVX
   886  	AVMULHVV
   887  	AVMULHVX
   888  	AVMULHUVV
   889  	AVMULHUVX
   890  	AVMULHSUVV
   891  	AVMULHSUVX
   892  
   893  	// 31.11.11: Vector Integer Divide Instructions
   894  	AVDIVUVV
   895  	AVDIVUVX
   896  	AVDIVVV
   897  	AVDIVVX
   898  	AVREMUVV
   899  	AVREMUVX
   900  	AVREMVV
   901  	AVREMVX
   902  
   903  	// 31.11.12: Vector Widening Integer Multiply Instructions
   904  	AVWMULVV
   905  	AVWMULVX
   906  	AVWMULUVV
   907  	AVWMULUVX
   908  	AVWMULSUVV
   909  	AVWMULSUVX
   910  
   911  	// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
   912  	AVMACCVV
   913  	AVMACCVX
   914  	AVNMSACVV
   915  	AVNMSACVX
   916  	AVMADDVV
   917  	AVMADDVX
   918  	AVNMSUBVV
   919  	AVNMSUBVX
   920  
   921  	// 31.11.14: Vector Widening Integer Multiply-Add Instructions
   922  	AVWMACCUVV
   923  	AVWMACCUVX
   924  	AVWMACCVV
   925  	AVWMACCVX
   926  	AVWMACCSUVV
   927  	AVWMACCSUVX
   928  	AVWMACCUSVX
   929  
   930  	// 31.11.15: Vector Integer Merge Instructions
   931  	AVMERGEVVM
   932  	AVMERGEVXM
   933  	AVMERGEVIM
   934  
   935  	// 31.11.16: Vector Integer Move Instructions
   936  	AVMVVV
   937  	AVMVVX
   938  	AVMVVI
   939  
   940  	// 31.12.1: Vector Single-Width Saturating Add and Subtract
   941  	AVSADDUVV
   942  	AVSADDUVX
   943  	AVSADDUVI
   944  	AVSADDVV
   945  	AVSADDVX
   946  	AVSADDVI
   947  	AVSSUBUVV
   948  	AVSSUBUVX
   949  	AVSSUBVV
   950  	AVSSUBVX
   951  
   952  	// 31.12.2: Vector Single-Width Averaging Add and Subtract
   953  	AVAADDUVV
   954  	AVAADDUVX
   955  	AVAADDVV
   956  	AVAADDVX
   957  	AVASUBUVV
   958  	AVASUBUVX
   959  	AVASUBVV
   960  	AVASUBVX
   961  
   962  	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
   963  	AVSMULVV
   964  	AVSMULVX
   965  
   966  	// 31.12.4: Vector Single-Width Scaling Shift Instructions
   967  	AVSSRLVV
   968  	AVSSRLVX
   969  	AVSSRLVI
   970  	AVSSRAVV
   971  	AVSSRAVX
   972  	AVSSRAVI
   973  
   974  	// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
   975  	AVNCLIPUWV
   976  	AVNCLIPUWX
   977  	AVNCLIPUWI
   978  	AVNCLIPWV
   979  	AVNCLIPWX
   980  	AVNCLIPWI
   981  
   982  	// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
   983  	AVFADDVV
   984  	AVFADDVF
   985  	AVFSUBVV
   986  	AVFSUBVF
   987  	AVFRSUBVF
   988  
   989  	// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
   990  	AVFWADDVV
   991  	AVFWADDVF
   992  	AVFWSUBVV
   993  	AVFWSUBVF
   994  	AVFWADDWV
   995  	AVFWADDWF
   996  	AVFWSUBWV
   997  	AVFWSUBWF
   998  
   999  	// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
  1000  	AVFMULVV
  1001  	AVFMULVF
  1002  	AVFDIVVV
  1003  	AVFDIVVF
  1004  	AVFRDIVVF
  1005  
  1006  	// 31.13.5: Vector Widening Floating-Point Multiply
  1007  	AVFWMULVV
  1008  	AVFWMULVF
  1009  
  1010  	// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
  1011  	AVFMACCVV
  1012  	AVFMACCVF
  1013  	AVFNMACCVV
  1014  	AVFNMACCVF
  1015  	AVFMSACVV
  1016  	AVFMSACVF
  1017  	AVFNMSACVV
  1018  	AVFNMSACVF
  1019  	AVFMADDVV
  1020  	AVFMADDVF
  1021  	AVFNMADDVV
  1022  	AVFNMADDVF
  1023  	AVFMSUBVV
  1024  	AVFMSUBVF
  1025  	AVFNMSUBVV
  1026  	AVFNMSUBVF
  1027  
  1028  	// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
  1029  	AVFWMACCVV
  1030  	AVFWMACCVF
  1031  	AVFWNMACCVV
  1032  	AVFWNMACCVF
  1033  	AVFWMSACVV
  1034  	AVFWMSACVF
  1035  	AVFWNMSACVV
  1036  	AVFWNMSACVF
  1037  
  1038  	// 31.13.8: Vector Floating-Point Square-Root Instruction
  1039  	AVFSQRTV
  1040  
  1041  	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
  1042  	AVFRSQRT7V
  1043  
  1044  	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
  1045  	AVFREC7V
  1046  
  1047  	// 31.13.11: Vector Floating-Point MIN/MAX Instructions
  1048  	AVFMINVV
  1049  	AVFMINVF
  1050  	AVFMAXVV
  1051  	AVFMAXVF
  1052  
  1053  	// 31.13.12: Vector Floating-Point Sign-Injection Instructions
  1054  	AVFSGNJVV
  1055  	AVFSGNJVF
  1056  	AVFSGNJNVV
  1057  	AVFSGNJNVF
  1058  	AVFSGNJXVV
  1059  	AVFSGNJXVF
  1060  
  1061  	// 31.13.13: Vector Floating-Point Compare Instructions
  1062  	AVMFEQVV
  1063  	AVMFEQVF
  1064  	AVMFNEVV
  1065  	AVMFNEVF
  1066  	AVMFLTVV
  1067  	AVMFLTVF
  1068  	AVMFLEVV
  1069  	AVMFLEVF
  1070  	AVMFGTVF
  1071  	AVMFGEVF
  1072  
  1073  	// 31.13.14: Vector Floating-Point Classify Instruction
  1074  	AVFCLASSV
  1075  
  1076  	// 31.13.15: Vector Floating-Point Merge Instruction
  1077  	AVFMERGEVFM
  1078  
  1079  	// 31.13.16: Vector Floating-Point Move Instruction
  1080  	AVFMVVF
  1081  
  1082  	// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
  1083  	AVFCVTXUFV
  1084  	AVFCVTXFV
  1085  	AVFCVTRTZXUFV
  1086  	AVFCVTRTZXFV
  1087  	AVFCVTFXUV
  1088  	AVFCVTFXV
  1089  
  1090  	// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
  1091  	AVFWCVTXUFV
  1092  	AVFWCVTXFV
  1093  	AVFWCVTRTZXUFV
  1094  	AVFWCVTRTZXFV
  1095  	AVFWCVTFXUV
  1096  	AVFWCVTFXV
  1097  	AVFWCVTFFV
  1098  
  1099  	// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
  1100  	AVFNCVTXUFW
  1101  	AVFNCVTXFW
  1102  	AVFNCVTRTZXUFW
  1103  	AVFNCVTRTZXFW
  1104  	AVFNCVTFXUW
  1105  	AVFNCVTFXW
  1106  	AVFNCVTFFW
  1107  	AVFNCVTRODFFW
  1108  
  1109  	// 31.14.1: Vector Single-Width Integer Reduction Instructions
  1110  	AVREDSUMVS
  1111  	AVREDMAXUVS
  1112  	AVREDMAXVS
  1113  	AVREDMINUVS
  1114  	AVREDMINVS
  1115  	AVREDANDVS
  1116  	AVREDORVS
  1117  	AVREDXORVS
  1118  
  1119  	// 31.14.2: Vector Widening Integer Reduction Instructions
  1120  	AVWREDSUMUVS
  1121  	AVWREDSUMVS
  1122  
  1123  	// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
  1124  	AVFREDOSUMVS
  1125  	AVFREDUSUMVS
  1126  	AVFREDMAXVS
  1127  	AVFREDMINVS
  1128  
  1129  	// 31.14.4: Vector Widening Floating-Point Reduction Instructions
  1130  	AVFWREDOSUMVS
  1131  	AVFWREDUSUMVS
  1132  
  1133  	// 31.15: Vector Mask Instructions
  1134  	AVMANDMM
  1135  	AVMNANDMM
  1136  	AVMANDNMM
  1137  	AVMXORMM
  1138  	AVMORMM
  1139  	AVMNORMM
  1140  	AVMORNMM
  1141  	AVMXNORMM
  1142  	AVCPOPM
  1143  	AVFIRSTM
  1144  	AVMSBFM
  1145  	AVMSIFM
  1146  	AVMSOFM
  1147  	AVIOTAM
  1148  	AVIDV
  1149  
  1150  	// 31.16.1: Integer Scalar Move Instructions
  1151  	AVMVXS
  1152  	AVMVSX
  1153  
  1154  	// 31.16.2: Floating-Point Scalar Move Instructions
  1155  	AVFMVFS
  1156  	AVFMVSF
  1157  
  1158  	// 31.16.3: Vector Slide Instructions
  1159  	AVSLIDEUPVX
  1160  	AVSLIDEUPVI
  1161  	AVSLIDEDOWNVX
  1162  	AVSLIDEDOWNVI
  1163  	AVSLIDE1UPVX
  1164  	AVFSLIDE1UPVF
  1165  	AVSLIDE1DOWNVX
  1166  	AVFSLIDE1DOWNVF
  1167  
  1168  	// 31.16.4: Vector Register Gather Instructions
  1169  	AVRGATHERVV
  1170  	AVRGATHEREI16VV
  1171  	AVRGATHERVX
  1172  	AVRGATHERVI
  1173  
  1174  	// 31.16.5: Vector Compress Instruction
  1175  	AVCOMPRESSVM
  1176  
  1177  	// 31.16.6: Whole Vector Register Move
  1178  	AVMV1RV
  1179  	AVMV2RV
  1180  	AVMV4RV
  1181  	AVMV8RV
  1182  
  1183  	//
  1184  	// Privileged ISA (version 20240411)
  1185  	//
  1186  
  1187  	// 3.3.1: Environment Call and Breakpoint
  1188  	AECALL
  1189  	ASCALL
  1190  	AEBREAK
  1191  	ASBREAK
  1192  
  1193  	// 3.3.2: Trap-Return Instructions
  1194  	AMRET
  1195  	ASRET
  1196  	ADRET
  1197  
  1198  	// 3.3.3: Wait for Interrupt
  1199  	AWFI
  1200  
  1201  	// 10.2: Supervisor Memory-Management Fence Instruction
  1202  	ASFENCEVMA
  1203  
  1204  	// The escape hatch. Inserts a single 32-bit word.
  1205  	AWORD
  1206  
  1207  	// Pseudo-instructions.  These get translated by the assembler into other
  1208  	// instructions, based on their operands.
  1209  	ABEQZ
  1210  	ABGEZ
  1211  	ABGT
  1212  	ABGTU
  1213  	ABGTZ
  1214  	ABLE
  1215  	ABLEU
  1216  	ABLEZ
  1217  	ABLTZ
  1218  	ABNEZ
  1219  	AFABSD
  1220  	AFABSS
  1221  	AFNED
  1222  	AFNEGD
  1223  	AFNEGS
  1224  	AFNES
  1225  	AMOV
  1226  	AMOVB
  1227  	AMOVBU
  1228  	AMOVD
  1229  	AMOVF
  1230  	AMOVH
  1231  	AMOVHU
  1232  	AMOVW
  1233  	AMOVWU
  1234  	ANEG
  1235  	ANEGW
  1236  	ANOT
  1237  	ARDCYCLE
  1238  	ARDINSTRET
  1239  	ARDTIME
  1240  	ASEQZ
  1241  	ASNEZ
  1242  	AVFABSV
  1243  	AVFNEGV
  1244  	AVL1RV
  1245  	AVL2RV
  1246  	AVL4RV
  1247  	AVL8RV
  1248  	AVMCLRM
  1249  	AVMFGEVV
  1250  	AVMFGTVV
  1251  	AVMMVM
  1252  	AVMNOTM
  1253  	AVMSETM
  1254  	AVMSGEUVI
  1255  	AVMSGEUVV
  1256  	AVMSGEVI
  1257  	AVMSGEVV
  1258  	AVMSGTUVV
  1259  	AVMSGTVV
  1260  	AVMSLTUVI
  1261  	AVMSLTVI
  1262  	AVNCVTXXW
  1263  	AVNEGV
  1264  	AVNOTV
  1265  	AVWCVTUXXV
  1266  	AVWCVTXXV
  1267  
  1268  	// End marker
  1269  	ALAST
  1270  )
  1271  
  1272  // opSuffix encoding to uint8 which fit into p.Scond
  1273  var rmSuffixSet = map[string]uint8{
  1274  	"RNE": RM_RNE,
  1275  	"RTZ": RM_RTZ,
  1276  	"RDN": RM_RDN,
  1277  	"RUP": RM_RUP,
  1278  	"RMM": RM_RMM,
  1279  }
  1280  
  1281  const rmSuffixBit uint8 = 1 << 7
  1282  
  1283  func rmSuffixEncode(s string) (uint8, error) {
  1284  	if s == "" {
  1285  		return 0, errors.New("empty suffix")
  1286  	}
  1287  	enc, ok := rmSuffixSet[s]
  1288  	if !ok {
  1289  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
  1290  	}
  1291  	return enc | rmSuffixBit, nil
  1292  }
  1293  
  1294  func rmSuffixString(u uint8) (string, error) {
  1295  	if u&rmSuffixBit == 0 {
  1296  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
  1297  	}
  1298  
  1299  	u &^= rmSuffixBit
  1300  	for k, v := range rmSuffixSet {
  1301  		if v == u {
  1302  			return k, nil
  1303  		}
  1304  	}
  1305  	return "", fmt.Errorf("unknown suffix:%x", u)
  1306  }
  1307  
  1308  const (
  1309  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
  1310  	RM_RTZ              // Round towards Zero
  1311  	RM_RDN              // Round Down
  1312  	RM_RUP              // Round Up
  1313  	RM_RMM              // Round to Nearest, ties to Max Magnitude
  1314  )
  1315  
  1316  type SpecialOperand int
  1317  
  1318  const (
  1319  	SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase
  1320  	SPOP_RVV_BEGIN
  1321  
  1322  	// Vector mask policy.
  1323  	SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 2
  1324  	SPOP_MU
  1325  
  1326  	// Vector tail policy.
  1327  	SPOP_TA
  1328  	SPOP_TU
  1329  
  1330  	// Vector register group multiplier (VLMUL).
  1331  	SPOP_M1
  1332  	SPOP_M2
  1333  	SPOP_M4
  1334  	SPOP_M8
  1335  	SPOP_MF2
  1336  	SPOP_MF4
  1337  	SPOP_MF8
  1338  
  1339  	// Vector selected element width (VSEW).
  1340  	SPOP_E8
  1341  	SPOP_E16
  1342  	SPOP_E32
  1343  	SPOP_E64
  1344  	SPOP_RVV_END
  1345  
  1346  	// CSR names.  4096 special operands are reserved for RISC-V CSR names.
  1347  	SPOP_CSR_BEGIN = SPOP_RVV_END
  1348  	SPOP_CSR_END   = SPOP_CSR_BEGIN + 4096
  1349  
  1350  	SPOP_END = SPOP_CSR_END + 1
  1351  )
  1352  
  1353  var specialOperands = map[SpecialOperand]struct {
  1354  	encoding uint32
  1355  	name     string
  1356  }{
  1357  	SPOP_MA: {encoding: 1, name: "MA"},
  1358  	SPOP_MU: {encoding: 0, name: "MU"},
  1359  
  1360  	SPOP_TA: {encoding: 1, name: "TA"},
  1361  	SPOP_TU: {encoding: 0, name: "TU"},
  1362  
  1363  	SPOP_M1:  {encoding: 0, name: "M1"},
  1364  	SPOP_M2:  {encoding: 1, name: "M2"},
  1365  	SPOP_M4:  {encoding: 2, name: "M4"},
  1366  	SPOP_M8:  {encoding: 3, name: "M8"},
  1367  	SPOP_MF8: {encoding: 5, name: "MF8"},
  1368  	SPOP_MF4: {encoding: 6, name: "MF4"},
  1369  	SPOP_MF2: {encoding: 7, name: "MF2"},
  1370  
  1371  	SPOP_E8:  {encoding: 0, name: "E8"},
  1372  	SPOP_E16: {encoding: 1, name: "E16"},
  1373  	SPOP_E32: {encoding: 2, name: "E32"},
  1374  	SPOP_E64: {encoding: 3, name: "E64"},
  1375  }
  1376  
  1377  func (so SpecialOperand) encode() uint32 {
  1378  	switch {
  1379  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1380  		op, ok := specialOperands[so]
  1381  		if ok {
  1382  			return op.encoding
  1383  		}
  1384  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1385  		csrNum := uint16(so - SPOP_CSR_BEGIN)
  1386  		if _, ok := csrs[csrNum]; ok {
  1387  			return uint32(csrNum)
  1388  		}
  1389  	}
  1390  	return 0
  1391  }
  1392  
  1393  // String returns the textual representation of a SpecialOperand.
  1394  func (so SpecialOperand) String() string {
  1395  	switch {
  1396  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1397  		op, ok := specialOperands[so]
  1398  		if ok {
  1399  			return op.name
  1400  		}
  1401  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1402  		if csrName, ok := csrs[uint16(so-SPOP_CSR_BEGIN)]; ok {
  1403  			return csrName
  1404  		}
  1405  	}
  1406  	return ""
  1407  }
  1408  
  1409  // All unary instructions which write to their arguments (as opposed to reading
  1410  // from them) go here. The assembly parser uses this information to populate
  1411  // its AST in a semantically reasonable way.
  1412  //
  1413  // Any instructions not listed here are assumed to either be non-unary or to read
  1414  // from its argument.
  1415  var unaryDst = map[obj.As]bool{
  1416  	ARDCYCLE:   true,
  1417  	ARDTIME:    true,
  1418  	ARDINSTRET: true,
  1419  }
  1420  
  1421  // Instruction encoding masks.
  1422  const (
  1423  	// BTypeImmMask is a mask including only the immediate portion of
  1424  	// B-type instructions.
  1425  	BTypeImmMask = 0xfe000f80
  1426  
  1427  	// CBTypeImmMask is a mask including only the immediate portion of
  1428  	// CB-type instructions.
  1429  	CBTypeImmMask = 0x1c7c
  1430  
  1431  	// CJTypeImmMask is a mask including only the immediate portion of
  1432  	// CJ-type instructions.
  1433  	CJTypeImmMask = 0x1f7c
  1434  
  1435  	// ITypeImmMask is a mask including only the immediate portion of
  1436  	// I-type instructions.
  1437  	ITypeImmMask = 0xfff00000
  1438  
  1439  	// JTypeImmMask is a mask including only the immediate portion of
  1440  	// J-type instructions.
  1441  	JTypeImmMask = 0xfffff000
  1442  
  1443  	// STypeImmMask is a mask including only the immediate portion of
  1444  	// S-type instructions.
  1445  	STypeImmMask = 0xfe000f80
  1446  
  1447  	// UTypeImmMask is a mask including only the immediate portion of
  1448  	// U-type instructions.
  1449  	UTypeImmMask = 0xfffff000
  1450  )
  1451  

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