Source file src/cmd/internal/obj/riscv/cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    39  
    40  const (
    41  	// Base register numberings.
    42  	REG_X0 = obj.RBaseRISCV + iota
    43  	REG_X1
    44  	REG_X2
    45  	REG_X3
    46  	REG_X4
    47  	REG_X5
    48  	REG_X6
    49  	REG_X7
    50  	REG_X8
    51  	REG_X9
    52  	REG_X10
    53  	REG_X11
    54  	REG_X12
    55  	REG_X13
    56  	REG_X14
    57  	REG_X15
    58  	REG_X16
    59  	REG_X17
    60  	REG_X18
    61  	REG_X19
    62  	REG_X20
    63  	REG_X21
    64  	REG_X22
    65  	REG_X23
    66  	REG_X24
    67  	REG_X25
    68  	REG_X26
    69  	REG_X27
    70  	REG_X28
    71  	REG_X29
    72  	REG_X30
    73  	REG_X31
    74  
    75  	// Floating Point register numberings.
    76  	REG_F0
    77  	REG_F1
    78  	REG_F2
    79  	REG_F3
    80  	REG_F4
    81  	REG_F5
    82  	REG_F6
    83  	REG_F7
    84  	REG_F8
    85  	REG_F9
    86  	REG_F10
    87  	REG_F11
    88  	REG_F12
    89  	REG_F13
    90  	REG_F14
    91  	REG_F15
    92  	REG_F16
    93  	REG_F17
    94  	REG_F18
    95  	REG_F19
    96  	REG_F20
    97  	REG_F21
    98  	REG_F22
    99  	REG_F23
   100  	REG_F24
   101  	REG_F25
   102  	REG_F26
   103  	REG_F27
   104  	REG_F28
   105  	REG_F29
   106  	REG_F30
   107  	REG_F31
   108  
   109  	// Vector register numberings.
   110  	REG_V0
   111  	REG_V1
   112  	REG_V2
   113  	REG_V3
   114  	REG_V4
   115  	REG_V5
   116  	REG_V6
   117  	REG_V7
   118  	REG_V8
   119  	REG_V9
   120  	REG_V10
   121  	REG_V11
   122  	REG_V12
   123  	REG_V13
   124  	REG_V14
   125  	REG_V15
   126  	REG_V16
   127  	REG_V17
   128  	REG_V18
   129  	REG_V19
   130  	REG_V20
   131  	REG_V21
   132  	REG_V22
   133  	REG_V23
   134  	REG_V24
   135  	REG_V25
   136  	REG_V26
   137  	REG_V27
   138  	REG_V28
   139  	REG_V29
   140  	REG_V30
   141  	REG_V31
   142  
   143  	// This marks the end of the register numbering.
   144  	REG_END
   145  
   146  	// General registers reassigned to ABI names.
   147  	REG_ZERO = REG_X0
   148  	REG_RA   = REG_X1 // aka REG_LR
   149  	REG_SP   = REG_X2
   150  	REG_GP   = REG_X3 // aka REG_SB
   151  	REG_TP   = REG_X4
   152  	REG_T0   = REG_X5
   153  	REG_T1   = REG_X6
   154  	REG_T2   = REG_X7
   155  	REG_S0   = REG_X8
   156  	REG_S1   = REG_X9
   157  	REG_A0   = REG_X10
   158  	REG_A1   = REG_X11
   159  	REG_A2   = REG_X12
   160  	REG_A3   = REG_X13
   161  	REG_A4   = REG_X14
   162  	REG_A5   = REG_X15
   163  	REG_A6   = REG_X16
   164  	REG_A7   = REG_X17
   165  	REG_S2   = REG_X18
   166  	REG_S3   = REG_X19
   167  	REG_S4   = REG_X20
   168  	REG_S5   = REG_X21
   169  	REG_S6   = REG_X22
   170  	REG_S7   = REG_X23
   171  	REG_S8   = REG_X24
   172  	REG_S9   = REG_X25
   173  	REG_S10  = REG_X26 // aka REG_CTXT
   174  	REG_S11  = REG_X27 // aka REG_G
   175  	REG_T3   = REG_X28
   176  	REG_T4   = REG_X29
   177  	REG_T5   = REG_X30
   178  	REG_T6   = REG_X31 // aka REG_TMP
   179  
   180  	// Go runtime register names.
   181  	REG_CTXT = REG_S10 // Context for closures.
   182  	REG_G    = REG_S11 // G pointer.
   183  	REG_LR   = REG_RA  // Link register.
   184  	REG_TMP  = REG_T6  // Reserved for assembler use.
   185  
   186  	// ABI names for floating point registers.
   187  	REG_FT0  = REG_F0
   188  	REG_FT1  = REG_F1
   189  	REG_FT2  = REG_F2
   190  	REG_FT3  = REG_F3
   191  	REG_FT4  = REG_F4
   192  	REG_FT5  = REG_F5
   193  	REG_FT6  = REG_F6
   194  	REG_FT7  = REG_F7
   195  	REG_FS0  = REG_F8
   196  	REG_FS1  = REG_F9
   197  	REG_FA0  = REG_F10
   198  	REG_FA1  = REG_F11
   199  	REG_FA2  = REG_F12
   200  	REG_FA3  = REG_F13
   201  	REG_FA4  = REG_F14
   202  	REG_FA5  = REG_F15
   203  	REG_FA6  = REG_F16
   204  	REG_FA7  = REG_F17
   205  	REG_FS2  = REG_F18
   206  	REG_FS3  = REG_F19
   207  	REG_FS4  = REG_F20
   208  	REG_FS5  = REG_F21
   209  	REG_FS6  = REG_F22
   210  	REG_FS7  = REG_F23
   211  	REG_FS8  = REG_F24
   212  	REG_FS9  = REG_F25
   213  	REG_FS10 = REG_F26
   214  	REG_FS11 = REG_F27
   215  	REG_FT8  = REG_F28
   216  	REG_FT9  = REG_F29
   217  	REG_FT10 = REG_F30
   218  	REG_FT11 = REG_F31
   219  
   220  	// Names generated by the SSA compiler.
   221  	REGSP = REG_SP
   222  	REGG  = REG_G
   223  )
   224  
   225  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   226  var RISCV64DWARFRegisters = map[int16]int16{
   227  	// Integer Registers.
   228  	REG_X0:  0,
   229  	REG_X1:  1,
   230  	REG_X2:  2,
   231  	REG_X3:  3,
   232  	REG_X4:  4,
   233  	REG_X5:  5,
   234  	REG_X6:  6,
   235  	REG_X7:  7,
   236  	REG_X8:  8,
   237  	REG_X9:  9,
   238  	REG_X10: 10,
   239  	REG_X11: 11,
   240  	REG_X12: 12,
   241  	REG_X13: 13,
   242  	REG_X14: 14,
   243  	REG_X15: 15,
   244  	REG_X16: 16,
   245  	REG_X17: 17,
   246  	REG_X18: 18,
   247  	REG_X19: 19,
   248  	REG_X20: 20,
   249  	REG_X21: 21,
   250  	REG_X22: 22,
   251  	REG_X23: 23,
   252  	REG_X24: 24,
   253  	REG_X25: 25,
   254  	REG_X26: 26,
   255  	REG_X27: 27,
   256  	REG_X28: 28,
   257  	REG_X29: 29,
   258  	REG_X30: 30,
   259  	REG_X31: 31,
   260  
   261  	// Floating-Point Registers.
   262  	REG_F0:  32,
   263  	REG_F1:  33,
   264  	REG_F2:  34,
   265  	REG_F3:  35,
   266  	REG_F4:  36,
   267  	REG_F5:  37,
   268  	REG_F6:  38,
   269  	REG_F7:  39,
   270  	REG_F8:  40,
   271  	REG_F9:  41,
   272  	REG_F10: 42,
   273  	REG_F11: 43,
   274  	REG_F12: 44,
   275  	REG_F13: 45,
   276  	REG_F14: 46,
   277  	REG_F15: 47,
   278  	REG_F16: 48,
   279  	REG_F17: 49,
   280  	REG_F18: 50,
   281  	REG_F19: 51,
   282  	REG_F20: 52,
   283  	REG_F21: 53,
   284  	REG_F22: 54,
   285  	REG_F23: 55,
   286  	REG_F24: 56,
   287  	REG_F25: 57,
   288  	REG_F26: 58,
   289  	REG_F27: 59,
   290  	REG_F28: 60,
   291  	REG_F29: 61,
   292  	REG_F30: 62,
   293  	REG_F31: 63,
   294  }
   295  
   296  // Prog.Mark flags.
   297  const (
   298  	// USES_REG_TMP indicates that a machine instruction generated from the
   299  	// corresponding *obj.Prog uses the temporary register.
   300  	USES_REG_TMP = 1 << iota
   301  
   302  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   303  	// R_RISCV_JAL relocation is needed.
   304  	NEED_JAL_RELOC
   305  
   306  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   307  	// is the first instruction in an AUIPC + JAL pair that needs a
   308  	// R_RISCV_CALL relocation.
   309  	NEED_CALL_RELOC
   310  
   311  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   312  	// it is the first instruction in an AUIPC + I-type pair that needs a
   313  	// R_RISCV_PCREL_ITYPE relocation.
   314  	NEED_PCREL_ITYPE_RELOC
   315  
   316  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   317  	// it is the first instruction in an AUIPC + S-type pair that needs a
   318  	// R_RISCV_PCREL_STYPE relocation.
   319  	NEED_PCREL_STYPE_RELOC
   320  )
   321  
   322  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   323  // at https://github.com/riscv/riscv-opcodes.
   324  //
   325  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   326  //
   327  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
   328  //
   329  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   330  const (
   331  	//
   332  	// Unprivileged ISA (version 20240411)
   333  	//
   334  
   335  	// 2.4: Integer Computational Instructions
   336  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   337  	ASLTI
   338  	ASLTIU
   339  	AANDI
   340  	AORI
   341  	AXORI
   342  	ASLLI
   343  	ASRLI
   344  	ASRAI
   345  	ALUI
   346  	AAUIPC
   347  	AADD
   348  	ASLT
   349  	ASLTU
   350  	AAND
   351  	AOR
   352  	AXOR
   353  	ASLL
   354  	ASRL
   355  	ASUB
   356  	ASRA
   357  
   358  	// 2.5: Control Transfer Instructions
   359  	AJAL
   360  	AJALR
   361  	ABEQ
   362  	ABNE
   363  	ABLT
   364  	ABLTU
   365  	ABGE
   366  	ABGEU
   367  
   368  	// 2.6: Load and Store Instructions
   369  	ALW
   370  	ALWU
   371  	ALH
   372  	ALHU
   373  	ALB
   374  	ALBU
   375  	ASW
   376  	ASH
   377  	ASB
   378  
   379  	// 2.7: Memory Ordering Instructions
   380  	AFENCE
   381  
   382  	// 4.2: Integer Computational Instructions (RV64I)
   383  	AADDIW
   384  	ASLLIW
   385  	ASRLIW
   386  	ASRAIW
   387  	AADDW
   388  	ASLLW
   389  	ASRLW
   390  	ASUBW
   391  	ASRAW
   392  
   393  	// 4.3: Load and Store Instructions (RV64I)
   394  	ALD
   395  	ASD
   396  
   397  	// 7.1: CSR Instructions (Zicsr)
   398  	ACSRRW
   399  	ACSRRS
   400  	ACSRRC
   401  	ACSRRWI
   402  	ACSRRSI
   403  	ACSRRCI
   404  
   405  	// 13.1: Multiplication Operations
   406  	AMUL
   407  	AMULH
   408  	AMULHU
   409  	AMULHSU
   410  	AMULW
   411  
   412  	// 13.2: Division Operations
   413  	ADIV
   414  	ADIVU
   415  	AREM
   416  	AREMU
   417  	ADIVW
   418  	ADIVUW
   419  	AREMW
   420  	AREMUW
   421  
   422  	// 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
   423  	ALRD
   424  	ASCD
   425  	ALRW
   426  	ASCW
   427  
   428  	// 14.4: Atomic Memory Operations (Zaamo)
   429  	AAMOSWAPD
   430  	AAMOADDD
   431  	AAMOANDD
   432  	AAMOORD
   433  	AAMOXORD
   434  	AAMOMAXD
   435  	AAMOMAXUD
   436  	AAMOMIND
   437  	AAMOMINUD
   438  	AAMOSWAPW
   439  	AAMOADDW
   440  	AAMOANDW
   441  	AAMOORW
   442  	AAMOXORW
   443  	AAMOMAXW
   444  	AAMOMAXUW
   445  	AAMOMINW
   446  	AAMOMINUW
   447  
   448  	// 20.5: Single-Precision Load and Store Instructions
   449  	AFLW
   450  	AFSW
   451  
   452  	// 20.6: Single-Precision Floating-Point Computational Instructions
   453  	AFADDS
   454  	AFSUBS
   455  	AFMULS
   456  	AFDIVS
   457  	AFMINS
   458  	AFMAXS
   459  	AFSQRTS
   460  	AFMADDS
   461  	AFMSUBS
   462  	AFNMADDS
   463  	AFNMSUBS
   464  
   465  	// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
   466  	AFCVTWS
   467  	AFCVTLS
   468  	AFCVTSW
   469  	AFCVTSL
   470  	AFCVTWUS
   471  	AFCVTLUS
   472  	AFCVTSWU
   473  	AFCVTSLU
   474  	AFSGNJS
   475  	AFSGNJNS
   476  	AFSGNJXS
   477  	AFMVXS
   478  	AFMVSX
   479  	AFMVXW
   480  	AFMVWX
   481  
   482  	// 20.8: Single-Precision Floating-Point Compare Instructions
   483  	AFEQS
   484  	AFLTS
   485  	AFLES
   486  
   487  	// 20.9: Single-Precision Floating-Point Classify Instruction
   488  	AFCLASSS
   489  
   490  	// 21.3: Double-Precision Load and Store Instructions
   491  	AFLD
   492  	AFSD
   493  
   494  	// 21.4: Double-Precision Floating-Point Computational Instructions
   495  	AFADDD
   496  	AFSUBD
   497  	AFMULD
   498  	AFDIVD
   499  	AFMIND
   500  	AFMAXD
   501  	AFSQRTD
   502  	AFMADDD
   503  	AFMSUBD
   504  	AFNMADDD
   505  	AFNMSUBD
   506  
   507  	// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
   508  	AFCVTWD
   509  	AFCVTLD
   510  	AFCVTDW
   511  	AFCVTDL
   512  	AFCVTWUD
   513  	AFCVTLUD
   514  	AFCVTDWU
   515  	AFCVTDLU
   516  	AFCVTSD
   517  	AFCVTDS
   518  	AFSGNJD
   519  	AFSGNJND
   520  	AFSGNJXD
   521  	AFMVXD
   522  	AFMVDX
   523  
   524  	// 21.6: Double-Precision Floating-Point Compare Instructions
   525  	AFEQD
   526  	AFLTD
   527  	AFLED
   528  
   529  	// 21.7: Double-Precision Floating-Point Classify Instruction
   530  	AFCLASSD
   531  
   532  	// 22.1 Quad-Precision Load and Store Instructions
   533  	AFLQ
   534  	AFSQ
   535  
   536  	// 22.2: Quad-Precision Computational Instructions
   537  	AFADDQ
   538  	AFSUBQ
   539  	AFMULQ
   540  	AFDIVQ
   541  	AFMINQ
   542  	AFMAXQ
   543  	AFSQRTQ
   544  	AFMADDQ
   545  	AFMSUBQ
   546  	AFNMADDQ
   547  	AFNMSUBQ
   548  
   549  	// 22.3 Quad-Precision Convert and Move Instructions
   550  	AFCVTWQ
   551  	AFCVTLQ
   552  	AFCVTSQ
   553  	AFCVTDQ
   554  	AFCVTQW
   555  	AFCVTQL
   556  	AFCVTQS
   557  	AFCVTQD
   558  	AFCVTWUQ
   559  	AFCVTLUQ
   560  	AFCVTQWU
   561  	AFCVTQLU
   562  	AFSGNJQ
   563  	AFSGNJNQ
   564  	AFSGNJXQ
   565  
   566  	// 22.4 Quad-Precision Floating-Point Compare Instructions
   567  	AFEQQ
   568  	AFLEQ
   569  	AFLTQ
   570  
   571  	// 22.5 Quad-Precision Floating-Point Classify Instruction
   572  	AFCLASSQ
   573  
   574  	// 28.4.1: Address Generation Instructions (Zba)
   575  	AADDUW
   576  	ASH1ADD
   577  	ASH1ADDUW
   578  	ASH2ADD
   579  	ASH2ADDUW
   580  	ASH3ADD
   581  	ASH3ADDUW
   582  	ASLLIUW
   583  
   584  	// 28.4.2: Basic Bit Manipulation (Zbb)
   585  	AANDN
   586  	AORN
   587  	AXNOR
   588  	ACLZ
   589  	ACLZW
   590  	ACTZ
   591  	ACTZW
   592  	ACPOP
   593  	ACPOPW
   594  	AMAX
   595  	AMAXU
   596  	AMIN
   597  	AMINU
   598  	ASEXTB
   599  	ASEXTH
   600  	AZEXTH
   601  
   602  	// 28.4.3: Bitwise Rotation (Zbb)
   603  	AROL
   604  	AROLW
   605  	AROR
   606  	ARORI
   607  	ARORIW
   608  	ARORW
   609  	AORCB
   610  	AREV8
   611  
   612  	// 28.4.4: Single-bit Instructions (Zbs)
   613  	ABCLR
   614  	ABCLRI
   615  	ABEXT
   616  	ABEXTI
   617  	ABINV
   618  	ABINVI
   619  	ABSET
   620  	ABSETI
   621  
   622  	//
   623  	// RISC-V Vector ISA-extension (1.0) (Unprivileged 20240411)
   624  	//
   625  
   626  	// 31.6. Configuration-Setting Instructions
   627  	AVSETVLI
   628  	AVSETIVLI
   629  	AVSETVL
   630  
   631  	// 31.7.4. Vector Unit-Stride Instructions
   632  	AVLE8V
   633  	AVLE16V
   634  	AVLE32V
   635  	AVLE64V
   636  	AVSE8V
   637  	AVSE16V
   638  	AVSE32V
   639  	AVSE64V
   640  	AVLMV
   641  	AVSMV
   642  
   643  	// 31.7.5. Vector Strided Instructions
   644  	AVLSE8V
   645  	AVLSE16V
   646  	AVLSE32V
   647  	AVLSE64V
   648  	AVSSE8V
   649  	AVSSE16V
   650  	AVSSE32V
   651  	AVSSE64V
   652  
   653  	// 31.7.6. Vector Indexed Instructions
   654  	AVLUXEI8V
   655  	AVLUXEI16V
   656  	AVLUXEI32V
   657  	AVLUXEI64V
   658  	AVLOXEI8V
   659  	AVLOXEI16V
   660  	AVLOXEI32V
   661  	AVLOXEI64V
   662  	AVSUXEI8V
   663  	AVSUXEI16V
   664  	AVSUXEI32V
   665  	AVSUXEI64V
   666  	AVSOXEI8V
   667  	AVSOXEI16V
   668  	AVSOXEI32V
   669  	AVSOXEI64V
   670  
   671  	// 31.7.7. Unit-stride Fault-Only-First Loads
   672  	AVLE8FFV
   673  	AVLE16FFV
   674  	AVLE32FFV
   675  	AVLE64FFV
   676  
   677  	// 31.7.9. Vector Load/Store Whole Register Instructions
   678  	AVL1RE8V
   679  	AVL1RE16V
   680  	AVL1RE32V
   681  	AVL1RE64V
   682  	AVL2RE8V
   683  	AVL2RE16V
   684  	AVL2RE32V
   685  	AVL2RE64V
   686  	AVL4RE8V
   687  	AVL4RE16V
   688  	AVL4RE32V
   689  	AVL4RE64V
   690  	AVL8RE8V
   691  	AVL8RE16V
   692  	AVL8RE32V
   693  	AVL8RE64V
   694  	AVS1RV
   695  	AVS2RV
   696  	AVS4RV
   697  	AVS8RV
   698  
   699  	// 31.11.1. Vector Single-Width Integer Add and Subtract
   700  	AVADDVV
   701  	AVADDVX
   702  	AVADDVI
   703  	AVSUBVV
   704  	AVSUBVX
   705  	AVRSUBVX
   706  	AVRSUBVI
   707  
   708  	// 31.11.2. Vector Widening Integer Add/Subtract
   709  	AVWADDUVV
   710  	AVWADDUVX
   711  	AVWSUBUVV
   712  	AVWSUBUVX
   713  	AVWADDVV
   714  	AVWADDVX
   715  	AVWSUBVV
   716  	AVWSUBVX
   717  	AVWADDUWV
   718  	AVWADDUWX
   719  	AVWSUBUWV
   720  	AVWSUBUWX
   721  	AVWADDWV
   722  	AVWADDWX
   723  	AVWSUBWV
   724  	AVWSUBWX
   725  
   726  	// 31.11.3. Vector Integer Extension
   727  	AVZEXTVF2
   728  	AVSEXTVF2
   729  	AVZEXTVF4
   730  	AVSEXTVF4
   731  	AVZEXTVF8
   732  	AVSEXTVF8
   733  
   734  	// 31.11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
   735  	AVADCVVM
   736  	AVADCVXM
   737  	AVADCVIM
   738  	AVMADCVVM
   739  	AVMADCVXM
   740  	AVMADCVIM
   741  	AVMADCVV
   742  	AVMADCVX
   743  	AVMADCVI
   744  	AVSBCVVM
   745  	AVSBCVXM
   746  	AVMSBCVVM
   747  	AVMSBCVXM
   748  	AVMSBCVV
   749  	AVMSBCVX
   750  
   751  	// 31.11.5. Vector Bitwise Logical Instructions
   752  	AVANDVV
   753  	AVANDVX
   754  	AVANDVI
   755  	AVORVV
   756  	AVORVX
   757  	AVORVI
   758  	AVXORVV
   759  	AVXORVX
   760  	AVXORVI
   761  
   762  	// 31.11.6. Vector Single-Width Shift Instructions
   763  	AVSLLVV
   764  	AVSLLVX
   765  	AVSLLVI
   766  	AVSRLVV
   767  	AVSRLVX
   768  	AVSRLVI
   769  	AVSRAVV
   770  	AVSRAVX
   771  	AVSRAVI
   772  
   773  	// 31.11.7. Vector Narrowing Integer Right Shift Instructions
   774  	AVNSRLWV
   775  	AVNSRLWX
   776  	AVNSRLWI
   777  	AVNSRAWV
   778  	AVNSRAWX
   779  	AVNSRAWI
   780  
   781  	// 31.11.8. Vector Integer Compare Instructions
   782  	AVMSEQVV
   783  	AVMSEQVX
   784  	AVMSEQVI
   785  	AVMSNEVV
   786  	AVMSNEVX
   787  	AVMSNEVI
   788  	AVMSLTUVV
   789  	AVMSLTUVX
   790  	AVMSLTVV
   791  	AVMSLTVX
   792  	AVMSLEUVV
   793  	AVMSLEUVX
   794  	AVMSLEUVI
   795  	AVMSLEVV
   796  	AVMSLEVX
   797  	AVMSLEVI
   798  	AVMSGTUVX
   799  	AVMSGTUVI
   800  	AVMSGTVX
   801  	AVMSGTVI
   802  
   803  	// 31.11.9. Vector Integer Min/Max Instructions
   804  	AVMINUVV
   805  	AVMINUVX
   806  	AVMINVV
   807  	AVMINVX
   808  	AVMAXUVV
   809  	AVMAXUVX
   810  	AVMAXVV
   811  	AVMAXVX
   812  
   813  	// 31.11.10. Vector Single-Width Integer Multiply Instructions
   814  	AVMULVV
   815  	AVMULVX
   816  	AVMULHVV
   817  	AVMULHVX
   818  	AVMULHUVV
   819  	AVMULHUVX
   820  	AVMULHSUVV
   821  	AVMULHSUVX
   822  
   823  	// 31.11.11. Vector Integer Divide Instructions
   824  	AVDIVUVV
   825  	AVDIVUVX
   826  	AVDIVVV
   827  	AVDIVVX
   828  	AVREMUVV
   829  	AVREMUVX
   830  	AVREMVV
   831  	AVREMVX
   832  
   833  	// 31.11.12. Vector Widening Integer Multiply Instructions
   834  	AVWMULVV
   835  	AVWMULVX
   836  	AVWMULUVV
   837  	AVWMULUVX
   838  	AVWMULSUVV
   839  	AVWMULSUVX
   840  
   841  	// 31.11.13. Vector Single-Width Integer Multiply-Add Instructions
   842  	AVMACCVV
   843  	AVMACCVX
   844  	AVNMSACVV
   845  	AVNMSACVX
   846  	AVMADDVV
   847  	AVMADDVX
   848  	AVNMSUBVV
   849  	AVNMSUBVX
   850  
   851  	// 31.11.14. Vector Widening Integer Multiply-Add Instructions
   852  	AVWMACCUVV
   853  	AVWMACCUVX
   854  	AVWMACCVV
   855  	AVWMACCVX
   856  	AVWMACCSUVV
   857  	AVWMACCSUVX
   858  	AVWMACCUSVX
   859  
   860  	// 31.11.15. Vector Integer Merge Instructions
   861  	AVMERGEVVM
   862  	AVMERGEVXM
   863  	AVMERGEVIM
   864  
   865  	// 31.11.16. Vector Integer Move Instructions
   866  	AVMVVV
   867  	AVMVVX
   868  	AVMVVI
   869  
   870  	// 31.12.1. Vector Single-Width Saturating Add and Subtract
   871  	AVSADDUVV
   872  	AVSADDUVX
   873  	AVSADDUVI
   874  	AVSADDVV
   875  	AVSADDVX
   876  	AVSADDVI
   877  	AVSSUBUVV
   878  	AVSSUBUVX
   879  	AVSSUBVV
   880  	AVSSUBVX
   881  
   882  	// 31.12.2. Vector Single-Width Averaging Add and Subtract
   883  	AVAADDUVV
   884  	AVAADDUVX
   885  	AVAADDVV
   886  	AVAADDVX
   887  	AVASUBUVV
   888  	AVASUBUVX
   889  	AVASUBVV
   890  	AVASUBVX
   891  
   892  	// 31.12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
   893  	AVSMULVV
   894  	AVSMULVX
   895  
   896  	// 31.12.4. Vector Single-Width Scaling Shift Instructions
   897  	AVSSRLVV
   898  	AVSSRLVX
   899  	AVSSRLVI
   900  	AVSSRAVV
   901  	AVSSRAVX
   902  	AVSSRAVI
   903  
   904  	// 31.12.5. Vector Narrowing Fixed-Point Clip Instructions
   905  	AVNCLIPUWV
   906  	AVNCLIPUWX
   907  	AVNCLIPUWI
   908  	AVNCLIPWV
   909  	AVNCLIPWX
   910  	AVNCLIPWI
   911  
   912  	// 31.13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
   913  	AVFADDVV
   914  	AVFADDVF
   915  	AVFSUBVV
   916  	AVFSUBVF
   917  	AVFRSUBVF
   918  
   919  	// 31.13.3. Vector Widening Floating-Point Add/Subtract Instructions
   920  	AVFWADDVV
   921  	AVFWADDVF
   922  	AVFWSUBVV
   923  	AVFWSUBVF
   924  	AVFWADDWV
   925  	AVFWADDWF
   926  	AVFWSUBWV
   927  	AVFWSUBWF
   928  
   929  	// 31.13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
   930  	AVFMULVV
   931  	AVFMULVF
   932  	AVFDIVVV
   933  	AVFDIVVF
   934  	AVFRDIVVF
   935  
   936  	// 31.13.5. Vector Widening Floating-Point Multiply
   937  	AVFWMULVV
   938  	AVFWMULVF
   939  
   940  	// 31.13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
   941  	AVFMACCVV
   942  	AVFMACCVF
   943  	AVFNMACCVV
   944  	AVFNMACCVF
   945  	AVFMSACVV
   946  	AVFMSACVF
   947  	AVFNMSACVV
   948  	AVFNMSACVF
   949  	AVFMADDVV
   950  	AVFMADDVF
   951  	AVFNMADDVV
   952  	AVFNMADDVF
   953  	AVFMSUBVV
   954  	AVFMSUBVF
   955  	AVFNMSUBVV
   956  	AVFNMSUBVF
   957  
   958  	// 31.13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
   959  	AVFWMACCVV
   960  	AVFWMACCVF
   961  	AVFWNMACCVV
   962  	AVFWNMACCVF
   963  	AVFWMSACVV
   964  	AVFWMSACVF
   965  	AVFWNMSACVV
   966  	AVFWNMSACVF
   967  
   968  	// 31.13.8. Vector Floating-Point Square-Root Instruction
   969  	AVFSQRTV
   970  
   971  	// 31.13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
   972  	AVFRSQRT7V
   973  
   974  	// 31.13.10. Vector Floating-Point Reciprocal Estimate Instruction
   975  	AVFREC7V
   976  
   977  	// 31.13.11. Vector Floating-Point MIN/MAX Instructions
   978  	AVFMINVV
   979  	AVFMINVF
   980  	AVFMAXVV
   981  	AVFMAXVF
   982  
   983  	// 31.13.12. Vector Floating-Point Sign-Injection Instructions
   984  	AVFSGNJVV
   985  	AVFSGNJVF
   986  	AVFSGNJNVV
   987  	AVFSGNJNVF
   988  	AVFSGNJXVV
   989  	AVFSGNJXVF
   990  
   991  	// 31.13.13. Vector Floating-Point Compare Instructions
   992  	AVMFEQVV
   993  	AVMFEQVF
   994  	AVMFNEVV
   995  	AVMFNEVF
   996  	AVMFLTVV
   997  	AVMFLTVF
   998  	AVMFLEVV
   999  	AVMFLEVF
  1000  	AVMFGTVF
  1001  	AVMFGEVF
  1002  
  1003  	// 31.13.14. Vector Floating-Point Classify Instruction
  1004  	AVFCLASSV
  1005  
  1006  	// 31.13.15. Vector Floating-Point Merge Instruction
  1007  	AVFMERGEVFM
  1008  
  1009  	// 31.13.16. Vector Floating-Point Move Instruction
  1010  	AVFMVVF
  1011  
  1012  	// 31.13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
  1013  	AVFCVTXUFV
  1014  	AVFCVTXFV
  1015  	AVFCVTRTZXUFV
  1016  	AVFCVTRTZXFV
  1017  	AVFCVTFXUV
  1018  	AVFCVTFXV
  1019  
  1020  	// 31.13.18. Widening Floating-Point/Integer Type-Convert Instructions
  1021  	AVFWCVTXUFV
  1022  	AVFWCVTXFV
  1023  	AVFWCVTRTZXUFV
  1024  	AVFWCVTRTZXFV
  1025  	AVFWCVTFXUV
  1026  	AVFWCVTFXV
  1027  	AVFWCVTFFV
  1028  
  1029  	// 31.13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
  1030  	AVFNCVTXUFW
  1031  	AVFNCVTXFW
  1032  	AVFNCVTRTZXUFW
  1033  	AVFNCVTRTZXFW
  1034  	AVFNCVTFXUW
  1035  	AVFNCVTFXW
  1036  	AVFNCVTFFW
  1037  	AVFNCVTRODFFW
  1038  
  1039  	// 31.14.1. Vector Single-Width Integer Reduction Instructions
  1040  	AVREDSUMVS
  1041  	AVREDMAXUVS
  1042  	AVREDMAXVS
  1043  	AVREDMINUVS
  1044  	AVREDMINVS
  1045  	AVREDANDVS
  1046  	AVREDORVS
  1047  	AVREDXORVS
  1048  
  1049  	// 31.14.2. Vector Widening Integer Reduction Instructions
  1050  	AVWREDSUMUVS
  1051  	AVWREDSUMVS
  1052  
  1053  	// 31.14.3. Vector Single-Width Floating-Point Reduction Instructions
  1054  	AVFREDOSUMVS
  1055  	AVFREDUSUMVS
  1056  	AVFREDMAXVS
  1057  	AVFREDMINVS
  1058  
  1059  	// 31.14.4. Vector Widening Floating-Point Reduction Instructions
  1060  	AVFWREDOSUMVS
  1061  	AVFWREDUSUMVS
  1062  
  1063  	// 31.15. Vector Mask Instructions
  1064  	AVMANDMM
  1065  	AVMNANDMM
  1066  	AVMANDNMM
  1067  	AVMXORMM
  1068  	AVMORMM
  1069  	AVMNORMM
  1070  	AVMORNMM
  1071  	AVMXNORMM
  1072  	AVCPOPM
  1073  	AVFIRSTM
  1074  	AVMSBFM
  1075  	AVMSIFM
  1076  	AVMSOFM
  1077  	AVIOTAM
  1078  	AVIDV
  1079  
  1080  	// 31.16.1. Integer Scalar Move Instructions
  1081  	AVMVXS
  1082  	AVMVSX
  1083  
  1084  	// 31.16.2. Floating-Point Scalar Move Instructions
  1085  	AVFMVFS
  1086  	AVFMVSF
  1087  
  1088  	// 31.16.3. Vector Slide Instructions
  1089  	AVSLIDEUPVX
  1090  	AVSLIDEUPVI
  1091  	AVSLIDEDOWNVX
  1092  	AVSLIDEDOWNVI
  1093  	AVSLIDE1UPVX
  1094  	AVFSLIDE1UPVF
  1095  	AVSLIDE1DOWNVX
  1096  	AVFSLIDE1DOWNVF
  1097  
  1098  	// 31.16.4. Vector Register Gather Instructions
  1099  	AVRGATHERVV
  1100  	AVRGATHEREI16VV
  1101  	AVRGATHERVX
  1102  	AVRGATHERVI
  1103  
  1104  	// 31.16.5. Vector Compress Instruction
  1105  	AVCOMPRESSVM
  1106  
  1107  	// 31.16.6. Whole Vector Register Move
  1108  	AVMV1RV
  1109  	AVMV2RV
  1110  	AVMV4RV
  1111  	AVMV8RV
  1112  
  1113  	//
  1114  	// Privileged ISA (version 20240411)
  1115  	//
  1116  
  1117  	// 3.3.1: Environment Call and Breakpoint
  1118  	AECALL
  1119  	ASCALL
  1120  	AEBREAK
  1121  	ASBREAK
  1122  
  1123  	// 3.3.2: Trap-Return Instructions
  1124  	AMRET
  1125  	ASRET
  1126  	ADRET
  1127  
  1128  	// 3.3.3: Wait for Interrupt
  1129  	AWFI
  1130  
  1131  	// 10.2: Supervisor Memory-Management Fence Instruction
  1132  	ASFENCEVMA
  1133  
  1134  	// The escape hatch. Inserts a single 32-bit word.
  1135  	AWORD
  1136  
  1137  	// Pseudo-instructions.  These get translated by the assembler into other
  1138  	// instructions, based on their operands.
  1139  	ABEQZ
  1140  	ABGEZ
  1141  	ABGT
  1142  	ABGTU
  1143  	ABGTZ
  1144  	ABLE
  1145  	ABLEU
  1146  	ABLEZ
  1147  	ABLTZ
  1148  	ABNEZ
  1149  	AFABSD
  1150  	AFABSS
  1151  	AFNED
  1152  	AFNEGD
  1153  	AFNEGS
  1154  	AFNES
  1155  	AMOV
  1156  	AMOVB
  1157  	AMOVBU
  1158  	AMOVD
  1159  	AMOVF
  1160  	AMOVH
  1161  	AMOVHU
  1162  	AMOVW
  1163  	AMOVWU
  1164  	ANEG
  1165  	ANEGW
  1166  	ANOT
  1167  	ARDCYCLE
  1168  	ARDINSTRET
  1169  	ARDTIME
  1170  	ASEQZ
  1171  	ASNEZ
  1172  
  1173  	// End marker
  1174  	ALAST
  1175  )
  1176  
  1177  // opSuffix encoding to uint8 which fit into p.Scond
  1178  var rmSuffixSet = map[string]uint8{
  1179  	"RNE": RM_RNE,
  1180  	"RTZ": RM_RTZ,
  1181  	"RDN": RM_RDN,
  1182  	"RUP": RM_RUP,
  1183  	"RMM": RM_RMM,
  1184  }
  1185  
  1186  const rmSuffixBit uint8 = 1 << 7
  1187  
  1188  func rmSuffixEncode(s string) (uint8, error) {
  1189  	if s == "" {
  1190  		return 0, errors.New("empty suffix")
  1191  	}
  1192  	enc, ok := rmSuffixSet[s]
  1193  	if !ok {
  1194  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
  1195  	}
  1196  	return enc | rmSuffixBit, nil
  1197  }
  1198  
  1199  func rmSuffixString(u uint8) (string, error) {
  1200  	if u&rmSuffixBit == 0 {
  1201  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
  1202  	}
  1203  
  1204  	u &^= rmSuffixBit
  1205  	for k, v := range rmSuffixSet {
  1206  		if v == u {
  1207  			return k, nil
  1208  		}
  1209  	}
  1210  	return "", fmt.Errorf("unknown suffix:%x", u)
  1211  }
  1212  
  1213  const (
  1214  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
  1215  	RM_RTZ              // Round towards Zero
  1216  	RM_RDN              // Round Down
  1217  	RM_RUP              // Round Up
  1218  	RM_RMM              // Round to Nearest, ties to Max Magnitude
  1219  )
  1220  
  1221  // All unary instructions which write to their arguments (as opposed to reading
  1222  // from them) go here. The assembly parser uses this information to populate
  1223  // its AST in a semantically reasonable way.
  1224  //
  1225  // Any instructions not listed here are assumed to either be non-unary or to read
  1226  // from its argument.
  1227  var unaryDst = map[obj.As]bool{
  1228  	ARDCYCLE:   true,
  1229  	ARDTIME:    true,
  1230  	ARDINSTRET: true,
  1231  }
  1232  
  1233  // Instruction encoding masks.
  1234  const (
  1235  	// BTypeImmMask is a mask including only the immediate portion of
  1236  	// B-type instructions.
  1237  	BTypeImmMask = 0xfe000f80
  1238  
  1239  	// CBTypeImmMask is a mask including only the immediate portion of
  1240  	// CB-type instructions.
  1241  	CBTypeImmMask = 0x1c7c
  1242  
  1243  	// CJTypeImmMask is a mask including only the immediate portion of
  1244  	// CJ-type instructions.
  1245  	CJTypeImmMask = 0x1f7c
  1246  
  1247  	// ITypeImmMask is a mask including only the immediate portion of
  1248  	// I-type instructions.
  1249  	ITypeImmMask = 0xfff00000
  1250  
  1251  	// JTypeImmMask is a mask including only the immediate portion of
  1252  	// J-type instructions.
  1253  	JTypeImmMask = 0xfffff000
  1254  
  1255  	// STypeImmMask is a mask including only the immediate portion of
  1256  	// S-type instructions.
  1257  	STypeImmMask = 0xfe000f80
  1258  
  1259  	// UTypeImmMask is a mask including only the immediate portion of
  1260  	// U-type instructions.
  1261  	UTypeImmMask = 0xfffff000
  1262  )
  1263  

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