Source file src/cmd/internal/obj/riscv/cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    39  
    40  const (
    41  	// Base register numberings.
    42  	REG_X0 = obj.RBaseRISCV + iota
    43  	REG_X1
    44  	REG_X2
    45  	REG_X3
    46  	REG_X4
    47  	REG_X5
    48  	REG_X6
    49  	REG_X7
    50  	REG_X8
    51  	REG_X9
    52  	REG_X10
    53  	REG_X11
    54  	REG_X12
    55  	REG_X13
    56  	REG_X14
    57  	REG_X15
    58  	REG_X16
    59  	REG_X17
    60  	REG_X18
    61  	REG_X19
    62  	REG_X20
    63  	REG_X21
    64  	REG_X22
    65  	REG_X23
    66  	REG_X24
    67  	REG_X25
    68  	REG_X26
    69  	REG_X27
    70  	REG_X28
    71  	REG_X29
    72  	REG_X30
    73  	REG_X31
    74  
    75  	// Floating Point register numberings.
    76  	REG_F0
    77  	REG_F1
    78  	REG_F2
    79  	REG_F3
    80  	REG_F4
    81  	REG_F5
    82  	REG_F6
    83  	REG_F7
    84  	REG_F8
    85  	REG_F9
    86  	REG_F10
    87  	REG_F11
    88  	REG_F12
    89  	REG_F13
    90  	REG_F14
    91  	REG_F15
    92  	REG_F16
    93  	REG_F17
    94  	REG_F18
    95  	REG_F19
    96  	REG_F20
    97  	REG_F21
    98  	REG_F22
    99  	REG_F23
   100  	REG_F24
   101  	REG_F25
   102  	REG_F26
   103  	REG_F27
   104  	REG_F28
   105  	REG_F29
   106  	REG_F30
   107  	REG_F31
   108  
   109  	// Vector register numberings.
   110  	REG_V0
   111  	REG_V1
   112  	REG_V2
   113  	REG_V3
   114  	REG_V4
   115  	REG_V5
   116  	REG_V6
   117  	REG_V7
   118  	REG_V8
   119  	REG_V9
   120  	REG_V10
   121  	REG_V11
   122  	REG_V12
   123  	REG_V13
   124  	REG_V14
   125  	REG_V15
   126  	REG_V16
   127  	REG_V17
   128  	REG_V18
   129  	REG_V19
   130  	REG_V20
   131  	REG_V21
   132  	REG_V22
   133  	REG_V23
   134  	REG_V24
   135  	REG_V25
   136  	REG_V26
   137  	REG_V27
   138  	REG_V28
   139  	REG_V29
   140  	REG_V30
   141  	REG_V31
   142  
   143  	// This marks the end of the register numbering.
   144  	REG_END
   145  
   146  	// General registers reassigned to ABI names.
   147  	REG_ZERO = REG_X0
   148  	REG_RA   = REG_X1 // aka REG_LR
   149  	REG_SP   = REG_X2
   150  	REG_GP   = REG_X3 // aka REG_SB
   151  	REG_TP   = REG_X4
   152  	REG_T0   = REG_X5
   153  	REG_T1   = REG_X6
   154  	REG_T2   = REG_X7
   155  	REG_S0   = REG_X8
   156  	REG_S1   = REG_X9
   157  	REG_A0   = REG_X10
   158  	REG_A1   = REG_X11
   159  	REG_A2   = REG_X12
   160  	REG_A3   = REG_X13
   161  	REG_A4   = REG_X14
   162  	REG_A5   = REG_X15
   163  	REG_A6   = REG_X16
   164  	REG_A7   = REG_X17
   165  	REG_S2   = REG_X18
   166  	REG_S3   = REG_X19
   167  	REG_S4   = REG_X20
   168  	REG_S5   = REG_X21
   169  	REG_S6   = REG_X22
   170  	REG_S7   = REG_X23
   171  	REG_S8   = REG_X24
   172  	REG_S9   = REG_X25
   173  	REG_S10  = REG_X26 // aka REG_CTXT
   174  	REG_S11  = REG_X27 // aka REG_G
   175  	REG_T3   = REG_X28
   176  	REG_T4   = REG_X29
   177  	REG_T5   = REG_X30
   178  	REG_T6   = REG_X31 // aka REG_TMP
   179  
   180  	// Go runtime register names.
   181  	REG_CTXT = REG_S10 // Context for closures.
   182  	REG_G    = REG_S11 // G pointer.
   183  	REG_LR   = REG_RA  // Link register.
   184  	REG_TMP  = REG_T6  // Reserved for assembler use.
   185  
   186  	// ABI names for floating point registers.
   187  	REG_FT0  = REG_F0
   188  	REG_FT1  = REG_F1
   189  	REG_FT2  = REG_F2
   190  	REG_FT3  = REG_F3
   191  	REG_FT4  = REG_F4
   192  	REG_FT5  = REG_F5
   193  	REG_FT6  = REG_F6
   194  	REG_FT7  = REG_F7
   195  	REG_FS0  = REG_F8
   196  	REG_FS1  = REG_F9
   197  	REG_FA0  = REG_F10
   198  	REG_FA1  = REG_F11
   199  	REG_FA2  = REG_F12
   200  	REG_FA3  = REG_F13
   201  	REG_FA4  = REG_F14
   202  	REG_FA5  = REG_F15
   203  	REG_FA6  = REG_F16
   204  	REG_FA7  = REG_F17
   205  	REG_FS2  = REG_F18
   206  	REG_FS3  = REG_F19
   207  	REG_FS4  = REG_F20
   208  	REG_FS5  = REG_F21
   209  	REG_FS6  = REG_F22
   210  	REG_FS7  = REG_F23
   211  	REG_FS8  = REG_F24
   212  	REG_FS9  = REG_F25
   213  	REG_FS10 = REG_F26
   214  	REG_FS11 = REG_F27
   215  	REG_FT8  = REG_F28
   216  	REG_FT9  = REG_F29
   217  	REG_FT10 = REG_F30
   218  	REG_FT11 = REG_F31
   219  
   220  	// Names generated by the SSA compiler.
   221  	REGSP = REG_SP
   222  	REGG  = REG_G
   223  )
   224  
   225  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   226  var RISCV64DWARFRegisters = map[int16]int16{
   227  	// Integer Registers.
   228  	REG_X0:  0,
   229  	REG_X1:  1,
   230  	REG_X2:  2,
   231  	REG_X3:  3,
   232  	REG_X4:  4,
   233  	REG_X5:  5,
   234  	REG_X6:  6,
   235  	REG_X7:  7,
   236  	REG_X8:  8,
   237  	REG_X9:  9,
   238  	REG_X10: 10,
   239  	REG_X11: 11,
   240  	REG_X12: 12,
   241  	REG_X13: 13,
   242  	REG_X14: 14,
   243  	REG_X15: 15,
   244  	REG_X16: 16,
   245  	REG_X17: 17,
   246  	REG_X18: 18,
   247  	REG_X19: 19,
   248  	REG_X20: 20,
   249  	REG_X21: 21,
   250  	REG_X22: 22,
   251  	REG_X23: 23,
   252  	REG_X24: 24,
   253  	REG_X25: 25,
   254  	REG_X26: 26,
   255  	REG_X27: 27,
   256  	REG_X28: 28,
   257  	REG_X29: 29,
   258  	REG_X30: 30,
   259  	REG_X31: 31,
   260  
   261  	// Floating-Point Registers.
   262  	REG_F0:  32,
   263  	REG_F1:  33,
   264  	REG_F2:  34,
   265  	REG_F3:  35,
   266  	REG_F4:  36,
   267  	REG_F5:  37,
   268  	REG_F6:  38,
   269  	REG_F7:  39,
   270  	REG_F8:  40,
   271  	REG_F9:  41,
   272  	REG_F10: 42,
   273  	REG_F11: 43,
   274  	REG_F12: 44,
   275  	REG_F13: 45,
   276  	REG_F14: 46,
   277  	REG_F15: 47,
   278  	REG_F16: 48,
   279  	REG_F17: 49,
   280  	REG_F18: 50,
   281  	REG_F19: 51,
   282  	REG_F20: 52,
   283  	REG_F21: 53,
   284  	REG_F22: 54,
   285  	REG_F23: 55,
   286  	REG_F24: 56,
   287  	REG_F25: 57,
   288  	REG_F26: 58,
   289  	REG_F27: 59,
   290  	REG_F28: 60,
   291  	REG_F29: 61,
   292  	REG_F30: 62,
   293  	REG_F31: 63,
   294  }
   295  
   296  // Prog.Mark flags.
   297  const (
   298  	// USES_REG_TMP indicates that a machine instruction generated from the
   299  	// corresponding *obj.Prog uses the temporary register.
   300  	USES_REG_TMP = 1 << iota
   301  
   302  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   303  	// R_RISCV_JAL relocation is needed.
   304  	NEED_JAL_RELOC
   305  
   306  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   307  	// is the first instruction in an AUIPC + JAL pair that needs a
   308  	// R_RISCV_CALL relocation.
   309  	NEED_CALL_RELOC
   310  
   311  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   312  	// it is the first instruction in an AUIPC + I-type pair that needs a
   313  	// R_RISCV_PCREL_ITYPE relocation.
   314  	NEED_PCREL_ITYPE_RELOC
   315  
   316  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   317  	// it is the first instruction in an AUIPC + S-type pair that needs a
   318  	// R_RISCV_PCREL_STYPE relocation.
   319  	NEED_PCREL_STYPE_RELOC
   320  
   321  	// NEED_GOT_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   322  	// it is the first instruction in an AUIPC + I-type pair that needs a
   323  	// R_RISCV_GOT_PCREL_ITYPE relocation.
   324  	NEED_GOT_PCREL_ITYPE_RELOC
   325  )
   326  
   327  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   328  // at https://github.com/riscv/riscv-opcodes.
   329  //
   330  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   331  //
   332  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
   333  //
   334  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   335  const (
   336  	//
   337  	// Unprivileged ISA (version 20240411)
   338  	//
   339  
   340  	// 2.4: Integer Computational Instructions
   341  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   342  	ASLTI
   343  	ASLTIU
   344  	AANDI
   345  	AORI
   346  	AXORI
   347  	ASLLI
   348  	ASRLI
   349  	ASRAI
   350  	ALUI
   351  	AAUIPC
   352  	AADD
   353  	ASLT
   354  	ASLTU
   355  	AAND
   356  	AOR
   357  	AXOR
   358  	ASLL
   359  	ASRL
   360  	ASUB
   361  	ASRA
   362  
   363  	// 2.5: Control Transfer Instructions
   364  	AJAL
   365  	AJALR
   366  	ABEQ
   367  	ABNE
   368  	ABLT
   369  	ABLTU
   370  	ABGE
   371  	ABGEU
   372  
   373  	// 2.6: Load and Store Instructions
   374  	ALW
   375  	ALWU
   376  	ALH
   377  	ALHU
   378  	ALB
   379  	ALBU
   380  	ASW
   381  	ASH
   382  	ASB
   383  
   384  	// 2.7: Memory Ordering Instructions
   385  	AFENCE
   386  
   387  	// 4.2: Integer Computational Instructions (RV64I)
   388  	AADDIW
   389  	ASLLIW
   390  	ASRLIW
   391  	ASRAIW
   392  	AADDW
   393  	ASLLW
   394  	ASRLW
   395  	ASUBW
   396  	ASRAW
   397  
   398  	// 4.3: Load and Store Instructions (RV64I)
   399  	ALD
   400  	ASD
   401  
   402  	// 7.1: CSR Instructions (Zicsr)
   403  	ACSRRW
   404  	ACSRRS
   405  	ACSRRC
   406  	ACSRRWI
   407  	ACSRRSI
   408  	ACSRRCI
   409  
   410  	// 13.1: Multiplication Operations
   411  	AMUL
   412  	AMULH
   413  	AMULHU
   414  	AMULHSU
   415  	AMULW
   416  
   417  	// 13.2: Division Operations
   418  	ADIV
   419  	ADIVU
   420  	AREM
   421  	AREMU
   422  	ADIVW
   423  	ADIVUW
   424  	AREMW
   425  	AREMUW
   426  
   427  	// 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
   428  	ALRD
   429  	ASCD
   430  	ALRW
   431  	ASCW
   432  
   433  	// 14.4: Atomic Memory Operations (Zaamo)
   434  	AAMOSWAPD
   435  	AAMOADDD
   436  	AAMOANDD
   437  	AAMOORD
   438  	AAMOXORD
   439  	AAMOMAXD
   440  	AAMOMAXUD
   441  	AAMOMIND
   442  	AAMOMINUD
   443  	AAMOSWAPW
   444  	AAMOADDW
   445  	AAMOANDW
   446  	AAMOORW
   447  	AAMOXORW
   448  	AAMOMAXW
   449  	AAMOMAXUW
   450  	AAMOMINW
   451  	AAMOMINUW
   452  
   453  	// 20.5: Single-Precision Load and Store Instructions
   454  	AFLW
   455  	AFSW
   456  
   457  	// 20.6: Single-Precision Floating-Point Computational Instructions
   458  	AFADDS
   459  	AFSUBS
   460  	AFMULS
   461  	AFDIVS
   462  	AFMINS
   463  	AFMAXS
   464  	AFSQRTS
   465  	AFMADDS
   466  	AFMSUBS
   467  	AFNMADDS
   468  	AFNMSUBS
   469  
   470  	// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
   471  	AFCVTWS
   472  	AFCVTLS
   473  	AFCVTSW
   474  	AFCVTSL
   475  	AFCVTWUS
   476  	AFCVTLUS
   477  	AFCVTSWU
   478  	AFCVTSLU
   479  	AFSGNJS
   480  	AFSGNJNS
   481  	AFSGNJXS
   482  	AFMVXS
   483  	AFMVSX
   484  	AFMVXW
   485  	AFMVWX
   486  
   487  	// 20.8: Single-Precision Floating-Point Compare Instructions
   488  	AFEQS
   489  	AFLTS
   490  	AFLES
   491  
   492  	// 20.9: Single-Precision Floating-Point Classify Instruction
   493  	AFCLASSS
   494  
   495  	// 21.3: Double-Precision Load and Store Instructions
   496  	AFLD
   497  	AFSD
   498  
   499  	// 21.4: Double-Precision Floating-Point Computational Instructions
   500  	AFADDD
   501  	AFSUBD
   502  	AFMULD
   503  	AFDIVD
   504  	AFMIND
   505  	AFMAXD
   506  	AFSQRTD
   507  	AFMADDD
   508  	AFMSUBD
   509  	AFNMADDD
   510  	AFNMSUBD
   511  
   512  	// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
   513  	AFCVTWD
   514  	AFCVTLD
   515  	AFCVTDW
   516  	AFCVTDL
   517  	AFCVTWUD
   518  	AFCVTLUD
   519  	AFCVTDWU
   520  	AFCVTDLU
   521  	AFCVTSD
   522  	AFCVTDS
   523  	AFSGNJD
   524  	AFSGNJND
   525  	AFSGNJXD
   526  	AFMVXD
   527  	AFMVDX
   528  
   529  	// 21.6: Double-Precision Floating-Point Compare Instructions
   530  	AFEQD
   531  	AFLTD
   532  	AFLED
   533  
   534  	// 21.7: Double-Precision Floating-Point Classify Instruction
   535  	AFCLASSD
   536  
   537  	// 22.1 Quad-Precision Load and Store Instructions
   538  	AFLQ
   539  	AFSQ
   540  
   541  	// 22.2: Quad-Precision Computational Instructions
   542  	AFADDQ
   543  	AFSUBQ
   544  	AFMULQ
   545  	AFDIVQ
   546  	AFMINQ
   547  	AFMAXQ
   548  	AFSQRTQ
   549  	AFMADDQ
   550  	AFMSUBQ
   551  	AFNMADDQ
   552  	AFNMSUBQ
   553  
   554  	// 22.3 Quad-Precision Convert and Move Instructions
   555  	AFCVTWQ
   556  	AFCVTLQ
   557  	AFCVTSQ
   558  	AFCVTDQ
   559  	AFCVTQW
   560  	AFCVTQL
   561  	AFCVTQS
   562  	AFCVTQD
   563  	AFCVTWUQ
   564  	AFCVTLUQ
   565  	AFCVTQWU
   566  	AFCVTQLU
   567  	AFSGNJQ
   568  	AFSGNJNQ
   569  	AFSGNJXQ
   570  
   571  	// 22.4 Quad-Precision Floating-Point Compare Instructions
   572  	AFEQQ
   573  	AFLEQ
   574  	AFLTQ
   575  
   576  	// 22.5 Quad-Precision Floating-Point Classify Instruction
   577  	AFCLASSQ
   578  
   579  	//
   580  	// "B" Extension for Bit Manipulation, Version 1.0.0
   581  	//
   582  
   583  	// 28.4.1: Address Generation Instructions (Zba)
   584  	AADDUW
   585  	ASH1ADD
   586  	ASH1ADDUW
   587  	ASH2ADD
   588  	ASH2ADDUW
   589  	ASH3ADD
   590  	ASH3ADDUW
   591  	ASLLIUW
   592  
   593  	// 28.4.2: Basic Bit Manipulation (Zbb)
   594  	AANDN
   595  	AORN
   596  	AXNOR
   597  	ACLZ
   598  	ACLZW
   599  	ACTZ
   600  	ACTZW
   601  	ACPOP
   602  	ACPOPW
   603  	AMAX
   604  	AMAXU
   605  	AMIN
   606  	AMINU
   607  	ASEXTB
   608  	ASEXTH
   609  	AZEXTH
   610  
   611  	// 28.4.3: Bitwise Rotation (Zbb)
   612  	AROL
   613  	AROLW
   614  	AROR
   615  	ARORI
   616  	ARORIW
   617  	ARORW
   618  	AORCB
   619  	AREV8
   620  
   621  	// 28.4.4: Single-bit Instructions (Zbs)
   622  	ABCLR
   623  	ABCLRI
   624  	ABEXT
   625  	ABEXTI
   626  	ABINV
   627  	ABINVI
   628  	ABSET
   629  	ABSETI
   630  
   631  	//
   632  	// "V" Standard Extension for Vector Operations, Version 1.0
   633  	//
   634  
   635  	// 31.6: Configuration-Setting Instructions
   636  	AVSETVLI
   637  	AVSETIVLI
   638  	AVSETVL
   639  
   640  	// 31.7.4: Vector Unit-Stride Instructions
   641  	AVLE8V
   642  	AVLE16V
   643  	AVLE32V
   644  	AVLE64V
   645  	AVSE8V
   646  	AVSE16V
   647  	AVSE32V
   648  	AVSE64V
   649  	AVLMV
   650  	AVSMV
   651  
   652  	// 31.7.5: Vector Strided Instructions
   653  	AVLSE8V
   654  	AVLSE16V
   655  	AVLSE32V
   656  	AVLSE64V
   657  	AVSSE8V
   658  	AVSSE16V
   659  	AVSSE32V
   660  	AVSSE64V
   661  
   662  	// 31.7.6: Vector Indexed Instructions
   663  	AVLUXEI8V
   664  	AVLUXEI16V
   665  	AVLUXEI32V
   666  	AVLUXEI64V
   667  	AVLOXEI8V
   668  	AVLOXEI16V
   669  	AVLOXEI32V
   670  	AVLOXEI64V
   671  	AVSUXEI8V
   672  	AVSUXEI16V
   673  	AVSUXEI32V
   674  	AVSUXEI64V
   675  	AVSOXEI8V
   676  	AVSOXEI16V
   677  	AVSOXEI32V
   678  	AVSOXEI64V
   679  
   680  	// 31.7.7: Unit-stride Fault-Only-First Loads
   681  	AVLE8FFV
   682  	AVLE16FFV
   683  	AVLE32FFV
   684  	AVLE64FFV
   685  
   686  	// 31.7.9: Vector Load/Store Whole Register Instructions
   687  	AVL1RE8V
   688  	AVL1RE16V
   689  	AVL1RE32V
   690  	AVL1RE64V
   691  	AVL2RE8V
   692  	AVL2RE16V
   693  	AVL2RE32V
   694  	AVL2RE64V
   695  	AVL4RE8V
   696  	AVL4RE16V
   697  	AVL4RE32V
   698  	AVL4RE64V
   699  	AVL8RE8V
   700  	AVL8RE16V
   701  	AVL8RE32V
   702  	AVL8RE64V
   703  	AVS1RV
   704  	AVS2RV
   705  	AVS4RV
   706  	AVS8RV
   707  
   708  	// 31.11.1: Vector Single-Width Integer Add and Subtract
   709  	AVADDVV
   710  	AVADDVX
   711  	AVADDVI
   712  	AVSUBVV
   713  	AVSUBVX
   714  	AVRSUBVX
   715  	AVRSUBVI
   716  
   717  	// 31.11.2: Vector Widening Integer Add/Subtract
   718  	AVWADDUVV
   719  	AVWADDUVX
   720  	AVWSUBUVV
   721  	AVWSUBUVX
   722  	AVWADDVV
   723  	AVWADDVX
   724  	AVWSUBVV
   725  	AVWSUBVX
   726  	AVWADDUWV
   727  	AVWADDUWX
   728  	AVWSUBUWV
   729  	AVWSUBUWX
   730  	AVWADDWV
   731  	AVWADDWX
   732  	AVWSUBWV
   733  	AVWSUBWX
   734  
   735  	// 31.11.3: Vector Integer Extension
   736  	AVZEXTVF2
   737  	AVSEXTVF2
   738  	AVZEXTVF4
   739  	AVSEXTVF4
   740  	AVZEXTVF8
   741  	AVSEXTVF8
   742  
   743  	// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
   744  	AVADCVVM
   745  	AVADCVXM
   746  	AVADCVIM
   747  	AVMADCVVM
   748  	AVMADCVXM
   749  	AVMADCVIM
   750  	AVMADCVV
   751  	AVMADCVX
   752  	AVMADCVI
   753  	AVSBCVVM
   754  	AVSBCVXM
   755  	AVMSBCVVM
   756  	AVMSBCVXM
   757  	AVMSBCVV
   758  	AVMSBCVX
   759  
   760  	// 31.11.5: Vector Bitwise Logical Instructions
   761  	AVANDVV
   762  	AVANDVX
   763  	AVANDVI
   764  	AVORVV
   765  	AVORVX
   766  	AVORVI
   767  	AVXORVV
   768  	AVXORVX
   769  	AVXORVI
   770  
   771  	// 31.11.6: Vector Single-Width Shift Instructions
   772  	AVSLLVV
   773  	AVSLLVX
   774  	AVSLLVI
   775  	AVSRLVV
   776  	AVSRLVX
   777  	AVSRLVI
   778  	AVSRAVV
   779  	AVSRAVX
   780  	AVSRAVI
   781  
   782  	// 31.11.7: Vector Narrowing Integer Right Shift Instructions
   783  	AVNSRLWV
   784  	AVNSRLWX
   785  	AVNSRLWI
   786  	AVNSRAWV
   787  	AVNSRAWX
   788  	AVNSRAWI
   789  
   790  	// 31.11.8: Vector Integer Compare Instructions
   791  	AVMSEQVV
   792  	AVMSEQVX
   793  	AVMSEQVI
   794  	AVMSNEVV
   795  	AVMSNEVX
   796  	AVMSNEVI
   797  	AVMSLTUVV
   798  	AVMSLTUVX
   799  	AVMSLTVV
   800  	AVMSLTVX
   801  	AVMSLEUVV
   802  	AVMSLEUVX
   803  	AVMSLEUVI
   804  	AVMSLEVV
   805  	AVMSLEVX
   806  	AVMSLEVI
   807  	AVMSGTUVX
   808  	AVMSGTUVI
   809  	AVMSGTVX
   810  	AVMSGTVI
   811  
   812  	// 31.11.9: Vector Integer Min/Max Instructions
   813  	AVMINUVV
   814  	AVMINUVX
   815  	AVMINVV
   816  	AVMINVX
   817  	AVMAXUVV
   818  	AVMAXUVX
   819  	AVMAXVV
   820  	AVMAXVX
   821  
   822  	// 31.11.10: Vector Single-Width Integer Multiply Instructions
   823  	AVMULVV
   824  	AVMULVX
   825  	AVMULHVV
   826  	AVMULHVX
   827  	AVMULHUVV
   828  	AVMULHUVX
   829  	AVMULHSUVV
   830  	AVMULHSUVX
   831  
   832  	// 31.11.11: Vector Integer Divide Instructions
   833  	AVDIVUVV
   834  	AVDIVUVX
   835  	AVDIVVV
   836  	AVDIVVX
   837  	AVREMUVV
   838  	AVREMUVX
   839  	AVREMVV
   840  	AVREMVX
   841  
   842  	// 31.11.12: Vector Widening Integer Multiply Instructions
   843  	AVWMULVV
   844  	AVWMULVX
   845  	AVWMULUVV
   846  	AVWMULUVX
   847  	AVWMULSUVV
   848  	AVWMULSUVX
   849  
   850  	// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
   851  	AVMACCVV
   852  	AVMACCVX
   853  	AVNMSACVV
   854  	AVNMSACVX
   855  	AVMADDVV
   856  	AVMADDVX
   857  	AVNMSUBVV
   858  	AVNMSUBVX
   859  
   860  	// 31.11.14: Vector Widening Integer Multiply-Add Instructions
   861  	AVWMACCUVV
   862  	AVWMACCUVX
   863  	AVWMACCVV
   864  	AVWMACCVX
   865  	AVWMACCSUVV
   866  	AVWMACCSUVX
   867  	AVWMACCUSVX
   868  
   869  	// 31.11.15: Vector Integer Merge Instructions
   870  	AVMERGEVVM
   871  	AVMERGEVXM
   872  	AVMERGEVIM
   873  
   874  	// 31.11.16: Vector Integer Move Instructions
   875  	AVMVVV
   876  	AVMVVX
   877  	AVMVVI
   878  
   879  	// 31.12.1: Vector Single-Width Saturating Add and Subtract
   880  	AVSADDUVV
   881  	AVSADDUVX
   882  	AVSADDUVI
   883  	AVSADDVV
   884  	AVSADDVX
   885  	AVSADDVI
   886  	AVSSUBUVV
   887  	AVSSUBUVX
   888  	AVSSUBVV
   889  	AVSSUBVX
   890  
   891  	// 31.12.2: Vector Single-Width Averaging Add and Subtract
   892  	AVAADDUVV
   893  	AVAADDUVX
   894  	AVAADDVV
   895  	AVAADDVX
   896  	AVASUBUVV
   897  	AVASUBUVX
   898  	AVASUBVV
   899  	AVASUBVX
   900  
   901  	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
   902  	AVSMULVV
   903  	AVSMULVX
   904  
   905  	// 31.12.4: Vector Single-Width Scaling Shift Instructions
   906  	AVSSRLVV
   907  	AVSSRLVX
   908  	AVSSRLVI
   909  	AVSSRAVV
   910  	AVSSRAVX
   911  	AVSSRAVI
   912  
   913  	// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
   914  	AVNCLIPUWV
   915  	AVNCLIPUWX
   916  	AVNCLIPUWI
   917  	AVNCLIPWV
   918  	AVNCLIPWX
   919  	AVNCLIPWI
   920  
   921  	// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
   922  	AVFADDVV
   923  	AVFADDVF
   924  	AVFSUBVV
   925  	AVFSUBVF
   926  	AVFRSUBVF
   927  
   928  	// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
   929  	AVFWADDVV
   930  	AVFWADDVF
   931  	AVFWSUBVV
   932  	AVFWSUBVF
   933  	AVFWADDWV
   934  	AVFWADDWF
   935  	AVFWSUBWV
   936  	AVFWSUBWF
   937  
   938  	// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
   939  	AVFMULVV
   940  	AVFMULVF
   941  	AVFDIVVV
   942  	AVFDIVVF
   943  	AVFRDIVVF
   944  
   945  	// 31.13.5: Vector Widening Floating-Point Multiply
   946  	AVFWMULVV
   947  	AVFWMULVF
   948  
   949  	// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
   950  	AVFMACCVV
   951  	AVFMACCVF
   952  	AVFNMACCVV
   953  	AVFNMACCVF
   954  	AVFMSACVV
   955  	AVFMSACVF
   956  	AVFNMSACVV
   957  	AVFNMSACVF
   958  	AVFMADDVV
   959  	AVFMADDVF
   960  	AVFNMADDVV
   961  	AVFNMADDVF
   962  	AVFMSUBVV
   963  	AVFMSUBVF
   964  	AVFNMSUBVV
   965  	AVFNMSUBVF
   966  
   967  	// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
   968  	AVFWMACCVV
   969  	AVFWMACCVF
   970  	AVFWNMACCVV
   971  	AVFWNMACCVF
   972  	AVFWMSACVV
   973  	AVFWMSACVF
   974  	AVFWNMSACVV
   975  	AVFWNMSACVF
   976  
   977  	// 31.13.8: Vector Floating-Point Square-Root Instruction
   978  	AVFSQRTV
   979  
   980  	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
   981  	AVFRSQRT7V
   982  
   983  	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
   984  	AVFREC7V
   985  
   986  	// 31.13.11: Vector Floating-Point MIN/MAX Instructions
   987  	AVFMINVV
   988  	AVFMINVF
   989  	AVFMAXVV
   990  	AVFMAXVF
   991  
   992  	// 31.13.12: Vector Floating-Point Sign-Injection Instructions
   993  	AVFSGNJVV
   994  	AVFSGNJVF
   995  	AVFSGNJNVV
   996  	AVFSGNJNVF
   997  	AVFSGNJXVV
   998  	AVFSGNJXVF
   999  
  1000  	// 31.13.13: Vector Floating-Point Compare Instructions
  1001  	AVMFEQVV
  1002  	AVMFEQVF
  1003  	AVMFNEVV
  1004  	AVMFNEVF
  1005  	AVMFLTVV
  1006  	AVMFLTVF
  1007  	AVMFLEVV
  1008  	AVMFLEVF
  1009  	AVMFGTVF
  1010  	AVMFGEVF
  1011  
  1012  	// 31.13.14: Vector Floating-Point Classify Instruction
  1013  	AVFCLASSV
  1014  
  1015  	// 31.13.15: Vector Floating-Point Merge Instruction
  1016  	AVFMERGEVFM
  1017  
  1018  	// 31.13.16: Vector Floating-Point Move Instruction
  1019  	AVFMVVF
  1020  
  1021  	// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
  1022  	AVFCVTXUFV
  1023  	AVFCVTXFV
  1024  	AVFCVTRTZXUFV
  1025  	AVFCVTRTZXFV
  1026  	AVFCVTFXUV
  1027  	AVFCVTFXV
  1028  
  1029  	// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
  1030  	AVFWCVTXUFV
  1031  	AVFWCVTXFV
  1032  	AVFWCVTRTZXUFV
  1033  	AVFWCVTRTZXFV
  1034  	AVFWCVTFXUV
  1035  	AVFWCVTFXV
  1036  	AVFWCVTFFV
  1037  
  1038  	// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
  1039  	AVFNCVTXUFW
  1040  	AVFNCVTXFW
  1041  	AVFNCVTRTZXUFW
  1042  	AVFNCVTRTZXFW
  1043  	AVFNCVTFXUW
  1044  	AVFNCVTFXW
  1045  	AVFNCVTFFW
  1046  	AVFNCVTRODFFW
  1047  
  1048  	// 31.14.1: Vector Single-Width Integer Reduction Instructions
  1049  	AVREDSUMVS
  1050  	AVREDMAXUVS
  1051  	AVREDMAXVS
  1052  	AVREDMINUVS
  1053  	AVREDMINVS
  1054  	AVREDANDVS
  1055  	AVREDORVS
  1056  	AVREDXORVS
  1057  
  1058  	// 31.14.2: Vector Widening Integer Reduction Instructions
  1059  	AVWREDSUMUVS
  1060  	AVWREDSUMVS
  1061  
  1062  	// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
  1063  	AVFREDOSUMVS
  1064  	AVFREDUSUMVS
  1065  	AVFREDMAXVS
  1066  	AVFREDMINVS
  1067  
  1068  	// 31.14.4: Vector Widening Floating-Point Reduction Instructions
  1069  	AVFWREDOSUMVS
  1070  	AVFWREDUSUMVS
  1071  
  1072  	// 31.15: Vector Mask Instructions
  1073  	AVMANDMM
  1074  	AVMNANDMM
  1075  	AVMANDNMM
  1076  	AVMXORMM
  1077  	AVMORMM
  1078  	AVMNORMM
  1079  	AVMORNMM
  1080  	AVMXNORMM
  1081  	AVCPOPM
  1082  	AVFIRSTM
  1083  	AVMSBFM
  1084  	AVMSIFM
  1085  	AVMSOFM
  1086  	AVIOTAM
  1087  	AVIDV
  1088  
  1089  	// 31.16.1: Integer Scalar Move Instructions
  1090  	AVMVXS
  1091  	AVMVSX
  1092  
  1093  	// 31.16.2: Floating-Point Scalar Move Instructions
  1094  	AVFMVFS
  1095  	AVFMVSF
  1096  
  1097  	// 31.16.3: Vector Slide Instructions
  1098  	AVSLIDEUPVX
  1099  	AVSLIDEUPVI
  1100  	AVSLIDEDOWNVX
  1101  	AVSLIDEDOWNVI
  1102  	AVSLIDE1UPVX
  1103  	AVFSLIDE1UPVF
  1104  	AVSLIDE1DOWNVX
  1105  	AVFSLIDE1DOWNVF
  1106  
  1107  	// 31.16.4: Vector Register Gather Instructions
  1108  	AVRGATHERVV
  1109  	AVRGATHEREI16VV
  1110  	AVRGATHERVX
  1111  	AVRGATHERVI
  1112  
  1113  	// 31.16.5: Vector Compress Instruction
  1114  	AVCOMPRESSVM
  1115  
  1116  	// 31.16.6: Whole Vector Register Move
  1117  	AVMV1RV
  1118  	AVMV2RV
  1119  	AVMV4RV
  1120  	AVMV8RV
  1121  
  1122  	//
  1123  	// Privileged ISA (version 20240411)
  1124  	//
  1125  
  1126  	// 3.3.1: Environment Call and Breakpoint
  1127  	AECALL
  1128  	ASCALL
  1129  	AEBREAK
  1130  	ASBREAK
  1131  
  1132  	// 3.3.2: Trap-Return Instructions
  1133  	AMRET
  1134  	ASRET
  1135  	ADRET
  1136  
  1137  	// 3.3.3: Wait for Interrupt
  1138  	AWFI
  1139  
  1140  	// 10.2: Supervisor Memory-Management Fence Instruction
  1141  	ASFENCEVMA
  1142  
  1143  	// The escape hatch. Inserts a single 32-bit word.
  1144  	AWORD
  1145  
  1146  	// Pseudo-instructions.  These get translated by the assembler into other
  1147  	// instructions, based on their operands.
  1148  	ABEQZ
  1149  	ABGEZ
  1150  	ABGT
  1151  	ABGTU
  1152  	ABGTZ
  1153  	ABLE
  1154  	ABLEU
  1155  	ABLEZ
  1156  	ABLTZ
  1157  	ABNEZ
  1158  	AFABSD
  1159  	AFABSS
  1160  	AFNED
  1161  	AFNEGD
  1162  	AFNEGS
  1163  	AFNES
  1164  	AMOV
  1165  	AMOVB
  1166  	AMOVBU
  1167  	AMOVD
  1168  	AMOVF
  1169  	AMOVH
  1170  	AMOVHU
  1171  	AMOVW
  1172  	AMOVWU
  1173  	ANEG
  1174  	ANEGW
  1175  	ANOT
  1176  	ARDCYCLE
  1177  	ARDINSTRET
  1178  	ARDTIME
  1179  	ASEQZ
  1180  	ASNEZ
  1181  
  1182  	// End marker
  1183  	ALAST
  1184  )
  1185  
  1186  // opSuffix encoding to uint8 which fit into p.Scond
  1187  var rmSuffixSet = map[string]uint8{
  1188  	"RNE": RM_RNE,
  1189  	"RTZ": RM_RTZ,
  1190  	"RDN": RM_RDN,
  1191  	"RUP": RM_RUP,
  1192  	"RMM": RM_RMM,
  1193  }
  1194  
  1195  const rmSuffixBit uint8 = 1 << 7
  1196  
  1197  func rmSuffixEncode(s string) (uint8, error) {
  1198  	if s == "" {
  1199  		return 0, errors.New("empty suffix")
  1200  	}
  1201  	enc, ok := rmSuffixSet[s]
  1202  	if !ok {
  1203  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
  1204  	}
  1205  	return enc | rmSuffixBit, nil
  1206  }
  1207  
  1208  func rmSuffixString(u uint8) (string, error) {
  1209  	if u&rmSuffixBit == 0 {
  1210  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
  1211  	}
  1212  
  1213  	u &^= rmSuffixBit
  1214  	for k, v := range rmSuffixSet {
  1215  		if v == u {
  1216  			return k, nil
  1217  		}
  1218  	}
  1219  	return "", fmt.Errorf("unknown suffix:%x", u)
  1220  }
  1221  
  1222  const (
  1223  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
  1224  	RM_RTZ              // Round towards Zero
  1225  	RM_RDN              // Round Down
  1226  	RM_RUP              // Round Up
  1227  	RM_RMM              // Round to Nearest, ties to Max Magnitude
  1228  )
  1229  
  1230  type SpecialOperand int
  1231  
  1232  const (
  1233  	SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase
  1234  
  1235  	// Vector mask policy.
  1236  	SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 1
  1237  	SPOP_MU
  1238  
  1239  	// Vector tail policy.
  1240  	SPOP_TA
  1241  	SPOP_TU
  1242  
  1243  	// Vector register group multiplier (VLMUL).
  1244  	SPOP_M1
  1245  	SPOP_M2
  1246  	SPOP_M4
  1247  	SPOP_M8
  1248  	SPOP_MF2
  1249  	SPOP_MF4
  1250  	SPOP_MF8
  1251  
  1252  	// Vector selected element width (VSEW).
  1253  	SPOP_E8
  1254  	SPOP_E16
  1255  	SPOP_E32
  1256  	SPOP_E64
  1257  
  1258  	SPOP_END
  1259  )
  1260  
  1261  var specialOperands = map[SpecialOperand]struct {
  1262  	encoding uint32
  1263  	name     string
  1264  }{
  1265  	SPOP_MA: {encoding: 1, name: "MA"},
  1266  	SPOP_MU: {encoding: 0, name: "MU"},
  1267  
  1268  	SPOP_TA: {encoding: 1, name: "TA"},
  1269  	SPOP_TU: {encoding: 0, name: "TU"},
  1270  
  1271  	SPOP_M1:  {encoding: 0, name: "M1"},
  1272  	SPOP_M2:  {encoding: 1, name: "M2"},
  1273  	SPOP_M4:  {encoding: 2, name: "M4"},
  1274  	SPOP_M8:  {encoding: 3, name: "M8"},
  1275  	SPOP_MF2: {encoding: 5, name: "MF2"},
  1276  	SPOP_MF4: {encoding: 6, name: "MF4"},
  1277  	SPOP_MF8: {encoding: 7, name: "MF8"},
  1278  
  1279  	SPOP_E8:  {encoding: 0, name: "E8"},
  1280  	SPOP_E16: {encoding: 1, name: "E16"},
  1281  	SPOP_E32: {encoding: 2, name: "E32"},
  1282  	SPOP_E64: {encoding: 3, name: "E64"},
  1283  }
  1284  
  1285  func (so SpecialOperand) encode() uint32 {
  1286  	op, ok := specialOperands[so]
  1287  	if ok {
  1288  		return op.encoding
  1289  	}
  1290  	return 0
  1291  }
  1292  
  1293  func (so SpecialOperand) String() string {
  1294  	op, ok := specialOperands[so]
  1295  	if ok {
  1296  		return op.name
  1297  	}
  1298  	return ""
  1299  }
  1300  
  1301  // All unary instructions which write to their arguments (as opposed to reading
  1302  // from them) go here. The assembly parser uses this information to populate
  1303  // its AST in a semantically reasonable way.
  1304  //
  1305  // Any instructions not listed here are assumed to either be non-unary or to read
  1306  // from its argument.
  1307  var unaryDst = map[obj.As]bool{
  1308  	ARDCYCLE:   true,
  1309  	ARDTIME:    true,
  1310  	ARDINSTRET: true,
  1311  }
  1312  
  1313  // Instruction encoding masks.
  1314  const (
  1315  	// BTypeImmMask is a mask including only the immediate portion of
  1316  	// B-type instructions.
  1317  	BTypeImmMask = 0xfe000f80
  1318  
  1319  	// CBTypeImmMask is a mask including only the immediate portion of
  1320  	// CB-type instructions.
  1321  	CBTypeImmMask = 0x1c7c
  1322  
  1323  	// CJTypeImmMask is a mask including only the immediate portion of
  1324  	// CJ-type instructions.
  1325  	CJTypeImmMask = 0x1f7c
  1326  
  1327  	// ITypeImmMask is a mask including only the immediate portion of
  1328  	// I-type instructions.
  1329  	ITypeImmMask = 0xfff00000
  1330  
  1331  	// JTypeImmMask is a mask including only the immediate portion of
  1332  	// J-type instructions.
  1333  	JTypeImmMask = 0xfffff000
  1334  
  1335  	// STypeImmMask is a mask including only the immediate portion of
  1336  	// S-type instructions.
  1337  	STypeImmMask = 0xfe000f80
  1338  
  1339  	// UTypeImmMask is a mask including only the immediate portion of
  1340  	// U-type instructions.
  1341  	UTypeImmMask = 0xfffff000
  1342  )
  1343  

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