Source file src/cmd/internal/obj/riscv/cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  var CSRs map[uint16]string = csrs
    39  
    40  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    41  
    42  const (
    43  	// Base register numberings.
    44  	REG_X0 = obj.RBaseRISCV + iota
    45  	REG_X1
    46  	REG_X2
    47  	REG_X3
    48  	REG_X4
    49  	REG_X5
    50  	REG_X6
    51  	REG_X7
    52  	REG_X8
    53  	REG_X9
    54  	REG_X10
    55  	REG_X11
    56  	REG_X12
    57  	REG_X13
    58  	REG_X14
    59  	REG_X15
    60  	REG_X16
    61  	REG_X17
    62  	REG_X18
    63  	REG_X19
    64  	REG_X20
    65  	REG_X21
    66  	REG_X22
    67  	REG_X23
    68  	REG_X24
    69  	REG_X25
    70  	REG_X26
    71  	REG_X27
    72  	REG_X28
    73  	REG_X29
    74  	REG_X30
    75  	REG_X31
    76  
    77  	// Floating Point register numberings.
    78  	REG_F0
    79  	REG_F1
    80  	REG_F2
    81  	REG_F3
    82  	REG_F4
    83  	REG_F5
    84  	REG_F6
    85  	REG_F7
    86  	REG_F8
    87  	REG_F9
    88  	REG_F10
    89  	REG_F11
    90  	REG_F12
    91  	REG_F13
    92  	REG_F14
    93  	REG_F15
    94  	REG_F16
    95  	REG_F17
    96  	REG_F18
    97  	REG_F19
    98  	REG_F20
    99  	REG_F21
   100  	REG_F22
   101  	REG_F23
   102  	REG_F24
   103  	REG_F25
   104  	REG_F26
   105  	REG_F27
   106  	REG_F28
   107  	REG_F29
   108  	REG_F30
   109  	REG_F31
   110  
   111  	// Vector register numberings.
   112  	REG_V0
   113  	REG_V1
   114  	REG_V2
   115  	REG_V3
   116  	REG_V4
   117  	REG_V5
   118  	REG_V6
   119  	REG_V7
   120  	REG_V8
   121  	REG_V9
   122  	REG_V10
   123  	REG_V11
   124  	REG_V12
   125  	REG_V13
   126  	REG_V14
   127  	REG_V15
   128  	REG_V16
   129  	REG_V17
   130  	REG_V18
   131  	REG_V19
   132  	REG_V20
   133  	REG_V21
   134  	REG_V22
   135  	REG_V23
   136  	REG_V24
   137  	REG_V25
   138  	REG_V26
   139  	REG_V27
   140  	REG_V28
   141  	REG_V29
   142  	REG_V30
   143  	REG_V31
   144  
   145  	// This marks the end of the register numbering.
   146  	REG_END
   147  
   148  	// General registers reassigned to ABI names.
   149  	REG_ZERO = REG_X0
   150  	REG_RA   = REG_X1 // aka REG_LR
   151  	REG_SP   = REG_X2
   152  	REG_GP   = REG_X3 // aka REG_SB
   153  	REG_TP   = REG_X4
   154  	REG_T0   = REG_X5
   155  	REG_T1   = REG_X6
   156  	REG_T2   = REG_X7
   157  	REG_S0   = REG_X8
   158  	REG_S1   = REG_X9
   159  	REG_A0   = REG_X10
   160  	REG_A1   = REG_X11
   161  	REG_A2   = REG_X12
   162  	REG_A3   = REG_X13
   163  	REG_A4   = REG_X14
   164  	REG_A5   = REG_X15
   165  	REG_A6   = REG_X16
   166  	REG_A7   = REG_X17
   167  	REG_S2   = REG_X18
   168  	REG_S3   = REG_X19
   169  	REG_S4   = REG_X20
   170  	REG_S5   = REG_X21
   171  	REG_S6   = REG_X22
   172  	REG_S7   = REG_X23
   173  	REG_S8   = REG_X24
   174  	REG_S9   = REG_X25
   175  	REG_S10  = REG_X26 // aka REG_CTXT
   176  	REG_S11  = REG_X27 // aka REG_G
   177  	REG_T3   = REG_X28
   178  	REG_T4   = REG_X29
   179  	REG_T5   = REG_X30
   180  	REG_T6   = REG_X31 // aka REG_TMP
   181  
   182  	// Go runtime register names.
   183  	REG_CTXT = REG_S10 // Context for closures.
   184  	REG_G    = REG_S11 // G pointer.
   185  	REG_LR   = REG_RA  // Link register.
   186  	REG_TMP  = REG_T6  // Reserved for assembler use.
   187  
   188  	// ABI names for floating point registers.
   189  	REG_FT0  = REG_F0
   190  	REG_FT1  = REG_F1
   191  	REG_FT2  = REG_F2
   192  	REG_FT3  = REG_F3
   193  	REG_FT4  = REG_F4
   194  	REG_FT5  = REG_F5
   195  	REG_FT6  = REG_F6
   196  	REG_FT7  = REG_F7
   197  	REG_FS0  = REG_F8
   198  	REG_FS1  = REG_F9
   199  	REG_FA0  = REG_F10
   200  	REG_FA1  = REG_F11
   201  	REG_FA2  = REG_F12
   202  	REG_FA3  = REG_F13
   203  	REG_FA4  = REG_F14
   204  	REG_FA5  = REG_F15
   205  	REG_FA6  = REG_F16
   206  	REG_FA7  = REG_F17
   207  	REG_FS2  = REG_F18
   208  	REG_FS3  = REG_F19
   209  	REG_FS4  = REG_F20
   210  	REG_FS5  = REG_F21
   211  	REG_FS6  = REG_F22
   212  	REG_FS7  = REG_F23
   213  	REG_FS8  = REG_F24
   214  	REG_FS9  = REG_F25
   215  	REG_FS10 = REG_F26
   216  	REG_FS11 = REG_F27
   217  	REG_FT8  = REG_F28
   218  	REG_FT9  = REG_F29
   219  	REG_FT10 = REG_F30
   220  	REG_FT11 = REG_F31
   221  
   222  	// Names generated by the SSA compiler.
   223  	REGSP = REG_SP
   224  	REGG  = REG_G
   225  )
   226  
   227  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   228  var RISCV64DWARFRegisters = map[int16]int16{
   229  	// Integer Registers.
   230  	REG_X0:  0,
   231  	REG_X1:  1,
   232  	REG_X2:  2,
   233  	REG_X3:  3,
   234  	REG_X4:  4,
   235  	REG_X5:  5,
   236  	REG_X6:  6,
   237  	REG_X7:  7,
   238  	REG_X8:  8,
   239  	REG_X9:  9,
   240  	REG_X10: 10,
   241  	REG_X11: 11,
   242  	REG_X12: 12,
   243  	REG_X13: 13,
   244  	REG_X14: 14,
   245  	REG_X15: 15,
   246  	REG_X16: 16,
   247  	REG_X17: 17,
   248  	REG_X18: 18,
   249  	REG_X19: 19,
   250  	REG_X20: 20,
   251  	REG_X21: 21,
   252  	REG_X22: 22,
   253  	REG_X23: 23,
   254  	REG_X24: 24,
   255  	REG_X25: 25,
   256  	REG_X26: 26,
   257  	REG_X27: 27,
   258  	REG_X28: 28,
   259  	REG_X29: 29,
   260  	REG_X30: 30,
   261  	REG_X31: 31,
   262  
   263  	// Floating-Point Registers.
   264  	REG_F0:  32,
   265  	REG_F1:  33,
   266  	REG_F2:  34,
   267  	REG_F3:  35,
   268  	REG_F4:  36,
   269  	REG_F5:  37,
   270  	REG_F6:  38,
   271  	REG_F7:  39,
   272  	REG_F8:  40,
   273  	REG_F9:  41,
   274  	REG_F10: 42,
   275  	REG_F11: 43,
   276  	REG_F12: 44,
   277  	REG_F13: 45,
   278  	REG_F14: 46,
   279  	REG_F15: 47,
   280  	REG_F16: 48,
   281  	REG_F17: 49,
   282  	REG_F18: 50,
   283  	REG_F19: 51,
   284  	REG_F20: 52,
   285  	REG_F21: 53,
   286  	REG_F22: 54,
   287  	REG_F23: 55,
   288  	REG_F24: 56,
   289  	REG_F25: 57,
   290  	REG_F26: 58,
   291  	REG_F27: 59,
   292  	REG_F28: 60,
   293  	REG_F29: 61,
   294  	REG_F30: 62,
   295  	REG_F31: 63,
   296  }
   297  
   298  // Prog.Mark flags.
   299  const (
   300  	// USES_REG_TMP indicates that a machine instruction generated from the
   301  	// corresponding *obj.Prog uses the temporary register.
   302  	USES_REG_TMP = 1 << iota
   303  
   304  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   305  	// R_RISCV_JAL relocation is needed.
   306  	NEED_JAL_RELOC
   307  
   308  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   309  	// is the first instruction in an AUIPC + JAL pair that needs a
   310  	// R_RISCV_CALL relocation.
   311  	NEED_CALL_RELOC
   312  
   313  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   314  	// it is the first instruction in an AUIPC + I-type pair that needs a
   315  	// R_RISCV_PCREL_ITYPE relocation.
   316  	NEED_PCREL_ITYPE_RELOC
   317  
   318  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   319  	// it is the first instruction in an AUIPC + S-type pair that needs a
   320  	// R_RISCV_PCREL_STYPE relocation.
   321  	NEED_PCREL_STYPE_RELOC
   322  
   323  	// NEED_GOT_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   324  	// it is the first instruction in an AUIPC + I-type pair that needs a
   325  	// R_RISCV_GOT_PCREL_ITYPE relocation.
   326  	NEED_GOT_PCREL_ITYPE_RELOC
   327  )
   328  
   329  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   330  // at https://github.com/riscv/riscv-opcodes.
   331  //
   332  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   333  //
   334  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
   335  //
   336  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   337  const (
   338  	//
   339  	// Unprivileged ISA (version 20240411)
   340  	//
   341  
   342  	// 2.4: Integer Computational Instructions
   343  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   344  	ASLTI
   345  	ASLTIU
   346  	AANDI
   347  	AORI
   348  	AXORI
   349  	ASLLI
   350  	ASRLI
   351  	ASRAI
   352  	ALUI
   353  	AAUIPC
   354  	AADD
   355  	ASLT
   356  	ASLTU
   357  	AAND
   358  	AOR
   359  	AXOR
   360  	ASLL
   361  	ASRL
   362  	ASUB
   363  	ASRA
   364  
   365  	// 2.5: Control Transfer Instructions
   366  	AJAL
   367  	AJALR
   368  	ABEQ
   369  	ABNE
   370  	ABLT
   371  	ABLTU
   372  	ABGE
   373  	ABGEU
   374  
   375  	// 2.6: Load and Store Instructions
   376  	ALW
   377  	ALWU
   378  	ALH
   379  	ALHU
   380  	ALB
   381  	ALBU
   382  	ASW
   383  	ASH
   384  	ASB
   385  
   386  	// 2.7: Memory Ordering Instructions
   387  	AFENCE
   388  
   389  	// 4.2: Integer Computational Instructions (RV64I)
   390  	AADDIW
   391  	ASLLIW
   392  	ASRLIW
   393  	ASRAIW
   394  	AADDW
   395  	ASLLW
   396  	ASRLW
   397  	ASUBW
   398  	ASRAW
   399  
   400  	// 4.3: Load and Store Instructions (RV64I)
   401  	ALD
   402  	ASD
   403  
   404  	// 7.1: CSR Instructions (Zicsr)
   405  	ACSRRW
   406  	ACSRRS
   407  	ACSRRC
   408  	ACSRRWI
   409  	ACSRRSI
   410  	ACSRRCI
   411  
   412  	// 12.3: Integer Conditional Operations (Zicond)
   413  	ACZEROEQZ
   414  	ACZERONEZ
   415  
   416  	// 13.1: Multiplication Operations
   417  	AMUL
   418  	AMULH
   419  	AMULHU
   420  	AMULHSU
   421  	AMULW
   422  
   423  	// 13.2: Division Operations
   424  	ADIV
   425  	ADIVU
   426  	AREM
   427  	AREMU
   428  	ADIVW
   429  	ADIVUW
   430  	AREMW
   431  	AREMUW
   432  
   433  	// 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
   434  	ALRD
   435  	ASCD
   436  	ALRW
   437  	ASCW
   438  
   439  	// 14.4: Atomic Memory Operations (Zaamo)
   440  	AAMOSWAPD
   441  	AAMOADDD
   442  	AAMOANDD
   443  	AAMOORD
   444  	AAMOXORD
   445  	AAMOMAXD
   446  	AAMOMAXUD
   447  	AAMOMIND
   448  	AAMOMINUD
   449  	AAMOSWAPW
   450  	AAMOADDW
   451  	AAMOANDW
   452  	AAMOORW
   453  	AAMOXORW
   454  	AAMOMAXW
   455  	AAMOMAXUW
   456  	AAMOMINW
   457  	AAMOMINUW
   458  
   459  	// 20.5: Single-Precision Load and Store Instructions
   460  	AFLW
   461  	AFSW
   462  
   463  	// 20.6: Single-Precision Floating-Point Computational Instructions
   464  	AFADDS
   465  	AFSUBS
   466  	AFMULS
   467  	AFDIVS
   468  	AFMINS
   469  	AFMAXS
   470  	AFSQRTS
   471  	AFMADDS
   472  	AFMSUBS
   473  	AFNMADDS
   474  	AFNMSUBS
   475  
   476  	// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
   477  	AFCVTWS
   478  	AFCVTLS
   479  	AFCVTSW
   480  	AFCVTSL
   481  	AFCVTWUS
   482  	AFCVTLUS
   483  	AFCVTSWU
   484  	AFCVTSLU
   485  	AFSGNJS
   486  	AFSGNJNS
   487  	AFSGNJXS
   488  	AFMVXS
   489  	AFMVSX
   490  	AFMVXW
   491  	AFMVWX
   492  
   493  	// 20.8: Single-Precision Floating-Point Compare Instructions
   494  	AFEQS
   495  	AFLTS
   496  	AFLES
   497  
   498  	// 20.9: Single-Precision Floating-Point Classify Instruction
   499  	AFCLASSS
   500  
   501  	// 21.3: Double-Precision Load and Store Instructions
   502  	AFLD
   503  	AFSD
   504  
   505  	// 21.4: Double-Precision Floating-Point Computational Instructions
   506  	AFADDD
   507  	AFSUBD
   508  	AFMULD
   509  	AFDIVD
   510  	AFMIND
   511  	AFMAXD
   512  	AFSQRTD
   513  	AFMADDD
   514  	AFMSUBD
   515  	AFNMADDD
   516  	AFNMSUBD
   517  
   518  	// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
   519  	AFCVTWD
   520  	AFCVTLD
   521  	AFCVTDW
   522  	AFCVTDL
   523  	AFCVTWUD
   524  	AFCVTLUD
   525  	AFCVTDWU
   526  	AFCVTDLU
   527  	AFCVTSD
   528  	AFCVTDS
   529  	AFSGNJD
   530  	AFSGNJND
   531  	AFSGNJXD
   532  	AFMVXD
   533  	AFMVDX
   534  
   535  	// 21.6: Double-Precision Floating-Point Compare Instructions
   536  	AFEQD
   537  	AFLTD
   538  	AFLED
   539  
   540  	// 21.7: Double-Precision Floating-Point Classify Instruction
   541  	AFCLASSD
   542  
   543  	// 22.1 Quad-Precision Load and Store Instructions
   544  	AFLQ
   545  	AFSQ
   546  
   547  	// 22.2: Quad-Precision Computational Instructions
   548  	AFADDQ
   549  	AFSUBQ
   550  	AFMULQ
   551  	AFDIVQ
   552  	AFMINQ
   553  	AFMAXQ
   554  	AFSQRTQ
   555  	AFMADDQ
   556  	AFMSUBQ
   557  	AFNMADDQ
   558  	AFNMSUBQ
   559  
   560  	// 22.3: Quad-Precision Convert and Move Instructions
   561  	AFCVTWQ
   562  	AFCVTLQ
   563  	AFCVTSQ
   564  	AFCVTDQ
   565  	AFCVTQW
   566  	AFCVTQL
   567  	AFCVTQS
   568  	AFCVTQD
   569  	AFCVTWUQ
   570  	AFCVTLUQ
   571  	AFCVTQWU
   572  	AFCVTQLU
   573  	AFSGNJQ
   574  	AFSGNJNQ
   575  	AFSGNJXQ
   576  
   577  	// 22.4: Quad-Precision Floating-Point Compare Instructions
   578  	AFEQQ
   579  	AFLEQ
   580  	AFLTQ
   581  
   582  	// 22.5: Quad-Precision Floating-Point Classify Instruction
   583  	AFCLASSQ
   584  
   585  	//
   586  	// "C" Extension for Compressed Instructions
   587  	//
   588  
   589  	// 26.3.1: Compressed Stack-Pointer-Based Loads and Stores
   590  	ACLWSP
   591  	ACLDSP
   592  	ACFLDSP
   593  	ACSWSP
   594  	ACSDSP
   595  	ACFSDSP
   596  
   597  	// 26.3.2: Compressed Register-Based Loads and Stores
   598  	ACLW
   599  	ACLD
   600  	ACFLD
   601  	ACSW
   602  	ACSD
   603  	ACFSD
   604  
   605  	// 26.4: Compressed Control Transfer Instructions
   606  	ACJ
   607  	ACJR
   608  	ACJALR
   609  	ACBEQZ
   610  	ACBNEZ
   611  
   612  	// 26.5.1: Compressed Integer Constant-Generation Instructions
   613  	ACLI
   614  	ACLUI
   615  	ACADDI
   616  	ACADDIW
   617  	ACADDI16SP
   618  	ACADDI4SPN
   619  	ACSLLI
   620  	ACSRLI
   621  	ACSRAI
   622  	ACANDI
   623  
   624  	// 26.5.3: Compressed Integer Register-Register Operations
   625  	ACMV
   626  	ACADD
   627  	ACAND
   628  	ACOR
   629  	ACXOR
   630  	ACSUB
   631  	ACADDW
   632  	ACSUBW
   633  
   634  	// 26.5.5: Compressed NOP Instruction
   635  	ACNOP
   636  
   637  	// 26.5.6: Compressed Breakpoint Instruction
   638  	ACEBREAK
   639  
   640  	//
   641  	// "B" Extension for Bit Manipulation, Version 1.0.0
   642  	//
   643  
   644  	// 28.4.1: Address Generation Instructions (Zba)
   645  	AADDUW
   646  	ASH1ADD
   647  	ASH1ADDUW
   648  	ASH2ADD
   649  	ASH2ADDUW
   650  	ASH3ADD
   651  	ASH3ADDUW
   652  	ASLLIUW
   653  
   654  	// 28.4.2: Basic Bit Manipulation (Zbb)
   655  	AANDN
   656  	AORN
   657  	AXNOR
   658  	ACLZ
   659  	ACLZW
   660  	ACTZ
   661  	ACTZW
   662  	ACPOP
   663  	ACPOPW
   664  	AMAX
   665  	AMAXU
   666  	AMIN
   667  	AMINU
   668  	ASEXTB
   669  	ASEXTH
   670  	AZEXTH
   671  
   672  	// 28.4.3: Bitwise Rotation (Zbb)
   673  	AROL
   674  	AROLW
   675  	AROR
   676  	ARORI
   677  	ARORIW
   678  	ARORW
   679  	AORCB
   680  	AREV8
   681  
   682  	// 28.4.4: Single-bit Instructions (Zbs)
   683  	ABCLR
   684  	ABCLRI
   685  	ABEXT
   686  	ABEXTI
   687  	ABINV
   688  	ABINVI
   689  	ABSET
   690  	ABSETI
   691  
   692  	//
   693  	// "V" Standard Extension for Vector Operations, Version 1.0
   694  	//
   695  
   696  	// 31.6: Configuration-Setting Instructions
   697  	AVSETVLI
   698  	AVSETIVLI
   699  	AVSETVL
   700  
   701  	// 31.7.4: Vector Unit-Stride Instructions
   702  	AVLE8V
   703  	AVLE16V
   704  	AVLE32V
   705  	AVLE64V
   706  	AVSE8V
   707  	AVSE16V
   708  	AVSE32V
   709  	AVSE64V
   710  	AVLMV
   711  	AVSMV
   712  
   713  	// 31.7.5: Vector Strided Instructions
   714  	AVLSE8V
   715  	AVLSE16V
   716  	AVLSE32V
   717  	AVLSE64V
   718  	AVSSE8V
   719  	AVSSE16V
   720  	AVSSE32V
   721  	AVSSE64V
   722  
   723  	// 31.7.6: Vector Indexed Instructions
   724  	AVLUXEI8V
   725  	AVLUXEI16V
   726  	AVLUXEI32V
   727  	AVLUXEI64V
   728  	AVLOXEI8V
   729  	AVLOXEI16V
   730  	AVLOXEI32V
   731  	AVLOXEI64V
   732  	AVSUXEI8V
   733  	AVSUXEI16V
   734  	AVSUXEI32V
   735  	AVSUXEI64V
   736  	AVSOXEI8V
   737  	AVSOXEI16V
   738  	AVSOXEI32V
   739  	AVSOXEI64V
   740  
   741  	// 31.7.7: Unit-stride Fault-Only-First Loads
   742  	AVLE8FFV
   743  	AVLE16FFV
   744  	AVLE32FFV
   745  	AVLE64FFV
   746  
   747  	// 31.7.8. Vector Load/Store Segment Instructions
   748  
   749  	// 31.7.8.1. Vector Unit-Stride Segment Loads and Stores
   750  	AVLSEG2E8V
   751  	AVLSEG3E8V
   752  	AVLSEG4E8V
   753  	AVLSEG5E8V
   754  	AVLSEG6E8V
   755  	AVLSEG7E8V
   756  	AVLSEG8E8V
   757  	AVLSEG2E16V
   758  	AVLSEG3E16V
   759  	AVLSEG4E16V
   760  	AVLSEG5E16V
   761  	AVLSEG6E16V
   762  	AVLSEG7E16V
   763  	AVLSEG8E16V
   764  	AVLSEG2E32V
   765  	AVLSEG3E32V
   766  	AVLSEG4E32V
   767  	AVLSEG5E32V
   768  	AVLSEG6E32V
   769  	AVLSEG7E32V
   770  	AVLSEG8E32V
   771  	AVLSEG2E64V
   772  	AVLSEG3E64V
   773  	AVLSEG4E64V
   774  	AVLSEG5E64V
   775  	AVLSEG6E64V
   776  	AVLSEG7E64V
   777  	AVLSEG8E64V
   778  
   779  	AVSSEG2E8V
   780  	AVSSEG3E8V
   781  	AVSSEG4E8V
   782  	AVSSEG5E8V
   783  	AVSSEG6E8V
   784  	AVSSEG7E8V
   785  	AVSSEG8E8V
   786  	AVSSEG2E16V
   787  	AVSSEG3E16V
   788  	AVSSEG4E16V
   789  	AVSSEG5E16V
   790  	AVSSEG6E16V
   791  	AVSSEG7E16V
   792  	AVSSEG8E16V
   793  	AVSSEG2E32V
   794  	AVSSEG3E32V
   795  	AVSSEG4E32V
   796  	AVSSEG5E32V
   797  	AVSSEG6E32V
   798  	AVSSEG7E32V
   799  	AVSSEG8E32V
   800  	AVSSEG2E64V
   801  	AVSSEG3E64V
   802  	AVSSEG4E64V
   803  	AVSSEG5E64V
   804  	AVSSEG6E64V
   805  	AVSSEG7E64V
   806  	AVSSEG8E64V
   807  
   808  	AVLSEG2E8FFV
   809  	AVLSEG3E8FFV
   810  	AVLSEG4E8FFV
   811  	AVLSEG5E8FFV
   812  	AVLSEG6E8FFV
   813  	AVLSEG7E8FFV
   814  	AVLSEG8E8FFV
   815  	AVLSEG2E16FFV
   816  	AVLSEG3E16FFV
   817  	AVLSEG4E16FFV
   818  	AVLSEG5E16FFV
   819  	AVLSEG6E16FFV
   820  	AVLSEG7E16FFV
   821  	AVLSEG8E16FFV
   822  	AVLSEG2E32FFV
   823  	AVLSEG3E32FFV
   824  	AVLSEG4E32FFV
   825  	AVLSEG5E32FFV
   826  	AVLSEG6E32FFV
   827  	AVLSEG7E32FFV
   828  	AVLSEG8E32FFV
   829  	AVLSEG2E64FFV
   830  	AVLSEG3E64FFV
   831  	AVLSEG4E64FFV
   832  	AVLSEG5E64FFV
   833  	AVLSEG6E64FFV
   834  	AVLSEG7E64FFV
   835  	AVLSEG8E64FFV
   836  
   837  	// 31.7.8.2. Vector Strided Segment Loads and Stores
   838  	AVLSSEG2E8V
   839  	AVLSSEG3E8V
   840  	AVLSSEG4E8V
   841  	AVLSSEG5E8V
   842  	AVLSSEG6E8V
   843  	AVLSSEG7E8V
   844  	AVLSSEG8E8V
   845  	AVLSSEG2E16V
   846  	AVLSSEG3E16V
   847  	AVLSSEG4E16V
   848  	AVLSSEG5E16V
   849  	AVLSSEG6E16V
   850  	AVLSSEG7E16V
   851  	AVLSSEG8E16V
   852  	AVLSSEG2E32V
   853  	AVLSSEG3E32V
   854  	AVLSSEG4E32V
   855  	AVLSSEG5E32V
   856  	AVLSSEG6E32V
   857  	AVLSSEG7E32V
   858  	AVLSSEG8E32V
   859  	AVLSSEG2E64V
   860  	AVLSSEG3E64V
   861  	AVLSSEG4E64V
   862  	AVLSSEG5E64V
   863  	AVLSSEG6E64V
   864  	AVLSSEG7E64V
   865  	AVLSSEG8E64V
   866  
   867  	AVSSSEG2E8V
   868  	AVSSSEG3E8V
   869  	AVSSSEG4E8V
   870  	AVSSSEG5E8V
   871  	AVSSSEG6E8V
   872  	AVSSSEG7E8V
   873  	AVSSSEG8E8V
   874  	AVSSSEG2E16V
   875  	AVSSSEG3E16V
   876  	AVSSSEG4E16V
   877  	AVSSSEG5E16V
   878  	AVSSSEG6E16V
   879  	AVSSSEG7E16V
   880  	AVSSSEG8E16V
   881  	AVSSSEG2E32V
   882  	AVSSSEG3E32V
   883  	AVSSSEG4E32V
   884  	AVSSSEG5E32V
   885  	AVSSSEG6E32V
   886  	AVSSSEG7E32V
   887  	AVSSSEG8E32V
   888  	AVSSSEG2E64V
   889  	AVSSSEG3E64V
   890  	AVSSSEG4E64V
   891  	AVSSSEG5E64V
   892  	AVSSSEG6E64V
   893  	AVSSSEG7E64V
   894  	AVSSSEG8E64V
   895  
   896  	// 31.7.8.3. Vector Indexed Segment Loads and Stores
   897  	AVLOXSEG2EI8V
   898  	AVLOXSEG3EI8V
   899  	AVLOXSEG4EI8V
   900  	AVLOXSEG5EI8V
   901  	AVLOXSEG6EI8V
   902  	AVLOXSEG7EI8V
   903  	AVLOXSEG8EI8V
   904  	AVLOXSEG2EI16V
   905  	AVLOXSEG3EI16V
   906  	AVLOXSEG4EI16V
   907  	AVLOXSEG5EI16V
   908  	AVLOXSEG6EI16V
   909  	AVLOXSEG7EI16V
   910  	AVLOXSEG8EI16V
   911  	AVLOXSEG2EI32V
   912  	AVLOXSEG3EI32V
   913  	AVLOXSEG4EI32V
   914  	AVLOXSEG5EI32V
   915  	AVLOXSEG6EI32V
   916  	AVLOXSEG7EI32V
   917  	AVLOXSEG8EI32V
   918  	AVLOXSEG2EI64V
   919  	AVLOXSEG3EI64V
   920  	AVLOXSEG4EI64V
   921  	AVLOXSEG5EI64V
   922  	AVLOXSEG6EI64V
   923  	AVLOXSEG7EI64V
   924  	AVLOXSEG8EI64V
   925  
   926  	AVSOXSEG2EI8V
   927  	AVSOXSEG3EI8V
   928  	AVSOXSEG4EI8V
   929  	AVSOXSEG5EI8V
   930  	AVSOXSEG6EI8V
   931  	AVSOXSEG7EI8V
   932  	AVSOXSEG8EI8V
   933  	AVSOXSEG2EI16V
   934  	AVSOXSEG3EI16V
   935  	AVSOXSEG4EI16V
   936  	AVSOXSEG5EI16V
   937  	AVSOXSEG6EI16V
   938  	AVSOXSEG7EI16V
   939  	AVSOXSEG8EI16V
   940  	AVSOXSEG2EI32V
   941  	AVSOXSEG3EI32V
   942  	AVSOXSEG4EI32V
   943  	AVSOXSEG5EI32V
   944  	AVSOXSEG6EI32V
   945  	AVSOXSEG7EI32V
   946  	AVSOXSEG8EI32V
   947  	AVSOXSEG2EI64V
   948  	AVSOXSEG3EI64V
   949  	AVSOXSEG4EI64V
   950  	AVSOXSEG5EI64V
   951  	AVSOXSEG6EI64V
   952  	AVSOXSEG7EI64V
   953  	AVSOXSEG8EI64V
   954  
   955  	AVLUXSEG2EI8V
   956  	AVLUXSEG3EI8V
   957  	AVLUXSEG4EI8V
   958  	AVLUXSEG5EI8V
   959  	AVLUXSEG6EI8V
   960  	AVLUXSEG7EI8V
   961  	AVLUXSEG8EI8V
   962  	AVLUXSEG2EI16V
   963  	AVLUXSEG3EI16V
   964  	AVLUXSEG4EI16V
   965  	AVLUXSEG5EI16V
   966  	AVLUXSEG6EI16V
   967  	AVLUXSEG7EI16V
   968  	AVLUXSEG8EI16V
   969  	AVLUXSEG2EI32V
   970  	AVLUXSEG3EI32V
   971  	AVLUXSEG4EI32V
   972  	AVLUXSEG5EI32V
   973  	AVLUXSEG6EI32V
   974  	AVLUXSEG7EI32V
   975  	AVLUXSEG8EI32V
   976  	AVLUXSEG2EI64V
   977  	AVLUXSEG3EI64V
   978  	AVLUXSEG4EI64V
   979  	AVLUXSEG5EI64V
   980  	AVLUXSEG6EI64V
   981  	AVLUXSEG7EI64V
   982  	AVLUXSEG8EI64V
   983  
   984  	AVSUXSEG2EI8V
   985  	AVSUXSEG3EI8V
   986  	AVSUXSEG4EI8V
   987  	AVSUXSEG5EI8V
   988  	AVSUXSEG6EI8V
   989  	AVSUXSEG7EI8V
   990  	AVSUXSEG8EI8V
   991  	AVSUXSEG2EI16V
   992  	AVSUXSEG3EI16V
   993  	AVSUXSEG4EI16V
   994  	AVSUXSEG5EI16V
   995  	AVSUXSEG6EI16V
   996  	AVSUXSEG7EI16V
   997  	AVSUXSEG8EI16V
   998  	AVSUXSEG2EI32V
   999  	AVSUXSEG3EI32V
  1000  	AVSUXSEG4EI32V
  1001  	AVSUXSEG5EI32V
  1002  	AVSUXSEG6EI32V
  1003  	AVSUXSEG7EI32V
  1004  	AVSUXSEG8EI32V
  1005  	AVSUXSEG2EI64V
  1006  	AVSUXSEG3EI64V
  1007  	AVSUXSEG4EI64V
  1008  	AVSUXSEG5EI64V
  1009  	AVSUXSEG6EI64V
  1010  	AVSUXSEG7EI64V
  1011  	AVSUXSEG8EI64V
  1012  
  1013  	// 31.7.9: Vector Load/Store Whole Register Instructions
  1014  	AVL1RE8V
  1015  	AVL1RE16V
  1016  	AVL1RE32V
  1017  	AVL1RE64V
  1018  	AVL2RE8V
  1019  	AVL2RE16V
  1020  	AVL2RE32V
  1021  	AVL2RE64V
  1022  	AVL4RE8V
  1023  	AVL4RE16V
  1024  	AVL4RE32V
  1025  	AVL4RE64V
  1026  	AVL8RE8V
  1027  	AVL8RE16V
  1028  	AVL8RE32V
  1029  	AVL8RE64V
  1030  	AVS1RV
  1031  	AVS2RV
  1032  	AVS4RV
  1033  	AVS8RV
  1034  
  1035  	// 31.11.1: Vector Single-Width Integer Add and Subtract
  1036  	AVADDVV
  1037  	AVADDVX
  1038  	AVADDVI
  1039  	AVSUBVV
  1040  	AVSUBVX
  1041  	AVRSUBVX
  1042  	AVRSUBVI
  1043  
  1044  	// 31.11.2: Vector Widening Integer Add/Subtract
  1045  	AVWADDUVV
  1046  	AVWADDUVX
  1047  	AVWSUBUVV
  1048  	AVWSUBUVX
  1049  	AVWADDVV
  1050  	AVWADDVX
  1051  	AVWSUBVV
  1052  	AVWSUBVX
  1053  	AVWADDUWV
  1054  	AVWADDUWX
  1055  	AVWSUBUWV
  1056  	AVWSUBUWX
  1057  	AVWADDWV
  1058  	AVWADDWX
  1059  	AVWSUBWV
  1060  	AVWSUBWX
  1061  
  1062  	// 31.11.3: Vector Integer Extension
  1063  	AVZEXTVF2
  1064  	AVSEXTVF2
  1065  	AVZEXTVF4
  1066  	AVSEXTVF4
  1067  	AVZEXTVF8
  1068  	AVSEXTVF8
  1069  
  1070  	// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
  1071  	AVADCVVM
  1072  	AVADCVXM
  1073  	AVADCVIM
  1074  	AVMADCVVM
  1075  	AVMADCVXM
  1076  	AVMADCVIM
  1077  	AVMADCVV
  1078  	AVMADCVX
  1079  	AVMADCVI
  1080  	AVSBCVVM
  1081  	AVSBCVXM
  1082  	AVMSBCVVM
  1083  	AVMSBCVXM
  1084  	AVMSBCVV
  1085  	AVMSBCVX
  1086  
  1087  	// 31.11.5: Vector Bitwise Logical Instructions
  1088  	AVANDVV
  1089  	AVANDVX
  1090  	AVANDVI
  1091  	AVORVV
  1092  	AVORVX
  1093  	AVORVI
  1094  	AVXORVV
  1095  	AVXORVX
  1096  	AVXORVI
  1097  
  1098  	// 31.11.6: Vector Single-Width Shift Instructions
  1099  	AVSLLVV
  1100  	AVSLLVX
  1101  	AVSLLVI
  1102  	AVSRLVV
  1103  	AVSRLVX
  1104  	AVSRLVI
  1105  	AVSRAVV
  1106  	AVSRAVX
  1107  	AVSRAVI
  1108  
  1109  	// 31.11.7: Vector Narrowing Integer Right Shift Instructions
  1110  	AVNSRLWV
  1111  	AVNSRLWX
  1112  	AVNSRLWI
  1113  	AVNSRAWV
  1114  	AVNSRAWX
  1115  	AVNSRAWI
  1116  
  1117  	// 31.11.8: Vector Integer Compare Instructions
  1118  	AVMSEQVV
  1119  	AVMSEQVX
  1120  	AVMSEQVI
  1121  	AVMSNEVV
  1122  	AVMSNEVX
  1123  	AVMSNEVI
  1124  	AVMSLTUVV
  1125  	AVMSLTUVX
  1126  	AVMSLTVV
  1127  	AVMSLTVX
  1128  	AVMSLEUVV
  1129  	AVMSLEUVX
  1130  	AVMSLEUVI
  1131  	AVMSLEVV
  1132  	AVMSLEVX
  1133  	AVMSLEVI
  1134  	AVMSGTUVX
  1135  	AVMSGTUVI
  1136  	AVMSGTVX
  1137  	AVMSGTVI
  1138  
  1139  	// 31.11.9: Vector Integer Min/Max Instructions
  1140  	AVMINUVV
  1141  	AVMINUVX
  1142  	AVMINVV
  1143  	AVMINVX
  1144  	AVMAXUVV
  1145  	AVMAXUVX
  1146  	AVMAXVV
  1147  	AVMAXVX
  1148  
  1149  	// 31.11.10: Vector Single-Width Integer Multiply Instructions
  1150  	AVMULVV
  1151  	AVMULVX
  1152  	AVMULHVV
  1153  	AVMULHVX
  1154  	AVMULHUVV
  1155  	AVMULHUVX
  1156  	AVMULHSUVV
  1157  	AVMULHSUVX
  1158  
  1159  	// 31.11.11: Vector Integer Divide Instructions
  1160  	AVDIVUVV
  1161  	AVDIVUVX
  1162  	AVDIVVV
  1163  	AVDIVVX
  1164  	AVREMUVV
  1165  	AVREMUVX
  1166  	AVREMVV
  1167  	AVREMVX
  1168  
  1169  	// 31.11.12: Vector Widening Integer Multiply Instructions
  1170  	AVWMULVV
  1171  	AVWMULVX
  1172  	AVWMULUVV
  1173  	AVWMULUVX
  1174  	AVWMULSUVV
  1175  	AVWMULSUVX
  1176  
  1177  	// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
  1178  	AVMACCVV
  1179  	AVMACCVX
  1180  	AVNMSACVV
  1181  	AVNMSACVX
  1182  	AVMADDVV
  1183  	AVMADDVX
  1184  	AVNMSUBVV
  1185  	AVNMSUBVX
  1186  
  1187  	// 31.11.14: Vector Widening Integer Multiply-Add Instructions
  1188  	AVWMACCUVV
  1189  	AVWMACCUVX
  1190  	AVWMACCVV
  1191  	AVWMACCVX
  1192  	AVWMACCSUVV
  1193  	AVWMACCSUVX
  1194  	AVWMACCUSVX
  1195  
  1196  	// 31.11.15: Vector Integer Merge Instructions
  1197  	AVMERGEVVM
  1198  	AVMERGEVXM
  1199  	AVMERGEVIM
  1200  
  1201  	// 31.11.16: Vector Integer Move Instructions
  1202  	AVMVVV
  1203  	AVMVVX
  1204  	AVMVVI
  1205  
  1206  	// 31.12.1: Vector Single-Width Saturating Add and Subtract
  1207  	AVSADDUVV
  1208  	AVSADDUVX
  1209  	AVSADDUVI
  1210  	AVSADDVV
  1211  	AVSADDVX
  1212  	AVSADDVI
  1213  	AVSSUBUVV
  1214  	AVSSUBUVX
  1215  	AVSSUBVV
  1216  	AVSSUBVX
  1217  
  1218  	// 31.12.2: Vector Single-Width Averaging Add and Subtract
  1219  	AVAADDUVV
  1220  	AVAADDUVX
  1221  	AVAADDVV
  1222  	AVAADDVX
  1223  	AVASUBUVV
  1224  	AVASUBUVX
  1225  	AVASUBVV
  1226  	AVASUBVX
  1227  
  1228  	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
  1229  	AVSMULVV
  1230  	AVSMULVX
  1231  
  1232  	// 31.12.4: Vector Single-Width Scaling Shift Instructions
  1233  	AVSSRLVV
  1234  	AVSSRLVX
  1235  	AVSSRLVI
  1236  	AVSSRAVV
  1237  	AVSSRAVX
  1238  	AVSSRAVI
  1239  
  1240  	// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
  1241  	AVNCLIPUWV
  1242  	AVNCLIPUWX
  1243  	AVNCLIPUWI
  1244  	AVNCLIPWV
  1245  	AVNCLIPWX
  1246  	AVNCLIPWI
  1247  
  1248  	// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
  1249  	AVFADDVV
  1250  	AVFADDVF
  1251  	AVFSUBVV
  1252  	AVFSUBVF
  1253  	AVFRSUBVF
  1254  
  1255  	// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
  1256  	AVFWADDVV
  1257  	AVFWADDVF
  1258  	AVFWSUBVV
  1259  	AVFWSUBVF
  1260  	AVFWADDWV
  1261  	AVFWADDWF
  1262  	AVFWSUBWV
  1263  	AVFWSUBWF
  1264  
  1265  	// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
  1266  	AVFMULVV
  1267  	AVFMULVF
  1268  	AVFDIVVV
  1269  	AVFDIVVF
  1270  	AVFRDIVVF
  1271  
  1272  	// 31.13.5: Vector Widening Floating-Point Multiply
  1273  	AVFWMULVV
  1274  	AVFWMULVF
  1275  
  1276  	// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
  1277  	AVFMACCVV
  1278  	AVFMACCVF
  1279  	AVFNMACCVV
  1280  	AVFNMACCVF
  1281  	AVFMSACVV
  1282  	AVFMSACVF
  1283  	AVFNMSACVV
  1284  	AVFNMSACVF
  1285  	AVFMADDVV
  1286  	AVFMADDVF
  1287  	AVFNMADDVV
  1288  	AVFNMADDVF
  1289  	AVFMSUBVV
  1290  	AVFMSUBVF
  1291  	AVFNMSUBVV
  1292  	AVFNMSUBVF
  1293  
  1294  	// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
  1295  	AVFWMACCVV
  1296  	AVFWMACCVF
  1297  	AVFWNMACCVV
  1298  	AVFWNMACCVF
  1299  	AVFWMSACVV
  1300  	AVFWMSACVF
  1301  	AVFWNMSACVV
  1302  	AVFWNMSACVF
  1303  
  1304  	// 31.13.8: Vector Floating-Point Square-Root Instruction
  1305  	AVFSQRTV
  1306  
  1307  	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
  1308  	AVFRSQRT7V
  1309  
  1310  	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
  1311  	AVFREC7V
  1312  
  1313  	// 31.13.11: Vector Floating-Point MIN/MAX Instructions
  1314  	AVFMINVV
  1315  	AVFMINVF
  1316  	AVFMAXVV
  1317  	AVFMAXVF
  1318  
  1319  	// 31.13.12: Vector Floating-Point Sign-Injection Instructions
  1320  	AVFSGNJVV
  1321  	AVFSGNJVF
  1322  	AVFSGNJNVV
  1323  	AVFSGNJNVF
  1324  	AVFSGNJXVV
  1325  	AVFSGNJXVF
  1326  
  1327  	// 31.13.13: Vector Floating-Point Compare Instructions
  1328  	AVMFEQVV
  1329  	AVMFEQVF
  1330  	AVMFNEVV
  1331  	AVMFNEVF
  1332  	AVMFLTVV
  1333  	AVMFLTVF
  1334  	AVMFLEVV
  1335  	AVMFLEVF
  1336  	AVMFGTVF
  1337  	AVMFGEVF
  1338  
  1339  	// 31.13.14: Vector Floating-Point Classify Instruction
  1340  	AVFCLASSV
  1341  
  1342  	// 31.13.15: Vector Floating-Point Merge Instruction
  1343  	AVFMERGEVFM
  1344  
  1345  	// 31.13.16: Vector Floating-Point Move Instruction
  1346  	AVFMVVF
  1347  
  1348  	// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
  1349  	AVFCVTXUFV
  1350  	AVFCVTXFV
  1351  	AVFCVTRTZXUFV
  1352  	AVFCVTRTZXFV
  1353  	AVFCVTFXUV
  1354  	AVFCVTFXV
  1355  
  1356  	// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
  1357  	AVFWCVTXUFV
  1358  	AVFWCVTXFV
  1359  	AVFWCVTRTZXUFV
  1360  	AVFWCVTRTZXFV
  1361  	AVFWCVTFXUV
  1362  	AVFWCVTFXV
  1363  	AVFWCVTFFV
  1364  
  1365  	// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
  1366  	AVFNCVTXUFW
  1367  	AVFNCVTXFW
  1368  	AVFNCVTRTZXUFW
  1369  	AVFNCVTRTZXFW
  1370  	AVFNCVTFXUW
  1371  	AVFNCVTFXW
  1372  	AVFNCVTFFW
  1373  	AVFNCVTRODFFW
  1374  
  1375  	// 31.14.1: Vector Single-Width Integer Reduction Instructions
  1376  	AVREDSUMVS
  1377  	AVREDMAXUVS
  1378  	AVREDMAXVS
  1379  	AVREDMINUVS
  1380  	AVREDMINVS
  1381  	AVREDANDVS
  1382  	AVREDORVS
  1383  	AVREDXORVS
  1384  
  1385  	// 31.14.2: Vector Widening Integer Reduction Instructions
  1386  	AVWREDSUMUVS
  1387  	AVWREDSUMVS
  1388  
  1389  	// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
  1390  	AVFREDOSUMVS
  1391  	AVFREDUSUMVS
  1392  	AVFREDMAXVS
  1393  	AVFREDMINVS
  1394  
  1395  	// 31.14.4: Vector Widening Floating-Point Reduction Instructions
  1396  	AVFWREDOSUMVS
  1397  	AVFWREDUSUMVS
  1398  
  1399  	// 31.15: Vector Mask Instructions
  1400  	AVMANDMM
  1401  	AVMNANDMM
  1402  	AVMANDNMM
  1403  	AVMXORMM
  1404  	AVMORMM
  1405  	AVMNORMM
  1406  	AVMORNMM
  1407  	AVMXNORMM
  1408  	AVCPOPM
  1409  	AVFIRSTM
  1410  	AVMSBFM
  1411  	AVMSIFM
  1412  	AVMSOFM
  1413  	AVIOTAM
  1414  	AVIDV
  1415  
  1416  	// 31.16.1: Integer Scalar Move Instructions
  1417  	AVMVXS
  1418  	AVMVSX
  1419  
  1420  	// 31.16.2: Floating-Point Scalar Move Instructions
  1421  	AVFMVFS
  1422  	AVFMVSF
  1423  
  1424  	// 31.16.3: Vector Slide Instructions
  1425  	AVSLIDEUPVX
  1426  	AVSLIDEUPVI
  1427  	AVSLIDEDOWNVX
  1428  	AVSLIDEDOWNVI
  1429  	AVSLIDE1UPVX
  1430  	AVFSLIDE1UPVF
  1431  	AVSLIDE1DOWNVX
  1432  	AVFSLIDE1DOWNVF
  1433  
  1434  	// 31.16.4: Vector Register Gather Instructions
  1435  	AVRGATHERVV
  1436  	AVRGATHEREI16VV
  1437  	AVRGATHERVX
  1438  	AVRGATHERVI
  1439  
  1440  	// 31.16.5: Vector Compress Instruction
  1441  	AVCOMPRESSVM
  1442  
  1443  	// 31.16.6: Whole Vector Register Move
  1444  	AVMV1RV
  1445  	AVMV2RV
  1446  	AVMV4RV
  1447  	AVMV8RV
  1448  
  1449  	//
  1450  	// Privileged ISA (version 20240411)
  1451  	//
  1452  
  1453  	// 3.3.1: Environment Call and Breakpoint
  1454  	AECALL
  1455  	ASCALL
  1456  	AEBREAK
  1457  	ASBREAK
  1458  
  1459  	// 3.3.2: Trap-Return Instructions
  1460  	AMRET
  1461  	ASRET
  1462  	ADRET
  1463  
  1464  	// 3.3.3: Wait for Interrupt
  1465  	AWFI
  1466  
  1467  	// 10.2: Supervisor Memory-Management Fence Instruction
  1468  	ASFENCEVMA
  1469  
  1470  	// The escape hatch. Inserts a single 32-bit word.
  1471  	AWORD
  1472  
  1473  	// Pseudo-instructions.  These get translated by the assembler into other
  1474  	// instructions, based on their operands.
  1475  	ABEQZ
  1476  	ABGEZ
  1477  	ABGT
  1478  	ABGTU
  1479  	ABGTZ
  1480  	ABLE
  1481  	ABLEU
  1482  	ABLEZ
  1483  	ABLTZ
  1484  	ABNEZ
  1485  	AFABSD
  1486  	AFABSS
  1487  	AFNED
  1488  	AFNEGD
  1489  	AFNEGS
  1490  	AFNES
  1491  	AMOV
  1492  	AMOVB
  1493  	AMOVBU
  1494  	AMOVD
  1495  	AMOVF
  1496  	AMOVH
  1497  	AMOVHU
  1498  	AMOVW
  1499  	AMOVWU
  1500  	ANEG
  1501  	ANEGW
  1502  	ANOT
  1503  	ARDCYCLE
  1504  	ARDINSTRET
  1505  	ARDTIME
  1506  	ASEQZ
  1507  	ASNEZ
  1508  	AVFABSV
  1509  	AVFNEGV
  1510  	AVL1RV
  1511  	AVL2RV
  1512  	AVL4RV
  1513  	AVL8RV
  1514  	AVMCLRM
  1515  	AVMFGEVV
  1516  	AVMFGTVV
  1517  	AVMMVM
  1518  	AVMNOTM
  1519  	AVMSETM
  1520  	AVMSGEUVI
  1521  	AVMSGEUVV
  1522  	AVMSGEVI
  1523  	AVMSGEVV
  1524  	AVMSGTUVV
  1525  	AVMSGTVV
  1526  	AVMSLTUVI
  1527  	AVMSLTVI
  1528  	AVNCVTXXW
  1529  	AVNEGV
  1530  	AVNOTV
  1531  	AVWCVTUXXV
  1532  	AVWCVTXXV
  1533  
  1534  	// End marker
  1535  	ALAST
  1536  )
  1537  
  1538  // opSuffix encoding to uint8 which fit into p.Scond
  1539  var rmSuffixSet = map[string]uint8{
  1540  	"RNE": RM_RNE,
  1541  	"RTZ": RM_RTZ,
  1542  	"RDN": RM_RDN,
  1543  	"RUP": RM_RUP,
  1544  	"RMM": RM_RMM,
  1545  }
  1546  
  1547  const rmSuffixBit uint8 = 1 << 7
  1548  
  1549  func rmSuffixEncode(s string) (uint8, error) {
  1550  	if s == "" {
  1551  		return 0, errors.New("empty suffix")
  1552  	}
  1553  	enc, ok := rmSuffixSet[s]
  1554  	if !ok {
  1555  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
  1556  	}
  1557  	return enc | rmSuffixBit, nil
  1558  }
  1559  
  1560  func rmSuffixString(u uint8) (string, error) {
  1561  	if u&rmSuffixBit == 0 {
  1562  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
  1563  	}
  1564  
  1565  	u &^= rmSuffixBit
  1566  	for k, v := range rmSuffixSet {
  1567  		if v == u {
  1568  			return k, nil
  1569  		}
  1570  	}
  1571  	return "", fmt.Errorf("unknown suffix:%x", u)
  1572  }
  1573  
  1574  const (
  1575  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
  1576  	RM_RTZ              // Round towards Zero
  1577  	RM_RDN              // Round Down
  1578  	RM_RUP              // Round Up
  1579  	RM_RMM              // Round to Nearest, ties to Max Magnitude
  1580  )
  1581  
  1582  type SpecialOperand int
  1583  
  1584  const (
  1585  	SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase
  1586  	SPOP_RVV_BEGIN
  1587  
  1588  	// Vector mask policy.
  1589  	SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 2
  1590  	SPOP_MU
  1591  
  1592  	// Vector tail policy.
  1593  	SPOP_TA
  1594  	SPOP_TU
  1595  
  1596  	// Vector register group multiplier (VLMUL).
  1597  	SPOP_M1
  1598  	SPOP_M2
  1599  	SPOP_M4
  1600  	SPOP_M8
  1601  	SPOP_MF2
  1602  	SPOP_MF4
  1603  	SPOP_MF8
  1604  
  1605  	// Vector selected element width (VSEW).
  1606  	SPOP_E8
  1607  	SPOP_E16
  1608  	SPOP_E32
  1609  	SPOP_E64
  1610  	SPOP_RVV_END
  1611  
  1612  	// CSR names.  4096 special operands are reserved for RISC-V CSR names.
  1613  	SPOP_CSR_BEGIN = SPOP_RVV_END
  1614  	SPOP_CSR_END   = SPOP_CSR_BEGIN + 4096
  1615  
  1616  	SPOP_END = SPOP_CSR_END + 1
  1617  )
  1618  
  1619  var specialOperands = map[SpecialOperand]struct {
  1620  	encoding uint32
  1621  	name     string
  1622  }{
  1623  	SPOP_MA: {encoding: 1, name: "MA"},
  1624  	SPOP_MU: {encoding: 0, name: "MU"},
  1625  
  1626  	SPOP_TA: {encoding: 1, name: "TA"},
  1627  	SPOP_TU: {encoding: 0, name: "TU"},
  1628  
  1629  	SPOP_M1:  {encoding: 0, name: "M1"},
  1630  	SPOP_M2:  {encoding: 1, name: "M2"},
  1631  	SPOP_M4:  {encoding: 2, name: "M4"},
  1632  	SPOP_M8:  {encoding: 3, name: "M8"},
  1633  	SPOP_MF8: {encoding: 5, name: "MF8"},
  1634  	SPOP_MF4: {encoding: 6, name: "MF4"},
  1635  	SPOP_MF2: {encoding: 7, name: "MF2"},
  1636  
  1637  	SPOP_E8:  {encoding: 0, name: "E8"},
  1638  	SPOP_E16: {encoding: 1, name: "E16"},
  1639  	SPOP_E32: {encoding: 2, name: "E32"},
  1640  	SPOP_E64: {encoding: 3, name: "E64"},
  1641  }
  1642  
  1643  func (so SpecialOperand) encode() uint32 {
  1644  	switch {
  1645  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1646  		op, ok := specialOperands[so]
  1647  		if ok {
  1648  			return op.encoding
  1649  		}
  1650  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1651  		csrNum := uint16(so - SPOP_CSR_BEGIN)
  1652  		if _, ok := csrs[csrNum]; ok {
  1653  			return uint32(csrNum)
  1654  		}
  1655  	}
  1656  	return 0
  1657  }
  1658  
  1659  // String returns the textual representation of a SpecialOperand.
  1660  func (so SpecialOperand) String() string {
  1661  	switch {
  1662  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1663  		op, ok := specialOperands[so]
  1664  		if ok {
  1665  			return op.name
  1666  		}
  1667  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1668  		if csrName, ok := csrs[uint16(so-SPOP_CSR_BEGIN)]; ok {
  1669  			return csrName
  1670  		}
  1671  	}
  1672  	return ""
  1673  }
  1674  
  1675  // All unary instructions which write to their arguments (as opposed to reading
  1676  // from them) go here. The assembly parser uses this information to populate
  1677  // its AST in a semantically reasonable way.
  1678  //
  1679  // Any instructions not listed here are assumed to either be non-unary or to read
  1680  // from its argument.
  1681  var unaryDst = map[obj.As]bool{
  1682  	ARDCYCLE:   true,
  1683  	ARDTIME:    true,
  1684  	ARDINSTRET: true,
  1685  }
  1686  
  1687  // Instruction encoding masks.
  1688  const (
  1689  	// BTypeImmMask is a mask including only the immediate portion of
  1690  	// B-type instructions.
  1691  	BTypeImmMask = 0xfe000f80
  1692  
  1693  	// CBTypeImmMask is a mask including only the immediate portion of
  1694  	// CB-type instructions.
  1695  	CBTypeImmMask = 0x1c7c
  1696  
  1697  	// CJTypeImmMask is a mask including only the immediate portion of
  1698  	// CJ-type instructions.
  1699  	CJTypeImmMask = 0x1f7c
  1700  
  1701  	// ITypeImmMask is a mask including only the immediate portion of
  1702  	// I-type instructions.
  1703  	ITypeImmMask = 0xfff00000
  1704  
  1705  	// JTypeImmMask is a mask including only the immediate portion of
  1706  	// J-type instructions.
  1707  	JTypeImmMask = 0xfffff000
  1708  
  1709  	// STypeImmMask is a mask including only the immediate portion of
  1710  	// S-type instructions.
  1711  	STypeImmMask = 0xfe000f80
  1712  
  1713  	// UTypeImmMask is a mask including only the immediate portion of
  1714  	// U-type instructions.
  1715  	UTypeImmMask = 0xfffff000
  1716  )
  1717  

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