Source file src/cmd/internal/obj/riscv/cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  var CSRs map[uint16]string = csrs
    39  
    40  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    41  
    42  const (
    43  	// Base register numberings.
    44  	REG_X0 = obj.RBaseRISCV + iota
    45  	REG_X1
    46  	REG_X2
    47  	REG_X3
    48  	REG_X4
    49  	REG_X5
    50  	REG_X6
    51  	REG_X7
    52  	REG_X8
    53  	REG_X9
    54  	REG_X10
    55  	REG_X11
    56  	REG_X12
    57  	REG_X13
    58  	REG_X14
    59  	REG_X15
    60  	REG_X16
    61  	REG_X17
    62  	REG_X18
    63  	REG_X19
    64  	REG_X20
    65  	REG_X21
    66  	REG_X22
    67  	REG_X23
    68  	REG_X24
    69  	REG_X25
    70  	REG_X26
    71  	REG_X27
    72  	REG_X28
    73  	REG_X29
    74  	REG_X30
    75  	REG_X31
    76  
    77  	// Floating Point register numberings.
    78  	REG_F0
    79  	REG_F1
    80  	REG_F2
    81  	REG_F3
    82  	REG_F4
    83  	REG_F5
    84  	REG_F6
    85  	REG_F7
    86  	REG_F8
    87  	REG_F9
    88  	REG_F10
    89  	REG_F11
    90  	REG_F12
    91  	REG_F13
    92  	REG_F14
    93  	REG_F15
    94  	REG_F16
    95  	REG_F17
    96  	REG_F18
    97  	REG_F19
    98  	REG_F20
    99  	REG_F21
   100  	REG_F22
   101  	REG_F23
   102  	REG_F24
   103  	REG_F25
   104  	REG_F26
   105  	REG_F27
   106  	REG_F28
   107  	REG_F29
   108  	REG_F30
   109  	REG_F31
   110  
   111  	// Vector register numberings.
   112  	REG_V0
   113  	REG_V1
   114  	REG_V2
   115  	REG_V3
   116  	REG_V4
   117  	REG_V5
   118  	REG_V6
   119  	REG_V7
   120  	REG_V8
   121  	REG_V9
   122  	REG_V10
   123  	REG_V11
   124  	REG_V12
   125  	REG_V13
   126  	REG_V14
   127  	REG_V15
   128  	REG_V16
   129  	REG_V17
   130  	REG_V18
   131  	REG_V19
   132  	REG_V20
   133  	REG_V21
   134  	REG_V22
   135  	REG_V23
   136  	REG_V24
   137  	REG_V25
   138  	REG_V26
   139  	REG_V27
   140  	REG_V28
   141  	REG_V29
   142  	REG_V30
   143  	REG_V31
   144  
   145  	// This marks the end of the register numbering.
   146  	REG_END
   147  
   148  	// General registers reassigned to ABI names.
   149  	REG_ZERO = REG_X0
   150  	REG_RA   = REG_X1 // aka REG_LR
   151  	REG_SP   = REG_X2
   152  	REG_GP   = REG_X3 // aka REG_SB
   153  	REG_TP   = REG_X4
   154  	REG_T0   = REG_X5
   155  	REG_T1   = REG_X6
   156  	REG_T2   = REG_X7
   157  	REG_S0   = REG_X8
   158  	REG_S1   = REG_X9
   159  	REG_A0   = REG_X10
   160  	REG_A1   = REG_X11
   161  	REG_A2   = REG_X12
   162  	REG_A3   = REG_X13
   163  	REG_A4   = REG_X14
   164  	REG_A5   = REG_X15
   165  	REG_A6   = REG_X16
   166  	REG_A7   = REG_X17
   167  	REG_S2   = REG_X18
   168  	REG_S3   = REG_X19
   169  	REG_S4   = REG_X20
   170  	REG_S5   = REG_X21
   171  	REG_S6   = REG_X22
   172  	REG_S7   = REG_X23
   173  	REG_S8   = REG_X24
   174  	REG_S9   = REG_X25
   175  	REG_S10  = REG_X26 // aka REG_CTXT
   176  	REG_S11  = REG_X27 // aka REG_G
   177  	REG_T3   = REG_X28
   178  	REG_T4   = REG_X29
   179  	REG_T5   = REG_X30
   180  	REG_T6   = REG_X31 // aka REG_TMP
   181  
   182  	// Go runtime register names.
   183  	REG_CTXT = REG_S10 // Context for closures.
   184  	REG_G    = REG_S11 // G pointer.
   185  	REG_LR   = REG_RA  // Link register.
   186  	REG_TMP  = REG_T6  // Reserved for assembler use.
   187  
   188  	// ABI names for floating point registers.
   189  	REG_FT0  = REG_F0
   190  	REG_FT1  = REG_F1
   191  	REG_FT2  = REG_F2
   192  	REG_FT3  = REG_F3
   193  	REG_FT4  = REG_F4
   194  	REG_FT5  = REG_F5
   195  	REG_FT6  = REG_F6
   196  	REG_FT7  = REG_F7
   197  	REG_FS0  = REG_F8
   198  	REG_FS1  = REG_F9
   199  	REG_FA0  = REG_F10
   200  	REG_FA1  = REG_F11
   201  	REG_FA2  = REG_F12
   202  	REG_FA3  = REG_F13
   203  	REG_FA4  = REG_F14
   204  	REG_FA5  = REG_F15
   205  	REG_FA6  = REG_F16
   206  	REG_FA7  = REG_F17
   207  	REG_FS2  = REG_F18
   208  	REG_FS3  = REG_F19
   209  	REG_FS4  = REG_F20
   210  	REG_FS5  = REG_F21
   211  	REG_FS6  = REG_F22
   212  	REG_FS7  = REG_F23
   213  	REG_FS8  = REG_F24
   214  	REG_FS9  = REG_F25
   215  	REG_FS10 = REG_F26
   216  	REG_FS11 = REG_F27
   217  	REG_FT8  = REG_F28
   218  	REG_FT9  = REG_F29
   219  	REG_FT10 = REG_F30
   220  	REG_FT11 = REG_F31
   221  
   222  	// Names generated by the SSA compiler.
   223  	REGSP = REG_SP
   224  	REGG  = REG_G
   225  )
   226  
   227  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   228  var RISCV64DWARFRegisters = map[int16]int16{
   229  	// Integer Registers.
   230  	REG_X0:  0,
   231  	REG_X1:  1,
   232  	REG_X2:  2,
   233  	REG_X3:  3,
   234  	REG_X4:  4,
   235  	REG_X5:  5,
   236  	REG_X6:  6,
   237  	REG_X7:  7,
   238  	REG_X8:  8,
   239  	REG_X9:  9,
   240  	REG_X10: 10,
   241  	REG_X11: 11,
   242  	REG_X12: 12,
   243  	REG_X13: 13,
   244  	REG_X14: 14,
   245  	REG_X15: 15,
   246  	REG_X16: 16,
   247  	REG_X17: 17,
   248  	REG_X18: 18,
   249  	REG_X19: 19,
   250  	REG_X20: 20,
   251  	REG_X21: 21,
   252  	REG_X22: 22,
   253  	REG_X23: 23,
   254  	REG_X24: 24,
   255  	REG_X25: 25,
   256  	REG_X26: 26,
   257  	REG_X27: 27,
   258  	REG_X28: 28,
   259  	REG_X29: 29,
   260  	REG_X30: 30,
   261  	REG_X31: 31,
   262  
   263  	// Floating-Point Registers.
   264  	REG_F0:  32,
   265  	REG_F1:  33,
   266  	REG_F2:  34,
   267  	REG_F3:  35,
   268  	REG_F4:  36,
   269  	REG_F5:  37,
   270  	REG_F6:  38,
   271  	REG_F7:  39,
   272  	REG_F8:  40,
   273  	REG_F9:  41,
   274  	REG_F10: 42,
   275  	REG_F11: 43,
   276  	REG_F12: 44,
   277  	REG_F13: 45,
   278  	REG_F14: 46,
   279  	REG_F15: 47,
   280  	REG_F16: 48,
   281  	REG_F17: 49,
   282  	REG_F18: 50,
   283  	REG_F19: 51,
   284  	REG_F20: 52,
   285  	REG_F21: 53,
   286  	REG_F22: 54,
   287  	REG_F23: 55,
   288  	REG_F24: 56,
   289  	REG_F25: 57,
   290  	REG_F26: 58,
   291  	REG_F27: 59,
   292  	REG_F28: 60,
   293  	REG_F29: 61,
   294  	REG_F30: 62,
   295  	REG_F31: 63,
   296  
   297  	// Vector Registers.
   298  	REG_V0:  96,
   299  	REG_V1:  97,
   300  	REG_V2:  98,
   301  	REG_V3:  99,
   302  	REG_V4:  100,
   303  	REG_V5:  101,
   304  	REG_V6:  102,
   305  	REG_V7:  103,
   306  	REG_V8:  104,
   307  	REG_V9:  105,
   308  	REG_V10: 106,
   309  	REG_V11: 107,
   310  	REG_V12: 108,
   311  	REG_V13: 109,
   312  	REG_V14: 110,
   313  	REG_V15: 111,
   314  	REG_V16: 112,
   315  	REG_V17: 113,
   316  	REG_V18: 114,
   317  	REG_V19: 115,
   318  	REG_V20: 116,
   319  	REG_V21: 117,
   320  	REG_V22: 118,
   321  	REG_V23: 119,
   322  	REG_V24: 120,
   323  	REG_V25: 121,
   324  	REG_V26: 122,
   325  	REG_V27: 123,
   326  	REG_V28: 124,
   327  	REG_V29: 125,
   328  	REG_V30: 126,
   329  	REG_V31: 127,
   330  }
   331  
   332  // Prog.Mark flags.
   333  const (
   334  	// USES_REG_TMP indicates that a machine instruction generated from the
   335  	// corresponding *obj.Prog uses the temporary register.
   336  	USES_REG_TMP = 1 << iota
   337  
   338  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   339  	// R_RISCV_JAL relocation is needed.
   340  	NEED_JAL_RELOC
   341  
   342  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   343  	// is the first instruction in an AUIPC + JAL pair that needs a
   344  	// R_RISCV_CALL relocation.
   345  	NEED_CALL_RELOC
   346  
   347  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   348  	// it is the first instruction in an AUIPC + I-type pair that needs a
   349  	// R_RISCV_PCREL_ITYPE relocation.
   350  	NEED_PCREL_ITYPE_RELOC
   351  
   352  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   353  	// it is the first instruction in an AUIPC + S-type pair that needs a
   354  	// R_RISCV_PCREL_STYPE relocation.
   355  	NEED_PCREL_STYPE_RELOC
   356  
   357  	// NEED_GOT_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   358  	// it is the first instruction in an AUIPC + I-type pair that needs a
   359  	// R_RISCV_GOT_PCREL_ITYPE relocation.
   360  	NEED_GOT_PCREL_ITYPE_RELOC
   361  )
   362  
   363  const NEED_RELOC = NEED_JAL_RELOC | NEED_CALL_RELOC | NEED_PCREL_ITYPE_RELOC |
   364  	NEED_PCREL_STYPE_RELOC | NEED_GOT_PCREL_ITYPE_RELOC
   365  
   366  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   367  // at https://github.com/riscv/riscv-opcodes.
   368  //
   369  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   370  //
   371  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
   372  //
   373  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   374  const (
   375  	//
   376  	// Unprivileged ISA (version 20260120)
   377  	//
   378  
   379  	// 2.4: Integer Computational Instructions
   380  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   381  	ASLTI
   382  	ASLTIU
   383  	AANDI
   384  	AORI
   385  	AXORI
   386  	ASLLI
   387  	ASRLI
   388  	ASRAI
   389  	ALUI
   390  	AAUIPC
   391  	AADD
   392  	ASLT
   393  	ASLTU
   394  	AAND
   395  	AOR
   396  	AXOR
   397  	ASLL
   398  	ASRL
   399  	ASUB
   400  	ASRA
   401  
   402  	// 2.5: Control Transfer Instructions
   403  	AJAL
   404  	AJALR
   405  	ABEQ
   406  	ABNE
   407  	ABLT
   408  	ABLTU
   409  	ABGE
   410  	ABGEU
   411  
   412  	// 2.6: Load and Store Instructions
   413  	ALW
   414  	ALWU
   415  	ALH
   416  	ALHU
   417  	ALB
   418  	ALBU
   419  	ASW
   420  	ASH
   421  	ASB
   422  
   423  	// 2.7: Memory Ordering Instructions
   424  	AFENCE
   425  
   426  	// 4.2: Integer Computational Instructions (RV64I)
   427  	AADDIW
   428  	ASLLIW
   429  	ASRLIW
   430  	ASRAIW
   431  	AADDW
   432  	ASLLW
   433  	ASRLW
   434  	ASUBW
   435  	ASRAW
   436  
   437  	// 4.3: Load and Store Instructions (RV64I)
   438  	ALD
   439  	ASD
   440  
   441  	// 6.1: CSR Instructions (Zicsr)
   442  	ACSRRW
   443  	ACSRRS
   444  	ACSRRC
   445  	ACSRRWI
   446  	ACSRRSI
   447  	ACSRRCI
   448  
   449  	// 11.1: Integer Conditional Operations (Zicond)
   450  	ACZEROEQZ
   451  	ACZERONEZ
   452  
   453  	// 12.1: Multiplication Operations
   454  	AMUL
   455  	AMULH
   456  	AMULHU
   457  	AMULHSU
   458  	AMULW
   459  
   460  	// 12.2: Division Operations
   461  	ADIV
   462  	ADIVU
   463  	AREM
   464  	AREMU
   465  	ADIVW
   466  	ADIVUW
   467  	AREMW
   468  	AREMUW
   469  
   470  	// 13.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
   471  	ALRD
   472  	ASCD
   473  	ALRW
   474  	ASCW
   475  
   476  	// 13.4: Atomic Memory Operations (Zaamo)
   477  	AAMOSWAPD
   478  	AAMOADDD
   479  	AAMOANDD
   480  	AAMOORD
   481  	AAMOXORD
   482  	AAMOMAXD
   483  	AAMOMAXUD
   484  	AAMOMIND
   485  	AAMOMINUD
   486  	AAMOSWAPW
   487  	AAMOADDW
   488  	AAMOANDW
   489  	AAMOORW
   490  	AAMOXORW
   491  	AAMOMAXW
   492  	AAMOMAXUW
   493  	AAMOMINW
   494  	AAMOMINUW
   495  
   496  	// 21.5: Single-Precision Load and Store Instructions
   497  	AFLW
   498  	AFSW
   499  
   500  	// 21.6: Single-Precision Floating-Point Computational Instructions
   501  	AFADDS
   502  	AFSUBS
   503  	AFMULS
   504  	AFDIVS
   505  	AFMINS
   506  	AFMAXS
   507  	AFSQRTS
   508  	AFMADDS
   509  	AFMSUBS
   510  	AFNMADDS
   511  	AFNMSUBS
   512  
   513  	// 21.7: Single-Precision Floating-Point Conversion and Move Instructions
   514  	AFCVTWS
   515  	AFCVTLS
   516  	AFCVTSW
   517  	AFCVTSL
   518  	AFCVTWUS
   519  	AFCVTLUS
   520  	AFCVTSWU
   521  	AFCVTSLU
   522  	AFSGNJS
   523  	AFSGNJNS
   524  	AFSGNJXS
   525  	AFMVXS
   526  	AFMVSX
   527  	AFMVXW
   528  	AFMVWX
   529  
   530  	// 21.8: Single-Precision Floating-Point Compare Instructions
   531  	AFEQS
   532  	AFLTS
   533  	AFLES
   534  
   535  	// 21.9: Single-Precision Floating-Point Classify Instruction
   536  	AFCLASSS
   537  
   538  	// 22.3: Double-Precision Load and Store Instructions
   539  	AFLD
   540  	AFSD
   541  
   542  	// 22.4: Double-Precision Floating-Point Computational Instructions
   543  	AFADDD
   544  	AFSUBD
   545  	AFMULD
   546  	AFDIVD
   547  	AFMIND
   548  	AFMAXD
   549  	AFSQRTD
   550  	AFMADDD
   551  	AFMSUBD
   552  	AFNMADDD
   553  	AFNMSUBD
   554  
   555  	// 22.5: Double-Precision Floating-Point Conversion and Move Instructions
   556  	AFCVTWD
   557  	AFCVTLD
   558  	AFCVTDW
   559  	AFCVTDL
   560  	AFCVTWUD
   561  	AFCVTLUD
   562  	AFCVTDWU
   563  	AFCVTDLU
   564  	AFCVTSD
   565  	AFCVTDS
   566  	AFSGNJD
   567  	AFSGNJND
   568  	AFSGNJXD
   569  	AFMVXD
   570  	AFMVDX
   571  
   572  	// 22.6: Double-Precision Floating-Point Compare Instructions
   573  	AFEQD
   574  	AFLTD
   575  	AFLED
   576  
   577  	// 22.7: Double-Precision Floating-Point Classify Instruction
   578  	AFCLASSD
   579  
   580  	// 23.1: Quad-Precision Load and Store Instructions
   581  	AFLQ
   582  	AFSQ
   583  
   584  	// 23.2: Quad-Precision Computational Instructions
   585  	AFADDQ
   586  	AFSUBQ
   587  	AFMULQ
   588  	AFDIVQ
   589  	AFMINQ
   590  	AFMAXQ
   591  	AFSQRTQ
   592  	AFMADDQ
   593  	AFMSUBQ
   594  	AFNMADDQ
   595  	AFNMSUBQ
   596  
   597  	// 23.3: Quad-Precision Convert and Move Instructions
   598  	AFCVTWQ
   599  	AFCVTLQ
   600  	AFCVTSQ
   601  	AFCVTDQ
   602  	AFCVTQW
   603  	AFCVTQL
   604  	AFCVTQS
   605  	AFCVTQD
   606  	AFCVTWUQ
   607  	AFCVTLUQ
   608  	AFCVTQWU
   609  	AFCVTQLU
   610  	AFSGNJQ
   611  	AFSGNJNQ
   612  	AFSGNJXQ
   613  
   614  	// 23.4: Quad-Precision Floating-Point Compare Instructions
   615  	AFEQQ
   616  	AFLEQ
   617  	AFLTQ
   618  
   619  	// 23.5: Quad-Precision Floating-Point Classify Instruction
   620  	AFCLASSQ
   621  
   622  	//
   623  	// "C" Extension for Compressed Instructions
   624  	//
   625  
   626  	// 28.3.1: Compressed Stack-Pointer-Based Loads and Stores
   627  	ACLWSP
   628  	ACLDSP
   629  	ACFLDSP
   630  	ACSWSP
   631  	ACSDSP
   632  	ACFSDSP
   633  
   634  	// 28.3.2: Compressed Register-Based Loads and Stores
   635  	ACLW
   636  	ACLD
   637  	ACFLD
   638  	ACSW
   639  	ACSD
   640  	ACFSD
   641  
   642  	// 28.4: Compressed Control Transfer Instructions
   643  	ACJ
   644  	ACJR
   645  	ACJALR
   646  	ACBEQZ
   647  	ACBNEZ
   648  
   649  	// 28.5.1: Compressed Integer Constant-Generation Instructions
   650  	ACLI
   651  	ACLUI
   652  
   653  	// 28.5.2: Compressed Integer Register-Immediate Operations
   654  	ACADDI
   655  	ACADDIW
   656  	ACADDI16SP
   657  	ACADDI4SPN
   658  	ACSLLI
   659  	ACSRLI
   660  	ACSRAI
   661  	ACANDI
   662  
   663  	// 28.5.3: Compressed Integer Register-Register Operations
   664  	ACMV
   665  	ACADD
   666  	ACAND
   667  	ACOR
   668  	ACXOR
   669  	ACSUB
   670  	ACADDW
   671  	ACSUBW
   672  
   673  	// 28.5.5: Compressed NOP Instruction
   674  	ACNOP
   675  
   676  	// 28.5.6: Compressed Breakpoint Instruction
   677  	ACEBREAK
   678  
   679  	//
   680  	// "B" Extension for Bit Manipulation, Version 1.0.0
   681  	//
   682  
   683  	// 30.2: Address Generation Instructions (Zba)
   684  	AADDUW
   685  	ASH1ADD
   686  	ASH1ADDUW
   687  	ASH2ADD
   688  	ASH2ADDUW
   689  	ASH3ADD
   690  	ASH3ADDUW
   691  	ASLLIUW
   692  
   693  	// 30.3: Basic Bit Manipulation (Zbb)
   694  	AANDN
   695  	AORN
   696  	AXNOR
   697  	ACLZ
   698  	ACLZW
   699  	ACTZ
   700  	ACTZW
   701  	ACPOP
   702  	ACPOPW
   703  	AMAX
   704  	AMAXU
   705  	AMIN
   706  	AMINU
   707  	ASEXTB
   708  	ASEXTH
   709  	AZEXTH
   710  	AROL
   711  	AROLW
   712  	AROR
   713  	ARORI
   714  	ARORIW
   715  	ARORW
   716  	AORCB
   717  	AREV8
   718  
   719  	// 30.4: Carry-less multiplication (Zbc)
   720  	ACLMUL
   721  	ACLMULH
   722  	ACLMULR
   723  
   724  	// 30.5: Single-bit Instructions (Zbs)
   725  	ABCLR
   726  	ABCLRI
   727  	ABEXT
   728  	ABEXTI
   729  	ABINV
   730  	ABINVI
   731  	ABSET
   732  	ABSETI
   733  
   734  	//
   735  	// "V" Standard Extension for Vector Operations, Version 1.0
   736  	//
   737  
   738  	// 31.6: Configuration-Setting Instructions
   739  	AVSETVLI
   740  	AVSETIVLI
   741  	AVSETVL
   742  
   743  	// 31.7.4: Vector Unit-Stride Instructions
   744  	AVLE8V
   745  	AVLE16V
   746  	AVLE32V
   747  	AVLE64V
   748  	AVSE8V
   749  	AVSE16V
   750  	AVSE32V
   751  	AVSE64V
   752  	AVLMV
   753  	AVSMV
   754  
   755  	// 31.7.5: Vector Constant-Stride Instructions
   756  	AVLSE8V
   757  	AVLSE16V
   758  	AVLSE32V
   759  	AVLSE64V
   760  	AVSSE8V
   761  	AVSSE16V
   762  	AVSSE32V
   763  	AVSSE64V
   764  
   765  	// 31.7.6: Vector Indexed Instructions
   766  	AVLUXEI8V
   767  	AVLUXEI16V
   768  	AVLUXEI32V
   769  	AVLUXEI64V
   770  	AVLOXEI8V
   771  	AVLOXEI16V
   772  	AVLOXEI32V
   773  	AVLOXEI64V
   774  	AVSUXEI8V
   775  	AVSUXEI16V
   776  	AVSUXEI32V
   777  	AVSUXEI64V
   778  	AVSOXEI8V
   779  	AVSOXEI16V
   780  	AVSOXEI32V
   781  	AVSOXEI64V
   782  
   783  	// 31.7.7: Vector Unit-Stride Fault-Only-First Loads
   784  	AVLE8FFV
   785  	AVLE16FFV
   786  	AVLE32FFV
   787  	AVLE64FFV
   788  
   789  	// 31.7.8.1: Vector Unit-Stride Segment Loads and Stores
   790  	AVLSEG2E8V
   791  	AVLSEG3E8V
   792  	AVLSEG4E8V
   793  	AVLSEG5E8V
   794  	AVLSEG6E8V
   795  	AVLSEG7E8V
   796  	AVLSEG8E8V
   797  	AVLSEG2E16V
   798  	AVLSEG3E16V
   799  	AVLSEG4E16V
   800  	AVLSEG5E16V
   801  	AVLSEG6E16V
   802  	AVLSEG7E16V
   803  	AVLSEG8E16V
   804  	AVLSEG2E32V
   805  	AVLSEG3E32V
   806  	AVLSEG4E32V
   807  	AVLSEG5E32V
   808  	AVLSEG6E32V
   809  	AVLSEG7E32V
   810  	AVLSEG8E32V
   811  	AVLSEG2E64V
   812  	AVLSEG3E64V
   813  	AVLSEG4E64V
   814  	AVLSEG5E64V
   815  	AVLSEG6E64V
   816  	AVLSEG7E64V
   817  	AVLSEG8E64V
   818  
   819  	AVSSEG2E8V
   820  	AVSSEG3E8V
   821  	AVSSEG4E8V
   822  	AVSSEG5E8V
   823  	AVSSEG6E8V
   824  	AVSSEG7E8V
   825  	AVSSEG8E8V
   826  	AVSSEG2E16V
   827  	AVSSEG3E16V
   828  	AVSSEG4E16V
   829  	AVSSEG5E16V
   830  	AVSSEG6E16V
   831  	AVSSEG7E16V
   832  	AVSSEG8E16V
   833  	AVSSEG2E32V
   834  	AVSSEG3E32V
   835  	AVSSEG4E32V
   836  	AVSSEG5E32V
   837  	AVSSEG6E32V
   838  	AVSSEG7E32V
   839  	AVSSEG8E32V
   840  	AVSSEG2E64V
   841  	AVSSEG3E64V
   842  	AVSSEG4E64V
   843  	AVSSEG5E64V
   844  	AVSSEG6E64V
   845  	AVSSEG7E64V
   846  	AVSSEG8E64V
   847  
   848  	AVLSEG2E8FFV
   849  	AVLSEG3E8FFV
   850  	AVLSEG4E8FFV
   851  	AVLSEG5E8FFV
   852  	AVLSEG6E8FFV
   853  	AVLSEG7E8FFV
   854  	AVLSEG8E8FFV
   855  	AVLSEG2E16FFV
   856  	AVLSEG3E16FFV
   857  	AVLSEG4E16FFV
   858  	AVLSEG5E16FFV
   859  	AVLSEG6E16FFV
   860  	AVLSEG7E16FFV
   861  	AVLSEG8E16FFV
   862  	AVLSEG2E32FFV
   863  	AVLSEG3E32FFV
   864  	AVLSEG4E32FFV
   865  	AVLSEG5E32FFV
   866  	AVLSEG6E32FFV
   867  	AVLSEG7E32FFV
   868  	AVLSEG8E32FFV
   869  	AVLSEG2E64FFV
   870  	AVLSEG3E64FFV
   871  	AVLSEG4E64FFV
   872  	AVLSEG5E64FFV
   873  	AVLSEG6E64FFV
   874  	AVLSEG7E64FFV
   875  	AVLSEG8E64FFV
   876  
   877  	// 31.7.8.2: Vector Constant-Stride Segment Loads and Stores
   878  	AVLSSEG2E8V
   879  	AVLSSEG3E8V
   880  	AVLSSEG4E8V
   881  	AVLSSEG5E8V
   882  	AVLSSEG6E8V
   883  	AVLSSEG7E8V
   884  	AVLSSEG8E8V
   885  	AVLSSEG2E16V
   886  	AVLSSEG3E16V
   887  	AVLSSEG4E16V
   888  	AVLSSEG5E16V
   889  	AVLSSEG6E16V
   890  	AVLSSEG7E16V
   891  	AVLSSEG8E16V
   892  	AVLSSEG2E32V
   893  	AVLSSEG3E32V
   894  	AVLSSEG4E32V
   895  	AVLSSEG5E32V
   896  	AVLSSEG6E32V
   897  	AVLSSEG7E32V
   898  	AVLSSEG8E32V
   899  	AVLSSEG2E64V
   900  	AVLSSEG3E64V
   901  	AVLSSEG4E64V
   902  	AVLSSEG5E64V
   903  	AVLSSEG6E64V
   904  	AVLSSEG7E64V
   905  	AVLSSEG8E64V
   906  
   907  	AVSSSEG2E8V
   908  	AVSSSEG3E8V
   909  	AVSSSEG4E8V
   910  	AVSSSEG5E8V
   911  	AVSSSEG6E8V
   912  	AVSSSEG7E8V
   913  	AVSSSEG8E8V
   914  	AVSSSEG2E16V
   915  	AVSSSEG3E16V
   916  	AVSSSEG4E16V
   917  	AVSSSEG5E16V
   918  	AVSSSEG6E16V
   919  	AVSSSEG7E16V
   920  	AVSSSEG8E16V
   921  	AVSSSEG2E32V
   922  	AVSSSEG3E32V
   923  	AVSSSEG4E32V
   924  	AVSSSEG5E32V
   925  	AVSSSEG6E32V
   926  	AVSSSEG7E32V
   927  	AVSSSEG8E32V
   928  	AVSSSEG2E64V
   929  	AVSSSEG3E64V
   930  	AVSSSEG4E64V
   931  	AVSSSEG5E64V
   932  	AVSSSEG6E64V
   933  	AVSSSEG7E64V
   934  	AVSSSEG8E64V
   935  
   936  	// 31.7.8.3: Vector Indexed Segment Loads and Stores
   937  	AVLOXSEG2EI8V
   938  	AVLOXSEG3EI8V
   939  	AVLOXSEG4EI8V
   940  	AVLOXSEG5EI8V
   941  	AVLOXSEG6EI8V
   942  	AVLOXSEG7EI8V
   943  	AVLOXSEG8EI8V
   944  	AVLOXSEG2EI16V
   945  	AVLOXSEG3EI16V
   946  	AVLOXSEG4EI16V
   947  	AVLOXSEG5EI16V
   948  	AVLOXSEG6EI16V
   949  	AVLOXSEG7EI16V
   950  	AVLOXSEG8EI16V
   951  	AVLOXSEG2EI32V
   952  	AVLOXSEG3EI32V
   953  	AVLOXSEG4EI32V
   954  	AVLOXSEG5EI32V
   955  	AVLOXSEG6EI32V
   956  	AVLOXSEG7EI32V
   957  	AVLOXSEG8EI32V
   958  	AVLOXSEG2EI64V
   959  	AVLOXSEG3EI64V
   960  	AVLOXSEG4EI64V
   961  	AVLOXSEG5EI64V
   962  	AVLOXSEG6EI64V
   963  	AVLOXSEG7EI64V
   964  	AVLOXSEG8EI64V
   965  
   966  	AVSOXSEG2EI8V
   967  	AVSOXSEG3EI8V
   968  	AVSOXSEG4EI8V
   969  	AVSOXSEG5EI8V
   970  	AVSOXSEG6EI8V
   971  	AVSOXSEG7EI8V
   972  	AVSOXSEG8EI8V
   973  	AVSOXSEG2EI16V
   974  	AVSOXSEG3EI16V
   975  	AVSOXSEG4EI16V
   976  	AVSOXSEG5EI16V
   977  	AVSOXSEG6EI16V
   978  	AVSOXSEG7EI16V
   979  	AVSOXSEG8EI16V
   980  	AVSOXSEG2EI32V
   981  	AVSOXSEG3EI32V
   982  	AVSOXSEG4EI32V
   983  	AVSOXSEG5EI32V
   984  	AVSOXSEG6EI32V
   985  	AVSOXSEG7EI32V
   986  	AVSOXSEG8EI32V
   987  	AVSOXSEG2EI64V
   988  	AVSOXSEG3EI64V
   989  	AVSOXSEG4EI64V
   990  	AVSOXSEG5EI64V
   991  	AVSOXSEG6EI64V
   992  	AVSOXSEG7EI64V
   993  	AVSOXSEG8EI64V
   994  
   995  	AVLUXSEG2EI8V
   996  	AVLUXSEG3EI8V
   997  	AVLUXSEG4EI8V
   998  	AVLUXSEG5EI8V
   999  	AVLUXSEG6EI8V
  1000  	AVLUXSEG7EI8V
  1001  	AVLUXSEG8EI8V
  1002  	AVLUXSEG2EI16V
  1003  	AVLUXSEG3EI16V
  1004  	AVLUXSEG4EI16V
  1005  	AVLUXSEG5EI16V
  1006  	AVLUXSEG6EI16V
  1007  	AVLUXSEG7EI16V
  1008  	AVLUXSEG8EI16V
  1009  	AVLUXSEG2EI32V
  1010  	AVLUXSEG3EI32V
  1011  	AVLUXSEG4EI32V
  1012  	AVLUXSEG5EI32V
  1013  	AVLUXSEG6EI32V
  1014  	AVLUXSEG7EI32V
  1015  	AVLUXSEG8EI32V
  1016  	AVLUXSEG2EI64V
  1017  	AVLUXSEG3EI64V
  1018  	AVLUXSEG4EI64V
  1019  	AVLUXSEG5EI64V
  1020  	AVLUXSEG6EI64V
  1021  	AVLUXSEG7EI64V
  1022  	AVLUXSEG8EI64V
  1023  
  1024  	AVSUXSEG2EI8V
  1025  	AVSUXSEG3EI8V
  1026  	AVSUXSEG4EI8V
  1027  	AVSUXSEG5EI8V
  1028  	AVSUXSEG6EI8V
  1029  	AVSUXSEG7EI8V
  1030  	AVSUXSEG8EI8V
  1031  	AVSUXSEG2EI16V
  1032  	AVSUXSEG3EI16V
  1033  	AVSUXSEG4EI16V
  1034  	AVSUXSEG5EI16V
  1035  	AVSUXSEG6EI16V
  1036  	AVSUXSEG7EI16V
  1037  	AVSUXSEG8EI16V
  1038  	AVSUXSEG2EI32V
  1039  	AVSUXSEG3EI32V
  1040  	AVSUXSEG4EI32V
  1041  	AVSUXSEG5EI32V
  1042  	AVSUXSEG6EI32V
  1043  	AVSUXSEG7EI32V
  1044  	AVSUXSEG8EI32V
  1045  	AVSUXSEG2EI64V
  1046  	AVSUXSEG3EI64V
  1047  	AVSUXSEG4EI64V
  1048  	AVSUXSEG5EI64V
  1049  	AVSUXSEG6EI64V
  1050  	AVSUXSEG7EI64V
  1051  	AVSUXSEG8EI64V
  1052  
  1053  	// 31.7.9: Vector Load/Store Whole Register Instructions
  1054  	AVL1RE8V
  1055  	AVL1RE16V
  1056  	AVL1RE32V
  1057  	AVL1RE64V
  1058  	AVL2RE8V
  1059  	AVL2RE16V
  1060  	AVL2RE32V
  1061  	AVL2RE64V
  1062  	AVL4RE8V
  1063  	AVL4RE16V
  1064  	AVL4RE32V
  1065  	AVL4RE64V
  1066  	AVL8RE8V
  1067  	AVL8RE16V
  1068  	AVL8RE32V
  1069  	AVL8RE64V
  1070  	AVS1RV
  1071  	AVS2RV
  1072  	AVS4RV
  1073  	AVS8RV
  1074  
  1075  	// 31.11.1: Vector Single-Width Integer Add and Subtract
  1076  	AVADDVV
  1077  	AVADDVX
  1078  	AVADDVI
  1079  	AVSUBVV
  1080  	AVSUBVX
  1081  	AVRSUBVX
  1082  	AVRSUBVI
  1083  
  1084  	// 31.11.2: Vector Widening Integer Add/Subtract
  1085  	AVWADDUVV
  1086  	AVWADDUVX
  1087  	AVWSUBUVV
  1088  	AVWSUBUVX
  1089  	AVWADDVV
  1090  	AVWADDVX
  1091  	AVWSUBVV
  1092  	AVWSUBVX
  1093  	AVWADDUWV
  1094  	AVWADDUWX
  1095  	AVWSUBUWV
  1096  	AVWSUBUWX
  1097  	AVWADDWV
  1098  	AVWADDWX
  1099  	AVWSUBWV
  1100  	AVWSUBWX
  1101  
  1102  	// 31.11.3: Vector Integer Extension
  1103  	AVZEXTVF2
  1104  	AVSEXTVF2
  1105  	AVZEXTVF4
  1106  	AVSEXTVF4
  1107  	AVZEXTVF8
  1108  	AVSEXTVF8
  1109  
  1110  	// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
  1111  	AVADCVVM
  1112  	AVADCVXM
  1113  	AVADCVIM
  1114  	AVMADCVVM
  1115  	AVMADCVXM
  1116  	AVMADCVIM
  1117  	AVMADCVV
  1118  	AVMADCVX
  1119  	AVMADCVI
  1120  	AVSBCVVM
  1121  	AVSBCVXM
  1122  	AVMSBCVVM
  1123  	AVMSBCVXM
  1124  	AVMSBCVV
  1125  	AVMSBCVX
  1126  
  1127  	// 31.11.5: Vector Bitwise Logical Instructions
  1128  	AVANDVV
  1129  	AVANDVX
  1130  	AVANDVI
  1131  	AVORVV
  1132  	AVORVX
  1133  	AVORVI
  1134  	AVXORVV
  1135  	AVXORVX
  1136  	AVXORVI
  1137  
  1138  	// 31.11.6: Vector Single-Width Shift Instructions
  1139  	AVSLLVV
  1140  	AVSLLVX
  1141  	AVSLLVI
  1142  	AVSRLVV
  1143  	AVSRLVX
  1144  	AVSRLVI
  1145  	AVSRAVV
  1146  	AVSRAVX
  1147  	AVSRAVI
  1148  
  1149  	// 31.11.7: Vector Narrowing Integer Right Shift Instructions
  1150  	AVNSRLWV
  1151  	AVNSRLWX
  1152  	AVNSRLWI
  1153  	AVNSRAWV
  1154  	AVNSRAWX
  1155  	AVNSRAWI
  1156  
  1157  	// 31.11.8: Vector Integer Compare Instructions
  1158  	AVMSEQVV
  1159  	AVMSEQVX
  1160  	AVMSEQVI
  1161  	AVMSNEVV
  1162  	AVMSNEVX
  1163  	AVMSNEVI
  1164  	AVMSLTUVV
  1165  	AVMSLTUVX
  1166  	AVMSLTVV
  1167  	AVMSLTVX
  1168  	AVMSLEUVV
  1169  	AVMSLEUVX
  1170  	AVMSLEUVI
  1171  	AVMSLEVV
  1172  	AVMSLEVX
  1173  	AVMSLEVI
  1174  	AVMSGTUVX
  1175  	AVMSGTUVI
  1176  	AVMSGTVX
  1177  	AVMSGTVI
  1178  
  1179  	// 31.11.9: Vector Integer Min/Max Instructions
  1180  	AVMINUVV
  1181  	AVMINUVX
  1182  	AVMINVV
  1183  	AVMINVX
  1184  	AVMAXUVV
  1185  	AVMAXUVX
  1186  	AVMAXVV
  1187  	AVMAXVX
  1188  
  1189  	// 31.11.10: Vector Single-Width Integer Multiply Instructions
  1190  	AVMULVV
  1191  	AVMULVX
  1192  	AVMULHVV
  1193  	AVMULHVX
  1194  	AVMULHUVV
  1195  	AVMULHUVX
  1196  	AVMULHSUVV
  1197  	AVMULHSUVX
  1198  
  1199  	// 31.11.11: Vector Integer Divide Instructions
  1200  	AVDIVUVV
  1201  	AVDIVUVX
  1202  	AVDIVVV
  1203  	AVDIVVX
  1204  	AVREMUVV
  1205  	AVREMUVX
  1206  	AVREMVV
  1207  	AVREMVX
  1208  
  1209  	// 31.11.12: Vector Widening Integer Multiply Instructions
  1210  	AVWMULVV
  1211  	AVWMULVX
  1212  	AVWMULUVV
  1213  	AVWMULUVX
  1214  	AVWMULSUVV
  1215  	AVWMULSUVX
  1216  
  1217  	// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
  1218  	AVMACCVV
  1219  	AVMACCVX
  1220  	AVNMSACVV
  1221  	AVNMSACVX
  1222  	AVMADDVV
  1223  	AVMADDVX
  1224  	AVNMSUBVV
  1225  	AVNMSUBVX
  1226  
  1227  	// 31.11.14: Vector Widening Integer Multiply-Add Instructions
  1228  	AVWMACCUVV
  1229  	AVWMACCUVX
  1230  	AVWMACCVV
  1231  	AVWMACCVX
  1232  	AVWMACCSUVV
  1233  	AVWMACCSUVX
  1234  	AVWMACCUSVX
  1235  
  1236  	// 31.11.15: Vector Integer Merge Instructions
  1237  	AVMERGEVVM
  1238  	AVMERGEVXM
  1239  	AVMERGEVIM
  1240  
  1241  	// 31.11.16: Vector Integer Move Instructions
  1242  	AVMVVV
  1243  	AVMVVX
  1244  	AVMVVI
  1245  
  1246  	// 31.12.1: Vector Single-Width Saturating Add and Subtract
  1247  	AVSADDUVV
  1248  	AVSADDUVX
  1249  	AVSADDUVI
  1250  	AVSADDVV
  1251  	AVSADDVX
  1252  	AVSADDVI
  1253  	AVSSUBUVV
  1254  	AVSSUBUVX
  1255  	AVSSUBVV
  1256  	AVSSUBVX
  1257  
  1258  	// 31.12.2: Vector Single-Width Averaging Add and Subtract
  1259  	AVAADDUVV
  1260  	AVAADDUVX
  1261  	AVAADDVV
  1262  	AVAADDVX
  1263  	AVASUBUVV
  1264  	AVASUBUVX
  1265  	AVASUBVV
  1266  	AVASUBVX
  1267  
  1268  	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
  1269  	AVSMULVV
  1270  	AVSMULVX
  1271  
  1272  	// 31.12.4: Vector Single-Width Scaling Shift Instructions
  1273  	AVSSRLVV
  1274  	AVSSRLVX
  1275  	AVSSRLVI
  1276  	AVSSRAVV
  1277  	AVSSRAVX
  1278  	AVSSRAVI
  1279  
  1280  	// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
  1281  	AVNCLIPUWV
  1282  	AVNCLIPUWX
  1283  	AVNCLIPUWI
  1284  	AVNCLIPWV
  1285  	AVNCLIPWX
  1286  	AVNCLIPWI
  1287  
  1288  	// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
  1289  	AVFADDVV
  1290  	AVFADDVF
  1291  	AVFSUBVV
  1292  	AVFSUBVF
  1293  	AVFRSUBVF
  1294  
  1295  	// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
  1296  	AVFWADDVV
  1297  	AVFWADDVF
  1298  	AVFWSUBVV
  1299  	AVFWSUBVF
  1300  	AVFWADDWV
  1301  	AVFWADDWF
  1302  	AVFWSUBWV
  1303  	AVFWSUBWF
  1304  
  1305  	// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
  1306  	AVFMULVV
  1307  	AVFMULVF
  1308  	AVFDIVVV
  1309  	AVFDIVVF
  1310  	AVFRDIVVF
  1311  
  1312  	// 31.13.5: Vector Widening Floating-Point Multiply
  1313  	AVFWMULVV
  1314  	AVFWMULVF
  1315  
  1316  	// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
  1317  	AVFMACCVV
  1318  	AVFMACCVF
  1319  	AVFNMACCVV
  1320  	AVFNMACCVF
  1321  	AVFMSACVV
  1322  	AVFMSACVF
  1323  	AVFNMSACVV
  1324  	AVFNMSACVF
  1325  	AVFMADDVV
  1326  	AVFMADDVF
  1327  	AVFNMADDVV
  1328  	AVFNMADDVF
  1329  	AVFMSUBVV
  1330  	AVFMSUBVF
  1331  	AVFNMSUBVV
  1332  	AVFNMSUBVF
  1333  
  1334  	// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
  1335  	AVFWMACCVV
  1336  	AVFWMACCVF
  1337  	AVFWNMACCVV
  1338  	AVFWNMACCVF
  1339  	AVFWMSACVV
  1340  	AVFWMSACVF
  1341  	AVFWNMSACVV
  1342  	AVFWNMSACVF
  1343  
  1344  	// 31.13.8: Vector Floating-Point Square-Root Instruction
  1345  	AVFSQRTV
  1346  
  1347  	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
  1348  	AVFRSQRT7V
  1349  
  1350  	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
  1351  	AVFREC7V
  1352  
  1353  	// 31.13.11: Vector Floating-Point MIN/MAX Instructions
  1354  	AVFMINVV
  1355  	AVFMINVF
  1356  	AVFMAXVV
  1357  	AVFMAXVF
  1358  
  1359  	// 31.13.12: Vector Floating-Point Sign-Injection Instructions
  1360  	AVFSGNJVV
  1361  	AVFSGNJVF
  1362  	AVFSGNJNVV
  1363  	AVFSGNJNVF
  1364  	AVFSGNJXVV
  1365  	AVFSGNJXVF
  1366  
  1367  	// 31.13.13: Vector Floating-Point Compare Instructions
  1368  	AVMFEQVV
  1369  	AVMFEQVF
  1370  	AVMFNEVV
  1371  	AVMFNEVF
  1372  	AVMFLTVV
  1373  	AVMFLTVF
  1374  	AVMFLEVV
  1375  	AVMFLEVF
  1376  	AVMFGTVF
  1377  	AVMFGEVF
  1378  
  1379  	// 31.13.14: Vector Floating-Point Classify Instruction
  1380  	AVFCLASSV
  1381  
  1382  	// 31.13.15: Vector Floating-Point Merge Instruction
  1383  	AVFMERGEVFM
  1384  
  1385  	// 31.13.16: Vector Floating-Point Move Instruction
  1386  	AVFMVVF
  1387  
  1388  	// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
  1389  	AVFCVTXUFV
  1390  	AVFCVTXFV
  1391  	AVFCVTRTZXUFV
  1392  	AVFCVTRTZXFV
  1393  	AVFCVTFXUV
  1394  	AVFCVTFXV
  1395  
  1396  	// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
  1397  	AVFWCVTXUFV
  1398  	AVFWCVTXFV
  1399  	AVFWCVTRTZXUFV
  1400  	AVFWCVTRTZXFV
  1401  	AVFWCVTFXUV
  1402  	AVFWCVTFXV
  1403  	AVFWCVTFFV
  1404  
  1405  	// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
  1406  	AVFNCVTXUFW
  1407  	AVFNCVTXFW
  1408  	AVFNCVTRTZXUFW
  1409  	AVFNCVTRTZXFW
  1410  	AVFNCVTFXUW
  1411  	AVFNCVTFXW
  1412  	AVFNCVTFFW
  1413  	AVFNCVTRODFFW
  1414  
  1415  	// 31.14.1: Vector Single-Width Integer Reduction Instructions
  1416  	AVREDSUMVS
  1417  	AVREDMAXUVS
  1418  	AVREDMAXVS
  1419  	AVREDMINUVS
  1420  	AVREDMINVS
  1421  	AVREDANDVS
  1422  	AVREDORVS
  1423  	AVREDXORVS
  1424  
  1425  	// 31.14.2: Vector Widening Integer Reduction Instructions
  1426  	AVWREDSUMUVS
  1427  	AVWREDSUMVS
  1428  
  1429  	// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
  1430  	AVFREDOSUMVS
  1431  	AVFREDUSUMVS
  1432  	AVFREDMAXVS
  1433  	AVFREDMINVS
  1434  
  1435  	// 31.14.4: Vector Widening Floating-Point Reduction Instructions
  1436  	AVFWREDOSUMVS
  1437  	AVFWREDUSUMVS
  1438  
  1439  	// 31.15: Vector Mask Instructions
  1440  	AVMANDMM
  1441  	AVMNANDMM
  1442  	AVMANDNMM
  1443  	AVMXORMM
  1444  	AVMORMM
  1445  	AVMNORMM
  1446  	AVMORNMM
  1447  	AVMXNORMM
  1448  	AVCPOPM
  1449  	AVFIRSTM
  1450  	AVMSBFM
  1451  	AVMSIFM
  1452  	AVMSOFM
  1453  	AVIOTAM
  1454  	AVIDV
  1455  
  1456  	// 31.16.1: Integer Scalar Move Instructions
  1457  	AVMVXS
  1458  	AVMVSX
  1459  
  1460  	// 31.16.2: Floating-Point Scalar Move Instructions
  1461  	AVFMVFS
  1462  	AVFMVSF
  1463  
  1464  	// 31.16.3: Vector Slide Instructions
  1465  	AVSLIDEUPVX
  1466  	AVSLIDEUPVI
  1467  	AVSLIDEDOWNVX
  1468  	AVSLIDEDOWNVI
  1469  	AVSLIDE1UPVX
  1470  	AVFSLIDE1UPVF
  1471  	AVSLIDE1DOWNVX
  1472  	AVFSLIDE1DOWNVF
  1473  
  1474  	// 31.16.4: Vector Register Gather Instructions
  1475  	AVRGATHERVV
  1476  	AVRGATHEREI16VV
  1477  	AVRGATHERVX
  1478  	AVRGATHERVI
  1479  
  1480  	// 31.16.5: Vector Compress Instruction
  1481  	AVCOMPRESSVM
  1482  
  1483  	// 31.16.6: Whole Vector Register Move
  1484  	AVMV1RV
  1485  	AVMV2RV
  1486  	AVMV4RV
  1487  	AVMV8RV
  1488  
  1489  	// 33.2.1: Vector Basic Bit-manipulation (Zvbb)
  1490  	AVANDNVV
  1491  	AVANDNVX
  1492  	AVBREVV
  1493  	AVBREV8V
  1494  	AVREV8V
  1495  	AVCLZV
  1496  	AVCTZV
  1497  	AVCPOPV
  1498  	AVROLVV
  1499  	AVROLVX
  1500  	AVRORVV
  1501  	AVRORVX
  1502  	AVRORVI
  1503  	AVWSLLVV
  1504  	AVWSLLVX
  1505  	AVWSLLVI
  1506  
  1507  	// 33.2.2: Vector Carryless Multiplication (Zvbc)
  1508  	AVCLMULVV
  1509  	AVCLMULVX
  1510  	AVCLMULHVV
  1511  	AVCLMULHVX
  1512  
  1513  	// 33.2.4: Vector GCM/GMAC (Zvkg)
  1514  	AVGHSHVV
  1515  	AVGMULVV
  1516  
  1517  	// 33.2.5: NIST Suite: Vector AES Block Cipher (Zvkned)
  1518  	AVAESEFVV
  1519  	AVAESEFVS
  1520  	AVAESEMVV
  1521  	AVAESEMVS
  1522  	AVAESDFVV
  1523  	AVAESDFVS
  1524  	AVAESDMVV
  1525  	AVAESDMVS
  1526  	AVAESKF1VI
  1527  	AVAESKF2VI
  1528  	AVAESZVS
  1529  
  1530  	// 33.2.6: NIST Suite: Vector SHA-2 Secure Hash (Zvknh[ab])
  1531  	AVSHA2MSVV
  1532  	AVSHA2CHVV
  1533  	AVSHA2CLVV
  1534  
  1535  	// 33.2.7: ShangMi Suite: SM4 Block Cipher (Zvksed)
  1536  	AVSM4KVI
  1537  	AVSM4RVV
  1538  	AVSM4RVS
  1539  
  1540  	// 33.2.8: ShangMi Suite: SM3 Secure Hash (Zvksh)
  1541  	AVSM3MEVV
  1542  	AVSM3CVI
  1543  
  1544  	//
  1545  	// Privileged ISA (version 20260120)
  1546  	//
  1547  
  1548  	// 3.3.1: Environment Call and Breakpoint
  1549  	AECALL
  1550  	ASCALL
  1551  	AEBREAK
  1552  	ASBREAK
  1553  
  1554  	// 3.3.2: Trap-Return Instructions
  1555  	AMRET
  1556  	ASRET
  1557  	ADRET
  1558  
  1559  	// 3.3.3: Wait for Interrupt
  1560  	AWFI
  1561  
  1562  	// 12.2.1: Supervisor Memory-Management Fence Instruction
  1563  	ASFENCEVMA
  1564  
  1565  	// The escape hatch. Inserts a single 32-bit word.
  1566  	AWORD
  1567  
  1568  	// Pseudo-instructions.  These get translated by the assembler into other
  1569  	// instructions, based on their operands.
  1570  	ABEQZ
  1571  	ABGEZ
  1572  	ABGT
  1573  	ABGTU
  1574  	ABGTZ
  1575  	ABLE
  1576  	ABLEU
  1577  	ABLEZ
  1578  	ABLTZ
  1579  	ABNEZ
  1580  	ACSRC
  1581  	ACSRCI
  1582  	ACSRR
  1583  	ACSRS
  1584  	ACSRSI
  1585  	ACSRW
  1586  	ACSRWI
  1587  	AFABSD
  1588  	AFABSS
  1589  	AFNED
  1590  	AFNEGD
  1591  	AFNEGS
  1592  	AFNES
  1593  	AMOV
  1594  	AMOVB
  1595  	AMOVBU
  1596  	AMOVD
  1597  	AMOVF
  1598  	AMOVH
  1599  	AMOVHU
  1600  	AMOVW
  1601  	AMOVWU
  1602  	ANEG
  1603  	ANEGW
  1604  	ANOT
  1605  	APAUSE
  1606  	ARDCYCLE
  1607  	ARDINSTRET
  1608  	ARDTIME
  1609  	ASEQZ
  1610  	ASNEZ
  1611  	AVFABSV
  1612  	AVFNEGV
  1613  	AVL1RV
  1614  	AVL2RV
  1615  	AVL4RV
  1616  	AVL8RV
  1617  	AVMCLRM
  1618  	AVMFGEVV
  1619  	AVMFGTVV
  1620  	AVMMVM
  1621  	AVMNOTM
  1622  	AVMSETM
  1623  	AVMSGEUVI
  1624  	AVMSGEUVV
  1625  	AVMSGEVI
  1626  	AVMSGEVV
  1627  	AVMSGTUVV
  1628  	AVMSGTVV
  1629  	AVMSLTUVI
  1630  	AVMSLTVI
  1631  	AVNCVTXXW
  1632  	AVNEGV
  1633  	AVNOTV
  1634  	AVWCVTUXXV
  1635  	AVWCVTXXV
  1636  
  1637  	// End marker
  1638  	ALAST
  1639  )
  1640  
  1641  // opSuffix encoding to uint8 which fit into p.Scond
  1642  var rmSuffixSet = map[string]uint8{
  1643  	"RNE": RM_RNE,
  1644  	"RTZ": RM_RTZ,
  1645  	"RDN": RM_RDN,
  1646  	"RUP": RM_RUP,
  1647  	"RMM": RM_RMM,
  1648  }
  1649  
  1650  const (
  1651  	fenceTsoSuffixBit uint8 = 1 << 0
  1652  	rmSuffixBit       uint8 = 1 << 7
  1653  )
  1654  
  1655  func rmSuffixEncode(s string) (uint8, error) {
  1656  	if s == "" {
  1657  		return 0, errors.New("empty suffix")
  1658  	}
  1659  	enc, ok := rmSuffixSet[s]
  1660  	if !ok {
  1661  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
  1662  	}
  1663  	return enc | rmSuffixBit, nil
  1664  }
  1665  
  1666  func rmSuffixString(u uint8) (string, error) {
  1667  	if u&rmSuffixBit == 0 {
  1668  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
  1669  	}
  1670  
  1671  	u &^= rmSuffixBit
  1672  	for k, v := range rmSuffixSet {
  1673  		if v == u {
  1674  			return k, nil
  1675  		}
  1676  	}
  1677  	return "", fmt.Errorf("unknown suffix:%x", u)
  1678  }
  1679  
  1680  // RoundingModeSuffix returns the Scond value for an explicitly encoded
  1681  // floating-point rounding mode.
  1682  func RoundingModeSuffix(rm uint8) uint8 {
  1683  	return rm | rmSuffixBit
  1684  }
  1685  
  1686  const (
  1687  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
  1688  	RM_RTZ              // Round towards Zero
  1689  	RM_RDN              // Round Down
  1690  	RM_RUP              // Round Up
  1691  	RM_RMM              // Round to Nearest, ties to Max Magnitude
  1692  )
  1693  
  1694  type SpecialOperand int
  1695  
  1696  const (
  1697  	SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase
  1698  	SPOP_RVV_BEGIN
  1699  
  1700  	// Vector mask policy.
  1701  	SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 2
  1702  	SPOP_MU
  1703  
  1704  	// Vector tail policy.
  1705  	SPOP_TA
  1706  	SPOP_TU
  1707  
  1708  	// Vector register group multiplier (VLMUL).
  1709  	SPOP_M1
  1710  	SPOP_M2
  1711  	SPOP_M4
  1712  	SPOP_M8
  1713  	SPOP_MF2
  1714  	SPOP_MF4
  1715  	SPOP_MF8
  1716  
  1717  	// Vector selected element width (VSEW).
  1718  	SPOP_E8
  1719  	SPOP_E16
  1720  	SPOP_E32
  1721  	SPOP_E64
  1722  	SPOP_RVV_END
  1723  
  1724  	// CSR names.  4096 special operands are reserved for RISC-V CSR names.
  1725  	SPOP_CSR_BEGIN = SPOP_RVV_END
  1726  	SPOP_CSR_END   = SPOP_CSR_BEGIN + 4096
  1727  
  1728  	// FENCE operands. 16 special operands are reserved for FENCE flags (4 bits: IORW).
  1729  	SPOP_FENCE_BEGIN = SPOP_CSR_END
  1730  
  1731  	SPOP_FENCE_W SpecialOperand = SPOP_FENCE_BEGIN + iota - 20
  1732  	SPOP_FENCE_R
  1733  	SPOP_FENCE_RW
  1734  	SPOP_FENCE_O
  1735  	SPOP_FENCE_OW
  1736  	SPOP_FENCE_OR
  1737  	SPOP_FENCE_ORW
  1738  	SPOP_FENCE_I
  1739  	SPOP_FENCE_IW
  1740  	SPOP_FENCE_IR
  1741  	SPOP_FENCE_IRW
  1742  	SPOP_FENCE_IO
  1743  	SPOP_FENCE_IOW
  1744  	SPOP_FENCE_IOR
  1745  	SPOP_FENCE_IORW
  1746  
  1747  	SPOP_FENCE_END = SPOP_FENCE_BEGIN + 16
  1748  
  1749  	SPOP_END = SPOP_FENCE_END + 1
  1750  )
  1751  
  1752  var specialOperands = map[SpecialOperand]struct {
  1753  	encoding uint32
  1754  	name     string
  1755  }{
  1756  	SPOP_MA: {encoding: 1, name: "MA"},
  1757  	SPOP_MU: {encoding: 0, name: "MU"},
  1758  
  1759  	SPOP_TA: {encoding: 1, name: "TA"},
  1760  	SPOP_TU: {encoding: 0, name: "TU"},
  1761  
  1762  	SPOP_M1:  {encoding: 0, name: "M1"},
  1763  	SPOP_M2:  {encoding: 1, name: "M2"},
  1764  	SPOP_M4:  {encoding: 2, name: "M4"},
  1765  	SPOP_M8:  {encoding: 3, name: "M8"},
  1766  	SPOP_MF8: {encoding: 5, name: "MF8"},
  1767  	SPOP_MF4: {encoding: 6, name: "MF4"},
  1768  	SPOP_MF2: {encoding: 7, name: "MF2"},
  1769  
  1770  	SPOP_E8:  {encoding: 0, name: "E8"},
  1771  	SPOP_E16: {encoding: 1, name: "E16"},
  1772  	SPOP_E32: {encoding: 2, name: "E32"},
  1773  	SPOP_E64: {encoding: 3, name: "E64"},
  1774  
  1775  	SPOP_FENCE_W:    {encoding: 1, name: "W"},
  1776  	SPOP_FENCE_R:    {encoding: 2, name: "R"},
  1777  	SPOP_FENCE_RW:   {encoding: 3, name: "RW"},
  1778  	SPOP_FENCE_O:    {encoding: 4, name: "O"},
  1779  	SPOP_FENCE_OW:   {encoding: 5, name: "OW"},
  1780  	SPOP_FENCE_OR:   {encoding: 6, name: "OR"},
  1781  	SPOP_FENCE_ORW:  {encoding: 7, name: "ORW"},
  1782  	SPOP_FENCE_I:    {encoding: 8, name: "I"},
  1783  	SPOP_FENCE_IW:   {encoding: 9, name: "IW"},
  1784  	SPOP_FENCE_IR:   {encoding: 10, name: "IR"},
  1785  	SPOP_FENCE_IRW:  {encoding: 11, name: "IRW"},
  1786  	SPOP_FENCE_IO:   {encoding: 12, name: "IO"},
  1787  	SPOP_FENCE_IOW:  {encoding: 13, name: "IOW"},
  1788  	SPOP_FENCE_IOR:  {encoding: 14, name: "IOR"},
  1789  	SPOP_FENCE_IORW: {encoding: 15, name: "IORW"},
  1790  }
  1791  
  1792  func (so SpecialOperand) encode() uint32 {
  1793  	switch {
  1794  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1795  		op, ok := specialOperands[so]
  1796  		if ok {
  1797  			return op.encoding
  1798  		}
  1799  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1800  		csrNum := uint16(so - SPOP_CSR_BEGIN)
  1801  		if _, ok := csrs[csrNum]; ok {
  1802  			return uint32(csrNum)
  1803  		}
  1804  	case so > SPOP_FENCE_BEGIN && so < SPOP_FENCE_END:
  1805  		op, ok := specialOperands[so]
  1806  		if ok {
  1807  			return op.encoding
  1808  		}
  1809  	}
  1810  	return 0
  1811  }
  1812  
  1813  // String returns the textual representation of a SpecialOperand.
  1814  func (so SpecialOperand) String() string {
  1815  	switch {
  1816  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1817  		op, ok := specialOperands[so]
  1818  		if ok {
  1819  			return op.name
  1820  		}
  1821  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1822  		if csrName, ok := csrs[uint16(so-SPOP_CSR_BEGIN)]; ok {
  1823  			return csrName
  1824  		}
  1825  	case so > SPOP_FENCE_BEGIN && so < SPOP_FENCE_END:
  1826  		op, ok := specialOperands[so]
  1827  		if ok {
  1828  			return op.name
  1829  		}
  1830  	}
  1831  	return ""
  1832  }
  1833  
  1834  // All unary instructions which write to their arguments (as opposed to reading
  1835  // from them) go here. The assembly parser uses this information to populate
  1836  // its AST in a semantically reasonable way.
  1837  //
  1838  // Any instructions not listed here are assumed to either be non-unary or to read
  1839  // from its argument.
  1840  var unaryDst = map[obj.As]bool{
  1841  	ARDCYCLE:   true,
  1842  	ARDTIME:    true,
  1843  	ARDINSTRET: true,
  1844  }
  1845  
  1846  // Instruction encoding masks.
  1847  const (
  1848  	// BTypeImmMask is a mask including only the immediate portion of
  1849  	// B-type instructions.
  1850  	BTypeImmMask = 0xfe000f80
  1851  
  1852  	// CBTypeImmMask is a mask including only the immediate portion of
  1853  	// CB-type instructions.
  1854  	CBTypeImmMask = 0x1c7c
  1855  
  1856  	// CJTypeImmMask is a mask including only the immediate portion of
  1857  	// CJ-type instructions.
  1858  	CJTypeImmMask = 0x1f7c
  1859  
  1860  	// ITypeImmMask is a mask including only the immediate portion of
  1861  	// I-type instructions.
  1862  	ITypeImmMask = 0xfff00000
  1863  
  1864  	// JTypeImmMask is a mask including only the immediate portion of
  1865  	// J-type instructions.
  1866  	JTypeImmMask = 0xfffff000
  1867  
  1868  	// STypeImmMask is a mask including only the immediate portion of
  1869  	// S-type instructions.
  1870  	STypeImmMask = 0xfe000f80
  1871  
  1872  	// UTypeImmMask is a mask including only the immediate portion of
  1873  	// U-type instructions.
  1874  	UTypeImmMask = 0xfffff000
  1875  )
  1876  

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