Source file src/cmd/internal/obj/riscv/cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  var CSRs map[uint16]string = csrs
    39  
    40  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    41  
    42  const (
    43  	// Base register numberings.
    44  	REG_X0 = obj.RBaseRISCV + iota
    45  	REG_X1
    46  	REG_X2
    47  	REG_X3
    48  	REG_X4
    49  	REG_X5
    50  	REG_X6
    51  	REG_X7
    52  	REG_X8
    53  	REG_X9
    54  	REG_X10
    55  	REG_X11
    56  	REG_X12
    57  	REG_X13
    58  	REG_X14
    59  	REG_X15
    60  	REG_X16
    61  	REG_X17
    62  	REG_X18
    63  	REG_X19
    64  	REG_X20
    65  	REG_X21
    66  	REG_X22
    67  	REG_X23
    68  	REG_X24
    69  	REG_X25
    70  	REG_X26
    71  	REG_X27
    72  	REG_X28
    73  	REG_X29
    74  	REG_X30
    75  	REG_X31
    76  
    77  	// Floating Point register numberings.
    78  	REG_F0
    79  	REG_F1
    80  	REG_F2
    81  	REG_F3
    82  	REG_F4
    83  	REG_F5
    84  	REG_F6
    85  	REG_F7
    86  	REG_F8
    87  	REG_F9
    88  	REG_F10
    89  	REG_F11
    90  	REG_F12
    91  	REG_F13
    92  	REG_F14
    93  	REG_F15
    94  	REG_F16
    95  	REG_F17
    96  	REG_F18
    97  	REG_F19
    98  	REG_F20
    99  	REG_F21
   100  	REG_F22
   101  	REG_F23
   102  	REG_F24
   103  	REG_F25
   104  	REG_F26
   105  	REG_F27
   106  	REG_F28
   107  	REG_F29
   108  	REG_F30
   109  	REG_F31
   110  
   111  	// Vector register numberings.
   112  	REG_V0
   113  	REG_V1
   114  	REG_V2
   115  	REG_V3
   116  	REG_V4
   117  	REG_V5
   118  	REG_V6
   119  	REG_V7
   120  	REG_V8
   121  	REG_V9
   122  	REG_V10
   123  	REG_V11
   124  	REG_V12
   125  	REG_V13
   126  	REG_V14
   127  	REG_V15
   128  	REG_V16
   129  	REG_V17
   130  	REG_V18
   131  	REG_V19
   132  	REG_V20
   133  	REG_V21
   134  	REG_V22
   135  	REG_V23
   136  	REG_V24
   137  	REG_V25
   138  	REG_V26
   139  	REG_V27
   140  	REG_V28
   141  	REG_V29
   142  	REG_V30
   143  	REG_V31
   144  
   145  	// This marks the end of the register numbering.
   146  	REG_END
   147  
   148  	// General registers reassigned to ABI names.
   149  	REG_ZERO = REG_X0
   150  	REG_RA   = REG_X1 // aka REG_LR
   151  	REG_SP   = REG_X2
   152  	REG_GP   = REG_X3 // aka REG_SB
   153  	REG_TP   = REG_X4
   154  	REG_T0   = REG_X5
   155  	REG_T1   = REG_X6
   156  	REG_T2   = REG_X7
   157  	REG_S0   = REG_X8
   158  	REG_S1   = REG_X9
   159  	REG_A0   = REG_X10
   160  	REG_A1   = REG_X11
   161  	REG_A2   = REG_X12
   162  	REG_A3   = REG_X13
   163  	REG_A4   = REG_X14
   164  	REG_A5   = REG_X15
   165  	REG_A6   = REG_X16
   166  	REG_A7   = REG_X17
   167  	REG_S2   = REG_X18
   168  	REG_S3   = REG_X19
   169  	REG_S4   = REG_X20
   170  	REG_S5   = REG_X21
   171  	REG_S6   = REG_X22
   172  	REG_S7   = REG_X23
   173  	REG_S8   = REG_X24
   174  	REG_S9   = REG_X25
   175  	REG_S10  = REG_X26 // aka REG_CTXT
   176  	REG_S11  = REG_X27 // aka REG_G
   177  	REG_T3   = REG_X28
   178  	REG_T4   = REG_X29
   179  	REG_T5   = REG_X30
   180  	REG_T6   = REG_X31 // aka REG_TMP
   181  
   182  	// Go runtime register names.
   183  	REG_CTXT = REG_S10 // Context for closures.
   184  	REG_G    = REG_S11 // G pointer.
   185  	REG_LR   = REG_RA  // Link register.
   186  	REG_TMP  = REG_T6  // Reserved for assembler use.
   187  
   188  	// ABI names for floating point registers.
   189  	REG_FT0  = REG_F0
   190  	REG_FT1  = REG_F1
   191  	REG_FT2  = REG_F2
   192  	REG_FT3  = REG_F3
   193  	REG_FT4  = REG_F4
   194  	REG_FT5  = REG_F5
   195  	REG_FT6  = REG_F6
   196  	REG_FT7  = REG_F7
   197  	REG_FS0  = REG_F8
   198  	REG_FS1  = REG_F9
   199  	REG_FA0  = REG_F10
   200  	REG_FA1  = REG_F11
   201  	REG_FA2  = REG_F12
   202  	REG_FA3  = REG_F13
   203  	REG_FA4  = REG_F14
   204  	REG_FA5  = REG_F15
   205  	REG_FA6  = REG_F16
   206  	REG_FA7  = REG_F17
   207  	REG_FS2  = REG_F18
   208  	REG_FS3  = REG_F19
   209  	REG_FS4  = REG_F20
   210  	REG_FS5  = REG_F21
   211  	REG_FS6  = REG_F22
   212  	REG_FS7  = REG_F23
   213  	REG_FS8  = REG_F24
   214  	REG_FS9  = REG_F25
   215  	REG_FS10 = REG_F26
   216  	REG_FS11 = REG_F27
   217  	REG_FT8  = REG_F28
   218  	REG_FT9  = REG_F29
   219  	REG_FT10 = REG_F30
   220  	REG_FT11 = REG_F31
   221  
   222  	// Names generated by the SSA compiler.
   223  	REGSP = REG_SP
   224  	REGG  = REG_G
   225  )
   226  
   227  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   228  var RISCV64DWARFRegisters = map[int16]int16{
   229  	// Integer Registers.
   230  	REG_X0:  0,
   231  	REG_X1:  1,
   232  	REG_X2:  2,
   233  	REG_X3:  3,
   234  	REG_X4:  4,
   235  	REG_X5:  5,
   236  	REG_X6:  6,
   237  	REG_X7:  7,
   238  	REG_X8:  8,
   239  	REG_X9:  9,
   240  	REG_X10: 10,
   241  	REG_X11: 11,
   242  	REG_X12: 12,
   243  	REG_X13: 13,
   244  	REG_X14: 14,
   245  	REG_X15: 15,
   246  	REG_X16: 16,
   247  	REG_X17: 17,
   248  	REG_X18: 18,
   249  	REG_X19: 19,
   250  	REG_X20: 20,
   251  	REG_X21: 21,
   252  	REG_X22: 22,
   253  	REG_X23: 23,
   254  	REG_X24: 24,
   255  	REG_X25: 25,
   256  	REG_X26: 26,
   257  	REG_X27: 27,
   258  	REG_X28: 28,
   259  	REG_X29: 29,
   260  	REG_X30: 30,
   261  	REG_X31: 31,
   262  
   263  	// Floating-Point Registers.
   264  	REG_F0:  32,
   265  	REG_F1:  33,
   266  	REG_F2:  34,
   267  	REG_F3:  35,
   268  	REG_F4:  36,
   269  	REG_F5:  37,
   270  	REG_F6:  38,
   271  	REG_F7:  39,
   272  	REG_F8:  40,
   273  	REG_F9:  41,
   274  	REG_F10: 42,
   275  	REG_F11: 43,
   276  	REG_F12: 44,
   277  	REG_F13: 45,
   278  	REG_F14: 46,
   279  	REG_F15: 47,
   280  	REG_F16: 48,
   281  	REG_F17: 49,
   282  	REG_F18: 50,
   283  	REG_F19: 51,
   284  	REG_F20: 52,
   285  	REG_F21: 53,
   286  	REG_F22: 54,
   287  	REG_F23: 55,
   288  	REG_F24: 56,
   289  	REG_F25: 57,
   290  	REG_F26: 58,
   291  	REG_F27: 59,
   292  	REG_F28: 60,
   293  	REG_F29: 61,
   294  	REG_F30: 62,
   295  	REG_F31: 63,
   296  }
   297  
   298  // Prog.Mark flags.
   299  const (
   300  	// USES_REG_TMP indicates that a machine instruction generated from the
   301  	// corresponding *obj.Prog uses the temporary register.
   302  	USES_REG_TMP = 1 << iota
   303  
   304  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   305  	// R_RISCV_JAL relocation is needed.
   306  	NEED_JAL_RELOC
   307  
   308  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   309  	// is the first instruction in an AUIPC + JAL pair that needs a
   310  	// R_RISCV_CALL relocation.
   311  	NEED_CALL_RELOC
   312  
   313  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   314  	// it is the first instruction in an AUIPC + I-type pair that needs a
   315  	// R_RISCV_PCREL_ITYPE relocation.
   316  	NEED_PCREL_ITYPE_RELOC
   317  
   318  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   319  	// it is the first instruction in an AUIPC + S-type pair that needs a
   320  	// R_RISCV_PCREL_STYPE relocation.
   321  	NEED_PCREL_STYPE_RELOC
   322  
   323  	// NEED_GOT_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   324  	// it is the first instruction in an AUIPC + I-type pair that needs a
   325  	// R_RISCV_GOT_PCREL_ITYPE relocation.
   326  	NEED_GOT_PCREL_ITYPE_RELOC
   327  )
   328  
   329  const NEED_RELOC = NEED_JAL_RELOC | NEED_CALL_RELOC | NEED_PCREL_ITYPE_RELOC |
   330  	NEED_PCREL_STYPE_RELOC | NEED_GOT_PCREL_ITYPE_RELOC
   331  
   332  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   333  // at https://github.com/riscv/riscv-opcodes.
   334  //
   335  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   336  //
   337  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
   338  //
   339  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   340  const (
   341  	//
   342  	// Unprivileged ISA (version 20260120)
   343  	//
   344  
   345  	// 2.4: Integer Computational Instructions
   346  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   347  	ASLTI
   348  	ASLTIU
   349  	AANDI
   350  	AORI
   351  	AXORI
   352  	ASLLI
   353  	ASRLI
   354  	ASRAI
   355  	ALUI
   356  	AAUIPC
   357  	AADD
   358  	ASLT
   359  	ASLTU
   360  	AAND
   361  	AOR
   362  	AXOR
   363  	ASLL
   364  	ASRL
   365  	ASUB
   366  	ASRA
   367  
   368  	// 2.5: Control Transfer Instructions
   369  	AJAL
   370  	AJALR
   371  	ABEQ
   372  	ABNE
   373  	ABLT
   374  	ABLTU
   375  	ABGE
   376  	ABGEU
   377  
   378  	// 2.6: Load and Store Instructions
   379  	ALW
   380  	ALWU
   381  	ALH
   382  	ALHU
   383  	ALB
   384  	ALBU
   385  	ASW
   386  	ASH
   387  	ASB
   388  
   389  	// 2.7: Memory Ordering Instructions
   390  	AFENCE
   391  
   392  	// 4.2: Integer Computational Instructions (RV64I)
   393  	AADDIW
   394  	ASLLIW
   395  	ASRLIW
   396  	ASRAIW
   397  	AADDW
   398  	ASLLW
   399  	ASRLW
   400  	ASUBW
   401  	ASRAW
   402  
   403  	// 4.3: Load and Store Instructions (RV64I)
   404  	ALD
   405  	ASD
   406  
   407  	// 6.1: CSR Instructions (Zicsr)
   408  	ACSRRW
   409  	ACSRRS
   410  	ACSRRC
   411  	ACSRRWI
   412  	ACSRRSI
   413  	ACSRRCI
   414  
   415  	// 11.1: Integer Conditional Operations (Zicond)
   416  	ACZEROEQZ
   417  	ACZERONEZ
   418  
   419  	// 12.1: Multiplication Operations
   420  	AMUL
   421  	AMULH
   422  	AMULHU
   423  	AMULHSU
   424  	AMULW
   425  
   426  	// 12.2: Division Operations
   427  	ADIV
   428  	ADIVU
   429  	AREM
   430  	AREMU
   431  	ADIVW
   432  	ADIVUW
   433  	AREMW
   434  	AREMUW
   435  
   436  	// 13.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
   437  	ALRD
   438  	ASCD
   439  	ALRW
   440  	ASCW
   441  
   442  	// 13.4: Atomic Memory Operations (Zaamo)
   443  	AAMOSWAPD
   444  	AAMOADDD
   445  	AAMOANDD
   446  	AAMOORD
   447  	AAMOXORD
   448  	AAMOMAXD
   449  	AAMOMAXUD
   450  	AAMOMIND
   451  	AAMOMINUD
   452  	AAMOSWAPW
   453  	AAMOADDW
   454  	AAMOANDW
   455  	AAMOORW
   456  	AAMOXORW
   457  	AAMOMAXW
   458  	AAMOMAXUW
   459  	AAMOMINW
   460  	AAMOMINUW
   461  
   462  	// 21.5: Single-Precision Load and Store Instructions
   463  	AFLW
   464  	AFSW
   465  
   466  	// 21.6: Single-Precision Floating-Point Computational Instructions
   467  	AFADDS
   468  	AFSUBS
   469  	AFMULS
   470  	AFDIVS
   471  	AFMINS
   472  	AFMAXS
   473  	AFSQRTS
   474  	AFMADDS
   475  	AFMSUBS
   476  	AFNMADDS
   477  	AFNMSUBS
   478  
   479  	// 21.7: Single-Precision Floating-Point Conversion and Move Instructions
   480  	AFCVTWS
   481  	AFCVTLS
   482  	AFCVTSW
   483  	AFCVTSL
   484  	AFCVTWUS
   485  	AFCVTLUS
   486  	AFCVTSWU
   487  	AFCVTSLU
   488  	AFSGNJS
   489  	AFSGNJNS
   490  	AFSGNJXS
   491  	AFMVXS
   492  	AFMVSX
   493  	AFMVXW
   494  	AFMVWX
   495  
   496  	// 21.8: Single-Precision Floating-Point Compare Instructions
   497  	AFEQS
   498  	AFLTS
   499  	AFLES
   500  
   501  	// 21.9: Single-Precision Floating-Point Classify Instruction
   502  	AFCLASSS
   503  
   504  	// 22.3: Double-Precision Load and Store Instructions
   505  	AFLD
   506  	AFSD
   507  
   508  	// 22.4: Double-Precision Floating-Point Computational Instructions
   509  	AFADDD
   510  	AFSUBD
   511  	AFMULD
   512  	AFDIVD
   513  	AFMIND
   514  	AFMAXD
   515  	AFSQRTD
   516  	AFMADDD
   517  	AFMSUBD
   518  	AFNMADDD
   519  	AFNMSUBD
   520  
   521  	// 22.5: Double-Precision Floating-Point Conversion and Move Instructions
   522  	AFCVTWD
   523  	AFCVTLD
   524  	AFCVTDW
   525  	AFCVTDL
   526  	AFCVTWUD
   527  	AFCVTLUD
   528  	AFCVTDWU
   529  	AFCVTDLU
   530  	AFCVTSD
   531  	AFCVTDS
   532  	AFSGNJD
   533  	AFSGNJND
   534  	AFSGNJXD
   535  	AFMVXD
   536  	AFMVDX
   537  
   538  	// 22.6: Double-Precision Floating-Point Compare Instructions
   539  	AFEQD
   540  	AFLTD
   541  	AFLED
   542  
   543  	// 22.7: Double-Precision Floating-Point Classify Instruction
   544  	AFCLASSD
   545  
   546  	// 23.1: Quad-Precision Load and Store Instructions
   547  	AFLQ
   548  	AFSQ
   549  
   550  	// 23.2: Quad-Precision Computational Instructions
   551  	AFADDQ
   552  	AFSUBQ
   553  	AFMULQ
   554  	AFDIVQ
   555  	AFMINQ
   556  	AFMAXQ
   557  	AFSQRTQ
   558  	AFMADDQ
   559  	AFMSUBQ
   560  	AFNMADDQ
   561  	AFNMSUBQ
   562  
   563  	// 23.3: Quad-Precision Convert and Move Instructions
   564  	AFCVTWQ
   565  	AFCVTLQ
   566  	AFCVTSQ
   567  	AFCVTDQ
   568  	AFCVTQW
   569  	AFCVTQL
   570  	AFCVTQS
   571  	AFCVTQD
   572  	AFCVTWUQ
   573  	AFCVTLUQ
   574  	AFCVTQWU
   575  	AFCVTQLU
   576  	AFSGNJQ
   577  	AFSGNJNQ
   578  	AFSGNJXQ
   579  
   580  	// 23.4: Quad-Precision Floating-Point Compare Instructions
   581  	AFEQQ
   582  	AFLEQ
   583  	AFLTQ
   584  
   585  	// 23.5: Quad-Precision Floating-Point Classify Instruction
   586  	AFCLASSQ
   587  
   588  	//
   589  	// "C" Extension for Compressed Instructions
   590  	//
   591  
   592  	// 28.3.1: Compressed Stack-Pointer-Based Loads and Stores
   593  	ACLWSP
   594  	ACLDSP
   595  	ACFLDSP
   596  	ACSWSP
   597  	ACSDSP
   598  	ACFSDSP
   599  
   600  	// 28.3.2: Compressed Register-Based Loads and Stores
   601  	ACLW
   602  	ACLD
   603  	ACFLD
   604  	ACSW
   605  	ACSD
   606  	ACFSD
   607  
   608  	// 28.4: Compressed Control Transfer Instructions
   609  	ACJ
   610  	ACJR
   611  	ACJALR
   612  	ACBEQZ
   613  	ACBNEZ
   614  
   615  	// 28.5.1: Compressed Integer Constant-Generation Instructions
   616  	ACLI
   617  	ACLUI
   618  
   619  	// 28.5.2: Compressed Integer Register-Immediate Operations
   620  	ACADDI
   621  	ACADDIW
   622  	ACADDI16SP
   623  	ACADDI4SPN
   624  	ACSLLI
   625  	ACSRLI
   626  	ACSRAI
   627  	ACANDI
   628  
   629  	// 28.5.3: Compressed Integer Register-Register Operations
   630  	ACMV
   631  	ACADD
   632  	ACAND
   633  	ACOR
   634  	ACXOR
   635  	ACSUB
   636  	ACADDW
   637  	ACSUBW
   638  
   639  	// 28.5.5: Compressed NOP Instruction
   640  	ACNOP
   641  
   642  	// 28.5.6: Compressed Breakpoint Instruction
   643  	ACEBREAK
   644  
   645  	//
   646  	// "B" Extension for Bit Manipulation, Version 1.0.0
   647  	//
   648  
   649  	// 30.2: Address Generation Instructions (Zba)
   650  	AADDUW
   651  	ASH1ADD
   652  	ASH1ADDUW
   653  	ASH2ADD
   654  	ASH2ADDUW
   655  	ASH3ADD
   656  	ASH3ADDUW
   657  	ASLLIUW
   658  
   659  	// 30.3: Basic Bit Manipulation (Zbb)
   660  	AANDN
   661  	AORN
   662  	AXNOR
   663  	ACLZ
   664  	ACLZW
   665  	ACTZ
   666  	ACTZW
   667  	ACPOP
   668  	ACPOPW
   669  	AMAX
   670  	AMAXU
   671  	AMIN
   672  	AMINU
   673  	ASEXTB
   674  	ASEXTH
   675  	AZEXTH
   676  	AROL
   677  	AROLW
   678  	AROR
   679  	ARORI
   680  	ARORIW
   681  	ARORW
   682  	AORCB
   683  	AREV8
   684  
   685  	// 30.4: Carry-less multiplication (Zbc)
   686  	ACLMUL
   687  	ACLMULH
   688  	ACLMULR
   689  
   690  	// 30.5: Single-bit Instructions (Zbs)
   691  	ABCLR
   692  	ABCLRI
   693  	ABEXT
   694  	ABEXTI
   695  	ABINV
   696  	ABINVI
   697  	ABSET
   698  	ABSETI
   699  
   700  	//
   701  	// "V" Standard Extension for Vector Operations, Version 1.0
   702  	//
   703  
   704  	// 31.6: Configuration-Setting Instructions
   705  	AVSETVLI
   706  	AVSETIVLI
   707  	AVSETVL
   708  
   709  	// 31.7.4: Vector Unit-Stride Instructions
   710  	AVLE8V
   711  	AVLE16V
   712  	AVLE32V
   713  	AVLE64V
   714  	AVSE8V
   715  	AVSE16V
   716  	AVSE32V
   717  	AVSE64V
   718  	AVLMV
   719  	AVSMV
   720  
   721  	// 31.7.5: Vector Constant-Stride Instructions
   722  	AVLSE8V
   723  	AVLSE16V
   724  	AVLSE32V
   725  	AVLSE64V
   726  	AVSSE8V
   727  	AVSSE16V
   728  	AVSSE32V
   729  	AVSSE64V
   730  
   731  	// 31.7.6: Vector Indexed Instructions
   732  	AVLUXEI8V
   733  	AVLUXEI16V
   734  	AVLUXEI32V
   735  	AVLUXEI64V
   736  	AVLOXEI8V
   737  	AVLOXEI16V
   738  	AVLOXEI32V
   739  	AVLOXEI64V
   740  	AVSUXEI8V
   741  	AVSUXEI16V
   742  	AVSUXEI32V
   743  	AVSUXEI64V
   744  	AVSOXEI8V
   745  	AVSOXEI16V
   746  	AVSOXEI32V
   747  	AVSOXEI64V
   748  
   749  	// 31.7.7: Vector Unit-Stride Fault-Only-First Loads
   750  	AVLE8FFV
   751  	AVLE16FFV
   752  	AVLE32FFV
   753  	AVLE64FFV
   754  
   755  	// 31.7.8.1: Vector Unit-Stride Segment Loads and Stores
   756  	AVLSEG2E8V
   757  	AVLSEG3E8V
   758  	AVLSEG4E8V
   759  	AVLSEG5E8V
   760  	AVLSEG6E8V
   761  	AVLSEG7E8V
   762  	AVLSEG8E8V
   763  	AVLSEG2E16V
   764  	AVLSEG3E16V
   765  	AVLSEG4E16V
   766  	AVLSEG5E16V
   767  	AVLSEG6E16V
   768  	AVLSEG7E16V
   769  	AVLSEG8E16V
   770  	AVLSEG2E32V
   771  	AVLSEG3E32V
   772  	AVLSEG4E32V
   773  	AVLSEG5E32V
   774  	AVLSEG6E32V
   775  	AVLSEG7E32V
   776  	AVLSEG8E32V
   777  	AVLSEG2E64V
   778  	AVLSEG3E64V
   779  	AVLSEG4E64V
   780  	AVLSEG5E64V
   781  	AVLSEG6E64V
   782  	AVLSEG7E64V
   783  	AVLSEG8E64V
   784  
   785  	AVSSEG2E8V
   786  	AVSSEG3E8V
   787  	AVSSEG4E8V
   788  	AVSSEG5E8V
   789  	AVSSEG6E8V
   790  	AVSSEG7E8V
   791  	AVSSEG8E8V
   792  	AVSSEG2E16V
   793  	AVSSEG3E16V
   794  	AVSSEG4E16V
   795  	AVSSEG5E16V
   796  	AVSSEG6E16V
   797  	AVSSEG7E16V
   798  	AVSSEG8E16V
   799  	AVSSEG2E32V
   800  	AVSSEG3E32V
   801  	AVSSEG4E32V
   802  	AVSSEG5E32V
   803  	AVSSEG6E32V
   804  	AVSSEG7E32V
   805  	AVSSEG8E32V
   806  	AVSSEG2E64V
   807  	AVSSEG3E64V
   808  	AVSSEG4E64V
   809  	AVSSEG5E64V
   810  	AVSSEG6E64V
   811  	AVSSEG7E64V
   812  	AVSSEG8E64V
   813  
   814  	AVLSEG2E8FFV
   815  	AVLSEG3E8FFV
   816  	AVLSEG4E8FFV
   817  	AVLSEG5E8FFV
   818  	AVLSEG6E8FFV
   819  	AVLSEG7E8FFV
   820  	AVLSEG8E8FFV
   821  	AVLSEG2E16FFV
   822  	AVLSEG3E16FFV
   823  	AVLSEG4E16FFV
   824  	AVLSEG5E16FFV
   825  	AVLSEG6E16FFV
   826  	AVLSEG7E16FFV
   827  	AVLSEG8E16FFV
   828  	AVLSEG2E32FFV
   829  	AVLSEG3E32FFV
   830  	AVLSEG4E32FFV
   831  	AVLSEG5E32FFV
   832  	AVLSEG6E32FFV
   833  	AVLSEG7E32FFV
   834  	AVLSEG8E32FFV
   835  	AVLSEG2E64FFV
   836  	AVLSEG3E64FFV
   837  	AVLSEG4E64FFV
   838  	AVLSEG5E64FFV
   839  	AVLSEG6E64FFV
   840  	AVLSEG7E64FFV
   841  	AVLSEG8E64FFV
   842  
   843  	// 31.7.8.2: Vector Constant-Stride Segment Loads and Stores
   844  	AVLSSEG2E8V
   845  	AVLSSEG3E8V
   846  	AVLSSEG4E8V
   847  	AVLSSEG5E8V
   848  	AVLSSEG6E8V
   849  	AVLSSEG7E8V
   850  	AVLSSEG8E8V
   851  	AVLSSEG2E16V
   852  	AVLSSEG3E16V
   853  	AVLSSEG4E16V
   854  	AVLSSEG5E16V
   855  	AVLSSEG6E16V
   856  	AVLSSEG7E16V
   857  	AVLSSEG8E16V
   858  	AVLSSEG2E32V
   859  	AVLSSEG3E32V
   860  	AVLSSEG4E32V
   861  	AVLSSEG5E32V
   862  	AVLSSEG6E32V
   863  	AVLSSEG7E32V
   864  	AVLSSEG8E32V
   865  	AVLSSEG2E64V
   866  	AVLSSEG3E64V
   867  	AVLSSEG4E64V
   868  	AVLSSEG5E64V
   869  	AVLSSEG6E64V
   870  	AVLSSEG7E64V
   871  	AVLSSEG8E64V
   872  
   873  	AVSSSEG2E8V
   874  	AVSSSEG3E8V
   875  	AVSSSEG4E8V
   876  	AVSSSEG5E8V
   877  	AVSSSEG6E8V
   878  	AVSSSEG7E8V
   879  	AVSSSEG8E8V
   880  	AVSSSEG2E16V
   881  	AVSSSEG3E16V
   882  	AVSSSEG4E16V
   883  	AVSSSEG5E16V
   884  	AVSSSEG6E16V
   885  	AVSSSEG7E16V
   886  	AVSSSEG8E16V
   887  	AVSSSEG2E32V
   888  	AVSSSEG3E32V
   889  	AVSSSEG4E32V
   890  	AVSSSEG5E32V
   891  	AVSSSEG6E32V
   892  	AVSSSEG7E32V
   893  	AVSSSEG8E32V
   894  	AVSSSEG2E64V
   895  	AVSSSEG3E64V
   896  	AVSSSEG4E64V
   897  	AVSSSEG5E64V
   898  	AVSSSEG6E64V
   899  	AVSSSEG7E64V
   900  	AVSSSEG8E64V
   901  
   902  	// 31.7.8.3: Vector Indexed Segment Loads and Stores
   903  	AVLOXSEG2EI8V
   904  	AVLOXSEG3EI8V
   905  	AVLOXSEG4EI8V
   906  	AVLOXSEG5EI8V
   907  	AVLOXSEG6EI8V
   908  	AVLOXSEG7EI8V
   909  	AVLOXSEG8EI8V
   910  	AVLOXSEG2EI16V
   911  	AVLOXSEG3EI16V
   912  	AVLOXSEG4EI16V
   913  	AVLOXSEG5EI16V
   914  	AVLOXSEG6EI16V
   915  	AVLOXSEG7EI16V
   916  	AVLOXSEG8EI16V
   917  	AVLOXSEG2EI32V
   918  	AVLOXSEG3EI32V
   919  	AVLOXSEG4EI32V
   920  	AVLOXSEG5EI32V
   921  	AVLOXSEG6EI32V
   922  	AVLOXSEG7EI32V
   923  	AVLOXSEG8EI32V
   924  	AVLOXSEG2EI64V
   925  	AVLOXSEG3EI64V
   926  	AVLOXSEG4EI64V
   927  	AVLOXSEG5EI64V
   928  	AVLOXSEG6EI64V
   929  	AVLOXSEG7EI64V
   930  	AVLOXSEG8EI64V
   931  
   932  	AVSOXSEG2EI8V
   933  	AVSOXSEG3EI8V
   934  	AVSOXSEG4EI8V
   935  	AVSOXSEG5EI8V
   936  	AVSOXSEG6EI8V
   937  	AVSOXSEG7EI8V
   938  	AVSOXSEG8EI8V
   939  	AVSOXSEG2EI16V
   940  	AVSOXSEG3EI16V
   941  	AVSOXSEG4EI16V
   942  	AVSOXSEG5EI16V
   943  	AVSOXSEG6EI16V
   944  	AVSOXSEG7EI16V
   945  	AVSOXSEG8EI16V
   946  	AVSOXSEG2EI32V
   947  	AVSOXSEG3EI32V
   948  	AVSOXSEG4EI32V
   949  	AVSOXSEG5EI32V
   950  	AVSOXSEG6EI32V
   951  	AVSOXSEG7EI32V
   952  	AVSOXSEG8EI32V
   953  	AVSOXSEG2EI64V
   954  	AVSOXSEG3EI64V
   955  	AVSOXSEG4EI64V
   956  	AVSOXSEG5EI64V
   957  	AVSOXSEG6EI64V
   958  	AVSOXSEG7EI64V
   959  	AVSOXSEG8EI64V
   960  
   961  	AVLUXSEG2EI8V
   962  	AVLUXSEG3EI8V
   963  	AVLUXSEG4EI8V
   964  	AVLUXSEG5EI8V
   965  	AVLUXSEG6EI8V
   966  	AVLUXSEG7EI8V
   967  	AVLUXSEG8EI8V
   968  	AVLUXSEG2EI16V
   969  	AVLUXSEG3EI16V
   970  	AVLUXSEG4EI16V
   971  	AVLUXSEG5EI16V
   972  	AVLUXSEG6EI16V
   973  	AVLUXSEG7EI16V
   974  	AVLUXSEG8EI16V
   975  	AVLUXSEG2EI32V
   976  	AVLUXSEG3EI32V
   977  	AVLUXSEG4EI32V
   978  	AVLUXSEG5EI32V
   979  	AVLUXSEG6EI32V
   980  	AVLUXSEG7EI32V
   981  	AVLUXSEG8EI32V
   982  	AVLUXSEG2EI64V
   983  	AVLUXSEG3EI64V
   984  	AVLUXSEG4EI64V
   985  	AVLUXSEG5EI64V
   986  	AVLUXSEG6EI64V
   987  	AVLUXSEG7EI64V
   988  	AVLUXSEG8EI64V
   989  
   990  	AVSUXSEG2EI8V
   991  	AVSUXSEG3EI8V
   992  	AVSUXSEG4EI8V
   993  	AVSUXSEG5EI8V
   994  	AVSUXSEG6EI8V
   995  	AVSUXSEG7EI8V
   996  	AVSUXSEG8EI8V
   997  	AVSUXSEG2EI16V
   998  	AVSUXSEG3EI16V
   999  	AVSUXSEG4EI16V
  1000  	AVSUXSEG5EI16V
  1001  	AVSUXSEG6EI16V
  1002  	AVSUXSEG7EI16V
  1003  	AVSUXSEG8EI16V
  1004  	AVSUXSEG2EI32V
  1005  	AVSUXSEG3EI32V
  1006  	AVSUXSEG4EI32V
  1007  	AVSUXSEG5EI32V
  1008  	AVSUXSEG6EI32V
  1009  	AVSUXSEG7EI32V
  1010  	AVSUXSEG8EI32V
  1011  	AVSUXSEG2EI64V
  1012  	AVSUXSEG3EI64V
  1013  	AVSUXSEG4EI64V
  1014  	AVSUXSEG5EI64V
  1015  	AVSUXSEG6EI64V
  1016  	AVSUXSEG7EI64V
  1017  	AVSUXSEG8EI64V
  1018  
  1019  	// 31.7.9: Vector Load/Store Whole Register Instructions
  1020  	AVL1RE8V
  1021  	AVL1RE16V
  1022  	AVL1RE32V
  1023  	AVL1RE64V
  1024  	AVL2RE8V
  1025  	AVL2RE16V
  1026  	AVL2RE32V
  1027  	AVL2RE64V
  1028  	AVL4RE8V
  1029  	AVL4RE16V
  1030  	AVL4RE32V
  1031  	AVL4RE64V
  1032  	AVL8RE8V
  1033  	AVL8RE16V
  1034  	AVL8RE32V
  1035  	AVL8RE64V
  1036  	AVS1RV
  1037  	AVS2RV
  1038  	AVS4RV
  1039  	AVS8RV
  1040  
  1041  	// 31.11.1: Vector Single-Width Integer Add and Subtract
  1042  	AVADDVV
  1043  	AVADDVX
  1044  	AVADDVI
  1045  	AVSUBVV
  1046  	AVSUBVX
  1047  	AVRSUBVX
  1048  	AVRSUBVI
  1049  
  1050  	// 31.11.2: Vector Widening Integer Add/Subtract
  1051  	AVWADDUVV
  1052  	AVWADDUVX
  1053  	AVWSUBUVV
  1054  	AVWSUBUVX
  1055  	AVWADDVV
  1056  	AVWADDVX
  1057  	AVWSUBVV
  1058  	AVWSUBVX
  1059  	AVWADDUWV
  1060  	AVWADDUWX
  1061  	AVWSUBUWV
  1062  	AVWSUBUWX
  1063  	AVWADDWV
  1064  	AVWADDWX
  1065  	AVWSUBWV
  1066  	AVWSUBWX
  1067  
  1068  	// 31.11.3: Vector Integer Extension
  1069  	AVZEXTVF2
  1070  	AVSEXTVF2
  1071  	AVZEXTVF4
  1072  	AVSEXTVF4
  1073  	AVZEXTVF8
  1074  	AVSEXTVF8
  1075  
  1076  	// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
  1077  	AVADCVVM
  1078  	AVADCVXM
  1079  	AVADCVIM
  1080  	AVMADCVVM
  1081  	AVMADCVXM
  1082  	AVMADCVIM
  1083  	AVMADCVV
  1084  	AVMADCVX
  1085  	AVMADCVI
  1086  	AVSBCVVM
  1087  	AVSBCVXM
  1088  	AVMSBCVVM
  1089  	AVMSBCVXM
  1090  	AVMSBCVV
  1091  	AVMSBCVX
  1092  
  1093  	// 31.11.5: Vector Bitwise Logical Instructions
  1094  	AVANDVV
  1095  	AVANDVX
  1096  	AVANDVI
  1097  	AVORVV
  1098  	AVORVX
  1099  	AVORVI
  1100  	AVXORVV
  1101  	AVXORVX
  1102  	AVXORVI
  1103  
  1104  	// 31.11.6: Vector Single-Width Shift Instructions
  1105  	AVSLLVV
  1106  	AVSLLVX
  1107  	AVSLLVI
  1108  	AVSRLVV
  1109  	AVSRLVX
  1110  	AVSRLVI
  1111  	AVSRAVV
  1112  	AVSRAVX
  1113  	AVSRAVI
  1114  
  1115  	// 31.11.7: Vector Narrowing Integer Right Shift Instructions
  1116  	AVNSRLWV
  1117  	AVNSRLWX
  1118  	AVNSRLWI
  1119  	AVNSRAWV
  1120  	AVNSRAWX
  1121  	AVNSRAWI
  1122  
  1123  	// 31.11.8: Vector Integer Compare Instructions
  1124  	AVMSEQVV
  1125  	AVMSEQVX
  1126  	AVMSEQVI
  1127  	AVMSNEVV
  1128  	AVMSNEVX
  1129  	AVMSNEVI
  1130  	AVMSLTUVV
  1131  	AVMSLTUVX
  1132  	AVMSLTVV
  1133  	AVMSLTVX
  1134  	AVMSLEUVV
  1135  	AVMSLEUVX
  1136  	AVMSLEUVI
  1137  	AVMSLEVV
  1138  	AVMSLEVX
  1139  	AVMSLEVI
  1140  	AVMSGTUVX
  1141  	AVMSGTUVI
  1142  	AVMSGTVX
  1143  	AVMSGTVI
  1144  
  1145  	// 31.11.9: Vector Integer Min/Max Instructions
  1146  	AVMINUVV
  1147  	AVMINUVX
  1148  	AVMINVV
  1149  	AVMINVX
  1150  	AVMAXUVV
  1151  	AVMAXUVX
  1152  	AVMAXVV
  1153  	AVMAXVX
  1154  
  1155  	// 31.11.10: Vector Single-Width Integer Multiply Instructions
  1156  	AVMULVV
  1157  	AVMULVX
  1158  	AVMULHVV
  1159  	AVMULHVX
  1160  	AVMULHUVV
  1161  	AVMULHUVX
  1162  	AVMULHSUVV
  1163  	AVMULHSUVX
  1164  
  1165  	// 31.11.11: Vector Integer Divide Instructions
  1166  	AVDIVUVV
  1167  	AVDIVUVX
  1168  	AVDIVVV
  1169  	AVDIVVX
  1170  	AVREMUVV
  1171  	AVREMUVX
  1172  	AVREMVV
  1173  	AVREMVX
  1174  
  1175  	// 31.11.12: Vector Widening Integer Multiply Instructions
  1176  	AVWMULVV
  1177  	AVWMULVX
  1178  	AVWMULUVV
  1179  	AVWMULUVX
  1180  	AVWMULSUVV
  1181  	AVWMULSUVX
  1182  
  1183  	// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
  1184  	AVMACCVV
  1185  	AVMACCVX
  1186  	AVNMSACVV
  1187  	AVNMSACVX
  1188  	AVMADDVV
  1189  	AVMADDVX
  1190  	AVNMSUBVV
  1191  	AVNMSUBVX
  1192  
  1193  	// 31.11.14: Vector Widening Integer Multiply-Add Instructions
  1194  	AVWMACCUVV
  1195  	AVWMACCUVX
  1196  	AVWMACCVV
  1197  	AVWMACCVX
  1198  	AVWMACCSUVV
  1199  	AVWMACCSUVX
  1200  	AVWMACCUSVX
  1201  
  1202  	// 31.11.15: Vector Integer Merge Instructions
  1203  	AVMERGEVVM
  1204  	AVMERGEVXM
  1205  	AVMERGEVIM
  1206  
  1207  	// 31.11.16: Vector Integer Move Instructions
  1208  	AVMVVV
  1209  	AVMVVX
  1210  	AVMVVI
  1211  
  1212  	// 31.12.1: Vector Single-Width Saturating Add and Subtract
  1213  	AVSADDUVV
  1214  	AVSADDUVX
  1215  	AVSADDUVI
  1216  	AVSADDVV
  1217  	AVSADDVX
  1218  	AVSADDVI
  1219  	AVSSUBUVV
  1220  	AVSSUBUVX
  1221  	AVSSUBVV
  1222  	AVSSUBVX
  1223  
  1224  	// 31.12.2: Vector Single-Width Averaging Add and Subtract
  1225  	AVAADDUVV
  1226  	AVAADDUVX
  1227  	AVAADDVV
  1228  	AVAADDVX
  1229  	AVASUBUVV
  1230  	AVASUBUVX
  1231  	AVASUBVV
  1232  	AVASUBVX
  1233  
  1234  	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
  1235  	AVSMULVV
  1236  	AVSMULVX
  1237  
  1238  	// 31.12.4: Vector Single-Width Scaling Shift Instructions
  1239  	AVSSRLVV
  1240  	AVSSRLVX
  1241  	AVSSRLVI
  1242  	AVSSRAVV
  1243  	AVSSRAVX
  1244  	AVSSRAVI
  1245  
  1246  	// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
  1247  	AVNCLIPUWV
  1248  	AVNCLIPUWX
  1249  	AVNCLIPUWI
  1250  	AVNCLIPWV
  1251  	AVNCLIPWX
  1252  	AVNCLIPWI
  1253  
  1254  	// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
  1255  	AVFADDVV
  1256  	AVFADDVF
  1257  	AVFSUBVV
  1258  	AVFSUBVF
  1259  	AVFRSUBVF
  1260  
  1261  	// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
  1262  	AVFWADDVV
  1263  	AVFWADDVF
  1264  	AVFWSUBVV
  1265  	AVFWSUBVF
  1266  	AVFWADDWV
  1267  	AVFWADDWF
  1268  	AVFWSUBWV
  1269  	AVFWSUBWF
  1270  
  1271  	// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
  1272  	AVFMULVV
  1273  	AVFMULVF
  1274  	AVFDIVVV
  1275  	AVFDIVVF
  1276  	AVFRDIVVF
  1277  
  1278  	// 31.13.5: Vector Widening Floating-Point Multiply
  1279  	AVFWMULVV
  1280  	AVFWMULVF
  1281  
  1282  	// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
  1283  	AVFMACCVV
  1284  	AVFMACCVF
  1285  	AVFNMACCVV
  1286  	AVFNMACCVF
  1287  	AVFMSACVV
  1288  	AVFMSACVF
  1289  	AVFNMSACVV
  1290  	AVFNMSACVF
  1291  	AVFMADDVV
  1292  	AVFMADDVF
  1293  	AVFNMADDVV
  1294  	AVFNMADDVF
  1295  	AVFMSUBVV
  1296  	AVFMSUBVF
  1297  	AVFNMSUBVV
  1298  	AVFNMSUBVF
  1299  
  1300  	// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
  1301  	AVFWMACCVV
  1302  	AVFWMACCVF
  1303  	AVFWNMACCVV
  1304  	AVFWNMACCVF
  1305  	AVFWMSACVV
  1306  	AVFWMSACVF
  1307  	AVFWNMSACVV
  1308  	AVFWNMSACVF
  1309  
  1310  	// 31.13.8: Vector Floating-Point Square-Root Instruction
  1311  	AVFSQRTV
  1312  
  1313  	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
  1314  	AVFRSQRT7V
  1315  
  1316  	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
  1317  	AVFREC7V
  1318  
  1319  	// 31.13.11: Vector Floating-Point MIN/MAX Instructions
  1320  	AVFMINVV
  1321  	AVFMINVF
  1322  	AVFMAXVV
  1323  	AVFMAXVF
  1324  
  1325  	// 31.13.12: Vector Floating-Point Sign-Injection Instructions
  1326  	AVFSGNJVV
  1327  	AVFSGNJVF
  1328  	AVFSGNJNVV
  1329  	AVFSGNJNVF
  1330  	AVFSGNJXVV
  1331  	AVFSGNJXVF
  1332  
  1333  	// 31.13.13: Vector Floating-Point Compare Instructions
  1334  	AVMFEQVV
  1335  	AVMFEQVF
  1336  	AVMFNEVV
  1337  	AVMFNEVF
  1338  	AVMFLTVV
  1339  	AVMFLTVF
  1340  	AVMFLEVV
  1341  	AVMFLEVF
  1342  	AVMFGTVF
  1343  	AVMFGEVF
  1344  
  1345  	// 31.13.14: Vector Floating-Point Classify Instruction
  1346  	AVFCLASSV
  1347  
  1348  	// 31.13.15: Vector Floating-Point Merge Instruction
  1349  	AVFMERGEVFM
  1350  
  1351  	// 31.13.16: Vector Floating-Point Move Instruction
  1352  	AVFMVVF
  1353  
  1354  	// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
  1355  	AVFCVTXUFV
  1356  	AVFCVTXFV
  1357  	AVFCVTRTZXUFV
  1358  	AVFCVTRTZXFV
  1359  	AVFCVTFXUV
  1360  	AVFCVTFXV
  1361  
  1362  	// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
  1363  	AVFWCVTXUFV
  1364  	AVFWCVTXFV
  1365  	AVFWCVTRTZXUFV
  1366  	AVFWCVTRTZXFV
  1367  	AVFWCVTFXUV
  1368  	AVFWCVTFXV
  1369  	AVFWCVTFFV
  1370  
  1371  	// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
  1372  	AVFNCVTXUFW
  1373  	AVFNCVTXFW
  1374  	AVFNCVTRTZXUFW
  1375  	AVFNCVTRTZXFW
  1376  	AVFNCVTFXUW
  1377  	AVFNCVTFXW
  1378  	AVFNCVTFFW
  1379  	AVFNCVTRODFFW
  1380  
  1381  	// 31.14.1: Vector Single-Width Integer Reduction Instructions
  1382  	AVREDSUMVS
  1383  	AVREDMAXUVS
  1384  	AVREDMAXVS
  1385  	AVREDMINUVS
  1386  	AVREDMINVS
  1387  	AVREDANDVS
  1388  	AVREDORVS
  1389  	AVREDXORVS
  1390  
  1391  	// 31.14.2: Vector Widening Integer Reduction Instructions
  1392  	AVWREDSUMUVS
  1393  	AVWREDSUMVS
  1394  
  1395  	// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
  1396  	AVFREDOSUMVS
  1397  	AVFREDUSUMVS
  1398  	AVFREDMAXVS
  1399  	AVFREDMINVS
  1400  
  1401  	// 31.14.4: Vector Widening Floating-Point Reduction Instructions
  1402  	AVFWREDOSUMVS
  1403  	AVFWREDUSUMVS
  1404  
  1405  	// 31.15: Vector Mask Instructions
  1406  	AVMANDMM
  1407  	AVMNANDMM
  1408  	AVMANDNMM
  1409  	AVMXORMM
  1410  	AVMORMM
  1411  	AVMNORMM
  1412  	AVMORNMM
  1413  	AVMXNORMM
  1414  	AVCPOPM
  1415  	AVFIRSTM
  1416  	AVMSBFM
  1417  	AVMSIFM
  1418  	AVMSOFM
  1419  	AVIOTAM
  1420  	AVIDV
  1421  
  1422  	// 31.16.1: Integer Scalar Move Instructions
  1423  	AVMVXS
  1424  	AVMVSX
  1425  
  1426  	// 31.16.2: Floating-Point Scalar Move Instructions
  1427  	AVFMVFS
  1428  	AVFMVSF
  1429  
  1430  	// 31.16.3: Vector Slide Instructions
  1431  	AVSLIDEUPVX
  1432  	AVSLIDEUPVI
  1433  	AVSLIDEDOWNVX
  1434  	AVSLIDEDOWNVI
  1435  	AVSLIDE1UPVX
  1436  	AVFSLIDE1UPVF
  1437  	AVSLIDE1DOWNVX
  1438  	AVFSLIDE1DOWNVF
  1439  
  1440  	// 31.16.4: Vector Register Gather Instructions
  1441  	AVRGATHERVV
  1442  	AVRGATHEREI16VV
  1443  	AVRGATHERVX
  1444  	AVRGATHERVI
  1445  
  1446  	// 31.16.5: Vector Compress Instruction
  1447  	AVCOMPRESSVM
  1448  
  1449  	// 31.16.6: Whole Vector Register Move
  1450  	AVMV1RV
  1451  	AVMV2RV
  1452  	AVMV4RV
  1453  	AVMV8RV
  1454  
  1455  	// 33.2.1: Vector Basic Bit-manipulation (Zvbb)
  1456  	AVANDNVV
  1457  	AVANDNVX
  1458  	AVBREVV
  1459  	AVBREV8V
  1460  	AVREV8V
  1461  	AVCLZV
  1462  	AVCTZV
  1463  	AVCPOPV
  1464  	AVROLVV
  1465  	AVROLVX
  1466  	AVRORVV
  1467  	AVRORVX
  1468  	AVRORVI
  1469  	AVWSLLVV
  1470  	AVWSLLVX
  1471  	AVWSLLVI
  1472  
  1473  	// 33.2.2: Vector Carryless Multiplication (Zvbc)
  1474  	AVCLMULVV
  1475  	AVCLMULVX
  1476  	AVCLMULHVV
  1477  	AVCLMULHVX
  1478  
  1479  	//
  1480  	// Privileged ISA (version 20260120)
  1481  	//
  1482  
  1483  	// 3.3.1: Environment Call and Breakpoint
  1484  	AECALL
  1485  	ASCALL
  1486  	AEBREAK
  1487  	ASBREAK
  1488  
  1489  	// 3.3.2: Trap-Return Instructions
  1490  	AMRET
  1491  	ASRET
  1492  	ADRET
  1493  
  1494  	// 3.3.3: Wait for Interrupt
  1495  	AWFI
  1496  
  1497  	// 12.2.1: Supervisor Memory-Management Fence Instruction
  1498  	ASFENCEVMA
  1499  
  1500  	// The escape hatch. Inserts a single 32-bit word.
  1501  	AWORD
  1502  
  1503  	// Pseudo-instructions.  These get translated by the assembler into other
  1504  	// instructions, based on their operands.
  1505  	ABEQZ
  1506  	ABGEZ
  1507  	ABGT
  1508  	ABGTU
  1509  	ABGTZ
  1510  	ABLE
  1511  	ABLEU
  1512  	ABLEZ
  1513  	ABLTZ
  1514  	ABNEZ
  1515  	ACSRC
  1516  	ACSRCI
  1517  	ACSRR
  1518  	ACSRS
  1519  	ACSRSI
  1520  	ACSRW
  1521  	ACSRWI
  1522  	AFABSD
  1523  	AFABSS
  1524  	AFNED
  1525  	AFNEGD
  1526  	AFNEGS
  1527  	AFNES
  1528  	AMOV
  1529  	AMOVB
  1530  	AMOVBU
  1531  	AMOVD
  1532  	AMOVF
  1533  	AMOVH
  1534  	AMOVHU
  1535  	AMOVW
  1536  	AMOVWU
  1537  	ANEG
  1538  	ANEGW
  1539  	ANOT
  1540  	APAUSE
  1541  	ARDCYCLE
  1542  	ARDINSTRET
  1543  	ARDTIME
  1544  	ASEQZ
  1545  	ASNEZ
  1546  	AVFABSV
  1547  	AVFNEGV
  1548  	AVL1RV
  1549  	AVL2RV
  1550  	AVL4RV
  1551  	AVL8RV
  1552  	AVMCLRM
  1553  	AVMFGEVV
  1554  	AVMFGTVV
  1555  	AVMMVM
  1556  	AVMNOTM
  1557  	AVMSETM
  1558  	AVMSGEUVI
  1559  	AVMSGEUVV
  1560  	AVMSGEVI
  1561  	AVMSGEVV
  1562  	AVMSGTUVV
  1563  	AVMSGTVV
  1564  	AVMSLTUVI
  1565  	AVMSLTVI
  1566  	AVNCVTXXW
  1567  	AVNEGV
  1568  	AVNOTV
  1569  	AVWCVTUXXV
  1570  	AVWCVTXXV
  1571  
  1572  	// End marker
  1573  	ALAST
  1574  )
  1575  
  1576  // opSuffix encoding to uint8 which fit into p.Scond
  1577  var rmSuffixSet = map[string]uint8{
  1578  	"RNE": RM_RNE,
  1579  	"RTZ": RM_RTZ,
  1580  	"RDN": RM_RDN,
  1581  	"RUP": RM_RUP,
  1582  	"RMM": RM_RMM,
  1583  }
  1584  
  1585  const (
  1586  	fenceTsoSuffixBit uint8 = 1 << 0
  1587  	rmSuffixBit       uint8 = 1 << 7
  1588  )
  1589  
  1590  func rmSuffixEncode(s string) (uint8, error) {
  1591  	if s == "" {
  1592  		return 0, errors.New("empty suffix")
  1593  	}
  1594  	enc, ok := rmSuffixSet[s]
  1595  	if !ok {
  1596  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
  1597  	}
  1598  	return enc | rmSuffixBit, nil
  1599  }
  1600  
  1601  func rmSuffixString(u uint8) (string, error) {
  1602  	if u&rmSuffixBit == 0 {
  1603  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
  1604  	}
  1605  
  1606  	u &^= rmSuffixBit
  1607  	for k, v := range rmSuffixSet {
  1608  		if v == u {
  1609  			return k, nil
  1610  		}
  1611  	}
  1612  	return "", fmt.Errorf("unknown suffix:%x", u)
  1613  }
  1614  
  1615  const (
  1616  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
  1617  	RM_RTZ              // Round towards Zero
  1618  	RM_RDN              // Round Down
  1619  	RM_RUP              // Round Up
  1620  	RM_RMM              // Round to Nearest, ties to Max Magnitude
  1621  )
  1622  
  1623  type SpecialOperand int
  1624  
  1625  const (
  1626  	SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase
  1627  	SPOP_RVV_BEGIN
  1628  
  1629  	// Vector mask policy.
  1630  	SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 2
  1631  	SPOP_MU
  1632  
  1633  	// Vector tail policy.
  1634  	SPOP_TA
  1635  	SPOP_TU
  1636  
  1637  	// Vector register group multiplier (VLMUL).
  1638  	SPOP_M1
  1639  	SPOP_M2
  1640  	SPOP_M4
  1641  	SPOP_M8
  1642  	SPOP_MF2
  1643  	SPOP_MF4
  1644  	SPOP_MF8
  1645  
  1646  	// Vector selected element width (VSEW).
  1647  	SPOP_E8
  1648  	SPOP_E16
  1649  	SPOP_E32
  1650  	SPOP_E64
  1651  	SPOP_RVV_END
  1652  
  1653  	// CSR names.  4096 special operands are reserved for RISC-V CSR names.
  1654  	SPOP_CSR_BEGIN = SPOP_RVV_END
  1655  	SPOP_CSR_END   = SPOP_CSR_BEGIN + 4096
  1656  
  1657  	// FENCE operands. 16 special operands are reserved for FENCE flags (4 bits: IORW).
  1658  	SPOP_FENCE_BEGIN = SPOP_CSR_END
  1659  
  1660  	SPOP_FENCE_W SpecialOperand = SPOP_FENCE_BEGIN + iota - 20
  1661  	SPOP_FENCE_R
  1662  	SPOP_FENCE_RW
  1663  	SPOP_FENCE_O
  1664  	SPOP_FENCE_OW
  1665  	SPOP_FENCE_OR
  1666  	SPOP_FENCE_ORW
  1667  	SPOP_FENCE_I
  1668  	SPOP_FENCE_IW
  1669  	SPOP_FENCE_IR
  1670  	SPOP_FENCE_IRW
  1671  	SPOP_FENCE_IO
  1672  	SPOP_FENCE_IOW
  1673  	SPOP_FENCE_IOR
  1674  	SPOP_FENCE_IORW
  1675  
  1676  	SPOP_FENCE_END = SPOP_FENCE_BEGIN + 16
  1677  
  1678  	SPOP_END = SPOP_FENCE_END + 1
  1679  )
  1680  
  1681  var specialOperands = map[SpecialOperand]struct {
  1682  	encoding uint32
  1683  	name     string
  1684  }{
  1685  	SPOP_MA: {encoding: 1, name: "MA"},
  1686  	SPOP_MU: {encoding: 0, name: "MU"},
  1687  
  1688  	SPOP_TA: {encoding: 1, name: "TA"},
  1689  	SPOP_TU: {encoding: 0, name: "TU"},
  1690  
  1691  	SPOP_M1:  {encoding: 0, name: "M1"},
  1692  	SPOP_M2:  {encoding: 1, name: "M2"},
  1693  	SPOP_M4:  {encoding: 2, name: "M4"},
  1694  	SPOP_M8:  {encoding: 3, name: "M8"},
  1695  	SPOP_MF8: {encoding: 5, name: "MF8"},
  1696  	SPOP_MF4: {encoding: 6, name: "MF4"},
  1697  	SPOP_MF2: {encoding: 7, name: "MF2"},
  1698  
  1699  	SPOP_E8:  {encoding: 0, name: "E8"},
  1700  	SPOP_E16: {encoding: 1, name: "E16"},
  1701  	SPOP_E32: {encoding: 2, name: "E32"},
  1702  	SPOP_E64: {encoding: 3, name: "E64"},
  1703  
  1704  	SPOP_FENCE_W:    {encoding: 1, name: "W"},
  1705  	SPOP_FENCE_R:    {encoding: 2, name: "R"},
  1706  	SPOP_FENCE_RW:   {encoding: 3, name: "RW"},
  1707  	SPOP_FENCE_O:    {encoding: 4, name: "O"},
  1708  	SPOP_FENCE_OW:   {encoding: 5, name: "OW"},
  1709  	SPOP_FENCE_OR:   {encoding: 6, name: "OR"},
  1710  	SPOP_FENCE_ORW:  {encoding: 7, name: "ORW"},
  1711  	SPOP_FENCE_I:    {encoding: 8, name: "I"},
  1712  	SPOP_FENCE_IW:   {encoding: 9, name: "IW"},
  1713  	SPOP_FENCE_IR:   {encoding: 10, name: "IR"},
  1714  	SPOP_FENCE_IRW:  {encoding: 11, name: "IRW"},
  1715  	SPOP_FENCE_IO:   {encoding: 12, name: "IO"},
  1716  	SPOP_FENCE_IOW:  {encoding: 13, name: "IOW"},
  1717  	SPOP_FENCE_IOR:  {encoding: 14, name: "IOR"},
  1718  	SPOP_FENCE_IORW: {encoding: 15, name: "IORW"},
  1719  }
  1720  
  1721  func (so SpecialOperand) encode() uint32 {
  1722  	switch {
  1723  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1724  		op, ok := specialOperands[so]
  1725  		if ok {
  1726  			return op.encoding
  1727  		}
  1728  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1729  		csrNum := uint16(so - SPOP_CSR_BEGIN)
  1730  		if _, ok := csrs[csrNum]; ok {
  1731  			return uint32(csrNum)
  1732  		}
  1733  	case so > SPOP_FENCE_BEGIN && so < SPOP_FENCE_END:
  1734  		op, ok := specialOperands[so]
  1735  		if ok {
  1736  			return op.encoding
  1737  		}
  1738  	}
  1739  	return 0
  1740  }
  1741  
  1742  // String returns the textual representation of a SpecialOperand.
  1743  func (so SpecialOperand) String() string {
  1744  	switch {
  1745  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1746  		op, ok := specialOperands[so]
  1747  		if ok {
  1748  			return op.name
  1749  		}
  1750  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1751  		if csrName, ok := csrs[uint16(so-SPOP_CSR_BEGIN)]; ok {
  1752  			return csrName
  1753  		}
  1754  	case so > SPOP_FENCE_BEGIN && so < SPOP_FENCE_END:
  1755  		op, ok := specialOperands[so]
  1756  		if ok {
  1757  			return op.name
  1758  		}
  1759  	}
  1760  	return ""
  1761  }
  1762  
  1763  // All unary instructions which write to their arguments (as opposed to reading
  1764  // from them) go here. The assembly parser uses this information to populate
  1765  // its AST in a semantically reasonable way.
  1766  //
  1767  // Any instructions not listed here are assumed to either be non-unary or to read
  1768  // from its argument.
  1769  var unaryDst = map[obj.As]bool{
  1770  	ARDCYCLE:   true,
  1771  	ARDTIME:    true,
  1772  	ARDINSTRET: true,
  1773  }
  1774  
  1775  // Instruction encoding masks.
  1776  const (
  1777  	// BTypeImmMask is a mask including only the immediate portion of
  1778  	// B-type instructions.
  1779  	BTypeImmMask = 0xfe000f80
  1780  
  1781  	// CBTypeImmMask is a mask including only the immediate portion of
  1782  	// CB-type instructions.
  1783  	CBTypeImmMask = 0x1c7c
  1784  
  1785  	// CJTypeImmMask is a mask including only the immediate portion of
  1786  	// CJ-type instructions.
  1787  	CJTypeImmMask = 0x1f7c
  1788  
  1789  	// ITypeImmMask is a mask including only the immediate portion of
  1790  	// I-type instructions.
  1791  	ITypeImmMask = 0xfff00000
  1792  
  1793  	// JTypeImmMask is a mask including only the immediate portion of
  1794  	// J-type instructions.
  1795  	JTypeImmMask = 0xfffff000
  1796  
  1797  	// STypeImmMask is a mask including only the immediate portion of
  1798  	// S-type instructions.
  1799  	STypeImmMask = 0xfe000f80
  1800  
  1801  	// UTypeImmMask is a mask including only the immediate portion of
  1802  	// U-type instructions.
  1803  	UTypeImmMask = 0xfffff000
  1804  )
  1805  

View as plain text