Source file src/cmd/internal/obj/riscv/cpu.go

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  var CSRs map[uint16]string = csrs
    39  
    40  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    41  
    42  const (
    43  	// Base register numberings.
    44  	REG_X0 = obj.RBaseRISCV + iota
    45  	REG_X1
    46  	REG_X2
    47  	REG_X3
    48  	REG_X4
    49  	REG_X5
    50  	REG_X6
    51  	REG_X7
    52  	REG_X8
    53  	REG_X9
    54  	REG_X10
    55  	REG_X11
    56  	REG_X12
    57  	REG_X13
    58  	REG_X14
    59  	REG_X15
    60  	REG_X16
    61  	REG_X17
    62  	REG_X18
    63  	REG_X19
    64  	REG_X20
    65  	REG_X21
    66  	REG_X22
    67  	REG_X23
    68  	REG_X24
    69  	REG_X25
    70  	REG_X26
    71  	REG_X27
    72  	REG_X28
    73  	REG_X29
    74  	REG_X30
    75  	REG_X31
    76  
    77  	// Floating Point register numberings.
    78  	REG_F0
    79  	REG_F1
    80  	REG_F2
    81  	REG_F3
    82  	REG_F4
    83  	REG_F5
    84  	REG_F6
    85  	REG_F7
    86  	REG_F8
    87  	REG_F9
    88  	REG_F10
    89  	REG_F11
    90  	REG_F12
    91  	REG_F13
    92  	REG_F14
    93  	REG_F15
    94  	REG_F16
    95  	REG_F17
    96  	REG_F18
    97  	REG_F19
    98  	REG_F20
    99  	REG_F21
   100  	REG_F22
   101  	REG_F23
   102  	REG_F24
   103  	REG_F25
   104  	REG_F26
   105  	REG_F27
   106  	REG_F28
   107  	REG_F29
   108  	REG_F30
   109  	REG_F31
   110  
   111  	// Vector register numberings.
   112  	REG_V0
   113  	REG_V1
   114  	REG_V2
   115  	REG_V3
   116  	REG_V4
   117  	REG_V5
   118  	REG_V6
   119  	REG_V7
   120  	REG_V8
   121  	REG_V9
   122  	REG_V10
   123  	REG_V11
   124  	REG_V12
   125  	REG_V13
   126  	REG_V14
   127  	REG_V15
   128  	REG_V16
   129  	REG_V17
   130  	REG_V18
   131  	REG_V19
   132  	REG_V20
   133  	REG_V21
   134  	REG_V22
   135  	REG_V23
   136  	REG_V24
   137  	REG_V25
   138  	REG_V26
   139  	REG_V27
   140  	REG_V28
   141  	REG_V29
   142  	REG_V30
   143  	REG_V31
   144  
   145  	// This marks the end of the register numbering.
   146  	REG_END
   147  
   148  	// General registers reassigned to ABI names.
   149  	REG_ZERO = REG_X0
   150  	REG_RA   = REG_X1 // aka REG_LR
   151  	REG_SP   = REG_X2
   152  	REG_GP   = REG_X3 // aka REG_SB
   153  	REG_TP   = REG_X4
   154  	REG_T0   = REG_X5
   155  	REG_T1   = REG_X6
   156  	REG_T2   = REG_X7
   157  	REG_S0   = REG_X8
   158  	REG_S1   = REG_X9
   159  	REG_A0   = REG_X10
   160  	REG_A1   = REG_X11
   161  	REG_A2   = REG_X12
   162  	REG_A3   = REG_X13
   163  	REG_A4   = REG_X14
   164  	REG_A5   = REG_X15
   165  	REG_A6   = REG_X16
   166  	REG_A7   = REG_X17
   167  	REG_S2   = REG_X18
   168  	REG_S3   = REG_X19
   169  	REG_S4   = REG_X20
   170  	REG_S5   = REG_X21
   171  	REG_S6   = REG_X22
   172  	REG_S7   = REG_X23
   173  	REG_S8   = REG_X24
   174  	REG_S9   = REG_X25
   175  	REG_S10  = REG_X26 // aka REG_CTXT
   176  	REG_S11  = REG_X27 // aka REG_G
   177  	REG_T3   = REG_X28
   178  	REG_T4   = REG_X29
   179  	REG_T5   = REG_X30
   180  	REG_T6   = REG_X31 // aka REG_TMP
   181  
   182  	// Go runtime register names.
   183  	REG_CTXT = REG_S10 // Context for closures.
   184  	REG_G    = REG_S11 // G pointer.
   185  	REG_LR   = REG_RA  // Link register.
   186  	REG_TMP  = REG_T6  // Reserved for assembler use.
   187  
   188  	// ABI names for floating point registers.
   189  	REG_FT0  = REG_F0
   190  	REG_FT1  = REG_F1
   191  	REG_FT2  = REG_F2
   192  	REG_FT3  = REG_F3
   193  	REG_FT4  = REG_F4
   194  	REG_FT5  = REG_F5
   195  	REG_FT6  = REG_F6
   196  	REG_FT7  = REG_F7
   197  	REG_FS0  = REG_F8
   198  	REG_FS1  = REG_F9
   199  	REG_FA0  = REG_F10
   200  	REG_FA1  = REG_F11
   201  	REG_FA2  = REG_F12
   202  	REG_FA3  = REG_F13
   203  	REG_FA4  = REG_F14
   204  	REG_FA5  = REG_F15
   205  	REG_FA6  = REG_F16
   206  	REG_FA7  = REG_F17
   207  	REG_FS2  = REG_F18
   208  	REG_FS3  = REG_F19
   209  	REG_FS4  = REG_F20
   210  	REG_FS5  = REG_F21
   211  	REG_FS6  = REG_F22
   212  	REG_FS7  = REG_F23
   213  	REG_FS8  = REG_F24
   214  	REG_FS9  = REG_F25
   215  	REG_FS10 = REG_F26
   216  	REG_FS11 = REG_F27
   217  	REG_FT8  = REG_F28
   218  	REG_FT9  = REG_F29
   219  	REG_FT10 = REG_F30
   220  	REG_FT11 = REG_F31
   221  
   222  	// Names generated by the SSA compiler.
   223  	REGSP = REG_SP
   224  	REGG  = REG_G
   225  )
   226  
   227  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   228  var RISCV64DWARFRegisters = map[int16]int16{
   229  	// Integer Registers.
   230  	REG_X0:  0,
   231  	REG_X1:  1,
   232  	REG_X2:  2,
   233  	REG_X3:  3,
   234  	REG_X4:  4,
   235  	REG_X5:  5,
   236  	REG_X6:  6,
   237  	REG_X7:  7,
   238  	REG_X8:  8,
   239  	REG_X9:  9,
   240  	REG_X10: 10,
   241  	REG_X11: 11,
   242  	REG_X12: 12,
   243  	REG_X13: 13,
   244  	REG_X14: 14,
   245  	REG_X15: 15,
   246  	REG_X16: 16,
   247  	REG_X17: 17,
   248  	REG_X18: 18,
   249  	REG_X19: 19,
   250  	REG_X20: 20,
   251  	REG_X21: 21,
   252  	REG_X22: 22,
   253  	REG_X23: 23,
   254  	REG_X24: 24,
   255  	REG_X25: 25,
   256  	REG_X26: 26,
   257  	REG_X27: 27,
   258  	REG_X28: 28,
   259  	REG_X29: 29,
   260  	REG_X30: 30,
   261  	REG_X31: 31,
   262  
   263  	// Floating-Point Registers.
   264  	REG_F0:  32,
   265  	REG_F1:  33,
   266  	REG_F2:  34,
   267  	REG_F3:  35,
   268  	REG_F4:  36,
   269  	REG_F5:  37,
   270  	REG_F6:  38,
   271  	REG_F7:  39,
   272  	REG_F8:  40,
   273  	REG_F9:  41,
   274  	REG_F10: 42,
   275  	REG_F11: 43,
   276  	REG_F12: 44,
   277  	REG_F13: 45,
   278  	REG_F14: 46,
   279  	REG_F15: 47,
   280  	REG_F16: 48,
   281  	REG_F17: 49,
   282  	REG_F18: 50,
   283  	REG_F19: 51,
   284  	REG_F20: 52,
   285  	REG_F21: 53,
   286  	REG_F22: 54,
   287  	REG_F23: 55,
   288  	REG_F24: 56,
   289  	REG_F25: 57,
   290  	REG_F26: 58,
   291  	REG_F27: 59,
   292  	REG_F28: 60,
   293  	REG_F29: 61,
   294  	REG_F30: 62,
   295  	REG_F31: 63,
   296  }
   297  
   298  // Prog.Mark flags.
   299  const (
   300  	// USES_REG_TMP indicates that a machine instruction generated from the
   301  	// corresponding *obj.Prog uses the temporary register.
   302  	USES_REG_TMP = 1 << iota
   303  
   304  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   305  	// R_RISCV_JAL relocation is needed.
   306  	NEED_JAL_RELOC
   307  
   308  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   309  	// is the first instruction in an AUIPC + JAL pair that needs a
   310  	// R_RISCV_CALL relocation.
   311  	NEED_CALL_RELOC
   312  
   313  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   314  	// it is the first instruction in an AUIPC + I-type pair that needs a
   315  	// R_RISCV_PCREL_ITYPE relocation.
   316  	NEED_PCREL_ITYPE_RELOC
   317  
   318  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   319  	// it is the first instruction in an AUIPC + S-type pair that needs a
   320  	// R_RISCV_PCREL_STYPE relocation.
   321  	NEED_PCREL_STYPE_RELOC
   322  
   323  	// NEED_GOT_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   324  	// it is the first instruction in an AUIPC + I-type pair that needs a
   325  	// R_RISCV_GOT_PCREL_ITYPE relocation.
   326  	NEED_GOT_PCREL_ITYPE_RELOC
   327  )
   328  
   329  const NEED_RELOC = NEED_JAL_RELOC | NEED_CALL_RELOC | NEED_PCREL_ITYPE_RELOC |
   330  	NEED_PCREL_STYPE_RELOC | NEED_GOT_PCREL_ITYPE_RELOC
   331  
   332  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   333  // at https://github.com/riscv/riscv-opcodes.
   334  //
   335  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   336  //
   337  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
   338  //
   339  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   340  const (
   341  	//
   342  	// Unprivileged ISA (version 20240411)
   343  	//
   344  
   345  	// 2.4: Integer Computational Instructions
   346  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   347  	ASLTI
   348  	ASLTIU
   349  	AANDI
   350  	AORI
   351  	AXORI
   352  	ASLLI
   353  	ASRLI
   354  	ASRAI
   355  	ALUI
   356  	AAUIPC
   357  	AADD
   358  	ASLT
   359  	ASLTU
   360  	AAND
   361  	AOR
   362  	AXOR
   363  	ASLL
   364  	ASRL
   365  	ASUB
   366  	ASRA
   367  
   368  	// 2.5: Control Transfer Instructions
   369  	AJAL
   370  	AJALR
   371  	ABEQ
   372  	ABNE
   373  	ABLT
   374  	ABLTU
   375  	ABGE
   376  	ABGEU
   377  
   378  	// 2.6: Load and Store Instructions
   379  	ALW
   380  	ALWU
   381  	ALH
   382  	ALHU
   383  	ALB
   384  	ALBU
   385  	ASW
   386  	ASH
   387  	ASB
   388  
   389  	// 2.7: Memory Ordering Instructions
   390  	AFENCE
   391  
   392  	// 4.2: Integer Computational Instructions (RV64I)
   393  	AADDIW
   394  	ASLLIW
   395  	ASRLIW
   396  	ASRAIW
   397  	AADDW
   398  	ASLLW
   399  	ASRLW
   400  	ASUBW
   401  	ASRAW
   402  
   403  	// 4.3: Load and Store Instructions (RV64I)
   404  	ALD
   405  	ASD
   406  
   407  	// 7.1: CSR Instructions (Zicsr)
   408  	ACSRRW
   409  	ACSRRS
   410  	ACSRRC
   411  	ACSRRWI
   412  	ACSRRSI
   413  	ACSRRCI
   414  
   415  	// 12.3: Integer Conditional Operations (Zicond)
   416  	ACZEROEQZ
   417  	ACZERONEZ
   418  
   419  	// 13.1: Multiplication Operations
   420  	AMUL
   421  	AMULH
   422  	AMULHU
   423  	AMULHSU
   424  	AMULW
   425  
   426  	// 13.2: Division Operations
   427  	ADIV
   428  	ADIVU
   429  	AREM
   430  	AREMU
   431  	ADIVW
   432  	ADIVUW
   433  	AREMW
   434  	AREMUW
   435  
   436  	// 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
   437  	ALRD
   438  	ASCD
   439  	ALRW
   440  	ASCW
   441  
   442  	// 14.4: Atomic Memory Operations (Zaamo)
   443  	AAMOSWAPD
   444  	AAMOADDD
   445  	AAMOANDD
   446  	AAMOORD
   447  	AAMOXORD
   448  	AAMOMAXD
   449  	AAMOMAXUD
   450  	AAMOMIND
   451  	AAMOMINUD
   452  	AAMOSWAPW
   453  	AAMOADDW
   454  	AAMOANDW
   455  	AAMOORW
   456  	AAMOXORW
   457  	AAMOMAXW
   458  	AAMOMAXUW
   459  	AAMOMINW
   460  	AAMOMINUW
   461  
   462  	// 20.5: Single-Precision Load and Store Instructions
   463  	AFLW
   464  	AFSW
   465  
   466  	// 20.6: Single-Precision Floating-Point Computational Instructions
   467  	AFADDS
   468  	AFSUBS
   469  	AFMULS
   470  	AFDIVS
   471  	AFMINS
   472  	AFMAXS
   473  	AFSQRTS
   474  	AFMADDS
   475  	AFMSUBS
   476  	AFNMADDS
   477  	AFNMSUBS
   478  
   479  	// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
   480  	AFCVTWS
   481  	AFCVTLS
   482  	AFCVTSW
   483  	AFCVTSL
   484  	AFCVTWUS
   485  	AFCVTLUS
   486  	AFCVTSWU
   487  	AFCVTSLU
   488  	AFSGNJS
   489  	AFSGNJNS
   490  	AFSGNJXS
   491  	AFMVXS
   492  	AFMVSX
   493  	AFMVXW
   494  	AFMVWX
   495  
   496  	// 20.8: Single-Precision Floating-Point Compare Instructions
   497  	AFEQS
   498  	AFLTS
   499  	AFLES
   500  
   501  	// 20.9: Single-Precision Floating-Point Classify Instruction
   502  	AFCLASSS
   503  
   504  	// 21.3: Double-Precision Load and Store Instructions
   505  	AFLD
   506  	AFSD
   507  
   508  	// 21.4: Double-Precision Floating-Point Computational Instructions
   509  	AFADDD
   510  	AFSUBD
   511  	AFMULD
   512  	AFDIVD
   513  	AFMIND
   514  	AFMAXD
   515  	AFSQRTD
   516  	AFMADDD
   517  	AFMSUBD
   518  	AFNMADDD
   519  	AFNMSUBD
   520  
   521  	// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
   522  	AFCVTWD
   523  	AFCVTLD
   524  	AFCVTDW
   525  	AFCVTDL
   526  	AFCVTWUD
   527  	AFCVTLUD
   528  	AFCVTDWU
   529  	AFCVTDLU
   530  	AFCVTSD
   531  	AFCVTDS
   532  	AFSGNJD
   533  	AFSGNJND
   534  	AFSGNJXD
   535  	AFMVXD
   536  	AFMVDX
   537  
   538  	// 21.6: Double-Precision Floating-Point Compare Instructions
   539  	AFEQD
   540  	AFLTD
   541  	AFLED
   542  
   543  	// 21.7: Double-Precision Floating-Point Classify Instruction
   544  	AFCLASSD
   545  
   546  	// 22.1 Quad-Precision Load and Store Instructions
   547  	AFLQ
   548  	AFSQ
   549  
   550  	// 22.2: Quad-Precision Computational Instructions
   551  	AFADDQ
   552  	AFSUBQ
   553  	AFMULQ
   554  	AFDIVQ
   555  	AFMINQ
   556  	AFMAXQ
   557  	AFSQRTQ
   558  	AFMADDQ
   559  	AFMSUBQ
   560  	AFNMADDQ
   561  	AFNMSUBQ
   562  
   563  	// 22.3: Quad-Precision Convert and Move Instructions
   564  	AFCVTWQ
   565  	AFCVTLQ
   566  	AFCVTSQ
   567  	AFCVTDQ
   568  	AFCVTQW
   569  	AFCVTQL
   570  	AFCVTQS
   571  	AFCVTQD
   572  	AFCVTWUQ
   573  	AFCVTLUQ
   574  	AFCVTQWU
   575  	AFCVTQLU
   576  	AFSGNJQ
   577  	AFSGNJNQ
   578  	AFSGNJXQ
   579  
   580  	// 22.4: Quad-Precision Floating-Point Compare Instructions
   581  	AFEQQ
   582  	AFLEQ
   583  	AFLTQ
   584  
   585  	// 22.5: Quad-Precision Floating-Point Classify Instruction
   586  	AFCLASSQ
   587  
   588  	//
   589  	// "C" Extension for Compressed Instructions
   590  	//
   591  
   592  	// 26.3.1: Compressed Stack-Pointer-Based Loads and Stores
   593  	ACLWSP
   594  	ACLDSP
   595  	ACFLDSP
   596  	ACSWSP
   597  	ACSDSP
   598  	ACFSDSP
   599  
   600  	// 26.3.2: Compressed Register-Based Loads and Stores
   601  	ACLW
   602  	ACLD
   603  	ACFLD
   604  	ACSW
   605  	ACSD
   606  	ACFSD
   607  
   608  	// 26.4: Compressed Control Transfer Instructions
   609  	ACJ
   610  	ACJR
   611  	ACJALR
   612  	ACBEQZ
   613  	ACBNEZ
   614  
   615  	// 26.5.1: Compressed Integer Constant-Generation Instructions
   616  	ACLI
   617  	ACLUI
   618  	ACADDI
   619  	ACADDIW
   620  	ACADDI16SP
   621  	ACADDI4SPN
   622  	ACSLLI
   623  	ACSRLI
   624  	ACSRAI
   625  	ACANDI
   626  
   627  	// 26.5.3: Compressed Integer Register-Register Operations
   628  	ACMV
   629  	ACADD
   630  	ACAND
   631  	ACOR
   632  	ACXOR
   633  	ACSUB
   634  	ACADDW
   635  	ACSUBW
   636  
   637  	// 26.5.5: Compressed NOP Instruction
   638  	ACNOP
   639  
   640  	// 26.5.6: Compressed Breakpoint Instruction
   641  	ACEBREAK
   642  
   643  	//
   644  	// "B" Extension for Bit Manipulation, Version 1.0.0
   645  	//
   646  
   647  	// 28.4.1: Address Generation Instructions (Zba)
   648  	AADDUW
   649  	ASH1ADD
   650  	ASH1ADDUW
   651  	ASH2ADD
   652  	ASH2ADDUW
   653  	ASH3ADD
   654  	ASH3ADDUW
   655  	ASLLIUW
   656  
   657  	// 28.4.2: Basic Bit Manipulation (Zbb)
   658  	AANDN
   659  	AORN
   660  	AXNOR
   661  	ACLZ
   662  	ACLZW
   663  	ACTZ
   664  	ACTZW
   665  	ACPOP
   666  	ACPOPW
   667  	AMAX
   668  	AMAXU
   669  	AMIN
   670  	AMINU
   671  	ASEXTB
   672  	ASEXTH
   673  	AZEXTH
   674  
   675  	// 28.4.3: Bitwise Rotation (Zbb)
   676  	AROL
   677  	AROLW
   678  	AROR
   679  	ARORI
   680  	ARORIW
   681  	ARORW
   682  	AORCB
   683  	AREV8
   684  
   685  	// 28.4.4: Single-bit Instructions (Zbs)
   686  	ABCLR
   687  	ABCLRI
   688  	ABEXT
   689  	ABEXTI
   690  	ABINV
   691  	ABINVI
   692  	ABSET
   693  	ABSETI
   694  
   695  	//
   696  	// "V" Standard Extension for Vector Operations, Version 1.0
   697  	//
   698  
   699  	// 31.6: Configuration-Setting Instructions
   700  	AVSETVLI
   701  	AVSETIVLI
   702  	AVSETVL
   703  
   704  	// 31.7.4: Vector Unit-Stride Instructions
   705  	AVLE8V
   706  	AVLE16V
   707  	AVLE32V
   708  	AVLE64V
   709  	AVSE8V
   710  	AVSE16V
   711  	AVSE32V
   712  	AVSE64V
   713  	AVLMV
   714  	AVSMV
   715  
   716  	// 31.7.5: Vector Strided Instructions
   717  	AVLSE8V
   718  	AVLSE16V
   719  	AVLSE32V
   720  	AVLSE64V
   721  	AVSSE8V
   722  	AVSSE16V
   723  	AVSSE32V
   724  	AVSSE64V
   725  
   726  	// 31.7.6: Vector Indexed Instructions
   727  	AVLUXEI8V
   728  	AVLUXEI16V
   729  	AVLUXEI32V
   730  	AVLUXEI64V
   731  	AVLOXEI8V
   732  	AVLOXEI16V
   733  	AVLOXEI32V
   734  	AVLOXEI64V
   735  	AVSUXEI8V
   736  	AVSUXEI16V
   737  	AVSUXEI32V
   738  	AVSUXEI64V
   739  	AVSOXEI8V
   740  	AVSOXEI16V
   741  	AVSOXEI32V
   742  	AVSOXEI64V
   743  
   744  	// 31.7.7: Unit-stride Fault-Only-First Loads
   745  	AVLE8FFV
   746  	AVLE16FFV
   747  	AVLE32FFV
   748  	AVLE64FFV
   749  
   750  	// 31.7.8. Vector Load/Store Segment Instructions
   751  
   752  	// 31.7.8.1. Vector Unit-Stride Segment Loads and Stores
   753  	AVLSEG2E8V
   754  	AVLSEG3E8V
   755  	AVLSEG4E8V
   756  	AVLSEG5E8V
   757  	AVLSEG6E8V
   758  	AVLSEG7E8V
   759  	AVLSEG8E8V
   760  	AVLSEG2E16V
   761  	AVLSEG3E16V
   762  	AVLSEG4E16V
   763  	AVLSEG5E16V
   764  	AVLSEG6E16V
   765  	AVLSEG7E16V
   766  	AVLSEG8E16V
   767  	AVLSEG2E32V
   768  	AVLSEG3E32V
   769  	AVLSEG4E32V
   770  	AVLSEG5E32V
   771  	AVLSEG6E32V
   772  	AVLSEG7E32V
   773  	AVLSEG8E32V
   774  	AVLSEG2E64V
   775  	AVLSEG3E64V
   776  	AVLSEG4E64V
   777  	AVLSEG5E64V
   778  	AVLSEG6E64V
   779  	AVLSEG7E64V
   780  	AVLSEG8E64V
   781  
   782  	AVSSEG2E8V
   783  	AVSSEG3E8V
   784  	AVSSEG4E8V
   785  	AVSSEG5E8V
   786  	AVSSEG6E8V
   787  	AVSSEG7E8V
   788  	AVSSEG8E8V
   789  	AVSSEG2E16V
   790  	AVSSEG3E16V
   791  	AVSSEG4E16V
   792  	AVSSEG5E16V
   793  	AVSSEG6E16V
   794  	AVSSEG7E16V
   795  	AVSSEG8E16V
   796  	AVSSEG2E32V
   797  	AVSSEG3E32V
   798  	AVSSEG4E32V
   799  	AVSSEG5E32V
   800  	AVSSEG6E32V
   801  	AVSSEG7E32V
   802  	AVSSEG8E32V
   803  	AVSSEG2E64V
   804  	AVSSEG3E64V
   805  	AVSSEG4E64V
   806  	AVSSEG5E64V
   807  	AVSSEG6E64V
   808  	AVSSEG7E64V
   809  	AVSSEG8E64V
   810  
   811  	AVLSEG2E8FFV
   812  	AVLSEG3E8FFV
   813  	AVLSEG4E8FFV
   814  	AVLSEG5E8FFV
   815  	AVLSEG6E8FFV
   816  	AVLSEG7E8FFV
   817  	AVLSEG8E8FFV
   818  	AVLSEG2E16FFV
   819  	AVLSEG3E16FFV
   820  	AVLSEG4E16FFV
   821  	AVLSEG5E16FFV
   822  	AVLSEG6E16FFV
   823  	AVLSEG7E16FFV
   824  	AVLSEG8E16FFV
   825  	AVLSEG2E32FFV
   826  	AVLSEG3E32FFV
   827  	AVLSEG4E32FFV
   828  	AVLSEG5E32FFV
   829  	AVLSEG6E32FFV
   830  	AVLSEG7E32FFV
   831  	AVLSEG8E32FFV
   832  	AVLSEG2E64FFV
   833  	AVLSEG3E64FFV
   834  	AVLSEG4E64FFV
   835  	AVLSEG5E64FFV
   836  	AVLSEG6E64FFV
   837  	AVLSEG7E64FFV
   838  	AVLSEG8E64FFV
   839  
   840  	// 31.7.8.2. Vector Strided Segment Loads and Stores
   841  	AVLSSEG2E8V
   842  	AVLSSEG3E8V
   843  	AVLSSEG4E8V
   844  	AVLSSEG5E8V
   845  	AVLSSEG6E8V
   846  	AVLSSEG7E8V
   847  	AVLSSEG8E8V
   848  	AVLSSEG2E16V
   849  	AVLSSEG3E16V
   850  	AVLSSEG4E16V
   851  	AVLSSEG5E16V
   852  	AVLSSEG6E16V
   853  	AVLSSEG7E16V
   854  	AVLSSEG8E16V
   855  	AVLSSEG2E32V
   856  	AVLSSEG3E32V
   857  	AVLSSEG4E32V
   858  	AVLSSEG5E32V
   859  	AVLSSEG6E32V
   860  	AVLSSEG7E32V
   861  	AVLSSEG8E32V
   862  	AVLSSEG2E64V
   863  	AVLSSEG3E64V
   864  	AVLSSEG4E64V
   865  	AVLSSEG5E64V
   866  	AVLSSEG6E64V
   867  	AVLSSEG7E64V
   868  	AVLSSEG8E64V
   869  
   870  	AVSSSEG2E8V
   871  	AVSSSEG3E8V
   872  	AVSSSEG4E8V
   873  	AVSSSEG5E8V
   874  	AVSSSEG6E8V
   875  	AVSSSEG7E8V
   876  	AVSSSEG8E8V
   877  	AVSSSEG2E16V
   878  	AVSSSEG3E16V
   879  	AVSSSEG4E16V
   880  	AVSSSEG5E16V
   881  	AVSSSEG6E16V
   882  	AVSSSEG7E16V
   883  	AVSSSEG8E16V
   884  	AVSSSEG2E32V
   885  	AVSSSEG3E32V
   886  	AVSSSEG4E32V
   887  	AVSSSEG5E32V
   888  	AVSSSEG6E32V
   889  	AVSSSEG7E32V
   890  	AVSSSEG8E32V
   891  	AVSSSEG2E64V
   892  	AVSSSEG3E64V
   893  	AVSSSEG4E64V
   894  	AVSSSEG5E64V
   895  	AVSSSEG6E64V
   896  	AVSSSEG7E64V
   897  	AVSSSEG8E64V
   898  
   899  	// 31.7.8.3. Vector Indexed Segment Loads and Stores
   900  	AVLOXSEG2EI8V
   901  	AVLOXSEG3EI8V
   902  	AVLOXSEG4EI8V
   903  	AVLOXSEG5EI8V
   904  	AVLOXSEG6EI8V
   905  	AVLOXSEG7EI8V
   906  	AVLOXSEG8EI8V
   907  	AVLOXSEG2EI16V
   908  	AVLOXSEG3EI16V
   909  	AVLOXSEG4EI16V
   910  	AVLOXSEG5EI16V
   911  	AVLOXSEG6EI16V
   912  	AVLOXSEG7EI16V
   913  	AVLOXSEG8EI16V
   914  	AVLOXSEG2EI32V
   915  	AVLOXSEG3EI32V
   916  	AVLOXSEG4EI32V
   917  	AVLOXSEG5EI32V
   918  	AVLOXSEG6EI32V
   919  	AVLOXSEG7EI32V
   920  	AVLOXSEG8EI32V
   921  	AVLOXSEG2EI64V
   922  	AVLOXSEG3EI64V
   923  	AVLOXSEG4EI64V
   924  	AVLOXSEG5EI64V
   925  	AVLOXSEG6EI64V
   926  	AVLOXSEG7EI64V
   927  	AVLOXSEG8EI64V
   928  
   929  	AVSOXSEG2EI8V
   930  	AVSOXSEG3EI8V
   931  	AVSOXSEG4EI8V
   932  	AVSOXSEG5EI8V
   933  	AVSOXSEG6EI8V
   934  	AVSOXSEG7EI8V
   935  	AVSOXSEG8EI8V
   936  	AVSOXSEG2EI16V
   937  	AVSOXSEG3EI16V
   938  	AVSOXSEG4EI16V
   939  	AVSOXSEG5EI16V
   940  	AVSOXSEG6EI16V
   941  	AVSOXSEG7EI16V
   942  	AVSOXSEG8EI16V
   943  	AVSOXSEG2EI32V
   944  	AVSOXSEG3EI32V
   945  	AVSOXSEG4EI32V
   946  	AVSOXSEG5EI32V
   947  	AVSOXSEG6EI32V
   948  	AVSOXSEG7EI32V
   949  	AVSOXSEG8EI32V
   950  	AVSOXSEG2EI64V
   951  	AVSOXSEG3EI64V
   952  	AVSOXSEG4EI64V
   953  	AVSOXSEG5EI64V
   954  	AVSOXSEG6EI64V
   955  	AVSOXSEG7EI64V
   956  	AVSOXSEG8EI64V
   957  
   958  	AVLUXSEG2EI8V
   959  	AVLUXSEG3EI8V
   960  	AVLUXSEG4EI8V
   961  	AVLUXSEG5EI8V
   962  	AVLUXSEG6EI8V
   963  	AVLUXSEG7EI8V
   964  	AVLUXSEG8EI8V
   965  	AVLUXSEG2EI16V
   966  	AVLUXSEG3EI16V
   967  	AVLUXSEG4EI16V
   968  	AVLUXSEG5EI16V
   969  	AVLUXSEG6EI16V
   970  	AVLUXSEG7EI16V
   971  	AVLUXSEG8EI16V
   972  	AVLUXSEG2EI32V
   973  	AVLUXSEG3EI32V
   974  	AVLUXSEG4EI32V
   975  	AVLUXSEG5EI32V
   976  	AVLUXSEG6EI32V
   977  	AVLUXSEG7EI32V
   978  	AVLUXSEG8EI32V
   979  	AVLUXSEG2EI64V
   980  	AVLUXSEG3EI64V
   981  	AVLUXSEG4EI64V
   982  	AVLUXSEG5EI64V
   983  	AVLUXSEG6EI64V
   984  	AVLUXSEG7EI64V
   985  	AVLUXSEG8EI64V
   986  
   987  	AVSUXSEG2EI8V
   988  	AVSUXSEG3EI8V
   989  	AVSUXSEG4EI8V
   990  	AVSUXSEG5EI8V
   991  	AVSUXSEG6EI8V
   992  	AVSUXSEG7EI8V
   993  	AVSUXSEG8EI8V
   994  	AVSUXSEG2EI16V
   995  	AVSUXSEG3EI16V
   996  	AVSUXSEG4EI16V
   997  	AVSUXSEG5EI16V
   998  	AVSUXSEG6EI16V
   999  	AVSUXSEG7EI16V
  1000  	AVSUXSEG8EI16V
  1001  	AVSUXSEG2EI32V
  1002  	AVSUXSEG3EI32V
  1003  	AVSUXSEG4EI32V
  1004  	AVSUXSEG5EI32V
  1005  	AVSUXSEG6EI32V
  1006  	AVSUXSEG7EI32V
  1007  	AVSUXSEG8EI32V
  1008  	AVSUXSEG2EI64V
  1009  	AVSUXSEG3EI64V
  1010  	AVSUXSEG4EI64V
  1011  	AVSUXSEG5EI64V
  1012  	AVSUXSEG6EI64V
  1013  	AVSUXSEG7EI64V
  1014  	AVSUXSEG8EI64V
  1015  
  1016  	// 31.7.9: Vector Load/Store Whole Register Instructions
  1017  	AVL1RE8V
  1018  	AVL1RE16V
  1019  	AVL1RE32V
  1020  	AVL1RE64V
  1021  	AVL2RE8V
  1022  	AVL2RE16V
  1023  	AVL2RE32V
  1024  	AVL2RE64V
  1025  	AVL4RE8V
  1026  	AVL4RE16V
  1027  	AVL4RE32V
  1028  	AVL4RE64V
  1029  	AVL8RE8V
  1030  	AVL8RE16V
  1031  	AVL8RE32V
  1032  	AVL8RE64V
  1033  	AVS1RV
  1034  	AVS2RV
  1035  	AVS4RV
  1036  	AVS8RV
  1037  
  1038  	// 31.11.1: Vector Single-Width Integer Add and Subtract
  1039  	AVADDVV
  1040  	AVADDVX
  1041  	AVADDVI
  1042  	AVSUBVV
  1043  	AVSUBVX
  1044  	AVRSUBVX
  1045  	AVRSUBVI
  1046  
  1047  	// 31.11.2: Vector Widening Integer Add/Subtract
  1048  	AVWADDUVV
  1049  	AVWADDUVX
  1050  	AVWSUBUVV
  1051  	AVWSUBUVX
  1052  	AVWADDVV
  1053  	AVWADDVX
  1054  	AVWSUBVV
  1055  	AVWSUBVX
  1056  	AVWADDUWV
  1057  	AVWADDUWX
  1058  	AVWSUBUWV
  1059  	AVWSUBUWX
  1060  	AVWADDWV
  1061  	AVWADDWX
  1062  	AVWSUBWV
  1063  	AVWSUBWX
  1064  
  1065  	// 31.11.3: Vector Integer Extension
  1066  	AVZEXTVF2
  1067  	AVSEXTVF2
  1068  	AVZEXTVF4
  1069  	AVSEXTVF4
  1070  	AVZEXTVF8
  1071  	AVSEXTVF8
  1072  
  1073  	// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
  1074  	AVADCVVM
  1075  	AVADCVXM
  1076  	AVADCVIM
  1077  	AVMADCVVM
  1078  	AVMADCVXM
  1079  	AVMADCVIM
  1080  	AVMADCVV
  1081  	AVMADCVX
  1082  	AVMADCVI
  1083  	AVSBCVVM
  1084  	AVSBCVXM
  1085  	AVMSBCVVM
  1086  	AVMSBCVXM
  1087  	AVMSBCVV
  1088  	AVMSBCVX
  1089  
  1090  	// 31.11.5: Vector Bitwise Logical Instructions
  1091  	AVANDVV
  1092  	AVANDVX
  1093  	AVANDVI
  1094  	AVORVV
  1095  	AVORVX
  1096  	AVORVI
  1097  	AVXORVV
  1098  	AVXORVX
  1099  	AVXORVI
  1100  
  1101  	// 31.11.6: Vector Single-Width Shift Instructions
  1102  	AVSLLVV
  1103  	AVSLLVX
  1104  	AVSLLVI
  1105  	AVSRLVV
  1106  	AVSRLVX
  1107  	AVSRLVI
  1108  	AVSRAVV
  1109  	AVSRAVX
  1110  	AVSRAVI
  1111  
  1112  	// 31.11.7: Vector Narrowing Integer Right Shift Instructions
  1113  	AVNSRLWV
  1114  	AVNSRLWX
  1115  	AVNSRLWI
  1116  	AVNSRAWV
  1117  	AVNSRAWX
  1118  	AVNSRAWI
  1119  
  1120  	// 31.11.8: Vector Integer Compare Instructions
  1121  	AVMSEQVV
  1122  	AVMSEQVX
  1123  	AVMSEQVI
  1124  	AVMSNEVV
  1125  	AVMSNEVX
  1126  	AVMSNEVI
  1127  	AVMSLTUVV
  1128  	AVMSLTUVX
  1129  	AVMSLTVV
  1130  	AVMSLTVX
  1131  	AVMSLEUVV
  1132  	AVMSLEUVX
  1133  	AVMSLEUVI
  1134  	AVMSLEVV
  1135  	AVMSLEVX
  1136  	AVMSLEVI
  1137  	AVMSGTUVX
  1138  	AVMSGTUVI
  1139  	AVMSGTVX
  1140  	AVMSGTVI
  1141  
  1142  	// 31.11.9: Vector Integer Min/Max Instructions
  1143  	AVMINUVV
  1144  	AVMINUVX
  1145  	AVMINVV
  1146  	AVMINVX
  1147  	AVMAXUVV
  1148  	AVMAXUVX
  1149  	AVMAXVV
  1150  	AVMAXVX
  1151  
  1152  	// 31.11.10: Vector Single-Width Integer Multiply Instructions
  1153  	AVMULVV
  1154  	AVMULVX
  1155  	AVMULHVV
  1156  	AVMULHVX
  1157  	AVMULHUVV
  1158  	AVMULHUVX
  1159  	AVMULHSUVV
  1160  	AVMULHSUVX
  1161  
  1162  	// 31.11.11: Vector Integer Divide Instructions
  1163  	AVDIVUVV
  1164  	AVDIVUVX
  1165  	AVDIVVV
  1166  	AVDIVVX
  1167  	AVREMUVV
  1168  	AVREMUVX
  1169  	AVREMVV
  1170  	AVREMVX
  1171  
  1172  	// 31.11.12: Vector Widening Integer Multiply Instructions
  1173  	AVWMULVV
  1174  	AVWMULVX
  1175  	AVWMULUVV
  1176  	AVWMULUVX
  1177  	AVWMULSUVV
  1178  	AVWMULSUVX
  1179  
  1180  	// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
  1181  	AVMACCVV
  1182  	AVMACCVX
  1183  	AVNMSACVV
  1184  	AVNMSACVX
  1185  	AVMADDVV
  1186  	AVMADDVX
  1187  	AVNMSUBVV
  1188  	AVNMSUBVX
  1189  
  1190  	// 31.11.14: Vector Widening Integer Multiply-Add Instructions
  1191  	AVWMACCUVV
  1192  	AVWMACCUVX
  1193  	AVWMACCVV
  1194  	AVWMACCVX
  1195  	AVWMACCSUVV
  1196  	AVWMACCSUVX
  1197  	AVWMACCUSVX
  1198  
  1199  	// 31.11.15: Vector Integer Merge Instructions
  1200  	AVMERGEVVM
  1201  	AVMERGEVXM
  1202  	AVMERGEVIM
  1203  
  1204  	// 31.11.16: Vector Integer Move Instructions
  1205  	AVMVVV
  1206  	AVMVVX
  1207  	AVMVVI
  1208  
  1209  	// 31.12.1: Vector Single-Width Saturating Add and Subtract
  1210  	AVSADDUVV
  1211  	AVSADDUVX
  1212  	AVSADDUVI
  1213  	AVSADDVV
  1214  	AVSADDVX
  1215  	AVSADDVI
  1216  	AVSSUBUVV
  1217  	AVSSUBUVX
  1218  	AVSSUBVV
  1219  	AVSSUBVX
  1220  
  1221  	// 31.12.2: Vector Single-Width Averaging Add and Subtract
  1222  	AVAADDUVV
  1223  	AVAADDUVX
  1224  	AVAADDVV
  1225  	AVAADDVX
  1226  	AVASUBUVV
  1227  	AVASUBUVX
  1228  	AVASUBVV
  1229  	AVASUBVX
  1230  
  1231  	// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
  1232  	AVSMULVV
  1233  	AVSMULVX
  1234  
  1235  	// 31.12.4: Vector Single-Width Scaling Shift Instructions
  1236  	AVSSRLVV
  1237  	AVSSRLVX
  1238  	AVSSRLVI
  1239  	AVSSRAVV
  1240  	AVSSRAVX
  1241  	AVSSRAVI
  1242  
  1243  	// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
  1244  	AVNCLIPUWV
  1245  	AVNCLIPUWX
  1246  	AVNCLIPUWI
  1247  	AVNCLIPWV
  1248  	AVNCLIPWX
  1249  	AVNCLIPWI
  1250  
  1251  	// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
  1252  	AVFADDVV
  1253  	AVFADDVF
  1254  	AVFSUBVV
  1255  	AVFSUBVF
  1256  	AVFRSUBVF
  1257  
  1258  	// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
  1259  	AVFWADDVV
  1260  	AVFWADDVF
  1261  	AVFWSUBVV
  1262  	AVFWSUBVF
  1263  	AVFWADDWV
  1264  	AVFWADDWF
  1265  	AVFWSUBWV
  1266  	AVFWSUBWF
  1267  
  1268  	// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
  1269  	AVFMULVV
  1270  	AVFMULVF
  1271  	AVFDIVVV
  1272  	AVFDIVVF
  1273  	AVFRDIVVF
  1274  
  1275  	// 31.13.5: Vector Widening Floating-Point Multiply
  1276  	AVFWMULVV
  1277  	AVFWMULVF
  1278  
  1279  	// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
  1280  	AVFMACCVV
  1281  	AVFMACCVF
  1282  	AVFNMACCVV
  1283  	AVFNMACCVF
  1284  	AVFMSACVV
  1285  	AVFMSACVF
  1286  	AVFNMSACVV
  1287  	AVFNMSACVF
  1288  	AVFMADDVV
  1289  	AVFMADDVF
  1290  	AVFNMADDVV
  1291  	AVFNMADDVF
  1292  	AVFMSUBVV
  1293  	AVFMSUBVF
  1294  	AVFNMSUBVV
  1295  	AVFNMSUBVF
  1296  
  1297  	// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
  1298  	AVFWMACCVV
  1299  	AVFWMACCVF
  1300  	AVFWNMACCVV
  1301  	AVFWNMACCVF
  1302  	AVFWMSACVV
  1303  	AVFWMSACVF
  1304  	AVFWNMSACVV
  1305  	AVFWNMSACVF
  1306  
  1307  	// 31.13.8: Vector Floating-Point Square-Root Instruction
  1308  	AVFSQRTV
  1309  
  1310  	// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
  1311  	AVFRSQRT7V
  1312  
  1313  	// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
  1314  	AVFREC7V
  1315  
  1316  	// 31.13.11: Vector Floating-Point MIN/MAX Instructions
  1317  	AVFMINVV
  1318  	AVFMINVF
  1319  	AVFMAXVV
  1320  	AVFMAXVF
  1321  
  1322  	// 31.13.12: Vector Floating-Point Sign-Injection Instructions
  1323  	AVFSGNJVV
  1324  	AVFSGNJVF
  1325  	AVFSGNJNVV
  1326  	AVFSGNJNVF
  1327  	AVFSGNJXVV
  1328  	AVFSGNJXVF
  1329  
  1330  	// 31.13.13: Vector Floating-Point Compare Instructions
  1331  	AVMFEQVV
  1332  	AVMFEQVF
  1333  	AVMFNEVV
  1334  	AVMFNEVF
  1335  	AVMFLTVV
  1336  	AVMFLTVF
  1337  	AVMFLEVV
  1338  	AVMFLEVF
  1339  	AVMFGTVF
  1340  	AVMFGEVF
  1341  
  1342  	// 31.13.14: Vector Floating-Point Classify Instruction
  1343  	AVFCLASSV
  1344  
  1345  	// 31.13.15: Vector Floating-Point Merge Instruction
  1346  	AVFMERGEVFM
  1347  
  1348  	// 31.13.16: Vector Floating-Point Move Instruction
  1349  	AVFMVVF
  1350  
  1351  	// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
  1352  	AVFCVTXUFV
  1353  	AVFCVTXFV
  1354  	AVFCVTRTZXUFV
  1355  	AVFCVTRTZXFV
  1356  	AVFCVTFXUV
  1357  	AVFCVTFXV
  1358  
  1359  	// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
  1360  	AVFWCVTXUFV
  1361  	AVFWCVTXFV
  1362  	AVFWCVTRTZXUFV
  1363  	AVFWCVTRTZXFV
  1364  	AVFWCVTFXUV
  1365  	AVFWCVTFXV
  1366  	AVFWCVTFFV
  1367  
  1368  	// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
  1369  	AVFNCVTXUFW
  1370  	AVFNCVTXFW
  1371  	AVFNCVTRTZXUFW
  1372  	AVFNCVTRTZXFW
  1373  	AVFNCVTFXUW
  1374  	AVFNCVTFXW
  1375  	AVFNCVTFFW
  1376  	AVFNCVTRODFFW
  1377  
  1378  	// 31.14.1: Vector Single-Width Integer Reduction Instructions
  1379  	AVREDSUMVS
  1380  	AVREDMAXUVS
  1381  	AVREDMAXVS
  1382  	AVREDMINUVS
  1383  	AVREDMINVS
  1384  	AVREDANDVS
  1385  	AVREDORVS
  1386  	AVREDXORVS
  1387  
  1388  	// 31.14.2: Vector Widening Integer Reduction Instructions
  1389  	AVWREDSUMUVS
  1390  	AVWREDSUMVS
  1391  
  1392  	// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
  1393  	AVFREDOSUMVS
  1394  	AVFREDUSUMVS
  1395  	AVFREDMAXVS
  1396  	AVFREDMINVS
  1397  
  1398  	// 31.14.4: Vector Widening Floating-Point Reduction Instructions
  1399  	AVFWREDOSUMVS
  1400  	AVFWREDUSUMVS
  1401  
  1402  	// 31.15: Vector Mask Instructions
  1403  	AVMANDMM
  1404  	AVMNANDMM
  1405  	AVMANDNMM
  1406  	AVMXORMM
  1407  	AVMORMM
  1408  	AVMNORMM
  1409  	AVMORNMM
  1410  	AVMXNORMM
  1411  	AVCPOPM
  1412  	AVFIRSTM
  1413  	AVMSBFM
  1414  	AVMSIFM
  1415  	AVMSOFM
  1416  	AVIOTAM
  1417  	AVIDV
  1418  
  1419  	// 31.16.1: Integer Scalar Move Instructions
  1420  	AVMVXS
  1421  	AVMVSX
  1422  
  1423  	// 31.16.2: Floating-Point Scalar Move Instructions
  1424  	AVFMVFS
  1425  	AVFMVSF
  1426  
  1427  	// 31.16.3: Vector Slide Instructions
  1428  	AVSLIDEUPVX
  1429  	AVSLIDEUPVI
  1430  	AVSLIDEDOWNVX
  1431  	AVSLIDEDOWNVI
  1432  	AVSLIDE1UPVX
  1433  	AVFSLIDE1UPVF
  1434  	AVSLIDE1DOWNVX
  1435  	AVFSLIDE1DOWNVF
  1436  
  1437  	// 31.16.4: Vector Register Gather Instructions
  1438  	AVRGATHERVV
  1439  	AVRGATHEREI16VV
  1440  	AVRGATHERVX
  1441  	AVRGATHERVI
  1442  
  1443  	// 31.16.5: Vector Compress Instruction
  1444  	AVCOMPRESSVM
  1445  
  1446  	// 31.16.6: Whole Vector Register Move
  1447  	AVMV1RV
  1448  	AVMV2RV
  1449  	AVMV4RV
  1450  	AVMV8RV
  1451  
  1452  	//
  1453  	// Privileged ISA (version 20240411)
  1454  	//
  1455  
  1456  	// 3.3.1: Environment Call and Breakpoint
  1457  	AECALL
  1458  	ASCALL
  1459  	AEBREAK
  1460  	ASBREAK
  1461  
  1462  	// 3.3.2: Trap-Return Instructions
  1463  	AMRET
  1464  	ASRET
  1465  	ADRET
  1466  
  1467  	// 3.3.3: Wait for Interrupt
  1468  	AWFI
  1469  
  1470  	// 10.2: Supervisor Memory-Management Fence Instruction
  1471  	ASFENCEVMA
  1472  
  1473  	// The escape hatch. Inserts a single 32-bit word.
  1474  	AWORD
  1475  
  1476  	// Pseudo-instructions.  These get translated by the assembler into other
  1477  	// instructions, based on their operands.
  1478  	ABEQZ
  1479  	ABGEZ
  1480  	ABGT
  1481  	ABGTU
  1482  	ABGTZ
  1483  	ABLE
  1484  	ABLEU
  1485  	ABLEZ
  1486  	ABLTZ
  1487  	ABNEZ
  1488  	AFABSD
  1489  	AFABSS
  1490  	AFNED
  1491  	AFNEGD
  1492  	AFNEGS
  1493  	AFNES
  1494  	AMOV
  1495  	AMOVB
  1496  	AMOVBU
  1497  	AMOVD
  1498  	AMOVF
  1499  	AMOVH
  1500  	AMOVHU
  1501  	AMOVW
  1502  	AMOVWU
  1503  	ANEG
  1504  	ANEGW
  1505  	ANOT
  1506  	ARDCYCLE
  1507  	ARDINSTRET
  1508  	ARDTIME
  1509  	ASEQZ
  1510  	ASNEZ
  1511  	AVFABSV
  1512  	AVFNEGV
  1513  	AVL1RV
  1514  	AVL2RV
  1515  	AVL4RV
  1516  	AVL8RV
  1517  	AVMCLRM
  1518  	AVMFGEVV
  1519  	AVMFGTVV
  1520  	AVMMVM
  1521  	AVMNOTM
  1522  	AVMSETM
  1523  	AVMSGEUVI
  1524  	AVMSGEUVV
  1525  	AVMSGEVI
  1526  	AVMSGEVV
  1527  	AVMSGTUVV
  1528  	AVMSGTVV
  1529  	AVMSLTUVI
  1530  	AVMSLTVI
  1531  	AVNCVTXXW
  1532  	AVNEGV
  1533  	AVNOTV
  1534  	AVWCVTUXXV
  1535  	AVWCVTXXV
  1536  
  1537  	// End marker
  1538  	ALAST
  1539  )
  1540  
  1541  // opSuffix encoding to uint8 which fit into p.Scond
  1542  var rmSuffixSet = map[string]uint8{
  1543  	"RNE": RM_RNE,
  1544  	"RTZ": RM_RTZ,
  1545  	"RDN": RM_RDN,
  1546  	"RUP": RM_RUP,
  1547  	"RMM": RM_RMM,
  1548  }
  1549  
  1550  const rmSuffixBit uint8 = 1 << 7
  1551  
  1552  func rmSuffixEncode(s string) (uint8, error) {
  1553  	if s == "" {
  1554  		return 0, errors.New("empty suffix")
  1555  	}
  1556  	enc, ok := rmSuffixSet[s]
  1557  	if !ok {
  1558  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
  1559  	}
  1560  	return enc | rmSuffixBit, nil
  1561  }
  1562  
  1563  func rmSuffixString(u uint8) (string, error) {
  1564  	if u&rmSuffixBit == 0 {
  1565  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
  1566  	}
  1567  
  1568  	u &^= rmSuffixBit
  1569  	for k, v := range rmSuffixSet {
  1570  		if v == u {
  1571  			return k, nil
  1572  		}
  1573  	}
  1574  	return "", fmt.Errorf("unknown suffix:%x", u)
  1575  }
  1576  
  1577  const (
  1578  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
  1579  	RM_RTZ              // Round towards Zero
  1580  	RM_RDN              // Round Down
  1581  	RM_RUP              // Round Up
  1582  	RM_RMM              // Round to Nearest, ties to Max Magnitude
  1583  )
  1584  
  1585  type SpecialOperand int
  1586  
  1587  const (
  1588  	SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase
  1589  	SPOP_RVV_BEGIN
  1590  
  1591  	// Vector mask policy.
  1592  	SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 2
  1593  	SPOP_MU
  1594  
  1595  	// Vector tail policy.
  1596  	SPOP_TA
  1597  	SPOP_TU
  1598  
  1599  	// Vector register group multiplier (VLMUL).
  1600  	SPOP_M1
  1601  	SPOP_M2
  1602  	SPOP_M4
  1603  	SPOP_M8
  1604  	SPOP_MF2
  1605  	SPOP_MF4
  1606  	SPOP_MF8
  1607  
  1608  	// Vector selected element width (VSEW).
  1609  	SPOP_E8
  1610  	SPOP_E16
  1611  	SPOP_E32
  1612  	SPOP_E64
  1613  	SPOP_RVV_END
  1614  
  1615  	// CSR names.  4096 special operands are reserved for RISC-V CSR names.
  1616  	SPOP_CSR_BEGIN = SPOP_RVV_END
  1617  	SPOP_CSR_END   = SPOP_CSR_BEGIN + 4096
  1618  
  1619  	SPOP_END = SPOP_CSR_END + 1
  1620  )
  1621  
  1622  var specialOperands = map[SpecialOperand]struct {
  1623  	encoding uint32
  1624  	name     string
  1625  }{
  1626  	SPOP_MA: {encoding: 1, name: "MA"},
  1627  	SPOP_MU: {encoding: 0, name: "MU"},
  1628  
  1629  	SPOP_TA: {encoding: 1, name: "TA"},
  1630  	SPOP_TU: {encoding: 0, name: "TU"},
  1631  
  1632  	SPOP_M1:  {encoding: 0, name: "M1"},
  1633  	SPOP_M2:  {encoding: 1, name: "M2"},
  1634  	SPOP_M4:  {encoding: 2, name: "M4"},
  1635  	SPOP_M8:  {encoding: 3, name: "M8"},
  1636  	SPOP_MF8: {encoding: 5, name: "MF8"},
  1637  	SPOP_MF4: {encoding: 6, name: "MF4"},
  1638  	SPOP_MF2: {encoding: 7, name: "MF2"},
  1639  
  1640  	SPOP_E8:  {encoding: 0, name: "E8"},
  1641  	SPOP_E16: {encoding: 1, name: "E16"},
  1642  	SPOP_E32: {encoding: 2, name: "E32"},
  1643  	SPOP_E64: {encoding: 3, name: "E64"},
  1644  }
  1645  
  1646  func (so SpecialOperand) encode() uint32 {
  1647  	switch {
  1648  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1649  		op, ok := specialOperands[so]
  1650  		if ok {
  1651  			return op.encoding
  1652  		}
  1653  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1654  		csrNum := uint16(so - SPOP_CSR_BEGIN)
  1655  		if _, ok := csrs[csrNum]; ok {
  1656  			return uint32(csrNum)
  1657  		}
  1658  	}
  1659  	return 0
  1660  }
  1661  
  1662  // String returns the textual representation of a SpecialOperand.
  1663  func (so SpecialOperand) String() string {
  1664  	switch {
  1665  	case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
  1666  		op, ok := specialOperands[so]
  1667  		if ok {
  1668  			return op.name
  1669  		}
  1670  	case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
  1671  		if csrName, ok := csrs[uint16(so-SPOP_CSR_BEGIN)]; ok {
  1672  			return csrName
  1673  		}
  1674  	}
  1675  	return ""
  1676  }
  1677  
  1678  // All unary instructions which write to their arguments (as opposed to reading
  1679  // from them) go here. The assembly parser uses this information to populate
  1680  // its AST in a semantically reasonable way.
  1681  //
  1682  // Any instructions not listed here are assumed to either be non-unary or to read
  1683  // from its argument.
  1684  var unaryDst = map[obj.As]bool{
  1685  	ARDCYCLE:   true,
  1686  	ARDTIME:    true,
  1687  	ARDINSTRET: true,
  1688  }
  1689  
  1690  // Instruction encoding masks.
  1691  const (
  1692  	// BTypeImmMask is a mask including only the immediate portion of
  1693  	// B-type instructions.
  1694  	BTypeImmMask = 0xfe000f80
  1695  
  1696  	// CBTypeImmMask is a mask including only the immediate portion of
  1697  	// CB-type instructions.
  1698  	CBTypeImmMask = 0x1c7c
  1699  
  1700  	// CJTypeImmMask is a mask including only the immediate portion of
  1701  	// CJ-type instructions.
  1702  	CJTypeImmMask = 0x1f7c
  1703  
  1704  	// ITypeImmMask is a mask including only the immediate portion of
  1705  	// I-type instructions.
  1706  	ITypeImmMask = 0xfff00000
  1707  
  1708  	// JTypeImmMask is a mask including only the immediate portion of
  1709  	// J-type instructions.
  1710  	JTypeImmMask = 0xfffff000
  1711  
  1712  	// STypeImmMask is a mask including only the immediate portion of
  1713  	// S-type instructions.
  1714  	STypeImmMask = 0xfe000f80
  1715  
  1716  	// UTypeImmMask is a mask including only the immediate portion of
  1717  	// U-type instructions.
  1718  	UTypeImmMask = 0xfffff000
  1719  )
  1720  

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