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30 package s390x
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "fmt"
36 "log"
37 "math"
38 "slices"
39 )
40
41
42
43
44 type ctxtz struct {
45 ctxt *obj.Link
46 newprog obj.ProgAlloc
47 cursym *obj.LSym
48 autosize int32
49 instoffset int64
50 pc int64
51 }
52
53
54 const (
55 funcAlign = 16
56 )
57
58 type Optab struct {
59 as obj.As
60 i uint8
61 a1 uint8
62 a2 uint8
63 a3 uint8
64 a4 uint8
65 a5 uint8
66 a6 uint8
67 }
68
69 var optab = []Optab{
70
71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
75 {i: 0, as: obj.ANOP},
76 {i: 0, as: obj.ANOP, a1: C_SAUTO},
77
78
79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
86
87
88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
96
97
98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
118
119
120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
139
140
141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
160
161
162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
163
164
165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
166 {i: 2, as: AADD, a1: C_REG, a6: C_REG},
167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG},
169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG},
178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG},
182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG},
183 {i: 47, as: ANEG, a6: C_REG},
184
185
186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
187 {i: 6, as: AAND, a1: C_REG, a6: C_REG},
188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG},
189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG},
193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG},
197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
201
202
203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
204
205
206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
208 {i: 33, as: AFABS, a6: C_FREG},
209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
226
227
228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
232
233
234 {i: 5, as: ASYSCALL},
235 {i: 77, as: ASYSCALL, a1: C_SCON},
236
237
238 {i: 16, as: ABEQ, a6: C_SBRA},
239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA},
240 {i: 11, as: ABR, a6: C_LBRA},
241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
242 {i: 18, as: ABR, a6: C_REG},
243 {i: 18, as: ABR, a1: C_REG, a6: C_REG},
244 {i: 15, as: ABR, a6: C_ZOREG},
245 {i: 15, as: ABC, a6: C_ZOREG},
246
247
248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA},
254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
258
259
260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA},
261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA},
262
263
264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
265
266
267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG},
268
269
270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
271
272
273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
274
275
276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG},
277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
282
283
284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
285
286
287 {i: 92, as: AIPM, a1: C_REG},
288
289
290 {i: 76, as: ASPM, a1: C_REG},
291
292
293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
297
298
299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
301
302
303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
307
308
309 {i: 40, as: ABYTE, a1: C_SCON},
310 {i: 40, as: AWORD, a1: C_LCON},
311 {i: 31, as: ADWORD, a1: C_LCON},
312 {i: 31, as: ADWORD, a1: C_DCON},
313
314
315 {i: 80, as: ASYNC},
316
317
318 {i: 88, as: ASTCK, a6: C_SAUTO},
319 {i: 88, as: ASTCK, a6: C_SOREG},
320
321
322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
325
326
327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
332
333
334 {i: 78, as: obj.AUNDEF},
335
336
337 {i: 73, as: ABRRK},
338
339
340 {i: 66, as: ANOPH},
341
342
343
344
345 {i: 124, as: AKM, a1: C_REG, a6: C_REG},
346
347
348 {i: 125, as: AKDSA, a1: C_REG, a6: C_REG},
349
350
351 {i: 126, as: AKMA, a1: C_REG, a2: C_REG, a6: C_REG},
352
353
354
355
356 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
357 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
358 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
359 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
360
361
362 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
363 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
364 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
365 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
366
367
368 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
369 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
370
371
372 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
373 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
374
375
376 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
377 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
378 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
379 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
380 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
381 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
382 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
383 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
384
385
386 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
387 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
388
389
390 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
391 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
392
393
394 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
395 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
396
397
398 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
399 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
400
401
402 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
403 {i: 109, as: AVZERO, a6: C_VREG},
404 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
405 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
406 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
407 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
408
409
410 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
411
412
413 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
414
415
416
417 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
418 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
419
420
421 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
422
423
424 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
425
426
427 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
428
429
430 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
431 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
432 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
433
434
435 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
436 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
437 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
438 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
439
440
441 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
442 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
443
444
445 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
446
447
448 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
449
450
451 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
452 }
453
454 var oprange [ALAST & obj.AMask][]Optab
455
456 var xcmp [C_NCLASS][C_NCLASS]bool
457
458 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
459 if ctxt.Retpoline {
460 ctxt.Diag("-spectre=ret not supported on s390x")
461 ctxt.Retpoline = false
462 }
463
464 p := cursym.Func().Text
465 if p == nil || p.Link == nil {
466 return
467 }
468
469 if oprange[AORW&obj.AMask] == nil {
470 ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
471 }
472
473 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
474
475 buffer := make([]byte, 0)
476 changed := true
477 loop := 0
478 nrelocs0 := len(c.cursym.R)
479 for changed {
480 if loop > 100 {
481 c.ctxt.Diag("stuck in spanz loop")
482 break
483 }
484 changed = false
485 buffer = buffer[:0]
486 for i := range c.cursym.R[nrelocs0:] {
487 c.cursym.R[nrelocs0+i] = obj.Reloc{}
488 }
489 c.cursym.R = c.cursym.R[:nrelocs0]
490 for p := c.cursym.Func().Text; p != nil; p = p.Link {
491 pc := int64(len(buffer))
492 if pc != p.Pc {
493 changed = true
494 }
495 p.Pc = pc
496 c.pc = p.Pc
497 c.asmout(p, &buffer)
498 if pc == int64(len(buffer)) {
499 switch p.As {
500 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
501
502 default:
503 c.ctxt.Diag("zero-width instruction\n%v", p)
504 }
505 }
506 }
507 loop++
508 }
509
510 c.cursym.Size = int64(len(buffer))
511 if c.cursym.Size%funcAlign != 0 {
512 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
513 }
514 c.cursym.Grow(c.cursym.Size)
515 copy(c.cursym.P, buffer)
516
517
518
519
520
521 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil)
522 }
523
524
525 func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool {
526 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP {
527 return true
528 }
529 for _, a := range p.RestArgs {
530 if a.Reg == REGTMP {
531 return true
532 }
533 }
534 return p.Mark&USETMP != 0
535 }
536
537 func isint32(v int64) bool {
538 return int64(int32(v)) == v
539 }
540
541 func isuint32(v uint64) bool {
542 return uint64(uint32(v)) == v
543 }
544
545 func (c *ctxtz) aclass(a *obj.Addr) int {
546 switch a.Type {
547 case obj.TYPE_NONE:
548 return C_NONE
549
550 case obj.TYPE_REG:
551 if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
552 return C_REG
553 }
554 if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
555 return C_FREG
556 }
557 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
558 return C_AREG
559 }
560 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
561 return C_VREG
562 }
563 return C_GOK
564
565 case obj.TYPE_MEM:
566 switch a.Name {
567 case obj.NAME_EXTERN,
568 obj.NAME_STATIC:
569 if a.Sym == nil {
570
571 break
572 }
573 c.instoffset = a.Offset
574 if a.Sym.Type == objabi.STLSBSS {
575 if c.ctxt.Flag_shared {
576 return C_TLS_IE
577 }
578 return C_TLS_LE
579 }
580 return C_ADDR
581
582 case obj.NAME_GOTREF:
583 return C_GOTADDR
584
585 case obj.NAME_AUTO:
586 if a.Reg == REGSP {
587
588
589 a.Reg = obj.REG_NONE
590 }
591 c.instoffset = int64(c.autosize) + a.Offset
592 if c.instoffset >= -BIG && c.instoffset < BIG {
593 return C_SAUTO
594 }
595 return C_LAUTO
596
597 case obj.NAME_PARAM:
598 if a.Reg == REGSP {
599
600
601 a.Reg = obj.REG_NONE
602 }
603 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
604 if c.instoffset >= -BIG && c.instoffset < BIG {
605 return C_SAUTO
606 }
607 return C_LAUTO
608
609 case obj.NAME_NONE:
610 c.instoffset = a.Offset
611 if c.instoffset == 0 {
612 return C_ZOREG
613 }
614 if c.instoffset >= -BIG && c.instoffset < BIG {
615 return C_SOREG
616 }
617 return C_LOREG
618 }
619
620 return C_GOK
621
622 case obj.TYPE_TEXTSIZE:
623 return C_TEXTSIZE
624
625 case obj.TYPE_FCONST:
626 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
627 return C_ZCON
628 }
629 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
630
631 case obj.TYPE_CONST,
632 obj.TYPE_ADDR:
633 switch a.Name {
634 case obj.NAME_NONE:
635 c.instoffset = a.Offset
636 if a.Reg != 0 {
637 if -BIG <= c.instoffset && c.instoffset <= BIG {
638 return C_SACON
639 }
640 if isint32(c.instoffset) {
641 return C_LACON
642 }
643 return C_DACON
644 }
645
646 case obj.NAME_EXTERN,
647 obj.NAME_STATIC:
648 s := a.Sym
649 if s == nil {
650 return C_GOK
651 }
652 c.instoffset = a.Offset
653
654 return C_SYMADDR
655
656 case obj.NAME_AUTO:
657 if a.Reg == REGSP {
658
659
660 a.Reg = obj.REG_NONE
661 }
662 c.instoffset = int64(c.autosize) + a.Offset
663 if c.instoffset >= -BIG && c.instoffset < BIG {
664 return C_SACON
665 }
666 return C_LACON
667
668 case obj.NAME_PARAM:
669 if a.Reg == REGSP {
670
671
672 a.Reg = obj.REG_NONE
673 }
674 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
675 if c.instoffset >= -BIG && c.instoffset < BIG {
676 return C_SACON
677 }
678 return C_LACON
679
680 default:
681 return C_GOK
682 }
683
684 if c.instoffset == 0 {
685 return C_ZCON
686 }
687 if c.instoffset >= 0 {
688 if c.instoffset <= 0x7fff {
689 return C_SCON
690 }
691 if c.instoffset <= 0xffff {
692 return C_ANDCON
693 }
694 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) {
695 return C_UCON
696 }
697 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
698 return C_LCON
699 }
700 return C_DCON
701 }
702
703 if c.instoffset >= -0x8000 {
704 return C_ADDCON
705 }
706 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
707 return C_UCON
708 }
709 if isint32(c.instoffset) {
710 return C_LCON
711 }
712 return C_DCON
713
714 case obj.TYPE_BRANCH:
715 return C_SBRA
716 }
717
718 return C_GOK
719 }
720
721 func (c *ctxtz) oplook(p *obj.Prog) *Optab {
722
723 if p.Optab != 0 {
724 return &optab[p.Optab-1]
725 }
726 if len(p.RestArgs) > 3 {
727 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs))
728 return nil
729 }
730
731
732 p.From.Class = int8(c.aclass(&p.From) + 1)
733 p.To.Class = int8(c.aclass(&p.To) + 1)
734 for i := range p.RestArgs {
735 p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1)
736 }
737
738
739 args := [...]int8{
740 p.From.Class - 1,
741 C_NONE,
742 C_NONE,
743 C_NONE,
744 C_NONE,
745 p.To.Class - 1,
746 }
747
748 switch {
749 case REG_R0 <= p.Reg && p.Reg <= REG_R15:
750 args[1] = C_REG
751 case REG_V0 <= p.Reg && p.Reg <= REG_V31:
752 args[1] = C_VREG
753 case REG_F0 <= p.Reg && p.Reg <= REG_F15:
754 args[1] = C_FREG
755 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15:
756 args[1] = C_AREG
757 }
758
759 for i, a := range p.RestArgs {
760 args[2+i] = a.Class - 1
761 }
762
763
764 ops := oprange[p.As&obj.AMask]
765 cmp := [len(args)]*[C_NCLASS]bool{}
766 for i := range cmp {
767 cmp[i] = &xcmp[args[i]]
768 }
769 for i := range ops {
770 op := &ops[i]
771 if cmp[0][op.a1] && cmp[1][op.a2] &&
772 cmp[2][op.a3] && cmp[3][op.a4] &&
773 cmp[4][op.a5] && cmp[5][op.a6] {
774 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
775 return op
776 }
777 }
778
779
780 s := ""
781 for _, a := range args {
782 s += fmt.Sprintf(" %v", DRconv(int(a)))
783 }
784 c.ctxt.Diag("illegal combination %v%v\n", p.As, s)
785 c.ctxt.Diag("prog: %v\n", p)
786 return nil
787 }
788
789 func cmp(a int, b int) bool {
790 if a == b {
791 return true
792 }
793 switch a {
794 case C_DCON:
795 if b == C_LCON {
796 return true
797 }
798 fallthrough
799 case C_LCON:
800 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
801 return true
802 }
803
804 case C_ADDCON:
805 if b == C_ZCON || b == C_SCON {
806 return true
807 }
808
809 case C_ANDCON:
810 if b == C_ZCON || b == C_SCON {
811 return true
812 }
813
814 case C_UCON:
815 if b == C_ZCON || b == C_SCON {
816 return true
817 }
818
819 case C_SCON:
820 if b == C_ZCON {
821 return true
822 }
823
824 case C_LACON:
825 if b == C_SACON {
826 return true
827 }
828
829 case C_LBRA:
830 if b == C_SBRA {
831 return true
832 }
833
834 case C_LAUTO:
835 if b == C_SAUTO {
836 return true
837 }
838
839 case C_LOREG:
840 if b == C_ZOREG || b == C_SOREG {
841 return true
842 }
843
844 case C_SOREG:
845 if b == C_ZOREG {
846 return true
847 }
848
849 case C_ANY:
850 return true
851 }
852
853 return false
854 }
855
856 func ocmp(p1, p2 Optab) int {
857 if p1.as != p2.as {
858 return int(p1.as) - int(p2.as)
859 }
860 if p1.a1 != p2.a1 {
861 return int(p1.a1) - int(p2.a1)
862 }
863 if p1.a2 != p2.a2 {
864 return int(p1.a2) - int(p2.a2)
865 }
866 if p1.a3 != p2.a3 {
867 return int(p1.a3) - int(p2.a3)
868 }
869 if p1.a4 != p2.a4 {
870 return int(p1.a4) - int(p2.a4)
871 }
872 return 0
873 }
874 func opset(a, b obj.As) {
875 oprange[a&obj.AMask] = oprange[b&obj.AMask]
876 }
877
878 func buildop(ctxt *obj.Link) {
879 if oprange[AORW&obj.AMask] != nil {
880
881
882
883 return
884 }
885
886 for i := 0; i < C_NCLASS; i++ {
887 for n := 0; n < C_NCLASS; n++ {
888 if cmp(n, i) {
889 xcmp[i][n] = true
890 }
891 }
892 }
893 slices.SortFunc(optab, ocmp)
894 for i := 0; i < len(optab); i++ {
895 r := optab[i].as
896 start := i
897 for ; i+1 < len(optab); i++ {
898 if optab[i+1].as != r {
899 break
900 }
901 }
902 oprange[r&obj.AMask] = optab[start : i+1]
903
904
905
906 switch r {
907 case AADD:
908 opset(AADDC, r)
909 opset(AADDW, r)
910 opset(AADDE, r)
911 opset(AMULLD, r)
912 opset(AMULLW, r)
913 case ADIVW:
914 opset(ADIVD, r)
915 opset(ADIVDU, r)
916 opset(ADIVWU, r)
917 opset(AMODD, r)
918 opset(AMODDU, r)
919 opset(AMODW, r)
920 opset(AMODWU, r)
921 case AMULHD:
922 opset(AMULHDU, r)
923 case AMOVBZ:
924 opset(AMOVH, r)
925 opset(AMOVHZ, r)
926 case ALA:
927 opset(ALAY, r)
928 case AMVC:
929 opset(AMVCIN, r)
930 opset(ACLC, r)
931 opset(AXC, r)
932 opset(AOC, r)
933 opset(ANC, r)
934 case ASTCK:
935 opset(ASTCKC, r)
936 opset(ASTCKE, r)
937 opset(ASTCKF, r)
938 case ALAAG:
939 opset(ALAA, r)
940 opset(ALAAL, r)
941 opset(ALAALG, r)
942 opset(ALAN, r)
943 opset(ALANG, r)
944 opset(ALAX, r)
945 opset(ALAXG, r)
946 opset(ALAO, r)
947 opset(ALAOG, r)
948 case ASTMG:
949 opset(ASTMY, r)
950 case ALMG:
951 opset(ALMY, r)
952 case ABEQ:
953 opset(ABGE, r)
954 opset(ABGT, r)
955 opset(ABLE, r)
956 opset(ABLT, r)
957 opset(ABNE, r)
958 opset(ABVC, r)
959 opset(ABVS, r)
960 opset(ABLEU, r)
961 opset(ABLTU, r)
962 case ABR:
963 opset(ABL, r)
964 case ABC:
965 opset(ABCL, r)
966 case AFABS:
967 opset(AFNABS, r)
968 opset(ALPDFR, r)
969 opset(ALNDFR, r)
970 opset(AFNEG, r)
971 opset(AFNEGS, r)
972 opset(ALEDBR, r)
973 opset(ALDEBR, r)
974 opset(AFSQRT, r)
975 opset(AFSQRTS, r)
976 case AFADD:
977 opset(AFADDS, r)
978 opset(AFDIV, r)
979 opset(AFDIVS, r)
980 opset(AFSUB, r)
981 opset(AFSUBS, r)
982 case AFMADD:
983 opset(AFMADDS, r)
984 opset(AFMSUB, r)
985 opset(AFMSUBS, r)
986 case AFMUL:
987 opset(AFMULS, r)
988 case AFCMPO:
989 opset(AFCMPU, r)
990 opset(ACEBR, r)
991 case AAND:
992 opset(AOR, r)
993 opset(AXOR, r)
994 case AANDW:
995 opset(AORW, r)
996 opset(AXORW, r)
997 case ASLD:
998 opset(ASRD, r)
999 opset(ASLW, r)
1000 opset(ASRW, r)
1001 opset(ASRAD, r)
1002 opset(ASRAW, r)
1003 opset(ARLL, r)
1004 opset(ARLLG, r)
1005 case ARNSBG:
1006 opset(ARXSBG, r)
1007 opset(AROSBG, r)
1008 opset(ARNSBGT, r)
1009 opset(ARXSBGT, r)
1010 opset(AROSBGT, r)
1011 opset(ARISBG, r)
1012 opset(ARISBGN, r)
1013 opset(ARISBGZ, r)
1014 opset(ARISBGNZ, r)
1015 opset(ARISBHG, r)
1016 opset(ARISBLG, r)
1017 opset(ARISBHGZ, r)
1018 opset(ARISBLGZ, r)
1019 case ACSG:
1020 opset(ACS, r)
1021 case ASUB:
1022 opset(ASUBC, r)
1023 opset(ASUBE, r)
1024 opset(ASUBW, r)
1025 case ANEG:
1026 opset(ANEGW, r)
1027 case AFMOVD:
1028 opset(AFMOVS, r)
1029 case AMOVDBR:
1030 opset(AMOVWBR, r)
1031 case ACMP:
1032 opset(ACMPW, r)
1033 case ACMPU:
1034 opset(ACMPWU, r)
1035 case ATMHH:
1036 opset(ATMHL, r)
1037 opset(ATMLH, r)
1038 opset(ATMLL, r)
1039 case ACEFBRA:
1040 opset(ACDFBRA, r)
1041 opset(ACEGBRA, r)
1042 opset(ACDGBRA, r)
1043 opset(ACELFBR, r)
1044 opset(ACDLFBR, r)
1045 opset(ACELGBR, r)
1046 opset(ACDLGBR, r)
1047 case ACFEBRA:
1048 opset(ACFDBRA, r)
1049 opset(ACGEBRA, r)
1050 opset(ACGDBRA, r)
1051 opset(ACLFEBR, r)
1052 opset(ACLFDBR, r)
1053 opset(ACLGEBR, r)
1054 opset(ACLGDBR, r)
1055 case AFIEBR:
1056 opset(AFIDBR, r)
1057 case ACMPBEQ:
1058 opset(ACMPBGE, r)
1059 opset(ACMPBGT, r)
1060 opset(ACMPBLE, r)
1061 opset(ACMPBLT, r)
1062 opset(ACMPBNE, r)
1063 case ACMPUBEQ:
1064 opset(ACMPUBGE, r)
1065 opset(ACMPUBGT, r)
1066 opset(ACMPUBLE, r)
1067 opset(ACMPUBLT, r)
1068 opset(ACMPUBNE, r)
1069 case ACGRJ:
1070 opset(ACRJ, r)
1071 case ACLGRJ:
1072 opset(ACLRJ, r)
1073 case ACGIJ:
1074 opset(ACIJ, r)
1075 case ACLGIJ:
1076 opset(ACLIJ, r)
1077 case AMOVDEQ:
1078 opset(AMOVDGE, r)
1079 opset(AMOVDGT, r)
1080 opset(AMOVDLE, r)
1081 opset(AMOVDLT, r)
1082 opset(AMOVDNE, r)
1083 case ALOCGR:
1084 opset(ALOCR, r)
1085 case ALTDBR:
1086 opset(ALTEBR, r)
1087 case ATCDB:
1088 opset(ATCEB, r)
1089 case AVL:
1090 opset(AVLLEZB, r)
1091 opset(AVLLEZH, r)
1092 opset(AVLLEZF, r)
1093 opset(AVLLEZG, r)
1094 opset(AVLREPB, r)
1095 opset(AVLREPH, r)
1096 opset(AVLREPF, r)
1097 opset(AVLREPG, r)
1098 case AVLEG:
1099 opset(AVLBB, r)
1100 opset(AVLEB, r)
1101 opset(AVLEH, r)
1102 opset(AVLEF, r)
1103 opset(AVLEG, r)
1104 opset(AVLREP, r)
1105 case AVSTEG:
1106 opset(AVSTEB, r)
1107 opset(AVSTEH, r)
1108 opset(AVSTEF, r)
1109 case AVSCEG:
1110 opset(AVSCEF, r)
1111 case AVGEG:
1112 opset(AVGEF, r)
1113 case AVESLG:
1114 opset(AVESLB, r)
1115 opset(AVESLH, r)
1116 opset(AVESLF, r)
1117 opset(AVERLLB, r)
1118 opset(AVERLLH, r)
1119 opset(AVERLLF, r)
1120 opset(AVERLLG, r)
1121 opset(AVESRAB, r)
1122 opset(AVESRAH, r)
1123 opset(AVESRAF, r)
1124 opset(AVESRAG, r)
1125 opset(AVESRLB, r)
1126 opset(AVESRLH, r)
1127 opset(AVESRLF, r)
1128 opset(AVESRLG, r)
1129 case AVLGVG:
1130 opset(AVLGVB, r)
1131 opset(AVLGVH, r)
1132 opset(AVLGVF, r)
1133 case AVLVGG:
1134 opset(AVLVGB, r)
1135 opset(AVLVGH, r)
1136 opset(AVLVGF, r)
1137 case AVZERO:
1138 opset(AVONE, r)
1139 case AVREPIG:
1140 opset(AVREPIB, r)
1141 opset(AVREPIH, r)
1142 opset(AVREPIF, r)
1143 case AVLEIG:
1144 opset(AVLEIB, r)
1145 opset(AVLEIH, r)
1146 opset(AVLEIF, r)
1147 case AVGMG:
1148 opset(AVGMB, r)
1149 opset(AVGMH, r)
1150 opset(AVGMF, r)
1151 case AVREPG:
1152 opset(AVREPB, r)
1153 opset(AVREPH, r)
1154 opset(AVREPF, r)
1155 case AVERIMG:
1156 opset(AVERIMB, r)
1157 opset(AVERIMH, r)
1158 opset(AVERIMF, r)
1159 case AVFTCIDB:
1160 opset(AWFTCIDB, r)
1161 case AVLR:
1162 opset(AVUPHB, r)
1163 opset(AVUPHH, r)
1164 opset(AVUPHF, r)
1165 opset(AVUPLHB, r)
1166 opset(AVUPLHH, r)
1167 opset(AVUPLHF, r)
1168 opset(AVUPLB, r)
1169 opset(AVUPLHW, r)
1170 opset(AVUPLF, r)
1171 opset(AVUPLLB, r)
1172 opset(AVUPLLH, r)
1173 opset(AVUPLLF, r)
1174 opset(AVCLZB, r)
1175 opset(AVCLZH, r)
1176 opset(AVCLZF, r)
1177 opset(AVCLZG, r)
1178 opset(AVCTZB, r)
1179 opset(AVCTZH, r)
1180 opset(AVCTZF, r)
1181 opset(AVCTZG, r)
1182 opset(AVLDEB, r)
1183 opset(AWLDEB, r)
1184 opset(AVFLCDB, r)
1185 opset(AWFLCDB, r)
1186 opset(AVFLNDB, r)
1187 opset(AWFLNDB, r)
1188 opset(AVFLPDB, r)
1189 opset(AWFLPDB, r)
1190 opset(AVFSQDB, r)
1191 opset(AWFSQDB, r)
1192 opset(AVISTRB, r)
1193 opset(AVISTRH, r)
1194 opset(AVISTRF, r)
1195 opset(AVISTRBS, r)
1196 opset(AVISTRHS, r)
1197 opset(AVISTRFS, r)
1198 opset(AVLCB, r)
1199 opset(AVLCH, r)
1200 opset(AVLCF, r)
1201 opset(AVLCG, r)
1202 opset(AVLPB, r)
1203 opset(AVLPH, r)
1204 opset(AVLPF, r)
1205 opset(AVLPG, r)
1206 opset(AVPOPCT, r)
1207 opset(AVSEGB, r)
1208 opset(AVSEGH, r)
1209 opset(AVSEGF, r)
1210 case AVECG:
1211 opset(AVECB, r)
1212 opset(AVECH, r)
1213 opset(AVECF, r)
1214 opset(AVECLB, r)
1215 opset(AVECLH, r)
1216 opset(AVECLF, r)
1217 opset(AVECLG, r)
1218 opset(AWFCDB, r)
1219 opset(AWFKDB, r)
1220 case AVCEQG:
1221 opset(AVCEQB, r)
1222 opset(AVCEQH, r)
1223 opset(AVCEQF, r)
1224 opset(AVCEQBS, r)
1225 opset(AVCEQHS, r)
1226 opset(AVCEQFS, r)
1227 opset(AVCEQGS, r)
1228 opset(AVCHB, r)
1229 opset(AVCHH, r)
1230 opset(AVCHF, r)
1231 opset(AVCHG, r)
1232 opset(AVCHBS, r)
1233 opset(AVCHHS, r)
1234 opset(AVCHFS, r)
1235 opset(AVCHGS, r)
1236 opset(AVCHLB, r)
1237 opset(AVCHLH, r)
1238 opset(AVCHLF, r)
1239 opset(AVCHLG, r)
1240 opset(AVCHLBS, r)
1241 opset(AVCHLHS, r)
1242 opset(AVCHLFS, r)
1243 opset(AVCHLGS, r)
1244 case AVFAEF:
1245 opset(AVFAEB, r)
1246 opset(AVFAEH, r)
1247 opset(AVFAEBS, r)
1248 opset(AVFAEHS, r)
1249 opset(AVFAEFS, r)
1250 opset(AVFAEZB, r)
1251 opset(AVFAEZH, r)
1252 opset(AVFAEZF, r)
1253 opset(AVFAEZBS, r)
1254 opset(AVFAEZHS, r)
1255 opset(AVFAEZFS, r)
1256 opset(AVFEEB, r)
1257 opset(AVFEEH, r)
1258 opset(AVFEEF, r)
1259 opset(AVFEEBS, r)
1260 opset(AVFEEHS, r)
1261 opset(AVFEEFS, r)
1262 opset(AVFEEZB, r)
1263 opset(AVFEEZH, r)
1264 opset(AVFEEZF, r)
1265 opset(AVFEEZBS, r)
1266 opset(AVFEEZHS, r)
1267 opset(AVFEEZFS, r)
1268 opset(AVFENEB, r)
1269 opset(AVFENEH, r)
1270 opset(AVFENEF, r)
1271 opset(AVFENEBS, r)
1272 opset(AVFENEHS, r)
1273 opset(AVFENEFS, r)
1274 opset(AVFENEZB, r)
1275 opset(AVFENEZH, r)
1276 opset(AVFENEZF, r)
1277 opset(AVFENEZBS, r)
1278 opset(AVFENEZHS, r)
1279 opset(AVFENEZFS, r)
1280 case AVPKSG:
1281 opset(AVPKSH, r)
1282 opset(AVPKSF, r)
1283 opset(AVPKSHS, r)
1284 opset(AVPKSFS, r)
1285 opset(AVPKSGS, r)
1286 opset(AVPKLSH, r)
1287 opset(AVPKLSF, r)
1288 opset(AVPKLSG, r)
1289 opset(AVPKLSHS, r)
1290 opset(AVPKLSFS, r)
1291 opset(AVPKLSGS, r)
1292 case AVAQ:
1293 opset(AVAB, r)
1294 opset(AVAH, r)
1295 opset(AVAF, r)
1296 opset(AVAG, r)
1297 opset(AVACCB, r)
1298 opset(AVACCH, r)
1299 opset(AVACCF, r)
1300 opset(AVACCG, r)
1301 opset(AVACCQ, r)
1302 opset(AVN, r)
1303 opset(AVNC, r)
1304 opset(AVAVGB, r)
1305 opset(AVAVGH, r)
1306 opset(AVAVGF, r)
1307 opset(AVAVGG, r)
1308 opset(AVAVGLB, r)
1309 opset(AVAVGLH, r)
1310 opset(AVAVGLF, r)
1311 opset(AVAVGLG, r)
1312 opset(AVCKSM, r)
1313 opset(AVX, r)
1314 opset(AVFADB, r)
1315 opset(AWFADB, r)
1316 opset(AVFCEDB, r)
1317 opset(AVFCEDBS, r)
1318 opset(AWFCEDB, r)
1319 opset(AWFCEDBS, r)
1320 opset(AVFCHDB, r)
1321 opset(AVFCHDBS, r)
1322 opset(AWFCHDB, r)
1323 opset(AWFCHDBS, r)
1324 opset(AVFCHEDB, r)
1325 opset(AVFCHEDBS, r)
1326 opset(AWFCHEDB, r)
1327 opset(AWFCHEDBS, r)
1328 opset(AVFMDB, r)
1329 opset(AWFMDB, r)
1330 opset(AVGFMB, r)
1331 opset(AVGFMH, r)
1332 opset(AVGFMF, r)
1333 opset(AVGFMG, r)
1334 opset(AVMXB, r)
1335 opset(AVMXH, r)
1336 opset(AVMXF, r)
1337 opset(AVMXG, r)
1338 opset(AVMXLB, r)
1339 opset(AVMXLH, r)
1340 opset(AVMXLF, r)
1341 opset(AVMXLG, r)
1342 opset(AVMNB, r)
1343 opset(AVMNH, r)
1344 opset(AVMNF, r)
1345 opset(AVMNG, r)
1346 opset(AVMNLB, r)
1347 opset(AVMNLH, r)
1348 opset(AVMNLF, r)
1349 opset(AVMNLG, r)
1350 opset(AVMRHB, r)
1351 opset(AVMRHH, r)
1352 opset(AVMRHF, r)
1353 opset(AVMRHG, r)
1354 opset(AVMRLB, r)
1355 opset(AVMRLH, r)
1356 opset(AVMRLF, r)
1357 opset(AVMRLG, r)
1358 opset(AVMEB, r)
1359 opset(AVMEH, r)
1360 opset(AVMEF, r)
1361 opset(AVMLEB, r)
1362 opset(AVMLEH, r)
1363 opset(AVMLEF, r)
1364 opset(AVMOB, r)
1365 opset(AVMOH, r)
1366 opset(AVMOF, r)
1367 opset(AVMLOB, r)
1368 opset(AVMLOH, r)
1369 opset(AVMLOF, r)
1370 opset(AVMHB, r)
1371 opset(AVMHH, r)
1372 opset(AVMHF, r)
1373 opset(AVMLHB, r)
1374 opset(AVMLHH, r)
1375 opset(AVMLHF, r)
1376 opset(AVMLH, r)
1377 opset(AVMLHW, r)
1378 opset(AVMLF, r)
1379 opset(AVNO, r)
1380 opset(AVO, r)
1381 opset(AVPKH, r)
1382 opset(AVPKF, r)
1383 opset(AVPKG, r)
1384 opset(AVSUMGH, r)
1385 opset(AVSUMGF, r)
1386 opset(AVSUMQF, r)
1387 opset(AVSUMQG, r)
1388 opset(AVSUMB, r)
1389 opset(AVSUMH, r)
1390 case AVERLLVG:
1391 opset(AVERLLVB, r)
1392 opset(AVERLLVH, r)
1393 opset(AVERLLVF, r)
1394 opset(AVESLVB, r)
1395 opset(AVESLVH, r)
1396 opset(AVESLVF, r)
1397 opset(AVESLVG, r)
1398 opset(AVESRAVB, r)
1399 opset(AVESRAVH, r)
1400 opset(AVESRAVF, r)
1401 opset(AVESRAVG, r)
1402 opset(AVESRLVB, r)
1403 opset(AVESRLVH, r)
1404 opset(AVESRLVF, r)
1405 opset(AVESRLVG, r)
1406 opset(AVFDDB, r)
1407 opset(AWFDDB, r)
1408 opset(AVFSDB, r)
1409 opset(AWFSDB, r)
1410 opset(AVSL, r)
1411 opset(AVSLB, r)
1412 opset(AVSRA, r)
1413 opset(AVSRAB, r)
1414 opset(AVSRL, r)
1415 opset(AVSRLB, r)
1416 opset(AVSB, r)
1417 opset(AVSH, r)
1418 opset(AVSF, r)
1419 opset(AVSG, r)
1420 opset(AVSQ, r)
1421 opset(AVSCBIB, r)
1422 opset(AVSCBIH, r)
1423 opset(AVSCBIF, r)
1424 opset(AVSCBIG, r)
1425 opset(AVSCBIQ, r)
1426 case AVACQ:
1427 opset(AVACCCQ, r)
1428 opset(AVGFMAB, r)
1429 opset(AVGFMAH, r)
1430 opset(AVGFMAF, r)
1431 opset(AVGFMAG, r)
1432 opset(AVMALB, r)
1433 opset(AVMALHW, r)
1434 opset(AVMALF, r)
1435 opset(AVMAHB, r)
1436 opset(AVMAHH, r)
1437 opset(AVMAHF, r)
1438 opset(AVMALHB, r)
1439 opset(AVMALHH, r)
1440 opset(AVMALHF, r)
1441 opset(AVMAEB, r)
1442 opset(AVMAEH, r)
1443 opset(AVMAEF, r)
1444 opset(AVMALEB, r)
1445 opset(AVMALEH, r)
1446 opset(AVMALEF, r)
1447 opset(AVMAOB, r)
1448 opset(AVMAOH, r)
1449 opset(AVMAOF, r)
1450 opset(AVMALOB, r)
1451 opset(AVMALOH, r)
1452 opset(AVMALOF, r)
1453 opset(AVSTRC, r)
1454 opset(AVSTRCB, r)
1455 opset(AVSTRCH, r)
1456 opset(AVSTRCF, r)
1457 opset(AVSTRCBS, r)
1458 opset(AVSTRCHS, r)
1459 opset(AVSTRCFS, r)
1460 opset(AVSTRCZB, r)
1461 opset(AVSTRCZH, r)
1462 opset(AVSTRCZF, r)
1463 opset(AVSTRCZBS, r)
1464 opset(AVSTRCZHS, r)
1465 opset(AVSTRCZFS, r)
1466 opset(AVSBCBIQ, r)
1467 opset(AVSBIQ, r)
1468 opset(AVMSLG, r)
1469 opset(AVMSLEG, r)
1470 opset(AVMSLOG, r)
1471 opset(AVMSLEOG, r)
1472 case AVSEL:
1473 opset(AVFMADB, r)
1474 opset(AWFMADB, r)
1475 opset(AVFMSDB, r)
1476 opset(AWFMSDB, r)
1477 opset(AVPERM, r)
1478 case AKM:
1479 opset(AKMC, r)
1480 opset(AKLMD, r)
1481 opset(AKIMD, r)
1482 case AKMA:
1483 opset(AKMCTR, r)
1484 }
1485 }
1486 }
1487
1488 const (
1489 op_A uint32 = 0x5A00
1490 op_AD uint32 = 0x6A00
1491 op_ADB uint32 = 0xED1A
1492 op_ADBR uint32 = 0xB31A
1493 op_ADR uint32 = 0x2A00
1494 op_ADTR uint32 = 0xB3D2
1495 op_ADTRA uint32 = 0xB3D2
1496 op_AE uint32 = 0x7A00
1497 op_AEB uint32 = 0xED0A
1498 op_AEBR uint32 = 0xB30A
1499 op_AER uint32 = 0x3A00
1500 op_AFI uint32 = 0xC209
1501 op_AG uint32 = 0xE308
1502 op_AGF uint32 = 0xE318
1503 op_AGFI uint32 = 0xC208
1504 op_AGFR uint32 = 0xB918
1505 op_AGHI uint32 = 0xA70B
1506 op_AGHIK uint32 = 0xECD9
1507 op_AGR uint32 = 0xB908
1508 op_AGRK uint32 = 0xB9E8
1509 op_AGSI uint32 = 0xEB7A
1510 op_AH uint32 = 0x4A00
1511 op_AHHHR uint32 = 0xB9C8
1512 op_AHHLR uint32 = 0xB9D8
1513 op_AHI uint32 = 0xA70A
1514 op_AHIK uint32 = 0xECD8
1515 op_AHY uint32 = 0xE37A
1516 op_AIH uint32 = 0xCC08
1517 op_AL uint32 = 0x5E00
1518 op_ALC uint32 = 0xE398
1519 op_ALCG uint32 = 0xE388
1520 op_ALCGR uint32 = 0xB988
1521 op_ALCR uint32 = 0xB998
1522 op_ALFI uint32 = 0xC20B
1523 op_ALG uint32 = 0xE30A
1524 op_ALGF uint32 = 0xE31A
1525 op_ALGFI uint32 = 0xC20A
1526 op_ALGFR uint32 = 0xB91A
1527 op_ALGHSIK uint32 = 0xECDB
1528 op_ALGR uint32 = 0xB90A
1529 op_ALGRK uint32 = 0xB9EA
1530 op_ALGSI uint32 = 0xEB7E
1531 op_ALHHHR uint32 = 0xB9CA
1532 op_ALHHLR uint32 = 0xB9DA
1533 op_ALHSIK uint32 = 0xECDA
1534 op_ALR uint32 = 0x1E00
1535 op_ALRK uint32 = 0xB9FA
1536 op_ALSI uint32 = 0xEB6E
1537 op_ALSIH uint32 = 0xCC0A
1538 op_ALSIHN uint32 = 0xCC0B
1539 op_ALY uint32 = 0xE35E
1540 op_AP uint32 = 0xFA00
1541 op_AR uint32 = 0x1A00
1542 op_ARK uint32 = 0xB9F8
1543 op_ASI uint32 = 0xEB6A
1544 op_AU uint32 = 0x7E00
1545 op_AUR uint32 = 0x3E00
1546 op_AW uint32 = 0x6E00
1547 op_AWR uint32 = 0x2E00
1548 op_AXBR uint32 = 0xB34A
1549 op_AXR uint32 = 0x3600
1550 op_AXTR uint32 = 0xB3DA
1551 op_AXTRA uint32 = 0xB3DA
1552 op_AY uint32 = 0xE35A
1553 op_BAKR uint32 = 0xB240
1554 op_BAL uint32 = 0x4500
1555 op_BALR uint32 = 0x0500
1556 op_BAS uint32 = 0x4D00
1557 op_BASR uint32 = 0x0D00
1558 op_BASSM uint32 = 0x0C00
1559 op_BC uint32 = 0x4700
1560 op_BCR uint32 = 0x0700
1561 op_BCT uint32 = 0x4600
1562 op_BCTG uint32 = 0xE346
1563 op_BCTGR uint32 = 0xB946
1564 op_BCTR uint32 = 0x0600
1565 op_BPP uint32 = 0xC700
1566 op_BPRP uint32 = 0xC500
1567 op_BRAS uint32 = 0xA705
1568 op_BRASL uint32 = 0xC005
1569 op_BRC uint32 = 0xA704
1570 op_BRCL uint32 = 0xC004
1571 op_BRCT uint32 = 0xA706
1572 op_BRCTG uint32 = 0xA707
1573 op_BRCTH uint32 = 0xCC06
1574 op_BRXH uint32 = 0x8400
1575 op_BRXHG uint32 = 0xEC44
1576 op_BRXLE uint32 = 0x8500
1577 op_BRXLG uint32 = 0xEC45
1578 op_BSA uint32 = 0xB25A
1579 op_BSG uint32 = 0xB258
1580 op_BSM uint32 = 0x0B00
1581 op_BXH uint32 = 0x8600
1582 op_BXHG uint32 = 0xEB44
1583 op_BXLE uint32 = 0x8700
1584 op_BXLEG uint32 = 0xEB45
1585 op_C uint32 = 0x5900
1586 op_CD uint32 = 0x6900
1587 op_CDB uint32 = 0xED19
1588 op_CDBR uint32 = 0xB319
1589 op_CDFBR uint32 = 0xB395
1590 op_CDFBRA uint32 = 0xB395
1591 op_CDFR uint32 = 0xB3B5
1592 op_CDFTR uint32 = 0xB951
1593 op_CDGBR uint32 = 0xB3A5
1594 op_CDGBRA uint32 = 0xB3A5
1595 op_CDGR uint32 = 0xB3C5
1596 op_CDGTR uint32 = 0xB3F1
1597 op_CDGTRA uint32 = 0xB3F1
1598 op_CDLFBR uint32 = 0xB391
1599 op_CDLFTR uint32 = 0xB953
1600 op_CDLGBR uint32 = 0xB3A1
1601 op_CDLGTR uint32 = 0xB952
1602 op_CDR uint32 = 0x2900
1603 op_CDS uint32 = 0xBB00
1604 op_CDSG uint32 = 0xEB3E
1605 op_CDSTR uint32 = 0xB3F3
1606 op_CDSY uint32 = 0xEB31
1607 op_CDTR uint32 = 0xB3E4
1608 op_CDUTR uint32 = 0xB3F2
1609 op_CDZT uint32 = 0xEDAA
1610 op_CE uint32 = 0x7900
1611 op_CEB uint32 = 0xED09
1612 op_CEBR uint32 = 0xB309
1613 op_CEDTR uint32 = 0xB3F4
1614 op_CEFBR uint32 = 0xB394
1615 op_CEFBRA uint32 = 0xB394
1616 op_CEFR uint32 = 0xB3B4
1617 op_CEGBR uint32 = 0xB3A4
1618 op_CEGBRA uint32 = 0xB3A4
1619 op_CEGR uint32 = 0xB3C4
1620 op_CELFBR uint32 = 0xB390
1621 op_CELGBR uint32 = 0xB3A0
1622 op_CER uint32 = 0x3900
1623 op_CEXTR uint32 = 0xB3FC
1624 op_CFC uint32 = 0xB21A
1625 op_CFDBR uint32 = 0xB399
1626 op_CFDBRA uint32 = 0xB399
1627 op_CFDR uint32 = 0xB3B9
1628 op_CFDTR uint32 = 0xB941
1629 op_CFEBR uint32 = 0xB398
1630 op_CFEBRA uint32 = 0xB398
1631 op_CFER uint32 = 0xB3B8
1632 op_CFI uint32 = 0xC20D
1633 op_CFXBR uint32 = 0xB39A
1634 op_CFXBRA uint32 = 0xB39A
1635 op_CFXR uint32 = 0xB3BA
1636 op_CFXTR uint32 = 0xB949
1637 op_CG uint32 = 0xE320
1638 op_CGDBR uint32 = 0xB3A9
1639 op_CGDBRA uint32 = 0xB3A9
1640 op_CGDR uint32 = 0xB3C9
1641 op_CGDTR uint32 = 0xB3E1
1642 op_CGDTRA uint32 = 0xB3E1
1643 op_CGEBR uint32 = 0xB3A8
1644 op_CGEBRA uint32 = 0xB3A8
1645 op_CGER uint32 = 0xB3C8
1646 op_CGF uint32 = 0xE330
1647 op_CGFI uint32 = 0xC20C
1648 op_CGFR uint32 = 0xB930
1649 op_CGFRL uint32 = 0xC60C
1650 op_CGH uint32 = 0xE334
1651 op_CGHI uint32 = 0xA70F
1652 op_CGHRL uint32 = 0xC604
1653 op_CGHSI uint32 = 0xE558
1654 op_CGIB uint32 = 0xECFC
1655 op_CGIJ uint32 = 0xEC7C
1656 op_CGIT uint32 = 0xEC70
1657 op_CGR uint32 = 0xB920
1658 op_CGRB uint32 = 0xECE4
1659 op_CGRJ uint32 = 0xEC64
1660 op_CGRL uint32 = 0xC608
1661 op_CGRT uint32 = 0xB960
1662 op_CGXBR uint32 = 0xB3AA
1663 op_CGXBRA uint32 = 0xB3AA
1664 op_CGXR uint32 = 0xB3CA
1665 op_CGXTR uint32 = 0xB3E9
1666 op_CGXTRA uint32 = 0xB3E9
1667 op_CH uint32 = 0x4900
1668 op_CHF uint32 = 0xE3CD
1669 op_CHHR uint32 = 0xB9CD
1670 op_CHHSI uint32 = 0xE554
1671 op_CHI uint32 = 0xA70E
1672 op_CHLR uint32 = 0xB9DD
1673 op_CHRL uint32 = 0xC605
1674 op_CHSI uint32 = 0xE55C
1675 op_CHY uint32 = 0xE379
1676 op_CIB uint32 = 0xECFE
1677 op_CIH uint32 = 0xCC0D
1678 op_CIJ uint32 = 0xEC7E
1679 op_CIT uint32 = 0xEC72
1680 op_CKSM uint32 = 0xB241
1681 op_CL uint32 = 0x5500
1682 op_CLC uint32 = 0xD500
1683 op_CLCL uint32 = 0x0F00
1684 op_CLCLE uint32 = 0xA900
1685 op_CLCLU uint32 = 0xEB8F
1686 op_CLFDBR uint32 = 0xB39D
1687 op_CLFDTR uint32 = 0xB943
1688 op_CLFEBR uint32 = 0xB39C
1689 op_CLFHSI uint32 = 0xE55D
1690 op_CLFI uint32 = 0xC20F
1691 op_CLFIT uint32 = 0xEC73
1692 op_CLFXBR uint32 = 0xB39E
1693 op_CLFXTR uint32 = 0xB94B
1694 op_CLG uint32 = 0xE321
1695 op_CLGDBR uint32 = 0xB3AD
1696 op_CLGDTR uint32 = 0xB942
1697 op_CLGEBR uint32 = 0xB3AC
1698 op_CLGF uint32 = 0xE331
1699 op_CLGFI uint32 = 0xC20E
1700 op_CLGFR uint32 = 0xB931
1701 op_CLGFRL uint32 = 0xC60E
1702 op_CLGHRL uint32 = 0xC606
1703 op_CLGHSI uint32 = 0xE559
1704 op_CLGIB uint32 = 0xECFD
1705 op_CLGIJ uint32 = 0xEC7D
1706 op_CLGIT uint32 = 0xEC71
1707 op_CLGR uint32 = 0xB921
1708 op_CLGRB uint32 = 0xECE5
1709 op_CLGRJ uint32 = 0xEC65
1710 op_CLGRL uint32 = 0xC60A
1711 op_CLGRT uint32 = 0xB961
1712 op_CLGT uint32 = 0xEB2B
1713 op_CLGXBR uint32 = 0xB3AE
1714 op_CLGXTR uint32 = 0xB94A
1715 op_CLHF uint32 = 0xE3CF
1716 op_CLHHR uint32 = 0xB9CF
1717 op_CLHHSI uint32 = 0xE555
1718 op_CLHLR uint32 = 0xB9DF
1719 op_CLHRL uint32 = 0xC607
1720 op_CLI uint32 = 0x9500
1721 op_CLIB uint32 = 0xECFF
1722 op_CLIH uint32 = 0xCC0F
1723 op_CLIJ uint32 = 0xEC7F
1724 op_CLIY uint32 = 0xEB55
1725 op_CLM uint32 = 0xBD00
1726 op_CLMH uint32 = 0xEB20
1727 op_CLMY uint32 = 0xEB21
1728 op_CLR uint32 = 0x1500
1729 op_CLRB uint32 = 0xECF7
1730 op_CLRJ uint32 = 0xEC77
1731 op_CLRL uint32 = 0xC60F
1732 op_CLRT uint32 = 0xB973
1733 op_CLST uint32 = 0xB25D
1734 op_CLT uint32 = 0xEB23
1735 op_CLY uint32 = 0xE355
1736 op_CMPSC uint32 = 0xB263
1737 op_CP uint32 = 0xF900
1738 op_CPSDR uint32 = 0xB372
1739 op_CPYA uint32 = 0xB24D
1740 op_CR uint32 = 0x1900
1741 op_CRB uint32 = 0xECF6
1742 op_CRDTE uint32 = 0xB98F
1743 op_CRJ uint32 = 0xEC76
1744 op_CRL uint32 = 0xC60D
1745 op_CRT uint32 = 0xB972
1746 op_CS uint32 = 0xBA00
1747 op_CSCH uint32 = 0xB230
1748 op_CSDTR uint32 = 0xB3E3
1749 op_CSG uint32 = 0xEB30
1750 op_CSP uint32 = 0xB250
1751 op_CSPG uint32 = 0xB98A
1752 op_CSST uint32 = 0xC802
1753 op_CSXTR uint32 = 0xB3EB
1754 op_CSY uint32 = 0xEB14
1755 op_CU12 uint32 = 0xB2A7
1756 op_CU14 uint32 = 0xB9B0
1757 op_CU21 uint32 = 0xB2A6
1758 op_CU24 uint32 = 0xB9B1
1759 op_CU41 uint32 = 0xB9B2
1760 op_CU42 uint32 = 0xB9B3
1761 op_CUDTR uint32 = 0xB3E2
1762 op_CUSE uint32 = 0xB257
1763 op_CUTFU uint32 = 0xB2A7
1764 op_CUUTF uint32 = 0xB2A6
1765 op_CUXTR uint32 = 0xB3EA
1766 op_CVB uint32 = 0x4F00
1767 op_CVBG uint32 = 0xE30E
1768 op_CVBY uint32 = 0xE306
1769 op_CVD uint32 = 0x4E00
1770 op_CVDG uint32 = 0xE32E
1771 op_CVDY uint32 = 0xE326
1772 op_CXBR uint32 = 0xB349
1773 op_CXFBR uint32 = 0xB396
1774 op_CXFBRA uint32 = 0xB396
1775 op_CXFR uint32 = 0xB3B6
1776 op_CXFTR uint32 = 0xB959
1777 op_CXGBR uint32 = 0xB3A6
1778 op_CXGBRA uint32 = 0xB3A6
1779 op_CXGR uint32 = 0xB3C6
1780 op_CXGTR uint32 = 0xB3F9
1781 op_CXGTRA uint32 = 0xB3F9
1782 op_CXLFBR uint32 = 0xB392
1783 op_CXLFTR uint32 = 0xB95B
1784 op_CXLGBR uint32 = 0xB3A2
1785 op_CXLGTR uint32 = 0xB95A
1786 op_CXR uint32 = 0xB369
1787 op_CXSTR uint32 = 0xB3FB
1788 op_CXTR uint32 = 0xB3EC
1789 op_CXUTR uint32 = 0xB3FA
1790 op_CXZT uint32 = 0xEDAB
1791 op_CY uint32 = 0xE359
1792 op_CZDT uint32 = 0xEDA8
1793 op_CZXT uint32 = 0xEDA9
1794 op_D uint32 = 0x5D00
1795 op_DD uint32 = 0x6D00
1796 op_DDB uint32 = 0xED1D
1797 op_DDBR uint32 = 0xB31D
1798 op_DDR uint32 = 0x2D00
1799 op_DDTR uint32 = 0xB3D1
1800 op_DDTRA uint32 = 0xB3D1
1801 op_DE uint32 = 0x7D00
1802 op_DEB uint32 = 0xED0D
1803 op_DEBR uint32 = 0xB30D
1804 op_DER uint32 = 0x3D00
1805 op_DIDBR uint32 = 0xB35B
1806 op_DIEBR uint32 = 0xB353
1807 op_DL uint32 = 0xE397
1808 op_DLG uint32 = 0xE387
1809 op_DLGR uint32 = 0xB987
1810 op_DLR uint32 = 0xB997
1811 op_DP uint32 = 0xFD00
1812 op_DR uint32 = 0x1D00
1813 op_DSG uint32 = 0xE30D
1814 op_DSGF uint32 = 0xE31D
1815 op_DSGFR uint32 = 0xB91D
1816 op_DSGR uint32 = 0xB90D
1817 op_DXBR uint32 = 0xB34D
1818 op_DXR uint32 = 0xB22D
1819 op_DXTR uint32 = 0xB3D9
1820 op_DXTRA uint32 = 0xB3D9
1821 op_EAR uint32 = 0xB24F
1822 op_ECAG uint32 = 0xEB4C
1823 op_ECTG uint32 = 0xC801
1824 op_ED uint32 = 0xDE00
1825 op_EDMK uint32 = 0xDF00
1826 op_EEDTR uint32 = 0xB3E5
1827 op_EEXTR uint32 = 0xB3ED
1828 op_EFPC uint32 = 0xB38C
1829 op_EPAIR uint32 = 0xB99A
1830 op_EPAR uint32 = 0xB226
1831 op_EPSW uint32 = 0xB98D
1832 op_EREG uint32 = 0xB249
1833 op_EREGG uint32 = 0xB90E
1834 op_ESAIR uint32 = 0xB99B
1835 op_ESAR uint32 = 0xB227
1836 op_ESDTR uint32 = 0xB3E7
1837 op_ESEA uint32 = 0xB99D
1838 op_ESTA uint32 = 0xB24A
1839 op_ESXTR uint32 = 0xB3EF
1840 op_ETND uint32 = 0xB2EC
1841 op_EX uint32 = 0x4400
1842 op_EXRL uint32 = 0xC600
1843 op_FIDBR uint32 = 0xB35F
1844 op_FIDBRA uint32 = 0xB35F
1845 op_FIDR uint32 = 0xB37F
1846 op_FIDTR uint32 = 0xB3D7
1847 op_FIEBR uint32 = 0xB357
1848 op_FIEBRA uint32 = 0xB357
1849 op_FIER uint32 = 0xB377
1850 op_FIXBR uint32 = 0xB347
1851 op_FIXBRA uint32 = 0xB347
1852 op_FIXR uint32 = 0xB367
1853 op_FIXTR uint32 = 0xB3DF
1854 op_FLOGR uint32 = 0xB983
1855 op_HDR uint32 = 0x2400
1856 op_HER uint32 = 0x3400
1857 op_HSCH uint32 = 0xB231
1858 op_IAC uint32 = 0xB224
1859 op_IC uint32 = 0x4300
1860 op_ICM uint32 = 0xBF00
1861 op_ICMH uint32 = 0xEB80
1862 op_ICMY uint32 = 0xEB81
1863 op_ICY uint32 = 0xE373
1864 op_IDTE uint32 = 0xB98E
1865 op_IEDTR uint32 = 0xB3F6
1866 op_IEXTR uint32 = 0xB3FE
1867 op_IIHF uint32 = 0xC008
1868 op_IIHH uint32 = 0xA500
1869 op_IIHL uint32 = 0xA501
1870 op_IILF uint32 = 0xC009
1871 op_IILH uint32 = 0xA502
1872 op_IILL uint32 = 0xA503
1873 op_IPK uint32 = 0xB20B
1874 op_IPM uint32 = 0xB222
1875 op_IPTE uint32 = 0xB221
1876 op_ISKE uint32 = 0xB229
1877 op_IVSK uint32 = 0xB223
1878 op_KDB uint32 = 0xED18
1879 op_KDBR uint32 = 0xB318
1880 op_KDTR uint32 = 0xB3E0
1881 op_KEB uint32 = 0xED08
1882 op_KEBR uint32 = 0xB308
1883 op_KIMD uint32 = 0xB93E
1884 op_KLMD uint32 = 0xB93F
1885 op_KM uint32 = 0xB92E
1886 op_KMAC uint32 = 0xB91E
1887 op_KMC uint32 = 0xB92F
1888 op_KMA uint32 = 0xB929
1889 op_KMCTR uint32 = 0xB92D
1890 op_KMF uint32 = 0xB92A
1891 op_KMO uint32 = 0xB92B
1892 op_KXBR uint32 = 0xB348
1893 op_KXTR uint32 = 0xB3E8
1894 op_L uint32 = 0x5800
1895 op_LA uint32 = 0x4100
1896 op_LAA uint32 = 0xEBF8
1897 op_LAAG uint32 = 0xEBE8
1898 op_LAAL uint32 = 0xEBFA
1899 op_LAALG uint32 = 0xEBEA
1900 op_LAE uint32 = 0x5100
1901 op_LAEY uint32 = 0xE375
1902 op_LAM uint32 = 0x9A00
1903 op_LAMY uint32 = 0xEB9A
1904 op_LAN uint32 = 0xEBF4
1905 op_LANG uint32 = 0xEBE4
1906 op_LAO uint32 = 0xEBF6
1907 op_LAOG uint32 = 0xEBE6
1908 op_LARL uint32 = 0xC000
1909 op_LASP uint32 = 0xE500
1910 op_LAT uint32 = 0xE39F
1911 op_LAX uint32 = 0xEBF7
1912 op_LAXG uint32 = 0xEBE7
1913 op_LAY uint32 = 0xE371
1914 op_LB uint32 = 0xE376
1915 op_LBH uint32 = 0xE3C0
1916 op_LBR uint32 = 0xB926
1917 op_LCDBR uint32 = 0xB313
1918 op_LCDFR uint32 = 0xB373
1919 op_LCDR uint32 = 0x2300
1920 op_LCEBR uint32 = 0xB303
1921 op_LCER uint32 = 0x3300
1922 op_LCGFR uint32 = 0xB913
1923 op_LCGR uint32 = 0xB903
1924 op_LCR uint32 = 0x1300
1925 op_LCTL uint32 = 0xB700
1926 op_LCTLG uint32 = 0xEB2F
1927 op_LCXBR uint32 = 0xB343
1928 op_LCXR uint32 = 0xB363
1929 op_LD uint32 = 0x6800
1930 op_LDE uint32 = 0xED24
1931 op_LDEB uint32 = 0xED04
1932 op_LDEBR uint32 = 0xB304
1933 op_LDER uint32 = 0xB324
1934 op_LDETR uint32 = 0xB3D4
1935 op_LDGR uint32 = 0xB3C1
1936 op_LDR uint32 = 0x2800
1937 op_LDXBR uint32 = 0xB345
1938 op_LDXBRA uint32 = 0xB345
1939 op_LDXR uint32 = 0x2500
1940 op_LDXTR uint32 = 0xB3DD
1941 op_LDY uint32 = 0xED65
1942 op_LE uint32 = 0x7800
1943 op_LEDBR uint32 = 0xB344
1944 op_LEDBRA uint32 = 0xB344
1945 op_LEDR uint32 = 0x3500
1946 op_LEDTR uint32 = 0xB3D5
1947 op_LER uint32 = 0x3800
1948 op_LEXBR uint32 = 0xB346
1949 op_LEXBRA uint32 = 0xB346
1950 op_LEXR uint32 = 0xB366
1951 op_LEY uint32 = 0xED64
1952 op_LFAS uint32 = 0xB2BD
1953 op_LFH uint32 = 0xE3CA
1954 op_LFHAT uint32 = 0xE3C8
1955 op_LFPC uint32 = 0xB29D
1956 op_LG uint32 = 0xE304
1957 op_LGAT uint32 = 0xE385
1958 op_LGB uint32 = 0xE377
1959 op_LGBR uint32 = 0xB906
1960 op_LGDR uint32 = 0xB3CD
1961 op_LGF uint32 = 0xE314
1962 op_LGFI uint32 = 0xC001
1963 op_LGFR uint32 = 0xB914
1964 op_LGFRL uint32 = 0xC40C
1965 op_LGH uint32 = 0xE315
1966 op_LGHI uint32 = 0xA709
1967 op_LGHR uint32 = 0xB907
1968 op_LGHRL uint32 = 0xC404
1969 op_LGR uint32 = 0xB904
1970 op_LGRL uint32 = 0xC408
1971 op_LH uint32 = 0x4800
1972 op_LHH uint32 = 0xE3C4
1973 op_LHI uint32 = 0xA708
1974 op_LHR uint32 = 0xB927
1975 op_LHRL uint32 = 0xC405
1976 op_LHY uint32 = 0xE378
1977 op_LLC uint32 = 0xE394
1978 op_LLCH uint32 = 0xE3C2
1979 op_LLCR uint32 = 0xB994
1980 op_LLGC uint32 = 0xE390
1981 op_LLGCR uint32 = 0xB984
1982 op_LLGF uint32 = 0xE316
1983 op_LLGFAT uint32 = 0xE39D
1984 op_LLGFR uint32 = 0xB916
1985 op_LLGFRL uint32 = 0xC40E
1986 op_LLGH uint32 = 0xE391
1987 op_LLGHR uint32 = 0xB985
1988 op_LLGHRL uint32 = 0xC406
1989 op_LLGT uint32 = 0xE317
1990 op_LLGTAT uint32 = 0xE39C
1991 op_LLGTR uint32 = 0xB917
1992 op_LLH uint32 = 0xE395
1993 op_LLHH uint32 = 0xE3C6
1994 op_LLHR uint32 = 0xB995
1995 op_LLHRL uint32 = 0xC402
1996 op_LLIHF uint32 = 0xC00E
1997 op_LLIHH uint32 = 0xA50C
1998 op_LLIHL uint32 = 0xA50D
1999 op_LLILF uint32 = 0xC00F
2000 op_LLILH uint32 = 0xA50E
2001 op_LLILL uint32 = 0xA50F
2002 op_LM uint32 = 0x9800
2003 op_LMD uint32 = 0xEF00
2004 op_LMG uint32 = 0xEB04
2005 op_LMH uint32 = 0xEB96
2006 op_LMY uint32 = 0xEB98
2007 op_LNDBR uint32 = 0xB311
2008 op_LNDFR uint32 = 0xB371
2009 op_LNDR uint32 = 0x2100
2010 op_LNEBR uint32 = 0xB301
2011 op_LNER uint32 = 0x3100
2012 op_LNGFR uint32 = 0xB911
2013 op_LNGR uint32 = 0xB901
2014 op_LNR uint32 = 0x1100
2015 op_LNXBR uint32 = 0xB341
2016 op_LNXR uint32 = 0xB361
2017 op_LOC uint32 = 0xEBF2
2018 op_LOCG uint32 = 0xEBE2
2019 op_LOCGR uint32 = 0xB9E2
2020 op_LOCR uint32 = 0xB9F2
2021 op_LPD uint32 = 0xC804
2022 op_LPDBR uint32 = 0xB310
2023 op_LPDFR uint32 = 0xB370
2024 op_LPDG uint32 = 0xC805
2025 op_LPDR uint32 = 0x2000
2026 op_LPEBR uint32 = 0xB300
2027 op_LPER uint32 = 0x3000
2028 op_LPGFR uint32 = 0xB910
2029 op_LPGR uint32 = 0xB900
2030 op_LPQ uint32 = 0xE38F
2031 op_LPR uint32 = 0x1000
2032 op_LPSW uint32 = 0x8200
2033 op_LPSWE uint32 = 0xB2B2
2034 op_LPTEA uint32 = 0xB9AA
2035 op_LPXBR uint32 = 0xB340
2036 op_LPXR uint32 = 0xB360
2037 op_LR uint32 = 0x1800
2038 op_LRA uint32 = 0xB100
2039 op_LRAG uint32 = 0xE303
2040 op_LRAY uint32 = 0xE313
2041 op_LRDR uint32 = 0x2500
2042 op_LRER uint32 = 0x3500
2043 op_LRL uint32 = 0xC40D
2044 op_LRV uint32 = 0xE31E
2045 op_LRVG uint32 = 0xE30F
2046 op_LRVGR uint32 = 0xB90F
2047 op_LRVH uint32 = 0xE31F
2048 op_LRVR uint32 = 0xB91F
2049 op_LT uint32 = 0xE312
2050 op_LTDBR uint32 = 0xB312
2051 op_LTDR uint32 = 0x2200
2052 op_LTDTR uint32 = 0xB3D6
2053 op_LTEBR uint32 = 0xB302
2054 op_LTER uint32 = 0x3200
2055 op_LTG uint32 = 0xE302
2056 op_LTGF uint32 = 0xE332
2057 op_LTGFR uint32 = 0xB912
2058 op_LTGR uint32 = 0xB902
2059 op_LTR uint32 = 0x1200
2060 op_LTXBR uint32 = 0xB342
2061 op_LTXR uint32 = 0xB362
2062 op_LTXTR uint32 = 0xB3DE
2063 op_LURA uint32 = 0xB24B
2064 op_LURAG uint32 = 0xB905
2065 op_LXD uint32 = 0xED25
2066 op_LXDB uint32 = 0xED05
2067 op_LXDBR uint32 = 0xB305
2068 op_LXDR uint32 = 0xB325
2069 op_LXDTR uint32 = 0xB3DC
2070 op_LXE uint32 = 0xED26
2071 op_LXEB uint32 = 0xED06
2072 op_LXEBR uint32 = 0xB306
2073 op_LXER uint32 = 0xB326
2074 op_LXR uint32 = 0xB365
2075 op_LY uint32 = 0xE358
2076 op_LZDR uint32 = 0xB375
2077 op_LZER uint32 = 0xB374
2078 op_LZXR uint32 = 0xB376
2079 op_M uint32 = 0x5C00
2080 op_MAD uint32 = 0xED3E
2081 op_MADB uint32 = 0xED1E
2082 op_MADBR uint32 = 0xB31E
2083 op_MADR uint32 = 0xB33E
2084 op_MAE uint32 = 0xED2E
2085 op_MAEB uint32 = 0xED0E
2086 op_MAEBR uint32 = 0xB30E
2087 op_MAER uint32 = 0xB32E
2088 op_MAY uint32 = 0xED3A
2089 op_MAYH uint32 = 0xED3C
2090 op_MAYHR uint32 = 0xB33C
2091 op_MAYL uint32 = 0xED38
2092 op_MAYLR uint32 = 0xB338
2093 op_MAYR uint32 = 0xB33A
2094 op_MC uint32 = 0xAF00
2095 op_MD uint32 = 0x6C00
2096 op_MDB uint32 = 0xED1C
2097 op_MDBR uint32 = 0xB31C
2098 op_MDE uint32 = 0x7C00
2099 op_MDEB uint32 = 0xED0C
2100 op_MDEBR uint32 = 0xB30C
2101 op_MDER uint32 = 0x3C00
2102 op_MDR uint32 = 0x2C00
2103 op_MDTR uint32 = 0xB3D0
2104 op_MDTRA uint32 = 0xB3D0
2105 op_ME uint32 = 0x7C00
2106 op_MEE uint32 = 0xED37
2107 op_MEEB uint32 = 0xED17
2108 op_MEEBR uint32 = 0xB317
2109 op_MEER uint32 = 0xB337
2110 op_MER uint32 = 0x3C00
2111 op_MFY uint32 = 0xE35C
2112 op_MGHI uint32 = 0xA70D
2113 op_MH uint32 = 0x4C00
2114 op_MHI uint32 = 0xA70C
2115 op_MHY uint32 = 0xE37C
2116 op_ML uint32 = 0xE396
2117 op_MLG uint32 = 0xE386
2118 op_MLGR uint32 = 0xB986
2119 op_MLR uint32 = 0xB996
2120 op_MP uint32 = 0xFC00
2121 op_MR uint32 = 0x1C00
2122 op_MS uint32 = 0x7100
2123 op_MSCH uint32 = 0xB232
2124 op_MSD uint32 = 0xED3F
2125 op_MSDB uint32 = 0xED1F
2126 op_MSDBR uint32 = 0xB31F
2127 op_MSDR uint32 = 0xB33F
2128 op_MSE uint32 = 0xED2F
2129 op_MSEB uint32 = 0xED0F
2130 op_MSEBR uint32 = 0xB30F
2131 op_MSER uint32 = 0xB32F
2132 op_MSFI uint32 = 0xC201
2133 op_MSG uint32 = 0xE30C
2134 op_MSGF uint32 = 0xE31C
2135 op_MSGFI uint32 = 0xC200
2136 op_MSGFR uint32 = 0xB91C
2137 op_MSGR uint32 = 0xB90C
2138 op_MSR uint32 = 0xB252
2139 op_MSTA uint32 = 0xB247
2140 op_MSY uint32 = 0xE351
2141 op_MVC uint32 = 0xD200
2142 op_MVCDK uint32 = 0xE50F
2143 op_MVCIN uint32 = 0xE800
2144 op_MVCK uint32 = 0xD900
2145 op_MVCL uint32 = 0x0E00
2146 op_MVCLE uint32 = 0xA800
2147 op_MVCLU uint32 = 0xEB8E
2148 op_MVCOS uint32 = 0xC800
2149 op_MVCP uint32 = 0xDA00
2150 op_MVCS uint32 = 0xDB00
2151 op_MVCSK uint32 = 0xE50E
2152 op_MVGHI uint32 = 0xE548
2153 op_MVHHI uint32 = 0xE544
2154 op_MVHI uint32 = 0xE54C
2155 op_MVI uint32 = 0x9200
2156 op_MVIY uint32 = 0xEB52
2157 op_MVN uint32 = 0xD100
2158 op_MVO uint32 = 0xF100
2159 op_MVPG uint32 = 0xB254
2160 op_MVST uint32 = 0xB255
2161 op_MVZ uint32 = 0xD300
2162 op_MXBR uint32 = 0xB34C
2163 op_MXD uint32 = 0x6700
2164 op_MXDB uint32 = 0xED07
2165 op_MXDBR uint32 = 0xB307
2166 op_MXDR uint32 = 0x2700
2167 op_MXR uint32 = 0x2600
2168 op_MXTR uint32 = 0xB3D8
2169 op_MXTRA uint32 = 0xB3D8
2170 op_MY uint32 = 0xED3B
2171 op_MYH uint32 = 0xED3D
2172 op_MYHR uint32 = 0xB33D
2173 op_MYL uint32 = 0xED39
2174 op_MYLR uint32 = 0xB339
2175 op_MYR uint32 = 0xB33B
2176 op_N uint32 = 0x5400
2177 op_NC uint32 = 0xD400
2178 op_NG uint32 = 0xE380
2179 op_NGR uint32 = 0xB980
2180 op_NGRK uint32 = 0xB9E4
2181 op_NI uint32 = 0x9400
2182 op_NIAI uint32 = 0xB2FA
2183 op_NIHF uint32 = 0xC00A
2184 op_NIHH uint32 = 0xA504
2185 op_NIHL uint32 = 0xA505
2186 op_NILF uint32 = 0xC00B
2187 op_NILH uint32 = 0xA506
2188 op_NILL uint32 = 0xA507
2189 op_NIY uint32 = 0xEB54
2190 op_NR uint32 = 0x1400
2191 op_NRK uint32 = 0xB9F4
2192 op_NTSTG uint32 = 0xE325
2193 op_NY uint32 = 0xE354
2194 op_O uint32 = 0x5600
2195 op_OC uint32 = 0xD600
2196 op_OG uint32 = 0xE381
2197 op_OGR uint32 = 0xB981
2198 op_OGRK uint32 = 0xB9E6
2199 op_OI uint32 = 0x9600
2200 op_OIHF uint32 = 0xC00C
2201 op_OIHH uint32 = 0xA508
2202 op_OIHL uint32 = 0xA509
2203 op_OILF uint32 = 0xC00D
2204 op_OILH uint32 = 0xA50A
2205 op_OILL uint32 = 0xA50B
2206 op_OIY uint32 = 0xEB56
2207 op_OR uint32 = 0x1600
2208 op_ORK uint32 = 0xB9F6
2209 op_OY uint32 = 0xE356
2210 op_PACK uint32 = 0xF200
2211 op_PALB uint32 = 0xB248
2212 op_PC uint32 = 0xB218
2213 op_PCC uint32 = 0xB92C
2214 op_PCKMO uint32 = 0xB928
2215 op_PFD uint32 = 0xE336
2216 op_PFDRL uint32 = 0xC602
2217 op_PFMF uint32 = 0xB9AF
2218 op_PFPO uint32 = 0x010A
2219 op_PGIN uint32 = 0xB22E
2220 op_PGOUT uint32 = 0xB22F
2221 op_PKA uint32 = 0xE900
2222 op_PKU uint32 = 0xE100
2223 op_PLO uint32 = 0xEE00
2224 op_POPCNT uint32 = 0xB9E1
2225 op_PPA uint32 = 0xB2E8
2226 op_PR uint32 = 0x0101
2227 op_PT uint32 = 0xB228
2228 op_PTF uint32 = 0xB9A2
2229 op_PTFF uint32 = 0x0104
2230 op_PTI uint32 = 0xB99E
2231 op_PTLB uint32 = 0xB20D
2232 op_QADTR uint32 = 0xB3F5
2233 op_QAXTR uint32 = 0xB3FD
2234 op_RCHP uint32 = 0xB23B
2235 op_RISBG uint32 = 0xEC55
2236 op_RISBGN uint32 = 0xEC59
2237 op_RISBHG uint32 = 0xEC5D
2238 op_RISBLG uint32 = 0xEC51
2239 op_RLL uint32 = 0xEB1D
2240 op_RLLG uint32 = 0xEB1C
2241 op_RNSBG uint32 = 0xEC54
2242 op_ROSBG uint32 = 0xEC56
2243 op_RP uint32 = 0xB277
2244 op_RRBE uint32 = 0xB22A
2245 op_RRBM uint32 = 0xB9AE
2246 op_RRDTR uint32 = 0xB3F7
2247 op_RRXTR uint32 = 0xB3FF
2248 op_RSCH uint32 = 0xB238
2249 op_RXSBG uint32 = 0xEC57
2250 op_S uint32 = 0x5B00
2251 op_SAC uint32 = 0xB219
2252 op_SACF uint32 = 0xB279
2253 op_SAL uint32 = 0xB237
2254 op_SAM24 uint32 = 0x010C
2255 op_SAM31 uint32 = 0x010D
2256 op_SAM64 uint32 = 0x010E
2257 op_SAR uint32 = 0xB24E
2258 op_SCHM uint32 = 0xB23C
2259 op_SCK uint32 = 0xB204
2260 op_SCKC uint32 = 0xB206
2261 op_SCKPF uint32 = 0x0107
2262 op_SD uint32 = 0x6B00
2263 op_SDB uint32 = 0xED1B
2264 op_SDBR uint32 = 0xB31B
2265 op_SDR uint32 = 0x2B00
2266 op_SDTR uint32 = 0xB3D3
2267 op_SDTRA uint32 = 0xB3D3
2268 op_SE uint32 = 0x7B00
2269 op_SEB uint32 = 0xED0B
2270 op_SEBR uint32 = 0xB30B
2271 op_SER uint32 = 0x3B00
2272 op_SFASR uint32 = 0xB385
2273 op_SFPC uint32 = 0xB384
2274 op_SG uint32 = 0xE309
2275 op_SGF uint32 = 0xE319
2276 op_SGFR uint32 = 0xB919
2277 op_SGR uint32 = 0xB909
2278 op_SGRK uint32 = 0xB9E9
2279 op_SH uint32 = 0x4B00
2280 op_SHHHR uint32 = 0xB9C9
2281 op_SHHLR uint32 = 0xB9D9
2282 op_SHY uint32 = 0xE37B
2283 op_SIGP uint32 = 0xAE00
2284 op_SL uint32 = 0x5F00
2285 op_SLA uint32 = 0x8B00
2286 op_SLAG uint32 = 0xEB0B
2287 op_SLAK uint32 = 0xEBDD
2288 op_SLB uint32 = 0xE399
2289 op_SLBG uint32 = 0xE389
2290 op_SLBGR uint32 = 0xB989
2291 op_SLBR uint32 = 0xB999
2292 op_SLDA uint32 = 0x8F00
2293 op_SLDL uint32 = 0x8D00
2294 op_SLDT uint32 = 0xED40
2295 op_SLFI uint32 = 0xC205
2296 op_SLG uint32 = 0xE30B
2297 op_SLGF uint32 = 0xE31B
2298 op_SLGFI uint32 = 0xC204
2299 op_SLGFR uint32 = 0xB91B
2300 op_SLGR uint32 = 0xB90B
2301 op_SLGRK uint32 = 0xB9EB
2302 op_SLHHHR uint32 = 0xB9CB
2303 op_SLHHLR uint32 = 0xB9DB
2304 op_SLL uint32 = 0x8900
2305 op_SLLG uint32 = 0xEB0D
2306 op_SLLK uint32 = 0xEBDF
2307 op_SLR uint32 = 0x1F00
2308 op_SLRK uint32 = 0xB9FB
2309 op_SLXT uint32 = 0xED48
2310 op_SLY uint32 = 0xE35F
2311 op_SP uint32 = 0xFB00
2312 op_SPKA uint32 = 0xB20A
2313 op_SPM uint32 = 0x0400
2314 op_SPT uint32 = 0xB208
2315 op_SPX uint32 = 0xB210
2316 op_SQD uint32 = 0xED35
2317 op_SQDB uint32 = 0xED15
2318 op_SQDBR uint32 = 0xB315
2319 op_SQDR uint32 = 0xB244
2320 op_SQE uint32 = 0xED34
2321 op_SQEB uint32 = 0xED14
2322 op_SQEBR uint32 = 0xB314
2323 op_SQER uint32 = 0xB245
2324 op_SQXBR uint32 = 0xB316
2325 op_SQXR uint32 = 0xB336
2326 op_SR uint32 = 0x1B00
2327 op_SRA uint32 = 0x8A00
2328 op_SRAG uint32 = 0xEB0A
2329 op_SRAK uint32 = 0xEBDC
2330 op_SRDA uint32 = 0x8E00
2331 op_SRDL uint32 = 0x8C00
2332 op_SRDT uint32 = 0xED41
2333 op_SRK uint32 = 0xB9F9
2334 op_SRL uint32 = 0x8800
2335 op_SRLG uint32 = 0xEB0C
2336 op_SRLK uint32 = 0xEBDE
2337 op_SRNM uint32 = 0xB299
2338 op_SRNMB uint32 = 0xB2B8
2339 op_SRNMT uint32 = 0xB2B9
2340 op_SRP uint32 = 0xF000
2341 op_SRST uint32 = 0xB25E
2342 op_SRSTU uint32 = 0xB9BE
2343 op_SRXT uint32 = 0xED49
2344 op_SSAIR uint32 = 0xB99F
2345 op_SSAR uint32 = 0xB225
2346 op_SSCH uint32 = 0xB233
2347 op_SSKE uint32 = 0xB22B
2348 op_SSM uint32 = 0x8000
2349 op_ST uint32 = 0x5000
2350 op_STAM uint32 = 0x9B00
2351 op_STAMY uint32 = 0xEB9B
2352 op_STAP uint32 = 0xB212
2353 op_STC uint32 = 0x4200
2354 op_STCH uint32 = 0xE3C3
2355 op_STCK uint32 = 0xB205
2356 op_STCKC uint32 = 0xB207
2357 op_STCKE uint32 = 0xB278
2358 op_STCKF uint32 = 0xB27C
2359 op_STCM uint32 = 0xBE00
2360 op_STCMH uint32 = 0xEB2C
2361 op_STCMY uint32 = 0xEB2D
2362 op_STCPS uint32 = 0xB23A
2363 op_STCRW uint32 = 0xB239
2364 op_STCTG uint32 = 0xEB25
2365 op_STCTL uint32 = 0xB600
2366 op_STCY uint32 = 0xE372
2367 op_STD uint32 = 0x6000
2368 op_STDY uint32 = 0xED67
2369 op_STE uint32 = 0x7000
2370 op_STEY uint32 = 0xED66
2371 op_STFH uint32 = 0xE3CB
2372 op_STFL uint32 = 0xB2B1
2373 op_STFLE uint32 = 0xB2B0
2374 op_STFPC uint32 = 0xB29C
2375 op_STG uint32 = 0xE324
2376 op_STGRL uint32 = 0xC40B
2377 op_STH uint32 = 0x4000
2378 op_STHH uint32 = 0xE3C7
2379 op_STHRL uint32 = 0xC407
2380 op_STHY uint32 = 0xE370
2381 op_STIDP uint32 = 0xB202
2382 op_STM uint32 = 0x9000
2383 op_STMG uint32 = 0xEB24
2384 op_STMH uint32 = 0xEB26
2385 op_STMY uint32 = 0xEB90
2386 op_STNSM uint32 = 0xAC00
2387 op_STOC uint32 = 0xEBF3
2388 op_STOCG uint32 = 0xEBE3
2389 op_STOSM uint32 = 0xAD00
2390 op_STPQ uint32 = 0xE38E
2391 op_STPT uint32 = 0xB209
2392 op_STPX uint32 = 0xB211
2393 op_STRAG uint32 = 0xE502
2394 op_STRL uint32 = 0xC40F
2395 op_STRV uint32 = 0xE33E
2396 op_STRVG uint32 = 0xE32F
2397 op_STRVH uint32 = 0xE33F
2398 op_STSCH uint32 = 0xB234
2399 op_STSI uint32 = 0xB27D
2400 op_STURA uint32 = 0xB246
2401 op_STURG uint32 = 0xB925
2402 op_STY uint32 = 0xE350
2403 op_SU uint32 = 0x7F00
2404 op_SUR uint32 = 0x3F00
2405 op_SVC uint32 = 0x0A00
2406 op_SW uint32 = 0x6F00
2407 op_SWR uint32 = 0x2F00
2408 op_SXBR uint32 = 0xB34B
2409 op_SXR uint32 = 0x3700
2410 op_SXTR uint32 = 0xB3DB
2411 op_SXTRA uint32 = 0xB3DB
2412 op_SY uint32 = 0xE35B
2413 op_TABORT uint32 = 0xB2FC
2414 op_TAM uint32 = 0x010B
2415 op_TAR uint32 = 0xB24C
2416 op_TB uint32 = 0xB22C
2417 op_TBDR uint32 = 0xB351
2418 op_TBEDR uint32 = 0xB350
2419 op_TBEGIN uint32 = 0xE560
2420 op_TBEGINC uint32 = 0xE561
2421 op_TCDB uint32 = 0xED11
2422 op_TCEB uint32 = 0xED10
2423 op_TCXB uint32 = 0xED12
2424 op_TDCDT uint32 = 0xED54
2425 op_TDCET uint32 = 0xED50
2426 op_TDCXT uint32 = 0xED58
2427 op_TDGDT uint32 = 0xED55
2428 op_TDGET uint32 = 0xED51
2429 op_TDGXT uint32 = 0xED59
2430 op_TEND uint32 = 0xB2F8
2431 op_THDER uint32 = 0xB358
2432 op_THDR uint32 = 0xB359
2433 op_TM uint32 = 0x9100
2434 op_TMH uint32 = 0xA700
2435 op_TMHH uint32 = 0xA702
2436 op_TMHL uint32 = 0xA703
2437 op_TML uint32 = 0xA701
2438 op_TMLH uint32 = 0xA700
2439 op_TMLL uint32 = 0xA701
2440 op_TMY uint32 = 0xEB51
2441 op_TP uint32 = 0xEBC0
2442 op_TPI uint32 = 0xB236
2443 op_TPROT uint32 = 0xE501
2444 op_TR uint32 = 0xDC00
2445 op_TRACE uint32 = 0x9900
2446 op_TRACG uint32 = 0xEB0F
2447 op_TRAP2 uint32 = 0x01FF
2448 op_TRAP4 uint32 = 0xB2FF
2449 op_TRE uint32 = 0xB2A5
2450 op_TROO uint32 = 0xB993
2451 op_TROT uint32 = 0xB992
2452 op_TRT uint32 = 0xDD00
2453 op_TRTE uint32 = 0xB9BF
2454 op_TRTO uint32 = 0xB991
2455 op_TRTR uint32 = 0xD000
2456 op_TRTRE uint32 = 0xB9BD
2457 op_TRTT uint32 = 0xB990
2458 op_TS uint32 = 0x9300
2459 op_TSCH uint32 = 0xB235
2460 op_UNPK uint32 = 0xF300
2461 op_UNPKA uint32 = 0xEA00
2462 op_UNPKU uint32 = 0xE200
2463 op_UPT uint32 = 0x0102
2464 op_X uint32 = 0x5700
2465 op_XC uint32 = 0xD700
2466 op_XG uint32 = 0xE382
2467 op_XGR uint32 = 0xB982
2468 op_XGRK uint32 = 0xB9E7
2469 op_XI uint32 = 0x9700
2470 op_XIHF uint32 = 0xC006
2471 op_XILF uint32 = 0xC007
2472 op_XIY uint32 = 0xEB57
2473 op_XR uint32 = 0x1700
2474 op_XRK uint32 = 0xB9F7
2475 op_XSCH uint32 = 0xB276
2476 op_XY uint32 = 0xE357
2477 op_ZAP uint32 = 0xF800
2478 op_BRRK uint32 = 0x0001
2479
2480
2481 op_CXPT uint32 = 0xEDAF
2482 op_CDPT uint32 = 0xEDAE
2483 op_CPXT uint32 = 0xEDAD
2484 op_CPDT uint32 = 0xEDAC
2485 op_LZRF uint32 = 0xE33B
2486 op_LZRG uint32 = 0xE32A
2487 op_LCCB uint32 = 0xE727
2488 op_LOCHHI uint32 = 0xEC4E
2489 op_LOCHI uint32 = 0xEC42
2490 op_LOCGHI uint32 = 0xEC46
2491 op_LOCFH uint32 = 0xEBE0
2492 op_LOCFHR uint32 = 0xB9E0
2493 op_LLZRGF uint32 = 0xE33A
2494 op_STOCFH uint32 = 0xEBE1
2495 op_VA uint32 = 0xE7F3
2496 op_VACC uint32 = 0xE7F1
2497 op_VAC uint32 = 0xE7BB
2498 op_VACCC uint32 = 0xE7B9
2499 op_VN uint32 = 0xE768
2500 op_VNC uint32 = 0xE769
2501 op_VAVG uint32 = 0xE7F2
2502 op_VAVGL uint32 = 0xE7F0
2503 op_VCKSM uint32 = 0xE766
2504 op_VCEQ uint32 = 0xE7F8
2505 op_VCH uint32 = 0xE7FB
2506 op_VCHL uint32 = 0xE7F9
2507 op_VCLZ uint32 = 0xE753
2508 op_VCTZ uint32 = 0xE752
2509 op_VEC uint32 = 0xE7DB
2510 op_VECL uint32 = 0xE7D9
2511 op_VERIM uint32 = 0xE772
2512 op_VERLL uint32 = 0xE733
2513 op_VERLLV uint32 = 0xE773
2514 op_VESLV uint32 = 0xE770
2515 op_VESL uint32 = 0xE730
2516 op_VESRA uint32 = 0xE73A
2517 op_VESRAV uint32 = 0xE77A
2518 op_VESRL uint32 = 0xE738
2519 op_VESRLV uint32 = 0xE778
2520 op_VX uint32 = 0xE76D
2521 op_VFAE uint32 = 0xE782
2522 op_VFEE uint32 = 0xE780
2523 op_VFENE uint32 = 0xE781
2524 op_VFA uint32 = 0xE7E3
2525 op_WFK uint32 = 0xE7CA
2526 op_VFCE uint32 = 0xE7E8
2527 op_VFCH uint32 = 0xE7EB
2528 op_VFCHE uint32 = 0xE7EA
2529 op_WFC uint32 = 0xE7CB
2530 op_VCDG uint32 = 0xE7C3
2531 op_VCDLG uint32 = 0xE7C1
2532 op_VCGD uint32 = 0xE7C2
2533 op_VCLGD uint32 = 0xE7C0
2534 op_VFD uint32 = 0xE7E5
2535 op_VLDE uint32 = 0xE7C4
2536 op_VLED uint32 = 0xE7C5
2537 op_VFM uint32 = 0xE7E7
2538 op_VFMA uint32 = 0xE78F
2539 op_VFMS uint32 = 0xE78E
2540 op_VFPSO uint32 = 0xE7CC
2541 op_VFSQ uint32 = 0xE7CE
2542 op_VFS uint32 = 0xE7E2
2543 op_VFTCI uint32 = 0xE74A
2544 op_VGFM uint32 = 0xE7B4
2545 op_VGFMA uint32 = 0xE7BC
2546 op_VGEF uint32 = 0xE713
2547 op_VGEG uint32 = 0xE712
2548 op_VGBM uint32 = 0xE744
2549 op_VGM uint32 = 0xE746
2550 op_VISTR uint32 = 0xE75C
2551 op_VL uint32 = 0xE706
2552 op_VLR uint32 = 0xE756
2553 op_VLREP uint32 = 0xE705
2554 op_VLC uint32 = 0xE7DE
2555 op_VLEH uint32 = 0xE701
2556 op_VLEF uint32 = 0xE703
2557 op_VLEG uint32 = 0xE702
2558 op_VLEB uint32 = 0xE700
2559 op_VLEIH uint32 = 0xE741
2560 op_VLEIF uint32 = 0xE743
2561 op_VLEIG uint32 = 0xE742
2562 op_VLEIB uint32 = 0xE740
2563 op_VFI uint32 = 0xE7C7
2564 op_VLGV uint32 = 0xE721
2565 op_VLLEZ uint32 = 0xE704
2566 op_VLM uint32 = 0xE736
2567 op_VLP uint32 = 0xE7DF
2568 op_VLBB uint32 = 0xE707
2569 op_VLVG uint32 = 0xE722
2570 op_VLVGP uint32 = 0xE762
2571 op_VLL uint32 = 0xE737
2572 op_VMX uint32 = 0xE7FF
2573 op_VMXL uint32 = 0xE7FD
2574 op_VMRH uint32 = 0xE761
2575 op_VMRL uint32 = 0xE760
2576 op_VMN uint32 = 0xE7FE
2577 op_VMNL uint32 = 0xE7FC
2578 op_VMAE uint32 = 0xE7AE
2579 op_VMAH uint32 = 0xE7AB
2580 op_VMALE uint32 = 0xE7AC
2581 op_VMALH uint32 = 0xE7A9
2582 op_VMALO uint32 = 0xE7AD
2583 op_VMAL uint32 = 0xE7AA
2584 op_VMAO uint32 = 0xE7AF
2585 op_VME uint32 = 0xE7A6
2586 op_VMH uint32 = 0xE7A3
2587 op_VMLE uint32 = 0xE7A4
2588 op_VMLH uint32 = 0xE7A1
2589 op_VMLO uint32 = 0xE7A5
2590 op_VML uint32 = 0xE7A2
2591 op_VMO uint32 = 0xE7A7
2592 op_VNO uint32 = 0xE76B
2593 op_VO uint32 = 0xE76A
2594 op_VPK uint32 = 0xE794
2595 op_VPKLS uint32 = 0xE795
2596 op_VPKS uint32 = 0xE797
2597 op_VPERM uint32 = 0xE78C
2598 op_VPDI uint32 = 0xE784
2599 op_VPOPCT uint32 = 0xE750
2600 op_VREP uint32 = 0xE74D
2601 op_VREPI uint32 = 0xE745
2602 op_VSCEF uint32 = 0xE71B
2603 op_VSCEG uint32 = 0xE71A
2604 op_VSEL uint32 = 0xE78D
2605 op_VSL uint32 = 0xE774
2606 op_VSLB uint32 = 0xE775
2607 op_VSLDB uint32 = 0xE777
2608 op_VSRA uint32 = 0xE77E
2609 op_VSRAB uint32 = 0xE77F
2610 op_VSRL uint32 = 0xE77C
2611 op_VSRLB uint32 = 0xE77D
2612 op_VSEG uint32 = 0xE75F
2613 op_VST uint32 = 0xE70E
2614 op_VSTEH uint32 = 0xE709
2615 op_VSTEF uint32 = 0xE70B
2616 op_VSTEG uint32 = 0xE70A
2617 op_VSTEB uint32 = 0xE708
2618 op_VSTM uint32 = 0xE73E
2619 op_VSTL uint32 = 0xE73F
2620 op_VSTRC uint32 = 0xE78A
2621 op_VS uint32 = 0xE7F7
2622 op_VSCBI uint32 = 0xE7F5
2623 op_VSBCBI uint32 = 0xE7BD
2624 op_VSBI uint32 = 0xE7BF
2625 op_VSUMG uint32 = 0xE765
2626 op_VSUMQ uint32 = 0xE767
2627 op_VSUM uint32 = 0xE764
2628 op_VTM uint32 = 0xE7D8
2629 op_VUPH uint32 = 0xE7D7
2630 op_VUPLH uint32 = 0xE7D5
2631 op_VUPLL uint32 = 0xE7D4
2632 op_VUPL uint32 = 0xE7D6
2633 op_VMSL uint32 = 0xE7B8
2634
2635
2636 op_KDSA uint32 = 0xB93A
2637
2638 )
2639
2640 func oclass(a *obj.Addr) int {
2641 return int(a.Class) - 1
2642 }
2643
2644
2645
2646 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) {
2647 if sym == nil {
2648 c.ctxt.Diag("require symbol to apply relocation")
2649 }
2650 offset := int64(2)
2651 c.cursym.AddRel(c.ctxt, obj.Reloc{
2652 Type: objabi.R_PCRELDBL,
2653 Off: int32(c.pc + offset),
2654 Siz: 4,
2655 Sym: sym,
2656 Add: add + offset + 4,
2657 })
2658 }
2659
2660 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) {
2661 if sym == nil {
2662 c.ctxt.Diag("require symbol to apply relocation")
2663 }
2664 offset += int64(2)
2665 c.cursym.AddRel(c.ctxt, obj.Reloc{
2666 Type: objabi.R_PCRELDBL,
2667 Off: int32(c.pc + offset),
2668 Siz: 4,
2669 Sym: sym,
2670 Add: add + offset + 4,
2671 })
2672 }
2673
2674
2675
2676 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) {
2677 if sym == nil {
2678 c.ctxt.Diag("require symbol to apply relocation")
2679 }
2680 offset := int64(2)
2681 c.cursym.AddRel(c.ctxt, obj.Reloc{
2682 Type: objabi.R_CALL,
2683 Off: int32(c.pc + offset),
2684 Siz: 4,
2685 Sym: sym,
2686 Add: add + offset + int64(4),
2687 })
2688 }
2689
2690 func (c *ctxtz) branchMask(p *obj.Prog) CCMask {
2691 switch p.As {
2692 case ABRC, ALOCR, ALOCGR,
2693 ACRJ, ACGRJ, ACIJ, ACGIJ,
2694 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ:
2695 return CCMask(p.From.Offset)
2696 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ:
2697 return Equal
2698 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE:
2699 return GreaterOrEqual
2700 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT:
2701 return Greater
2702 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE:
2703 return LessOrEqual
2704 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT:
2705 return Less
2706 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE:
2707 return NotEqual
2708 case ABLEU:
2709 return NotGreater
2710 case ABLTU:
2711 return LessOrUnordered
2712 case ABVC:
2713 return Never
2714 case ABVS:
2715 return Unordered
2716 }
2717 c.ctxt.Diag("unknown conditional branch %v", p.As)
2718 return Always
2719 }
2720
2721 func regtmp(p *obj.Prog) uint32 {
2722 p.Mark |= USETMP
2723 return REGTMP
2724 }
2725
2726 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
2727 o := c.oplook(p)
2728
2729 if o == nil {
2730 return
2731 }
2732
2733
2734
2735
2736 switch o.i {
2737 default:
2738 c.ctxt.Diag("unknown index %d", o.i)
2739
2740 case 0:
2741 break
2742
2743 case 1:
2744 switch p.As {
2745 default:
2746 c.ctxt.Diag("unhandled operation: %v", p.As)
2747 case AMOVD:
2748 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2749
2750 case AMOVW:
2751 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2752 case AMOVH:
2753 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2754 case AMOVB:
2755 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2756
2757 case AMOVWZ:
2758 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2759 case AMOVHZ:
2760 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2761 case AMOVBZ:
2762 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2763
2764 case AMOVDBR:
2765 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2766 case AMOVWBR:
2767 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2768
2769 case AFMOVD, AFMOVS:
2770 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2771 }
2772
2773 case 2:
2774 r := p.Reg
2775 if r == 0 {
2776 r = p.To.Reg
2777 }
2778
2779 var opcode uint32
2780
2781 switch p.As {
2782 default:
2783 c.ctxt.Diag("invalid opcode")
2784 case AADD:
2785 opcode = op_AGRK
2786 case AADDC:
2787 opcode = op_ALGRK
2788 case AADDE:
2789 opcode = op_ALCGR
2790 case AADDW:
2791 opcode = op_ARK
2792 case AMULLW:
2793 opcode = op_MSGFR
2794 case AMULLD:
2795 opcode = op_MSGR
2796 case ADIVW, AMODW:
2797 opcode = op_DSGFR
2798 case ADIVWU, AMODWU:
2799 opcode = op_DLR
2800 case ADIVD, AMODD:
2801 opcode = op_DSGR
2802 case ADIVDU, AMODDU:
2803 opcode = op_DLGR
2804 }
2805
2806 switch p.As {
2807 default:
2808
2809 case AADD, AADDC, AADDW:
2810 if p.As == AADDW && r == p.To.Reg {
2811 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2812 } else {
2813 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2814 }
2815
2816 case AADDE, AMULLW, AMULLD:
2817 if r == p.To.Reg {
2818 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2819 } else if p.From.Reg == p.To.Reg {
2820 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2821 } else {
2822 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2823 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2824 }
2825
2826 case ADIVW, ADIVWU, ADIVD, ADIVDU:
2827 if p.As == ADIVWU || p.As == ADIVDU {
2828 zRI(op_LGHI, regtmp(p), 0, asm)
2829 }
2830 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2831 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2832 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
2833
2834 case AMODW, AMODWU, AMODD, AMODDU:
2835 if p.As == AMODWU || p.As == AMODDU {
2836 zRI(op_LGHI, regtmp(p), 0, asm)
2837 }
2838 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2839 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2840 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2841
2842 }
2843
2844 case 3:
2845 v := c.vregoff(&p.From)
2846 switch p.As {
2847 case AMOVBZ:
2848 v = int64(uint8(v))
2849 case AMOVHZ:
2850 v = int64(uint16(v))
2851 case AMOVWZ:
2852 v = int64(uint32(v))
2853 case AMOVB:
2854 v = int64(int8(v))
2855 case AMOVH:
2856 v = int64(int16(v))
2857 case AMOVW:
2858 v = int64(int32(v))
2859 }
2860 if int64(int16(v)) == v {
2861 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
2862 } else if v&0xffff0000 == v {
2863 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
2864 } else if v&0xffff00000000 == v {
2865 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
2866 } else if uint64(v)&0xffff000000000000 == uint64(v) {
2867 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
2868 } else if int64(int32(v)) == v {
2869 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
2870 } else if int64(uint32(v)) == v {
2871 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2872 } else if uint64(v)&0xffffffff00000000 == uint64(v) {
2873 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2874 } else {
2875 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2876 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2877 }
2878
2879 case 4:
2880 r := p.Reg
2881 if r == 0 {
2882 r = p.To.Reg
2883 }
2884 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2885 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm)
2886 switch p.As {
2887 case AMULHDU:
2888
2889 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2890 case AMULHD:
2891
2892
2893 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm)
2894 zRRE(op_NGR, REGTMP2, uint32(r), asm)
2895 zRRE(op_SGR, regtmp(p), REGTMP2, asm)
2896 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm)
2897 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm)
2898 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm)
2899 }
2900
2901 case 5:
2902 zI(op_SVC, 0, asm)
2903
2904 case 6:
2905 var oprr, oprre, oprrf uint32
2906 switch p.As {
2907 case AAND:
2908 oprre = op_NGR
2909 oprrf = op_NGRK
2910 case AANDW:
2911 oprr = op_NR
2912 oprrf = op_NRK
2913 case AOR:
2914 oprre = op_OGR
2915 oprrf = op_OGRK
2916 case AORW:
2917 oprr = op_OR
2918 oprrf = op_ORK
2919 case AXOR:
2920 oprre = op_XGR
2921 oprrf = op_XGRK
2922 case AXORW:
2923 oprr = op_XR
2924 oprrf = op_XRK
2925 }
2926 if p.Reg == 0 {
2927 if oprr != 0 {
2928 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2929 } else {
2930 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2931 }
2932 } else {
2933 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2934 }
2935
2936 case 7:
2937 d2 := c.vregoff(&p.From)
2938 b2 := p.From.Reg
2939 r3 := p.Reg
2940 if r3 == 0 {
2941 r3 = p.To.Reg
2942 }
2943 r1 := p.To.Reg
2944 var opcode uint32
2945 switch p.As {
2946 default:
2947 case ASLD:
2948 opcode = op_SLLG
2949 case ASRD:
2950 opcode = op_SRLG
2951 case ASLW:
2952 opcode = op_SLLK
2953 case ASRW:
2954 opcode = op_SRLK
2955 case ARLL:
2956 opcode = op_RLL
2957 case ARLLG:
2958 opcode = op_RLLG
2959 case ASRAW:
2960 opcode = op_SRAK
2961 case ASRAD:
2962 opcode = op_SRAG
2963 }
2964 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm)
2965
2966 case 8:
2967 if p.To.Reg&1 != 0 {
2968 c.ctxt.Diag("target must be an even-numbered register")
2969 }
2970
2971 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2972
2973 case 9:
2974 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2975
2976 case 10:
2977 r := int(p.Reg)
2978
2979 switch p.As {
2980 default:
2981 case ASUB:
2982 if r == 0 {
2983 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2984 } else {
2985 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2986 }
2987 case ASUBC:
2988 if r == 0 {
2989 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2990 } else {
2991 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2992 }
2993 case ASUBE:
2994 if r == 0 {
2995 r = int(p.To.Reg)
2996 }
2997 if r == int(p.To.Reg) {
2998 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2999 } else if p.From.Reg == p.To.Reg {
3000 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm)
3001 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3002 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm)
3003 } else {
3004 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3005 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3006 }
3007 case ASUBW:
3008 if r == 0 {
3009 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3010 } else {
3011 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
3012 }
3013 }
3014
3015 case 11:
3016 v := int32(0)
3017
3018 if p.To.Target() != nil {
3019 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3020 }
3021
3022 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v {
3023 zRI(op_BRC, 0xF, uint32(v), asm)
3024 } else {
3025 if p.As == ABL {
3026 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm)
3027 } else {
3028 zRIL(_c, op_BRCL, 0xF, uint32(v), asm)
3029 }
3030 if p.To.Sym != nil {
3031 c.addcallreloc(p.To.Sym, p.To.Offset)
3032 }
3033 }
3034
3035 case 12:
3036 r1 := p.To.Reg
3037 d2 := c.vregoff(&p.From)
3038 b2 := p.From.Reg
3039 if b2 == 0 {
3040 b2 = REGSP
3041 }
3042 x2 := p.From.Index
3043 if -DISP20/2 > d2 || d2 >= DISP20/2 {
3044 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3045 if x2 != 0 {
3046 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3047 }
3048 x2 = int16(regtmp(p))
3049 d2 = 0
3050 }
3051 var opx, opxy uint32
3052 switch p.As {
3053 case AADD:
3054 opxy = op_AG
3055 case AADDC:
3056 opxy = op_ALG
3057 case AADDE:
3058 opxy = op_ALCG
3059 case AADDW:
3060 opx = op_A
3061 opxy = op_AY
3062 case AMULLW:
3063 opx = op_MS
3064 opxy = op_MSY
3065 case AMULLD:
3066 opxy = op_MSG
3067 case ASUB:
3068 opxy = op_SG
3069 case ASUBC:
3070 opxy = op_SLG
3071 case ASUBE:
3072 opxy = op_SLBG
3073 case ASUBW:
3074 opx = op_S
3075 opxy = op_SY
3076 case AAND:
3077 opxy = op_NG
3078 case AANDW:
3079 opx = op_N
3080 opxy = op_NY
3081 case AOR:
3082 opxy = op_OG
3083 case AORW:
3084 opx = op_O
3085 opxy = op_OY
3086 case AXOR:
3087 opxy = op_XG
3088 case AXORW:
3089 opx = op_X
3090 opxy = op_XY
3091 }
3092 if opx != 0 && 0 <= d2 && d2 < DISP12 {
3093 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3094 } else {
3095 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3096 }
3097
3098 case 13:
3099 r1 := p.To.Reg
3100 r2 := p.RestArgs[2].Reg
3101 i3 := uint8(p.From.Offset)
3102 i4 := uint8(p.RestArgs[0].Offset)
3103 i5 := uint8(p.RestArgs[1].Offset)
3104 switch p.As {
3105 case ARNSBGT, ARXSBGT, AROSBGT:
3106 i3 |= 0x80
3107 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ:
3108 i4 |= 0x80
3109 }
3110 var opcode uint32
3111 switch p.As {
3112 case ARNSBG, ARNSBGT:
3113 opcode = op_RNSBG
3114 case ARXSBG, ARXSBGT:
3115 opcode = op_RXSBG
3116 case AROSBG, AROSBGT:
3117 opcode = op_ROSBG
3118 case ARISBG, ARISBGZ:
3119 opcode = op_RISBG
3120 case ARISBGN, ARISBGNZ:
3121 opcode = op_RISBGN
3122 case ARISBHG, ARISBHGZ:
3123 opcode = op_RISBHG
3124 case ARISBLG, ARISBLGZ:
3125 opcode = op_RISBLG
3126 }
3127 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm)
3128
3129 case 15:
3130 r := p.To.Reg
3131 if p.As == ABCL || p.As == ABL {
3132 zRR(op_BASR, uint32(REG_LR), uint32(r), asm)
3133 } else {
3134 zRR(op_BCR, uint32(Always), uint32(r), asm)
3135 }
3136
3137 case 16:
3138 v := int32(0)
3139 if p.To.Target() != nil {
3140 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3141 }
3142 mask := uint32(c.branchMask(p))
3143 if p.To.Sym == nil && int32(int16(v)) == v {
3144 zRI(op_BRC, mask, uint32(v), asm)
3145 } else {
3146 zRIL(_c, op_BRCL, mask, uint32(v), asm)
3147 }
3148 if p.To.Sym != nil {
3149 c.addrilreloc(p.To.Sym, p.To.Offset)
3150 }
3151
3152 case 17:
3153 m3 := uint32(c.branchMask(p))
3154 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3155
3156 case 18:
3157 if p.As == ABL {
3158 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
3159 } else {
3160 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm)
3161 }
3162
3163 case 19:
3164 d := c.vregoff(&p.From)
3165 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm)
3166 if d&1 != 0 {
3167 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm)
3168 d -= 1
3169 }
3170 c.addrilreloc(p.From.Sym, d)
3171
3172 case 21:
3173 v := c.vregoff(&p.From)
3174 r := p.Reg
3175 if r == 0 {
3176 r = p.To.Reg
3177 }
3178 switch p.As {
3179 case ASUB:
3180 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm)
3181 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm)
3182 case ASUBC:
3183 if r != p.To.Reg {
3184 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3185 }
3186 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm)
3187 case ASUBW:
3188 if r != p.To.Reg {
3189 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3190 }
3191 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm)
3192 }
3193
3194 case 22:
3195 v := c.vregoff(&p.From)
3196 r := p.Reg
3197 if r == 0 {
3198 r = p.To.Reg
3199 }
3200 var opri, opril, oprie uint32
3201 switch p.As {
3202 case AADD:
3203 opri = op_AGHI
3204 opril = op_AGFI
3205 oprie = op_AGHIK
3206 case AADDC:
3207 opril = op_ALGFI
3208 oprie = op_ALGHSIK
3209 case AADDW:
3210 opri = op_AHI
3211 opril = op_AFI
3212 oprie = op_AHIK
3213 case AMULLW:
3214 opri = op_MHI
3215 opril = op_MSFI
3216 case AMULLD:
3217 opri = op_MGHI
3218 opril = op_MSGFI
3219 }
3220 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) {
3221 switch p.As {
3222 case AADD, AADDC, AMULLD:
3223 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3224 case AADDW, AMULLW:
3225 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3226 }
3227 r = p.To.Reg
3228 }
3229 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v {
3230 zRI(opri, uint32(p.To.Reg), uint32(v), asm)
3231 } else if oprie != 0 && int64(int16(v)) == v {
3232 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
3233 } else {
3234 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm)
3235 }
3236
3237 case 23:
3238
3239 v := c.vregoff(&p.From)
3240 switch p.As {
3241 default:
3242 c.ctxt.Diag("%v is not supported", p)
3243 case AAND:
3244 if v >= 0 {
3245 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3246 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm)
3247 } else if int64(int16(v)) == v {
3248 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3249 } else {
3250 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3251 }
3252 case AOR:
3253 if int64(uint32(v)) != v {
3254 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3255 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm)
3256 } else if int64(uint16(v)) == v {
3257 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3258 } else {
3259 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3260 }
3261 case AXOR:
3262 if int64(uint32(v)) != v {
3263 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3264 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm)
3265 } else {
3266 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3267 }
3268 }
3269
3270 case 24:
3271 v := c.vregoff(&p.From)
3272 switch p.As {
3273 case AANDW:
3274 if uint32(v&0xffff0000) == 0xffff0000 {
3275 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3276 } else if uint32(v&0x0000ffff) == 0x0000ffff {
3277 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3278 } else {
3279 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3280 }
3281 case AORW:
3282 if uint32(v&0xffff0000) == 0 {
3283 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3284 } else if uint32(v&0x0000ffff) == 0 {
3285 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3286 } else {
3287 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3288 }
3289 case AXORW:
3290 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3291 }
3292
3293 case 25:
3294 m3 := uint32(c.branchMask(p))
3295 var opcode uint32
3296 switch p.As {
3297 case ALOCR:
3298 opcode = op_LOCR
3299 case ALOCGR:
3300 opcode = op_LOCGR
3301 }
3302 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3303
3304 case 26:
3305 v := c.regoff(&p.From)
3306 r := p.From.Reg
3307 if r == 0 {
3308 r = REGSP
3309 }
3310 i := p.From.Index
3311 if v >= 0 && v < DISP12 {
3312 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3313 } else if v >= -DISP20/2 && v < DISP20/2 {
3314 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3315 } else {
3316 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3317 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm)
3318 }
3319
3320 case 31:
3321 wd := uint64(c.vregoff(&p.From))
3322 *asm = append(*asm,
3323 uint8(wd>>56),
3324 uint8(wd>>48),
3325 uint8(wd>>40),
3326 uint8(wd>>32),
3327 uint8(wd>>24),
3328 uint8(wd>>16),
3329 uint8(wd>>8),
3330 uint8(wd))
3331
3332 case 32:
3333 var opcode uint32
3334 switch p.As {
3335 default:
3336 c.ctxt.Diag("invalid opcode")
3337 case AFADD:
3338 opcode = op_ADBR
3339 case AFADDS:
3340 opcode = op_AEBR
3341 case AFDIV:
3342 opcode = op_DDBR
3343 case AFDIVS:
3344 opcode = op_DEBR
3345 case AFMUL:
3346 opcode = op_MDBR
3347 case AFMULS:
3348 opcode = op_MEEBR
3349 case AFSUB:
3350 opcode = op_SDBR
3351 case AFSUBS:
3352 opcode = op_SEBR
3353 }
3354 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3355
3356 case 33:
3357 r := p.From.Reg
3358 if oclass(&p.From) == C_NONE {
3359 r = p.To.Reg
3360 }
3361 var opcode uint32
3362 switch p.As {
3363 default:
3364 case AFABS:
3365 opcode = op_LPDBR
3366 case AFNABS:
3367 opcode = op_LNDBR
3368 case ALPDFR:
3369 opcode = op_LPDFR
3370 case ALNDFR:
3371 opcode = op_LNDFR
3372 case AFNEG:
3373 opcode = op_LCDFR
3374 case AFNEGS:
3375 opcode = op_LCEBR
3376 case ALEDBR:
3377 opcode = op_LEDBR
3378 case ALDEBR:
3379 opcode = op_LDEBR
3380 case AFSQRT:
3381 opcode = op_SQDBR
3382 case AFSQRTS:
3383 opcode = op_SQEBR
3384 }
3385 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3386
3387 case 34:
3388 var opcode uint32
3389 switch p.As {
3390 default:
3391 c.ctxt.Diag("invalid opcode")
3392 case AFMADD:
3393 opcode = op_MADBR
3394 case AFMADDS:
3395 opcode = op_MAEBR
3396 case AFMSUB:
3397 opcode = op_MSDBR
3398 case AFMSUBS:
3399 opcode = op_MSEBR
3400 }
3401 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
3402
3403 case 35:
3404 d2 := c.regoff(&p.To)
3405 b2 := p.To.Reg
3406 if b2 == 0 {
3407 b2 = REGSP
3408 }
3409 x2 := p.To.Index
3410 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3411 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3412 if x2 != 0 {
3413 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3414 }
3415 x2 = int16(regtmp(p))
3416 d2 = 0
3417 }
3418
3419 if op, ok := c.zopstore12(p.As); ok && isU12(d2) {
3420 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3421 } else {
3422 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3423 }
3424
3425 case 36:
3426 d2 := c.regoff(&p.From)
3427 b2 := p.From.Reg
3428 if b2 == 0 {
3429 b2 = REGSP
3430 }
3431 x2 := p.From.Index
3432 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3433 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3434 if x2 != 0 {
3435 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3436 }
3437 x2 = int16(regtmp(p))
3438 d2 = 0
3439 }
3440
3441 if op, ok := c.zopload12(p.As); ok && isU12(d2) {
3442 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3443 } else {
3444 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3445 }
3446
3447 case 40:
3448 wd := uint32(c.regoff(&p.From))
3449 if p.As == AWORD {
3450 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd))
3451 } else {
3452 *asm = append(*asm, uint8(wd))
3453 }
3454
3455 case 41:
3456 r1 := p.From.Reg
3457 ri2 := (p.To.Target().Pc - p.Pc) >> 1
3458 if int64(int16(ri2)) != ri2 {
3459 c.ctxt.Diag("branch target too far away")
3460 }
3461 var opcode uint32
3462 switch p.As {
3463 case ABRCT:
3464 opcode = op_BRCT
3465 case ABRCTG:
3466 opcode = op_BRCTG
3467 }
3468 zRI(opcode, uint32(r1), uint32(ri2), asm)
3469
3470 case 47:
3471 r := p.From.Reg
3472 if r == 0 {
3473 r = p.To.Reg
3474 }
3475 switch p.As {
3476 case ANEG:
3477 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
3478 case ANEGW:
3479 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
3480 }
3481
3482 case 48:
3483 m3 := c.vregoff(&p.From)
3484 if 0 > m3 || m3 > 7 {
3485 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3)
3486 }
3487 var opcode uint32
3488 switch p.As {
3489 case AFIEBR:
3490 opcode = op_FIEBR
3491 case AFIDBR:
3492 opcode = op_FIDBR
3493 }
3494 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3495
3496 case 49:
3497 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3498
3499 case 50:
3500 var opcode uint32
3501 switch p.As {
3502 case ALTEBR:
3503 opcode = op_LTEBR
3504 case ALTDBR:
3505 opcode = op_LTDBR
3506 }
3507 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3508
3509 case 51:
3510 var opcode uint32
3511 switch p.As {
3512 case ATCEB:
3513 opcode = op_TCEB
3514 case ATCDB:
3515 opcode = op_TCDB
3516 }
3517 d2 := c.regoff(&p.To)
3518 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm)
3519
3520 case 62:
3521 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3522
3523 case 66:
3524 zRR(op_BCR, uint32(Never), 0, asm)
3525
3526 case 67:
3527 var opcode uint32
3528 switch p.As {
3529 case AFMOVS:
3530 opcode = op_LZER
3531 case AFMOVD:
3532 opcode = op_LZDR
3533 }
3534 zRRE(opcode, uint32(p.To.Reg), 0, asm)
3535
3536 case 68:
3537 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm)
3538
3539 case 69:
3540 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm)
3541
3542 case 70:
3543 if p.As == ACMPW || p.As == ACMPWU {
3544 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3545 } else {
3546 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3547 }
3548
3549 case 71:
3550 v := c.vregoff(&p.To)
3551 switch p.As {
3552 case ACMP, ACMPW:
3553 if int64(int32(v)) != v {
3554 c.ctxt.Diag("%v overflows an int32", v)
3555 }
3556 case ACMPU, ACMPWU:
3557 if int64(uint32(v)) != v {
3558 c.ctxt.Diag("%v overflows a uint32", v)
3559 }
3560 }
3561 if p.As == ACMP && int64(int16(v)) == v {
3562 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm)
3563 } else if p.As == ACMPW && int64(int16(v)) == v {
3564 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm)
3565 } else {
3566 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm)
3567 }
3568
3569 case 72:
3570 v := c.regoff(&p.From)
3571 d := c.regoff(&p.To)
3572 r := p.To.Reg
3573 if p.To.Index != 0 {
3574 c.ctxt.Diag("cannot use index register")
3575 }
3576 if r == 0 {
3577 r = REGSP
3578 }
3579 var opcode uint32
3580 switch p.As {
3581 case AMOVD:
3582 opcode = op_MVGHI
3583 case AMOVW, AMOVWZ:
3584 opcode = op_MVHI
3585 case AMOVH, AMOVHZ:
3586 opcode = op_MVHHI
3587 case AMOVB, AMOVBZ:
3588 opcode = op_MVI
3589 }
3590 if d < 0 || d >= DISP12 {
3591 if r == int16(regtmp(p)) {
3592 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r)
3593 }
3594 if d >= -DISP20/2 && d < DISP20/2 {
3595 if opcode == op_MVI {
3596 opcode = op_MVIY
3597 } else {
3598 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm)
3599 r = int16(regtmp(p))
3600 d = 0
3601 }
3602 } else {
3603 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm)
3604 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm)
3605 r = int16(regtmp(p))
3606 d = 0
3607 }
3608 }
3609 switch opcode {
3610 case op_MVI:
3611 zSI(opcode, uint32(v), uint32(r), uint32(d), asm)
3612 case op_MVIY:
3613 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm)
3614 default:
3615 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm)
3616 }
3617
3618 case 73:
3619 zE(op_BRRK, asm)
3620
3621 case 74:
3622 i2 := c.regoff(&p.To)
3623 switch p.As {
3624 case AMOVD:
3625 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm)
3626 case AMOVW, AMOVWZ:
3627 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm)
3628 case AMOVH, AMOVHZ:
3629 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm)
3630 case AMOVB, AMOVBZ:
3631 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3632 adj := uint32(0)
3633 if i2&1 != 0 {
3634 i2 -= 1
3635 adj = 1
3636 }
3637 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm)
3638 case AFMOVD:
3639 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3640 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3641 case AFMOVS:
3642 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3643 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3644 }
3645 c.addrilreloc(p.To.Sym, int64(i2))
3646
3647 case 75:
3648 i2 := c.regoff(&p.From)
3649 switch p.As {
3650 case AMOVD:
3651 if i2&1 != 0 {
3652 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3653 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm)
3654 i2 -= 1
3655 } else {
3656 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3657 }
3658 case AMOVW:
3659 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm)
3660 case AMOVWZ:
3661 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm)
3662 case AMOVH:
3663 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm)
3664 case AMOVHZ:
3665 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm)
3666 case AMOVB, AMOVBZ:
3667 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3668 adj := uint32(0)
3669 if i2&1 != 0 {
3670 i2 -= 1
3671 adj = 1
3672 }
3673 switch p.As {
3674 case AMOVB:
3675 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3676 case AMOVBZ:
3677 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3678 }
3679 case AFMOVD:
3680 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3681 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3682 case AFMOVS:
3683 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3684 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3685 }
3686 c.addrilreloc(p.From.Sym, int64(i2))
3687
3688 case 76:
3689 zRR(op_SPM, uint32(p.From.Reg), 0, asm)
3690
3691 case 77:
3692 if p.From.Offset > 255 || p.From.Offset < 1 {
3693 c.ctxt.Diag("illegal system call; system call number out of range: %v", p)
3694 zE(op_TRAP2, asm)
3695 } else {
3696 zI(op_SVC, uint32(p.From.Offset), asm)
3697 }
3698
3699 case 78:
3700
3701
3702 *asm = append(*asm, 0, 0, 0, 0)
3703
3704 case 79:
3705 v := c.regoff(&p.To)
3706 if v < 0 {
3707 v = 0
3708 }
3709 if p.As == ACS {
3710 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3711 } else if p.As == ACSG {
3712 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3713 }
3714
3715 case 80:
3716 zRR(op_BCR, 14, 0, asm)
3717
3718 case 81:
3719 switch p.As {
3720 case ALDGR:
3721 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3722 case ALGDR:
3723 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3724 }
3725
3726 case 82:
3727 var opcode uint32
3728 switch p.As {
3729 default:
3730 log.Fatalf("unexpected opcode %v", p.As)
3731 case ACEFBRA:
3732 opcode = op_CEFBRA
3733 case ACDFBRA:
3734 opcode = op_CDFBRA
3735 case ACEGBRA:
3736 opcode = op_CEGBRA
3737 case ACDGBRA:
3738 opcode = op_CDGBRA
3739 case ACELFBR:
3740 opcode = op_CELFBR
3741 case ACDLFBR:
3742 opcode = op_CDLFBR
3743 case ACELGBR:
3744 opcode = op_CELGBR
3745 case ACDLGBR:
3746 opcode = op_CDLGBR
3747 }
3748
3749
3750
3751
3752 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3753
3754 case 83:
3755 var opcode uint32
3756 switch p.As {
3757 default:
3758 log.Fatalf("unexpected opcode %v", p.As)
3759 case ACFEBRA:
3760 opcode = op_CFEBRA
3761 case ACFDBRA:
3762 opcode = op_CFDBRA
3763 case ACGEBRA:
3764 opcode = op_CGEBRA
3765 case ACGDBRA:
3766 opcode = op_CGDBRA
3767 case ACLFEBR:
3768 opcode = op_CLFEBR
3769 case ACLFDBR:
3770 opcode = op_CLFDBR
3771 case ACLGEBR:
3772 opcode = op_CLGEBR
3773 case ACLGDBR:
3774 opcode = op_CLGDBR
3775 }
3776
3777
3778 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3779
3780 case 84:
3781 l := c.regoff(&p.From)
3782 if l < 1 || l > 256 {
3783 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l)
3784 }
3785 if p.GetFrom3().Index != 0 || p.To.Index != 0 {
3786 c.ctxt.Diag("cannot use index reg")
3787 }
3788 b1 := p.To.Reg
3789 b2 := p.GetFrom3().Reg
3790 if b1 == 0 {
3791 b1 = REGSP
3792 }
3793 if b2 == 0 {
3794 b2 = REGSP
3795 }
3796 d1 := c.regoff(&p.To)
3797 d2 := c.regoff(p.GetFrom3())
3798 if d1 < 0 || d1 >= DISP12 {
3799 if b2 == int16(regtmp(p)) {
3800 c.ctxt.Diag("regtmp(p) conflict")
3801 }
3802 if b1 != int16(regtmp(p)) {
3803 zRRE(op_LGR, regtmp(p), uint32(b1), asm)
3804 }
3805 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm)
3806 if d1 == d2 && b1 == b2 {
3807 d2 = 0
3808 b2 = int16(regtmp(p))
3809 }
3810 d1 = 0
3811 b1 = int16(regtmp(p))
3812 }
3813 if d2 < 0 || d2 >= DISP12 {
3814 if b1 == REGTMP2 {
3815 c.ctxt.Diag("REGTMP2 conflict")
3816 }
3817 if b2 != REGTMP2 {
3818 zRRE(op_LGR, REGTMP2, uint32(b2), asm)
3819 }
3820 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm)
3821 d2 = 0
3822 b2 = REGTMP2
3823 }
3824 var opcode uint32
3825 switch p.As {
3826 default:
3827 c.ctxt.Diag("unexpected opcode %v", p.As)
3828 case AMVC:
3829 opcode = op_MVC
3830 case AMVCIN:
3831 opcode = op_MVCIN
3832 case ACLC:
3833 opcode = op_CLC
3834
3835 b1, b2 = b2, b1
3836 d1, d2 = d2, d1
3837 case AXC:
3838 opcode = op_XC
3839 case AOC:
3840 opcode = op_OC
3841 case ANC:
3842 opcode = op_NC
3843 }
3844 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm)
3845
3846 case 85:
3847 v := c.regoff(&p.From)
3848 if p.From.Sym == nil {
3849 if (v & 1) != 0 {
3850 c.ctxt.Diag("cannot use LARL with odd offset: %v", v)
3851 }
3852 } else {
3853 c.addrilreloc(p.From.Sym, int64(v))
3854 v = 0
3855 }
3856 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm)
3857
3858 case 86:
3859 d := c.vregoff(&p.From)
3860 x := p.From.Index
3861 b := p.From.Reg
3862 if b == 0 {
3863 b = REGSP
3864 }
3865 switch p.As {
3866 case ALA:
3867 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3868 case ALAY:
3869 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3870 }
3871
3872 case 87:
3873 v := c.vregoff(&p.From)
3874 if p.From.Sym == nil {
3875 if v&1 != 0 {
3876 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v)
3877 }
3878 } else {
3879 c.addrilreloc(p.From.Sym, v)
3880 v = 0
3881 }
3882 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm)
3883
3884 case 88:
3885 var opcode uint32
3886 switch p.As {
3887 case ASTCK:
3888 opcode = op_STCK
3889 case ASTCKC:
3890 opcode = op_STCKC
3891 case ASTCKE:
3892 opcode = op_STCKE
3893 case ASTCKF:
3894 opcode = op_STCKF
3895 }
3896 v := c.vregoff(&p.To)
3897 r := p.To.Reg
3898 if r == 0 {
3899 r = REGSP
3900 }
3901 zS(opcode, uint32(r), uint32(v), asm)
3902
3903 case 89:
3904 var v int32
3905 if p.To.Target() != nil {
3906 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3907 }
3908
3909
3910 r1, r2 := p.From.Reg, p.Reg
3911 if p.From.Type == obj.TYPE_CONST {
3912 r1, r2 = p.Reg, p.RestArgs[0].Reg
3913 }
3914 m3 := uint32(c.branchMask(p))
3915
3916 var opcode uint32
3917 switch p.As {
3918 case ACRJ:
3919
3920 opcode = op_CRJ
3921 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3922
3923 opcode = op_CGRJ
3924 case ACLRJ:
3925
3926 opcode = op_CLRJ
3927 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3928
3929 opcode = op_CLGRJ
3930 }
3931
3932 if int32(int16(v)) != v {
3933
3934
3935
3936
3937
3938
3939
3940
3941 m3 ^= 0xe
3942 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm)
3943 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3944 } else {
3945 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm)
3946 }
3947
3948 case 90:
3949 var v int32
3950 if p.To.Target() != nil {
3951 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3952 }
3953
3954
3955 r1, i2 := p.From.Reg, p.RestArgs[0].Offset
3956 if p.From.Type == obj.TYPE_CONST {
3957 r1 = p.Reg
3958 }
3959 m3 := uint32(c.branchMask(p))
3960
3961 var opcode uint32
3962 switch p.As {
3963 case ACIJ:
3964 opcode = op_CIJ
3965 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3966 opcode = op_CGIJ
3967 case ACLIJ:
3968 opcode = op_CLIJ
3969 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3970 opcode = op_CLGIJ
3971 }
3972 if int32(int16(v)) != v {
3973
3974
3975
3976
3977
3978
3979
3980
3981 m3 ^= 0xe
3982 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm)
3983 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3984 } else {
3985 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm)
3986 }
3987
3988 case 91:
3989 var opcode uint32
3990 switch p.As {
3991 case ATMHH:
3992 opcode = op_TMHH
3993 case ATMHL:
3994 opcode = op_TMHL
3995 case ATMLH:
3996 opcode = op_TMLH
3997 case ATMLL:
3998 opcode = op_TMLL
3999 }
4000 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
4001
4002 case 92:
4003 zRRE(op_IPM, uint32(p.From.Reg), 0, asm)
4004
4005 case 93:
4006 v := c.vregoff(&p.To)
4007 if v != 0 {
4008 c.ctxt.Diag("invalid offset against GOT slot %v", p)
4009 }
4010 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
4011 c.cursym.AddRel(c.ctxt, obj.Reloc{
4012 Type: objabi.R_GOTPCREL,
4013 Off: int32(c.pc + 2),
4014 Siz: 4,
4015 Sym: p.From.Sym,
4016 Add: 2 + 4,
4017 })
4018
4019 case 94:
4020 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm)
4021 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4022 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm)
4023 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0)
4024 c.cursym.AddRel(c.ctxt, obj.Reloc{
4025 Type: objabi.R_TLS_LE,
4026 Off: int32(c.pc + sizeRIL + sizeRXY + sizeRI),
4027 Siz: 8,
4028 Sym: p.From.Sym,
4029 })
4030
4031 case 95:
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043 zRIL(_b, op_LARL, regtmp(p), 0, asm)
4044 c.cursym.AddRel(c.ctxt, obj.Reloc{
4045 Type: objabi.R_TLS_IE,
4046 Off: int32(c.pc + 2),
4047 Siz: 4,
4048 Sym: p.From.Sym,
4049 Add: 2 + 4,
4050 })
4051
4052
4053 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4054
4055
4056
4057 case 96:
4058 length := c.vregoff(&p.From)
4059 offset := c.vregoff(&p.To)
4060 reg := p.To.Reg
4061 if reg == 0 {
4062 reg = REGSP
4063 }
4064 if length <= 0 {
4065 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length)
4066 }
4067 for length > 0 {
4068 if offset < 0 || offset >= DISP12 {
4069 if offset >= -DISP20/2 && offset < DISP20/2 {
4070 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm)
4071 } else {
4072 if reg != int16(regtmp(p)) {
4073 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4074 }
4075 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4076 }
4077 reg = int16(regtmp(p))
4078 offset = 0
4079 }
4080 size := length
4081 if size > 256 {
4082 size = 256
4083 }
4084
4085 switch size {
4086 case 1:
4087 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm)
4088 case 2:
4089 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm)
4090 case 4:
4091 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm)
4092 case 8:
4093 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm)
4094 default:
4095 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm)
4096 }
4097
4098 length -= size
4099 offset += size
4100 }
4101
4102 case 97:
4103 rstart := p.From.Reg
4104 rend := p.Reg
4105 offset := c.regoff(&p.To)
4106 reg := p.To.Reg
4107 if reg == 0 {
4108 reg = REGSP
4109 }
4110 if offset < -DISP20/2 || offset >= DISP20/2 {
4111 if reg != int16(regtmp(p)) {
4112 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4113 }
4114 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4115 reg = int16(regtmp(p))
4116 offset = 0
4117 }
4118 switch p.As {
4119 case ASTMY:
4120 if offset >= 0 && offset < DISP12 {
4121 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4122 } else {
4123 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4124 }
4125 case ASTMG:
4126 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4127 }
4128
4129 case 98:
4130 rstart := p.Reg
4131 rend := p.To.Reg
4132 offset := c.regoff(&p.From)
4133 reg := p.From.Reg
4134 if reg == 0 {
4135 reg = REGSP
4136 }
4137 if offset < -DISP20/2 || offset >= DISP20/2 {
4138 if reg != int16(regtmp(p)) {
4139 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4140 }
4141 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4142 reg = int16(regtmp(p))
4143 offset = 0
4144 }
4145 switch p.As {
4146 case ALMY:
4147 if offset >= 0 && offset < DISP12 {
4148 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4149 } else {
4150 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4151 }
4152 case ALMG:
4153 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4154 }
4155
4156 case 99:
4157 if p.To.Index != 0 {
4158 c.ctxt.Diag("cannot use indexed address")
4159 }
4160 offset := c.regoff(&p.To)
4161 if offset < -DISP20/2 || offset >= DISP20/2 {
4162 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset)
4163 }
4164 var opcode uint32
4165 switch p.As {
4166 case ALAA:
4167 opcode = op_LAA
4168 case ALAAG:
4169 opcode = op_LAAG
4170 case ALAAL:
4171 opcode = op_LAAL
4172 case ALAALG:
4173 opcode = op_LAALG
4174 case ALAN:
4175 opcode = op_LAN
4176 case ALANG:
4177 opcode = op_LANG
4178 case ALAX:
4179 opcode = op_LAX
4180 case ALAXG:
4181 opcode = op_LAXG
4182 case ALAO:
4183 opcode = op_LAO
4184 case ALAOG:
4185 opcode = op_LAOG
4186 }
4187 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm)
4188
4189 case 100:
4190 op, m3, _ := vop(p.As)
4191 v1 := p.From.Reg
4192 if p.Reg != 0 {
4193 m3 = uint32(c.vregoff(&p.From))
4194 v1 = p.Reg
4195 }
4196 b2 := p.To.Reg
4197 if b2 == 0 {
4198 b2 = REGSP
4199 }
4200 d2 := uint32(c.vregoff(&p.To))
4201 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4202
4203 case 101:
4204 op, m3, _ := vop(p.As)
4205 src := &p.From
4206 if p.GetFrom3() != nil {
4207 m3 = uint32(c.vregoff(&p.From))
4208 src = p.GetFrom3()
4209 }
4210 b2 := src.Reg
4211 if b2 == 0 {
4212 b2 = REGSP
4213 }
4214 d2 := uint32(c.vregoff(src))
4215 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm)
4216
4217 case 102:
4218 op, _, _ := vop(p.As)
4219 m3 := uint32(c.vregoff(&p.From))
4220 b2 := p.To.Reg
4221 if b2 == 0 {
4222 b2 = REGSP
4223 }
4224 d2 := uint32(c.vregoff(&p.To))
4225 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4226
4227 case 103:
4228 op, _, _ := vop(p.As)
4229 m3 := uint32(c.vregoff(&p.From))
4230 b2 := p.GetFrom3().Reg
4231 if b2 == 0 {
4232 b2 = REGSP
4233 }
4234 d2 := uint32(c.vregoff(p.GetFrom3()))
4235 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm)
4236
4237 case 104:
4238 op, m4, _ := vop(p.As)
4239 fr := p.Reg
4240 if fr == 0 {
4241 fr = p.To.Reg
4242 }
4243 bits := uint32(c.vregoff(&p.From))
4244 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm)
4245
4246 case 105:
4247 op, _, _ := vop(p.As)
4248 offset := uint32(c.vregoff(&p.To))
4249 reg := p.To.Reg
4250 if reg == 0 {
4251 reg = REGSP
4252 }
4253 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm)
4254
4255 case 106:
4256 op, _, _ := vop(p.As)
4257 offset := uint32(c.vregoff(&p.From))
4258 reg := p.From.Reg
4259 if reg == 0 {
4260 reg = REGSP
4261 }
4262 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm)
4263
4264 case 107:
4265 op, _, _ := vop(p.As)
4266 offset := uint32(c.vregoff(&p.To))
4267 reg := p.To.Reg
4268 if reg == 0 {
4269 reg = REGSP
4270 }
4271 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4272
4273 case 108:
4274 op, _, _ := vop(p.As)
4275 offset := uint32(c.vregoff(p.GetFrom3()))
4276 reg := p.GetFrom3().Reg
4277 if reg == 0 {
4278 reg = REGSP
4279 }
4280 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4281
4282 case 109:
4283 op, m3, _ := vop(p.As)
4284 i2 := uint32(c.vregoff(&p.From))
4285 if p.GetFrom3() != nil {
4286 m3 = uint32(c.vregoff(&p.From))
4287 i2 = uint32(c.vregoff(p.GetFrom3()))
4288 }
4289 switch p.As {
4290 case AVZERO:
4291 i2 = 0
4292 case AVONE:
4293 i2 = 0xffff
4294 }
4295 zVRIa(op, uint32(p.To.Reg), i2, m3, asm)
4296
4297 case 110:
4298 op, m4, _ := vop(p.As)
4299 i2 := uint32(c.vregoff(&p.From))
4300 i3 := uint32(c.vregoff(p.GetFrom3()))
4301 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm)
4302
4303 case 111:
4304 op, m4, _ := vop(p.As)
4305 i2 := uint32(c.vregoff(&p.From))
4306 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm)
4307
4308 case 112:
4309 op, m5, _ := vop(p.As)
4310 i4 := uint32(c.vregoff(&p.From))
4311 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm)
4312
4313 case 113:
4314 op, m4, _ := vop(p.As)
4315 m5 := singleElementMask(p.As)
4316 i3 := uint32(c.vregoff(&p.From))
4317 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm)
4318
4319 case 114:
4320 op, m3, m5 := vop(p.As)
4321 m4 := singleElementMask(p.As)
4322 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm)
4323
4324 case 115:
4325 op, m3, m5 := vop(p.As)
4326 m4 := singleElementMask(p.As)
4327 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm)
4328
4329 case 117:
4330 op, m4, m5 := vop(p.As)
4331 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm)
4332
4333 case 118:
4334 op, m4, m6 := vop(p.As)
4335 m5 := singleElementMask(p.As)
4336 v3 := p.Reg
4337 if v3 == 0 {
4338 v3 = p.To.Reg
4339 }
4340 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm)
4341
4342 case 119:
4343 op, m4, m6 := vop(p.As)
4344 m5 := singleElementMask(p.As)
4345 v2 := p.Reg
4346 if v2 == 0 {
4347 v2 = p.To.Reg
4348 }
4349 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
4350
4351 case 120:
4352 op, m6, m5 := vop(p.As)
4353 v1 := uint32(p.To.Reg)
4354 v2 := uint32(p.From.Reg)
4355 v3 := uint32(p.Reg)
4356 v4 := uint32(p.GetFrom3().Reg)
4357 zVRRd(op, v1, v2, v3, m6, m5, v4, asm)
4358
4359 case 121:
4360 op, m6, _ := vop(p.As)
4361 m5 := singleElementMask(p.As)
4362 v1 := uint32(p.To.Reg)
4363 v2 := uint32(p.From.Reg)
4364 v3 := uint32(p.Reg)
4365 v4 := uint32(p.GetFrom3().Reg)
4366 zVRRe(op, v1, v2, v3, m6, m5, v4, asm)
4367
4368 case 122:
4369 op, _, _ := vop(p.As)
4370 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
4371
4372 case 123:
4373 op, _, _ := vop(p.As)
4374 m4 := c.regoff(&p.From)
4375 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm)
4376
4377 case 124:
4378 var opcode uint32
4379 switch p.As {
4380 default:
4381 c.ctxt.Diag("unexpected opcode %v", p.As)
4382 case AKM, AKMC, AKLMD:
4383 if p.From.Reg == REG_R0 {
4384 c.ctxt.Diag("input must not be R0 in %v", p)
4385 }
4386 if p.From.Reg&1 != 0 {
4387 c.ctxt.Diag("input must be even register in %v", p)
4388 }
4389 if p.To.Reg == REG_R0 {
4390 c.ctxt.Diag("second argument must not be R0 in %v", p)
4391 }
4392 if p.To.Reg&1 != 0 {
4393 c.ctxt.Diag("second argument must be even register in %v", p)
4394 }
4395 if p.As == AKM {
4396 opcode = op_KM
4397 } else if p.As == AKMC {
4398 opcode = op_KMC
4399 } else {
4400 opcode = op_KLMD
4401 }
4402 case AKIMD:
4403 if p.To.Reg == REG_R0 {
4404 c.ctxt.Diag("second argument must not be R0 in %v", p)
4405 }
4406 if p.To.Reg&1 != 0 {
4407 c.ctxt.Diag("second argument must be even register in %v", p)
4408 }
4409 opcode = op_KIMD
4410 }
4411 zRRE(opcode, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4412
4413 case 125:
4414 if p.To.Reg == REG_R0 {
4415 c.ctxt.Diag("second argument must not be R0 in %v", p)
4416 }
4417 if p.To.Reg&1 != 0 {
4418 c.ctxt.Diag("second argument must be an even register in %v", p)
4419 }
4420 zRRE(op_KDSA, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4421
4422 case 126:
4423 var opcode uint32
4424 switch p.As {
4425 default:
4426 c.ctxt.Diag("unexpected opcode %v", p.As)
4427 case AKMA, AKMCTR:
4428 if p.From.Reg == REG_R0 {
4429 c.ctxt.Diag("input argument must not be R0 in %v", p)
4430 }
4431 if p.From.Reg&1 != 0 {
4432 c.ctxt.Diag("input argument must be even register in %v", p)
4433 }
4434 if p.To.Reg == REG_R0 {
4435 c.ctxt.Diag("output argument must not be R0 in %v", p)
4436 }
4437 if p.To.Reg&1 != 0 {
4438 c.ctxt.Diag("output argument must be an even register in %v", p)
4439 }
4440 if p.Reg == REG_R0 {
4441 c.ctxt.Diag("third argument must not be R0 in %v", p)
4442 }
4443 if p.Reg&1 != 0 {
4444 c.ctxt.Diag("third argument must be even register in %v", p)
4445 }
4446 if p.As == AKMA {
4447 opcode = op_KMA
4448 } else if p.As == AKMCTR {
4449 opcode = op_KMCTR
4450 }
4451 }
4452 zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4453 }
4454 }
4455
4456 func (c *ctxtz) vregoff(a *obj.Addr) int64 {
4457 c.instoffset = 0
4458 if a != nil {
4459 c.aclass(a)
4460 }
4461 return c.instoffset
4462 }
4463
4464 func (c *ctxtz) regoff(a *obj.Addr) int32 {
4465 return int32(c.vregoff(a))
4466 }
4467
4468
4469 func isU12(displacement int32) bool {
4470 return displacement >= 0 && displacement < DISP12
4471 }
4472
4473
4474 func (c *ctxtz) zopload12(a obj.As) (uint32, bool) {
4475 switch a {
4476 case AFMOVD:
4477 return op_LD, true
4478 case AFMOVS:
4479 return op_LE, true
4480 }
4481 return 0, false
4482 }
4483
4484
4485 func (c *ctxtz) zopload(a obj.As) uint32 {
4486 switch a {
4487
4488 case AMOVD:
4489 return op_LG
4490 case AMOVW:
4491 return op_LGF
4492 case AMOVWZ:
4493 return op_LLGF
4494 case AMOVH:
4495 return op_LGH
4496 case AMOVHZ:
4497 return op_LLGH
4498 case AMOVB:
4499 return op_LGB
4500 case AMOVBZ:
4501 return op_LLGC
4502
4503
4504 case AFMOVD:
4505 return op_LDY
4506 case AFMOVS:
4507 return op_LEY
4508
4509
4510 case AMOVDBR:
4511 return op_LRVG
4512 case AMOVWBR:
4513 return op_LRV
4514 case AMOVHBR:
4515 return op_LRVH
4516 }
4517
4518 c.ctxt.Diag("unknown store opcode %v", a)
4519 return 0
4520 }
4521
4522
4523 func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) {
4524 switch a {
4525 case AFMOVD:
4526 return op_STD, true
4527 case AFMOVS:
4528 return op_STE, true
4529 case AMOVW, AMOVWZ:
4530 return op_ST, true
4531 case AMOVH, AMOVHZ:
4532 return op_STH, true
4533 case AMOVB, AMOVBZ:
4534 return op_STC, true
4535 }
4536 return 0, false
4537 }
4538
4539
4540 func (c *ctxtz) zopstore(a obj.As) uint32 {
4541 switch a {
4542
4543 case AMOVD:
4544 return op_STG
4545 case AMOVW, AMOVWZ:
4546 return op_STY
4547 case AMOVH, AMOVHZ:
4548 return op_STHY
4549 case AMOVB, AMOVBZ:
4550 return op_STCY
4551
4552
4553 case AFMOVD:
4554 return op_STDY
4555 case AFMOVS:
4556 return op_STEY
4557
4558
4559 case AMOVDBR:
4560 return op_STRVG
4561 case AMOVWBR:
4562 return op_STRV
4563 case AMOVHBR:
4564 return op_STRVH
4565 }
4566
4567 c.ctxt.Diag("unknown store opcode %v", a)
4568 return 0
4569 }
4570
4571
4572 func (c *ctxtz) zoprre(a obj.As) uint32 {
4573 switch a {
4574 case ACMP:
4575 return op_CGR
4576 case ACMPU:
4577 return op_CLGR
4578 case AFCMPO:
4579 return op_KDBR
4580 case AFCMPU:
4581 return op_CDBR
4582 case ACEBR:
4583 return op_CEBR
4584 }
4585 c.ctxt.Diag("unknown rre opcode %v", a)
4586 return 0
4587 }
4588
4589
4590 func (c *ctxtz) zoprr(a obj.As) uint32 {
4591 switch a {
4592 case ACMPW:
4593 return op_CR
4594 case ACMPWU:
4595 return op_CLR
4596 }
4597 c.ctxt.Diag("unknown rr opcode %v", a)
4598 return 0
4599 }
4600
4601
4602 func (c *ctxtz) zopril(a obj.As) uint32 {
4603 switch a {
4604 case ACMP:
4605 return op_CGFI
4606 case ACMPU:
4607 return op_CLGFI
4608 case ACMPW:
4609 return op_CFI
4610 case ACMPWU:
4611 return op_CLFI
4612 }
4613 c.ctxt.Diag("unknown ril opcode %v", a)
4614 return 0
4615 }
4616
4617
4618 const (
4619 sizeE = 2
4620 sizeI = 2
4621 sizeIE = 4
4622 sizeMII = 6
4623 sizeRI = 4
4624 sizeRI1 = 4
4625 sizeRI2 = 4
4626 sizeRI3 = 4
4627 sizeRIE = 6
4628 sizeRIE1 = 6
4629 sizeRIE2 = 6
4630 sizeRIE3 = 6
4631 sizeRIE4 = 6
4632 sizeRIE5 = 6
4633 sizeRIE6 = 6
4634 sizeRIL = 6
4635 sizeRIL1 = 6
4636 sizeRIL2 = 6
4637 sizeRIL3 = 6
4638 sizeRIS = 6
4639 sizeRR = 2
4640 sizeRRD = 4
4641 sizeRRE = 4
4642 sizeRRF = 4
4643 sizeRRF1 = 4
4644 sizeRRF2 = 4
4645 sizeRRF3 = 4
4646 sizeRRF4 = 4
4647 sizeRRF5 = 4
4648 sizeRRR = 2
4649 sizeRRS = 6
4650 sizeRS = 4
4651 sizeRS1 = 4
4652 sizeRS2 = 4
4653 sizeRSI = 4
4654 sizeRSL = 6
4655 sizeRSY = 6
4656 sizeRSY1 = 6
4657 sizeRSY2 = 6
4658 sizeRX = 4
4659 sizeRX1 = 4
4660 sizeRX2 = 4
4661 sizeRXE = 6
4662 sizeRXF = 6
4663 sizeRXY = 6
4664 sizeRXY1 = 6
4665 sizeRXY2 = 6
4666 sizeS = 4
4667 sizeSI = 4
4668 sizeSIL = 6
4669 sizeSIY = 6
4670 sizeSMI = 6
4671 sizeSS = 6
4672 sizeSS1 = 6
4673 sizeSS2 = 6
4674 sizeSS3 = 6
4675 sizeSS4 = 6
4676 sizeSS5 = 6
4677 sizeSS6 = 6
4678 sizeSSE = 6
4679 sizeSSF = 6
4680 )
4681
4682
4683 type form int
4684
4685 const (
4686 _a form = iota
4687 _b
4688 _c
4689 _d
4690 _e
4691 _f
4692 )
4693
4694 func zE(op uint32, asm *[]byte) {
4695 *asm = append(*asm, uint8(op>>8), uint8(op))
4696 }
4697
4698 func zI(op, i1 uint32, asm *[]byte) {
4699 *asm = append(*asm, uint8(op>>8), uint8(i1))
4700 }
4701
4702 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) {
4703 *asm = append(*asm,
4704 uint8(op>>8),
4705 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F),
4706 uint8(ri2),
4707 uint8(ri3>>16),
4708 uint8(ri3>>8),
4709 uint8(ri3))
4710 }
4711
4712 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4713 *asm = append(*asm,
4714 uint8(op>>8),
4715 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4716 uint8(i2_ri2>>8),
4717 uint8(i2_ri2))
4718 }
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) {
4732 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F))
4733
4734 switch f {
4735 default:
4736 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2))
4737 case _f:
4738 *asm = append(*asm, uint8(i3), uint8(i4))
4739 }
4740
4741 switch f {
4742 case _a, _b:
4743 *asm = append(*asm, uint8(m3)<<4)
4744 default:
4745 *asm = append(*asm, uint8(i2_i5))
4746 }
4747
4748 *asm = append(*asm, uint8(op))
4749 }
4750
4751 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4752 if f == _a || f == _b {
4753 r1_m1 = r1_m1 - obj.RBaseS390X
4754 }
4755 *asm = append(*asm,
4756 uint8(op>>8),
4757 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4758 uint8(i2_ri2>>24),
4759 uint8(i2_ri2>>16),
4760 uint8(i2_ri2>>8),
4761 uint8(i2_ri2))
4762 }
4763
4764 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) {
4765 *asm = append(*asm,
4766 uint8(op>>8),
4767 (uint8(r1)<<4)|uint8(m3&0x0F),
4768 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F),
4769 uint8(d4),
4770 uint8(i2),
4771 uint8(op))
4772 }
4773
4774 func zRR(op, r1, r2 uint32, asm *[]byte) {
4775 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F))
4776 }
4777
4778 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) {
4779 *asm = append(*asm,
4780 uint8(op>>8),
4781 uint8(op),
4782 uint8(r1)<<4,
4783 (uint8(r3)<<4)|uint8(r2&0x0F))
4784 }
4785
4786 func zRRE(op, r1, r2 uint32, asm *[]byte) {
4787 *asm = append(*asm,
4788 uint8(op>>8),
4789 uint8(op),
4790 0,
4791 (uint8(r1)<<4)|uint8(r2&0x0F))
4792 }
4793
4794 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) {
4795 *asm = append(*asm,
4796 uint8(op>>8),
4797 uint8(op),
4798 (uint8(r3_m3)<<4)|uint8(m4&0x0F),
4799 (uint8(r1)<<4)|uint8(r2&0x0F))
4800 }
4801
4802 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) {
4803 *asm = append(*asm,
4804 uint8(op>>8),
4805 (uint8(r1)<<4)|uint8(r2&0x0F),
4806 (uint8(b4)<<4)|uint8((d4>>8)&0x0F),
4807 uint8(d4),
4808 uint8(m3)<<4,
4809 uint8(op))
4810 }
4811
4812 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4813 *asm = append(*asm,
4814 uint8(op>>8),
4815 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4816 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4817 uint8(d2))
4818 }
4819
4820 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) {
4821 *asm = append(*asm,
4822 uint8(op>>8),
4823 (uint8(r1)<<4)|uint8(r3&0x0F),
4824 uint8(ri2>>8),
4825 uint8(ri2))
4826 }
4827
4828 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) {
4829 *asm = append(*asm,
4830 uint8(op>>8),
4831 uint8(l1),
4832 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4833 uint8(d2),
4834 uint8(op))
4835 }
4836
4837 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4838 dl2 := uint16(d2) & 0x0FFF
4839 *asm = append(*asm,
4840 uint8(op>>8),
4841 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4842 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4843 uint8(dl2),
4844 uint8(d2>>12),
4845 uint8(op))
4846 }
4847
4848 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4849 *asm = append(*asm,
4850 uint8(op>>8),
4851 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4852 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4853 uint8(d2))
4854 }
4855
4856 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) {
4857 *asm = append(*asm,
4858 uint8(op>>8),
4859 (uint8(r1)<<4)|uint8(x2&0x0F),
4860 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4861 uint8(d2),
4862 uint8(m3)<<4,
4863 uint8(op))
4864 }
4865
4866 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) {
4867 *asm = append(*asm,
4868 uint8(op>>8),
4869 (uint8(r3)<<4)|uint8(x2&0x0F),
4870 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4871 uint8(d2),
4872 uint8(m1)<<4,
4873 uint8(op))
4874 }
4875
4876 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4877 dl2 := uint16(d2) & 0x0FFF
4878 *asm = append(*asm,
4879 uint8(op>>8),
4880 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4881 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4882 uint8(dl2),
4883 uint8(d2>>12),
4884 uint8(op))
4885 }
4886
4887 func zS(op, b2, d2 uint32, asm *[]byte) {
4888 *asm = append(*asm,
4889 uint8(op>>8),
4890 uint8(op),
4891 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4892 uint8(d2))
4893 }
4894
4895 func zSI(op, i2, b1, d1 uint32, asm *[]byte) {
4896 *asm = append(*asm,
4897 uint8(op>>8),
4898 uint8(i2),
4899 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4900 uint8(d1))
4901 }
4902
4903 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) {
4904 *asm = append(*asm,
4905 uint8(op>>8),
4906 uint8(op),
4907 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4908 uint8(d1),
4909 uint8(i2>>8),
4910 uint8(i2))
4911 }
4912
4913 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) {
4914 dl1 := uint16(d1) & 0x0FFF
4915 *asm = append(*asm,
4916 uint8(op>>8),
4917 uint8(i2),
4918 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F),
4919 uint8(dl1),
4920 uint8(d1>>12),
4921 uint8(op))
4922 }
4923
4924 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) {
4925 *asm = append(*asm,
4926 uint8(op>>8),
4927 uint8(m1)<<4,
4928 (uint8(b3)<<4)|uint8((d3>>8)&0x0F),
4929 uint8(d3),
4930 uint8(ri2>>8),
4931 uint8(ri2))
4932 }
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) {
4945 *asm = append(*asm, uint8(op>>8))
4946
4947 switch f {
4948 case _a:
4949 *asm = append(*asm, uint8(l1_r1))
4950 case _b, _c, _d, _e:
4951 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F))
4952 case _f:
4953 *asm = append(*asm, uint8(l2_i3_r3))
4954 }
4955
4956 *asm = append(*asm,
4957 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F),
4958 uint8(d1_d2),
4959 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F),
4960 uint8(d2_d4))
4961 }
4962
4963 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) {
4964 *asm = append(*asm,
4965 uint8(op>>8),
4966 uint8(op),
4967 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4968 uint8(d1),
4969 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4970 uint8(d2))
4971 }
4972
4973 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) {
4974 *asm = append(*asm,
4975 uint8(op>>8),
4976 (uint8(r3)<<4)|(uint8(op)&0x0F),
4977 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4978 uint8(d1),
4979 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4980 uint8(d2))
4981 }
4982
4983 func rxb(va, vb, vc, vd uint32) uint8 {
4984 mask := uint8(0)
4985 if va >= REG_V16 && va <= REG_V31 {
4986 mask |= 0x8
4987 }
4988 if vb >= REG_V16 && vb <= REG_V31 {
4989 mask |= 0x4
4990 }
4991 if vc >= REG_V16 && vc <= REG_V31 {
4992 mask |= 0x2
4993 }
4994 if vd >= REG_V16 && vd <= REG_V31 {
4995 mask |= 0x1
4996 }
4997 return mask
4998 }
4999
5000 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) {
5001 *asm = append(*asm,
5002 uint8(op>>8),
5003 (uint8(v1)<<4)|(uint8(x2)&0xf),
5004 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5005 uint8(d2),
5006 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5007 uint8(op))
5008 }
5009
5010 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) {
5011 *asm = append(*asm,
5012 uint8(op>>8),
5013 (uint8(v1)<<4)|(uint8(v2)&0xf),
5014 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5015 uint8(d2),
5016 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
5017 uint8(op))
5018 }
5019
5020 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) {
5021 *asm = append(*asm,
5022 uint8(op>>8),
5023 (uint8(v1)<<4)|(uint8(v3_r3)&0xf),
5024 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5025 uint8(d2),
5026 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0),
5027 uint8(op))
5028 }
5029
5030 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) {
5031 *asm = append(*asm,
5032 uint8(op>>8),
5033 (uint8(v1)<<4)|(uint8(v2)&0xf),
5034 0,
5035 (uint8(m5)<<4)|(uint8(m4)&0xf),
5036 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
5037 uint8(op))
5038 }
5039
5040 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) {
5041 *asm = append(*asm,
5042 uint8(op>>8),
5043 (uint8(v1)<<4)|(uint8(v2)&0xf),
5044 uint8(v3)<<4,
5045 uint8(m5)<<4,
5046 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5047 uint8(op))
5048 }
5049
5050 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) {
5051 *asm = append(*asm,
5052 uint8(op>>8),
5053 (uint8(v1)<<4)|(uint8(v2)&0xf),
5054 uint8(v3)<<4,
5055 (uint8(m6)<<4)|(uint8(m5)&0xf),
5056 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5057 uint8(op))
5058 }
5059
5060 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) {
5061 *asm = append(*asm,
5062 uint8(op>>8),
5063 (uint8(v1)<<4)|(uint8(v2)&0xf),
5064 (uint8(v3)<<4)|(uint8(m5)&0xf),
5065 uint8(m6)<<4,
5066 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5067 uint8(op))
5068 }
5069
5070 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) {
5071 *asm = append(*asm,
5072 uint8(op>>8),
5073 (uint8(v1)<<4)|(uint8(v2)&0xf),
5074 (uint8(v3)<<4)|(uint8(m6)&0xf),
5075 uint8(m5),
5076 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5077 uint8(op))
5078 }
5079
5080 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) {
5081 *asm = append(*asm,
5082 uint8(op>>8),
5083 (uint8(v1)<<4)|(uint8(r2)&0xf),
5084 uint8(r3)<<4,
5085 0,
5086 rxb(v1, 0, 0, 0),
5087 uint8(op))
5088 }
5089
5090 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) {
5091 *asm = append(*asm,
5092 uint8(op>>8),
5093 uint8(v1)<<4,
5094 uint8(i2>>8),
5095 uint8(i2),
5096 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5097 uint8(op))
5098 }
5099
5100 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) {
5101 *asm = append(*asm,
5102 uint8(op>>8),
5103 uint8(v1)<<4,
5104 uint8(i2),
5105 uint8(i3),
5106 (uint8(m4)<<4)|rxb(v1, 0, 0, 0),
5107 uint8(op))
5108 }
5109
5110 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) {
5111 *asm = append(*asm,
5112 uint8(op>>8),
5113 (uint8(v1)<<4)|(uint8(v3)&0xf),
5114 uint8(i2>>8),
5115 uint8(i2),
5116 (uint8(m4)<<4)|rxb(v1, v3, 0, 0),
5117 uint8(op))
5118 }
5119
5120 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) {
5121 *asm = append(*asm,
5122 uint8(op>>8),
5123 (uint8(v1)<<4)|(uint8(v2)&0xf),
5124 uint8(v3)<<4,
5125 uint8(i4),
5126 (uint8(m5)<<4)|rxb(v1, v2, v3, 0),
5127 uint8(op))
5128 }
5129
5130 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) {
5131 *asm = append(*asm,
5132 uint8(op>>8),
5133 (uint8(v1)<<4)|(uint8(v2)&0xf),
5134 uint8(i3>>4),
5135 (uint8(i3)<<4)|(uint8(m5)&0xf),
5136 (uint8(m4)<<4)|rxb(v1, v2, 0, 0),
5137 uint8(op))
5138 }
5139
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