Source file src/cmd/vendor/golang.org/x/arch/loong64/loong64asm/tables.go

     1  // Code generated by loong64spec LoongArch-Vol1-EN.pdf, DO NOT EDIT.
     2  
     3  // Copyright 2024 The Go Authors. All rights reserved.
     4  // Use of this source code is governed by a BSD-style
     5  // license that can be found in the LICENSE file.
     6  
     7  package loong64asm
     8  
     9  const (
    10  	_ Op = iota
    11  	ADDI_D
    12  	ADDI_W
    13  	ADDU16I_D
    14  	ADD_D
    15  	ADD_W
    16  	ALSL_D
    17  	ALSL_W
    18  	ALSL_WU
    19  	AMADD_B
    20  	AMADD_D
    21  	AMADD_DB_B
    22  	AMADD_DB_D
    23  	AMADD_DB_H
    24  	AMADD_DB_W
    25  	AMADD_H
    26  	AMADD_W
    27  	AMAND_D
    28  	AMAND_DB_D
    29  	AMAND_DB_W
    30  	AMAND_W
    31  	AMCAS_B
    32  	AMCAS_D
    33  	AMCAS_DB_B
    34  	AMCAS_DB_D
    35  	AMCAS_DB_H
    36  	AMCAS_DB_W
    37  	AMCAS_H
    38  	AMCAS_W
    39  	AMMAX_D
    40  	AMMAX_DB_D
    41  	AMMAX_DB_DU
    42  	AMMAX_DB_W
    43  	AMMAX_DB_WU
    44  	AMMAX_DU
    45  	AMMAX_W
    46  	AMMAX_WU
    47  	AMMIN_D
    48  	AMMIN_DB_D
    49  	AMMIN_DB_DU
    50  	AMMIN_DB_W
    51  	AMMIN_DB_WU
    52  	AMMIN_DU
    53  	AMMIN_W
    54  	AMMIN_WU
    55  	AMOR_D
    56  	AMOR_DB_D
    57  	AMOR_DB_W
    58  	AMOR_W
    59  	AMSWAP_B
    60  	AMSWAP_D
    61  	AMSWAP_DB_B
    62  	AMSWAP_DB_D
    63  	AMSWAP_DB_H
    64  	AMSWAP_DB_W
    65  	AMSWAP_H
    66  	AMSWAP_W
    67  	AMXOR_D
    68  	AMXOR_DB_D
    69  	AMXOR_DB_W
    70  	AMXOR_W
    71  	AND
    72  	ANDI
    73  	ANDN
    74  	ASRTGT_D
    75  	ASRTLE_D
    76  	B
    77  	BCEQZ
    78  	BCNEZ
    79  	BEQ
    80  	BEQZ
    81  	BGE
    82  	BGEU
    83  	BITREV_4B
    84  	BITREV_8B
    85  	BITREV_D
    86  	BITREV_W
    87  	BL
    88  	BLT
    89  	BLTU
    90  	BNE
    91  	BNEZ
    92  	BREAK
    93  	BSTRINS_D
    94  	BSTRINS_W
    95  	BSTRPICK_D
    96  	BSTRPICK_W
    97  	BYTEPICK_D
    98  	BYTEPICK_W
    99  	CACOP
   100  	CLO_D
   101  	CLO_W
   102  	CLZ_D
   103  	CLZ_W
   104  	CPUCFG
   105  	CRCC_W_B_W
   106  	CRCC_W_D_W
   107  	CRCC_W_H_W
   108  	CRCC_W_W_W
   109  	CRC_W_B_W
   110  	CRC_W_D_W
   111  	CRC_W_H_W
   112  	CRC_W_W_W
   113  	CSRRD
   114  	CSRWR
   115  	CSRXCHG
   116  	CTO_D
   117  	CTO_W
   118  	CTZ_D
   119  	CTZ_W
   120  	DBAR
   121  	DBCL
   122  	DIV_D
   123  	DIV_DU
   124  	DIV_W
   125  	DIV_WU
   126  	ERTN
   127  	EXT_W_B
   128  	EXT_W_H
   129  	FABS_D
   130  	FABS_S
   131  	FADD_D
   132  	FADD_S
   133  	FCLASS_D
   134  	FCLASS_S
   135  	FCMP_CAF_D
   136  	FCMP_CAF_S
   137  	FCMP_CEQ_D
   138  	FCMP_CEQ_S
   139  	FCMP_CLE_D
   140  	FCMP_CLE_S
   141  	FCMP_CLT_D
   142  	FCMP_CLT_S
   143  	FCMP_CNE_D
   144  	FCMP_CNE_S
   145  	FCMP_COR_D
   146  	FCMP_COR_S
   147  	FCMP_CUEQ_D
   148  	FCMP_CUEQ_S
   149  	FCMP_CULE_D
   150  	FCMP_CULE_S
   151  	FCMP_CULT_D
   152  	FCMP_CULT_S
   153  	FCMP_CUNE_D
   154  	FCMP_CUNE_S
   155  	FCMP_CUN_D
   156  	FCMP_CUN_S
   157  	FCMP_SAF_D
   158  	FCMP_SAF_S
   159  	FCMP_SEQ_D
   160  	FCMP_SEQ_S
   161  	FCMP_SLE_D
   162  	FCMP_SLE_S
   163  	FCMP_SLT_D
   164  	FCMP_SLT_S
   165  	FCMP_SNE_D
   166  	FCMP_SNE_S
   167  	FCMP_SOR_D
   168  	FCMP_SOR_S
   169  	FCMP_SUEQ_D
   170  	FCMP_SUEQ_S
   171  	FCMP_SULE_D
   172  	FCMP_SULE_S
   173  	FCMP_SULT_D
   174  	FCMP_SULT_S
   175  	FCMP_SUNE_D
   176  	FCMP_SUNE_S
   177  	FCMP_SUN_D
   178  	FCMP_SUN_S
   179  	FCOPYSIGN_D
   180  	FCOPYSIGN_S
   181  	FCVT_D_S
   182  	FCVT_S_D
   183  	FDIV_D
   184  	FDIV_S
   185  	FFINT_D_L
   186  	FFINT_D_W
   187  	FFINT_S_L
   188  	FFINT_S_W
   189  	FLDGT_D
   190  	FLDGT_S
   191  	FLDLE_D
   192  	FLDLE_S
   193  	FLDX_D
   194  	FLDX_S
   195  	FLD_D
   196  	FLD_S
   197  	FLOGB_D
   198  	FLOGB_S
   199  	FMADD_D
   200  	FMADD_S
   201  	FMAXA_D
   202  	FMAXA_S
   203  	FMAX_D
   204  	FMAX_S
   205  	FMINA_D
   206  	FMINA_S
   207  	FMIN_D
   208  	FMIN_S
   209  	FMOV_D
   210  	FMOV_S
   211  	FMSUB_D
   212  	FMSUB_S
   213  	FMUL_D
   214  	FMUL_S
   215  	FNEG_D
   216  	FNEG_S
   217  	FNMADD_D
   218  	FNMADD_S
   219  	FNMSUB_D
   220  	FNMSUB_S
   221  	FRECIPE_D
   222  	FRECIPE_S
   223  	FRECIP_D
   224  	FRECIP_S
   225  	FRINT_D
   226  	FRINT_S
   227  	FRSQRTE_D
   228  	FRSQRTE_S
   229  	FRSQRT_D
   230  	FRSQRT_S
   231  	FSCALEB_D
   232  	FSCALEB_S
   233  	FSEL
   234  	FSQRT_D
   235  	FSQRT_S
   236  	FSTGT_D
   237  	FSTGT_S
   238  	FSTLE_D
   239  	FSTLE_S
   240  	FSTX_D
   241  	FSTX_S
   242  	FST_D
   243  	FST_S
   244  	FSUB_D
   245  	FSUB_S
   246  	FTINTRM_L_D
   247  	FTINTRM_L_S
   248  	FTINTRM_W_D
   249  	FTINTRM_W_S
   250  	FTINTRNE_L_D
   251  	FTINTRNE_L_S
   252  	FTINTRNE_W_D
   253  	FTINTRNE_W_S
   254  	FTINTRP_L_D
   255  	FTINTRP_L_S
   256  	FTINTRP_W_D
   257  	FTINTRP_W_S
   258  	FTINTRZ_L_D
   259  	FTINTRZ_L_S
   260  	FTINTRZ_W_D
   261  	FTINTRZ_W_S
   262  	FTINT_L_D
   263  	FTINT_L_S
   264  	FTINT_W_D
   265  	FTINT_W_S
   266  	IBAR
   267  	IDLE
   268  	INVTLB
   269  	IOCSRRD_B
   270  	IOCSRRD_D
   271  	IOCSRRD_H
   272  	IOCSRRD_W
   273  	IOCSRWR_B
   274  	IOCSRWR_D
   275  	IOCSRWR_H
   276  	IOCSRWR_W
   277  	JIRL
   278  	LDDIR
   279  	LDGT_B
   280  	LDGT_D
   281  	LDGT_H
   282  	LDGT_W
   283  	LDLE_B
   284  	LDLE_D
   285  	LDLE_H
   286  	LDLE_W
   287  	LDPTE
   288  	LDPTR_D
   289  	LDPTR_W
   290  	LDX_B
   291  	LDX_BU
   292  	LDX_D
   293  	LDX_H
   294  	LDX_HU
   295  	LDX_W
   296  	LDX_WU
   297  	LD_B
   298  	LD_BU
   299  	LD_D
   300  	LD_H
   301  	LD_HU
   302  	LD_W
   303  	LD_WU
   304  	LLACQ_D
   305  	LLACQ_W
   306  	LL_D
   307  	LL_W
   308  	LU12I_W
   309  	LU32I_D
   310  	LU52I_D
   311  	MASKEQZ
   312  	MASKNEZ
   313  	MOD_D
   314  	MOD_DU
   315  	MOD_W
   316  	MOD_WU
   317  	MOVCF2FR
   318  	MOVCF2GR
   319  	MOVFCSR2GR
   320  	MOVFR2CF
   321  	MOVFR2GR_D
   322  	MOVFR2GR_S
   323  	MOVFRH2GR_S
   324  	MOVGR2CF
   325  	MOVGR2FCSR
   326  	MOVGR2FRH_W
   327  	MOVGR2FR_D
   328  	MOVGR2FR_W
   329  	MULH_D
   330  	MULH_DU
   331  	MULH_W
   332  	MULH_WU
   333  	MULW_D_W
   334  	MULW_D_WU
   335  	MUL_D
   336  	MUL_W
   337  	NOR
   338  	OR
   339  	ORI
   340  	ORN
   341  	PCADDI
   342  	PCADDU12I
   343  	PCADDU18I
   344  	PCALAU12I
   345  	PRELD
   346  	PRELDX
   347  	RDTIMEH_W
   348  	RDTIMEL_W
   349  	RDTIME_D
   350  	REVB_2H
   351  	REVB_2W
   352  	REVB_4H
   353  	REVB_D
   354  	REVH_2W
   355  	REVH_D
   356  	ROTRI_D
   357  	ROTRI_W
   358  	ROTR_D
   359  	ROTR_W
   360  	SCREL_D
   361  	SCREL_W
   362  	SC_D
   363  	SC_Q
   364  	SC_W
   365  	SLLI_D
   366  	SLLI_W
   367  	SLL_D
   368  	SLL_W
   369  	SLT
   370  	SLTI
   371  	SLTU
   372  	SLTUI
   373  	SRAI_D
   374  	SRAI_W
   375  	SRA_D
   376  	SRA_W
   377  	SRLI_D
   378  	SRLI_W
   379  	SRL_D
   380  	SRL_W
   381  	STGT_B
   382  	STGT_D
   383  	STGT_H
   384  	STGT_W
   385  	STLE_B
   386  	STLE_D
   387  	STLE_H
   388  	STLE_W
   389  	STPTR_D
   390  	STPTR_W
   391  	STX_B
   392  	STX_D
   393  	STX_H
   394  	STX_W
   395  	ST_B
   396  	ST_D
   397  	ST_H
   398  	ST_W
   399  	SUB_D
   400  	SUB_W
   401  	SYSCALL
   402  	TLBCLR
   403  	TLBFILL
   404  	TLBFLUSH
   405  	TLBRD
   406  	TLBSRCH
   407  	TLBWR
   408  	XOR
   409  	XORI
   410  )
   411  
   412  var opstr = [...]string{
   413  	ADDI_D:       "ADDI.D",
   414  	ADDI_W:       "ADDI.W",
   415  	ADDU16I_D:    "ADDU16I.D",
   416  	ADD_D:        "ADD.D",
   417  	ADD_W:        "ADD.W",
   418  	ALSL_D:       "ALSL.D",
   419  	ALSL_W:       "ALSL.W",
   420  	ALSL_WU:      "ALSL.WU",
   421  	AMADD_B:      "AMADD.B",
   422  	AMADD_D:      "AMADD.D",
   423  	AMADD_DB_B:   "AMADD_DB.B",
   424  	AMADD_DB_D:   "AMADD_DB.D",
   425  	AMADD_DB_H:   "AMADD_DB.H",
   426  	AMADD_DB_W:   "AMADD_DB.W",
   427  	AMADD_H:      "AMADD.H",
   428  	AMADD_W:      "AMADD.W",
   429  	AMAND_D:      "AMAND.D",
   430  	AMAND_DB_D:   "AMAND_DB.D",
   431  	AMAND_DB_W:   "AMAND_DB.W",
   432  	AMAND_W:      "AMAND.W",
   433  	AMCAS_B:      "AMCAS.B",
   434  	AMCAS_D:      "AMCAS.D",
   435  	AMCAS_DB_B:   "AMCAS_DB.B",
   436  	AMCAS_DB_D:   "AMCAS_DB.D",
   437  	AMCAS_DB_H:   "AMCAS_DB.H",
   438  	AMCAS_DB_W:   "AMCAS_DB.W",
   439  	AMCAS_H:      "AMCAS.H",
   440  	AMCAS_W:      "AMCAS.W",
   441  	AMMAX_D:      "AMMAX.D",
   442  	AMMAX_DB_D:   "AMMAX_DB.D",
   443  	AMMAX_DB_DU:  "AMMAX_DB.DU",
   444  	AMMAX_DB_W:   "AMMAX_DB.W",
   445  	AMMAX_DB_WU:  "AMMAX_DB.WU",
   446  	AMMAX_DU:     "AMMAX.DU",
   447  	AMMAX_W:      "AMMAX.W",
   448  	AMMAX_WU:     "AMMAX.WU",
   449  	AMMIN_D:      "AMMIN.D",
   450  	AMMIN_DB_D:   "AMMIN_DB.D",
   451  	AMMIN_DB_DU:  "AMMIN_DB.DU",
   452  	AMMIN_DB_W:   "AMMIN_DB.W",
   453  	AMMIN_DB_WU:  "AMMIN_DB.WU",
   454  	AMMIN_DU:     "AMMIN.DU",
   455  	AMMIN_W:      "AMMIN.W",
   456  	AMMIN_WU:     "AMMIN.WU",
   457  	AMOR_D:       "AMOR.D",
   458  	AMOR_DB_D:    "AMOR_DB.D",
   459  	AMOR_DB_W:    "AMOR_DB.W",
   460  	AMOR_W:       "AMOR.W",
   461  	AMSWAP_B:     "AMSWAP.B",
   462  	AMSWAP_D:     "AMSWAP.D",
   463  	AMSWAP_DB_B:  "AMSWAP_DB.B",
   464  	AMSWAP_DB_D:  "AMSWAP_DB.D",
   465  	AMSWAP_DB_H:  "AMSWAP_DB.H",
   466  	AMSWAP_DB_W:  "AMSWAP_DB.W",
   467  	AMSWAP_H:     "AMSWAP.H",
   468  	AMSWAP_W:     "AMSWAP.W",
   469  	AMXOR_D:      "AMXOR.D",
   470  	AMXOR_DB_D:   "AMXOR_DB.D",
   471  	AMXOR_DB_W:   "AMXOR_DB.W",
   472  	AMXOR_W:      "AMXOR.W",
   473  	AND:          "AND",
   474  	ANDI:         "ANDI",
   475  	ANDN:         "ANDN",
   476  	ASRTGT_D:     "ASRTGT.D",
   477  	ASRTLE_D:     "ASRTLE.D",
   478  	B:            "B",
   479  	BCEQZ:        "BCEQZ",
   480  	BCNEZ:        "BCNEZ",
   481  	BEQ:          "BEQ",
   482  	BEQZ:         "BEQZ",
   483  	BGE:          "BGE",
   484  	BGEU:         "BGEU",
   485  	BITREV_4B:    "BITREV.4B",
   486  	BITREV_8B:    "BITREV.8B",
   487  	BITREV_D:     "BITREV.D",
   488  	BITREV_W:     "BITREV.W",
   489  	BL:           "BL",
   490  	BLT:          "BLT",
   491  	BLTU:         "BLTU",
   492  	BNE:          "BNE",
   493  	BNEZ:         "BNEZ",
   494  	BREAK:        "BREAK",
   495  	BSTRINS_D:    "BSTRINS.D",
   496  	BSTRINS_W:    "BSTRINS.W",
   497  	BSTRPICK_D:   "BSTRPICK.D",
   498  	BSTRPICK_W:   "BSTRPICK.W",
   499  	BYTEPICK_D:   "BYTEPICK.D",
   500  	BYTEPICK_W:   "BYTEPICK.W",
   501  	CACOP:        "CACOP",
   502  	CLO_D:        "CLO.D",
   503  	CLO_W:        "CLO.W",
   504  	CLZ_D:        "CLZ.D",
   505  	CLZ_W:        "CLZ.W",
   506  	CPUCFG:       "CPUCFG",
   507  	CRCC_W_B_W:   "CRCC.W.B.W",
   508  	CRCC_W_D_W:   "CRCC.W.D.W",
   509  	CRCC_W_H_W:   "CRCC.W.H.W",
   510  	CRCC_W_W_W:   "CRCC.W.W.W",
   511  	CRC_W_B_W:    "CRC.W.B.W",
   512  	CRC_W_D_W:    "CRC.W.D.W",
   513  	CRC_W_H_W:    "CRC.W.H.W",
   514  	CRC_W_W_W:    "CRC.W.W.W",
   515  	CSRRD:        "CSRRD",
   516  	CSRWR:        "CSRWR",
   517  	CSRXCHG:      "CSRXCHG",
   518  	CTO_D:        "CTO.D",
   519  	CTO_W:        "CTO.W",
   520  	CTZ_D:        "CTZ.D",
   521  	CTZ_W:        "CTZ.W",
   522  	DBAR:         "DBAR",
   523  	DBCL:         "DBCL",
   524  	DIV_D:        "DIV.D",
   525  	DIV_DU:       "DIV.DU",
   526  	DIV_W:        "DIV.W",
   527  	DIV_WU:       "DIV.WU",
   528  	ERTN:         "ERTN",
   529  	EXT_W_B:      "EXT.W.B",
   530  	EXT_W_H:      "EXT.W.H",
   531  	FABS_D:       "FABS.D",
   532  	FABS_S:       "FABS.S",
   533  	FADD_D:       "FADD.D",
   534  	FADD_S:       "FADD.S",
   535  	FCLASS_D:     "FCLASS.D",
   536  	FCLASS_S:     "FCLASS.S",
   537  	FCMP_CAF_D:   "FCMP.CAF.D",
   538  	FCMP_CAF_S:   "FCMP.CAF.S",
   539  	FCMP_CEQ_D:   "FCMP.CEQ.D",
   540  	FCMP_CEQ_S:   "FCMP.CEQ.S",
   541  	FCMP_CLE_D:   "FCMP.CLE.D",
   542  	FCMP_CLE_S:   "FCMP.CLE.S",
   543  	FCMP_CLT_D:   "FCMP.CLT.D",
   544  	FCMP_CLT_S:   "FCMP.CLT.S",
   545  	FCMP_CNE_D:   "FCMP.CNE.D",
   546  	FCMP_CNE_S:   "FCMP.CNE.S",
   547  	FCMP_COR_D:   "FCMP.COR.D",
   548  	FCMP_COR_S:   "FCMP.COR.S",
   549  	FCMP_CUEQ_D:  "FCMP.CUEQ.D",
   550  	FCMP_CUEQ_S:  "FCMP.CUEQ.S",
   551  	FCMP_CULE_D:  "FCMP.CULE.D",
   552  	FCMP_CULE_S:  "FCMP.CULE.S",
   553  	FCMP_CULT_D:  "FCMP.CULT.D",
   554  	FCMP_CULT_S:  "FCMP.CULT.S",
   555  	FCMP_CUNE_D:  "FCMP.CUNE.D",
   556  	FCMP_CUNE_S:  "FCMP.CUNE.S",
   557  	FCMP_CUN_D:   "FCMP.CUN.D",
   558  	FCMP_CUN_S:   "FCMP.CUN.S",
   559  	FCMP_SAF_D:   "FCMP.SAF.D",
   560  	FCMP_SAF_S:   "FCMP.SAF.S",
   561  	FCMP_SEQ_D:   "FCMP.SEQ.D",
   562  	FCMP_SEQ_S:   "FCMP.SEQ.S",
   563  	FCMP_SLE_D:   "FCMP.SLE.D",
   564  	FCMP_SLE_S:   "FCMP.SLE.S",
   565  	FCMP_SLT_D:   "FCMP.SLT.D",
   566  	FCMP_SLT_S:   "FCMP.SLT.S",
   567  	FCMP_SNE_D:   "FCMP.SNE.D",
   568  	FCMP_SNE_S:   "FCMP.SNE.S",
   569  	FCMP_SOR_D:   "FCMP.SOR.D",
   570  	FCMP_SOR_S:   "FCMP.SOR.S",
   571  	FCMP_SUEQ_D:  "FCMP.SUEQ.D",
   572  	FCMP_SUEQ_S:  "FCMP.SUEQ.S",
   573  	FCMP_SULE_D:  "FCMP.SULE.D",
   574  	FCMP_SULE_S:  "FCMP.SULE.S",
   575  	FCMP_SULT_D:  "FCMP.SULT.D",
   576  	FCMP_SULT_S:  "FCMP.SULT.S",
   577  	FCMP_SUNE_D:  "FCMP.SUNE.D",
   578  	FCMP_SUNE_S:  "FCMP.SUNE.S",
   579  	FCMP_SUN_D:   "FCMP.SUN.D",
   580  	FCMP_SUN_S:   "FCMP.SUN.S",
   581  	FCOPYSIGN_D:  "FCOPYSIGN.D",
   582  	FCOPYSIGN_S:  "FCOPYSIGN.S",
   583  	FCVT_D_S:     "FCVT.D.S",
   584  	FCVT_S_D:     "FCVT.S.D",
   585  	FDIV_D:       "FDIV.D",
   586  	FDIV_S:       "FDIV.S",
   587  	FFINT_D_L:    "FFINT.D.L",
   588  	FFINT_D_W:    "FFINT.D.W",
   589  	FFINT_S_L:    "FFINT.S.L",
   590  	FFINT_S_W:    "FFINT.S.W",
   591  	FLDGT_D:      "FLDGT.D",
   592  	FLDGT_S:      "FLDGT.S",
   593  	FLDLE_D:      "FLDLE.D",
   594  	FLDLE_S:      "FLDLE.S",
   595  	FLDX_D:       "FLDX.D",
   596  	FLDX_S:       "FLDX.S",
   597  	FLD_D:        "FLD.D",
   598  	FLD_S:        "FLD.S",
   599  	FLOGB_D:      "FLOGB.D",
   600  	FLOGB_S:      "FLOGB.S",
   601  	FMADD_D:      "FMADD.D",
   602  	FMADD_S:      "FMADD.S",
   603  	FMAXA_D:      "FMAXA.D",
   604  	FMAXA_S:      "FMAXA.S",
   605  	FMAX_D:       "FMAX.D",
   606  	FMAX_S:       "FMAX.S",
   607  	FMINA_D:      "FMINA.D",
   608  	FMINA_S:      "FMINA.S",
   609  	FMIN_D:       "FMIN.D",
   610  	FMIN_S:       "FMIN.S",
   611  	FMOV_D:       "FMOV.D",
   612  	FMOV_S:       "FMOV.S",
   613  	FMSUB_D:      "FMSUB.D",
   614  	FMSUB_S:      "FMSUB.S",
   615  	FMUL_D:       "FMUL.D",
   616  	FMUL_S:       "FMUL.S",
   617  	FNEG_D:       "FNEG.D",
   618  	FNEG_S:       "FNEG.S",
   619  	FNMADD_D:     "FNMADD.D",
   620  	FNMADD_S:     "FNMADD.S",
   621  	FNMSUB_D:     "FNMSUB.D",
   622  	FNMSUB_S:     "FNMSUB.S",
   623  	FRECIPE_D:    "FRECIPE.D",
   624  	FRECIPE_S:    "FRECIPE.S",
   625  	FRECIP_D:     "FRECIP.D",
   626  	FRECIP_S:     "FRECIP.S",
   627  	FRINT_D:      "FRINT.D",
   628  	FRINT_S:      "FRINT.S",
   629  	FRSQRTE_D:    "FRSQRTE.D",
   630  	FRSQRTE_S:    "FRSQRTE.S",
   631  	FRSQRT_D:     "FRSQRT.D",
   632  	FRSQRT_S:     "FRSQRT.S",
   633  	FSCALEB_D:    "FSCALEB.D",
   634  	FSCALEB_S:    "FSCALEB.S",
   635  	FSEL:         "FSEL",
   636  	FSQRT_D:      "FSQRT.D",
   637  	FSQRT_S:      "FSQRT.S",
   638  	FSTGT_D:      "FSTGT.D",
   639  	FSTGT_S:      "FSTGT.S",
   640  	FSTLE_D:      "FSTLE.D",
   641  	FSTLE_S:      "FSTLE.S",
   642  	FSTX_D:       "FSTX.D",
   643  	FSTX_S:       "FSTX.S",
   644  	FST_D:        "FST.D",
   645  	FST_S:        "FST.S",
   646  	FSUB_D:       "FSUB.D",
   647  	FSUB_S:       "FSUB.S",
   648  	FTINTRM_L_D:  "FTINTRM.L.D",
   649  	FTINTRM_L_S:  "FTINTRM.L.S",
   650  	FTINTRM_W_D:  "FTINTRM.W.D",
   651  	FTINTRM_W_S:  "FTINTRM.W.S",
   652  	FTINTRNE_L_D: "FTINTRNE.L.D",
   653  	FTINTRNE_L_S: "FTINTRNE.L.S",
   654  	FTINTRNE_W_D: "FTINTRNE.W.D",
   655  	FTINTRNE_W_S: "FTINTRNE.W.S",
   656  	FTINTRP_L_D:  "FTINTRP.L.D",
   657  	FTINTRP_L_S:  "FTINTRP.L.S",
   658  	FTINTRP_W_D:  "FTINTRP.W.D",
   659  	FTINTRP_W_S:  "FTINTRP.W.S",
   660  	FTINTRZ_L_D:  "FTINTRZ.L.D",
   661  	FTINTRZ_L_S:  "FTINTRZ.L.S",
   662  	FTINTRZ_W_D:  "FTINTRZ.W.D",
   663  	FTINTRZ_W_S:  "FTINTRZ.W.S",
   664  	FTINT_L_D:    "FTINT.L.D",
   665  	FTINT_L_S:    "FTINT.L.S",
   666  	FTINT_W_D:    "FTINT.W.D",
   667  	FTINT_W_S:    "FTINT.W.S",
   668  	IBAR:         "IBAR",
   669  	IDLE:         "IDLE",
   670  	INVTLB:       "INVTLB",
   671  	IOCSRRD_B:    "IOCSRRD.B",
   672  	IOCSRRD_D:    "IOCSRRD.D",
   673  	IOCSRRD_H:    "IOCSRRD.H",
   674  	IOCSRRD_W:    "IOCSRRD.W",
   675  	IOCSRWR_B:    "IOCSRWR.B",
   676  	IOCSRWR_D:    "IOCSRWR.D",
   677  	IOCSRWR_H:    "IOCSRWR.H",
   678  	IOCSRWR_W:    "IOCSRWR.W",
   679  	JIRL:         "JIRL",
   680  	LDDIR:        "LDDIR",
   681  	LDGT_B:       "LDGT.B",
   682  	LDGT_D:       "LDGT.D",
   683  	LDGT_H:       "LDGT.H",
   684  	LDGT_W:       "LDGT.W",
   685  	LDLE_B:       "LDLE.B",
   686  	LDLE_D:       "LDLE.D",
   687  	LDLE_H:       "LDLE.H",
   688  	LDLE_W:       "LDLE.W",
   689  	LDPTE:        "LDPTE",
   690  	LDPTR_D:      "LDPTR.D",
   691  	LDPTR_W:      "LDPTR.W",
   692  	LDX_B:        "LDX.B",
   693  	LDX_BU:       "LDX.BU",
   694  	LDX_D:        "LDX.D",
   695  	LDX_H:        "LDX.H",
   696  	LDX_HU:       "LDX.HU",
   697  	LDX_W:        "LDX.W",
   698  	LDX_WU:       "LDX.WU",
   699  	LD_B:         "LD.B",
   700  	LD_BU:        "LD.BU",
   701  	LD_D:         "LD.D",
   702  	LD_H:         "LD.H",
   703  	LD_HU:        "LD.HU",
   704  	LD_W:         "LD.W",
   705  	LD_WU:        "LD.WU",
   706  	LLACQ_D:      "LLACQ.D",
   707  	LLACQ_W:      "LLACQ.W",
   708  	LL_D:         "LL.D",
   709  	LL_W:         "LL.W",
   710  	LU12I_W:      "LU12I.W",
   711  	LU32I_D:      "LU32I.D",
   712  	LU52I_D:      "LU52I.D",
   713  	MASKEQZ:      "MASKEQZ",
   714  	MASKNEZ:      "MASKNEZ",
   715  	MOD_D:        "MOD.D",
   716  	MOD_DU:       "MOD.DU",
   717  	MOD_W:        "MOD.W",
   718  	MOD_WU:       "MOD.WU",
   719  	MOVCF2FR:     "MOVCF2FR",
   720  	MOVCF2GR:     "MOVCF2GR",
   721  	MOVFCSR2GR:   "MOVFCSR2GR",
   722  	MOVFR2CF:     "MOVFR2CF",
   723  	MOVFR2GR_D:   "MOVFR2GR.D",
   724  	MOVFR2GR_S:   "MOVFR2GR.S",
   725  	MOVFRH2GR_S:  "MOVFRH2GR.S",
   726  	MOVGR2CF:     "MOVGR2CF",
   727  	MOVGR2FCSR:   "MOVGR2FCSR",
   728  	MOVGR2FRH_W:  "MOVGR2FRH.W",
   729  	MOVGR2FR_D:   "MOVGR2FR.D",
   730  	MOVGR2FR_W:   "MOVGR2FR.W",
   731  	MULH_D:       "MULH.D",
   732  	MULH_DU:      "MULH.DU",
   733  	MULH_W:       "MULH.W",
   734  	MULH_WU:      "MULH.WU",
   735  	MULW_D_W:     "MULW.D.W",
   736  	MULW_D_WU:    "MULW.D.WU",
   737  	MUL_D:        "MUL.D",
   738  	MUL_W:        "MUL.W",
   739  	NOR:          "NOR",
   740  	OR:           "OR",
   741  	ORI:          "ORI",
   742  	ORN:          "ORN",
   743  	PCADDI:       "PCADDI",
   744  	PCADDU12I:    "PCADDU12I",
   745  	PCADDU18I:    "PCADDU18I",
   746  	PCALAU12I:    "PCALAU12I",
   747  	PRELD:        "PRELD",
   748  	PRELDX:       "PRELDX",
   749  	RDTIMEH_W:    "RDTIMEH.W",
   750  	RDTIMEL_W:    "RDTIMEL.W",
   751  	RDTIME_D:     "RDTIME.D",
   752  	REVB_2H:      "REVB.2H",
   753  	REVB_2W:      "REVB.2W",
   754  	REVB_4H:      "REVB.4H",
   755  	REVB_D:       "REVB.D",
   756  	REVH_2W:      "REVH.2W",
   757  	REVH_D:       "REVH.D",
   758  	ROTRI_D:      "ROTRI.D",
   759  	ROTRI_W:      "ROTRI.W",
   760  	ROTR_D:       "ROTR.D",
   761  	ROTR_W:       "ROTR.W",
   762  	SCREL_D:      "SCREL.D",
   763  	SCREL_W:      "SCREL.W",
   764  	SC_D:         "SC.D",
   765  	SC_Q:         "SC.Q",
   766  	SC_W:         "SC.W",
   767  	SLLI_D:       "SLLI.D",
   768  	SLLI_W:       "SLLI.W",
   769  	SLL_D:        "SLL.D",
   770  	SLL_W:        "SLL.W",
   771  	SLT:          "SLT",
   772  	SLTI:         "SLTI",
   773  	SLTU:         "SLTU",
   774  	SLTUI:        "SLTUI",
   775  	SRAI_D:       "SRAI.D",
   776  	SRAI_W:       "SRAI.W",
   777  	SRA_D:        "SRA.D",
   778  	SRA_W:        "SRA.W",
   779  	SRLI_D:       "SRLI.D",
   780  	SRLI_W:       "SRLI.W",
   781  	SRL_D:        "SRL.D",
   782  	SRL_W:        "SRL.W",
   783  	STGT_B:       "STGT.B",
   784  	STGT_D:       "STGT.D",
   785  	STGT_H:       "STGT.H",
   786  	STGT_W:       "STGT.W",
   787  	STLE_B:       "STLE.B",
   788  	STLE_D:       "STLE.D",
   789  	STLE_H:       "STLE.H",
   790  	STLE_W:       "STLE.W",
   791  	STPTR_D:      "STPTR.D",
   792  	STPTR_W:      "STPTR.W",
   793  	STX_B:        "STX.B",
   794  	STX_D:        "STX.D",
   795  	STX_H:        "STX.H",
   796  	STX_W:        "STX.W",
   797  	ST_B:         "ST.B",
   798  	ST_D:         "ST.D",
   799  	ST_H:         "ST.H",
   800  	ST_W:         "ST.W",
   801  	SUB_D:        "SUB.D",
   802  	SUB_W:        "SUB.W",
   803  	SYSCALL:      "SYSCALL",
   804  	TLBCLR:       "TLBCLR",
   805  	TLBFILL:      "TLBFILL",
   806  	TLBFLUSH:     "TLBFLUSH",
   807  	TLBRD:        "TLBRD",
   808  	TLBSRCH:      "TLBSRCH",
   809  	TLBWR:        "TLBWR",
   810  	XOR:          "XOR",
   811  	XORI:         "XORI",
   812  }
   813  
   814  var instFormats = [...]instFormat{
   815  	// ADDI.D rd, rj, si12
   816  	{mask: 0xffc00000, value: 0x02c00000, op: ADDI_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
   817  	// ADDI.W rd, rj, si12
   818  	{mask: 0xffc00000, value: 0x02800000, op: ADDI_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
   819  	// ADDU16I.D rd, rj, si16
   820  	{mask: 0xfc000000, value: 0x10000000, op: ADDU16I_D, args: instArgs{arg_rd, arg_rj, arg_si16_25_10}},
   821  	// ADD.D rd, rj, rk
   822  	{mask: 0xffff8000, value: 0x00108000, op: ADD_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
   823  	// ADD.W rd, rj, rk
   824  	{mask: 0xffff8000, value: 0x00100000, op: ADD_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
   825  	// ALSL.D rd, rj, rk, sa2
   826  	{mask: 0xfffe0000, value: 0x002c0000, op: ALSL_D, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
   827  	// ALSL.W rd, rj, rk, sa2
   828  	{mask: 0xfffe0000, value: 0x00040000, op: ALSL_W, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
   829  	// ALSL.WU rd, rj, rk, sa2
   830  	{mask: 0xfffe0000, value: 0x00060000, op: ALSL_WU, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
   831  	// AMADD.B rd, rk, rj
   832  	{mask: 0xffff8000, value: 0x385d0000, op: AMADD_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
   833  	// AMADD.D rd, rk, rj
   834  	{mask: 0xffff8000, value: 0x38618000, op: AMADD_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   835  	// AMADD_DB.B rd, rk, rj
   836  	{mask: 0xffff8000, value: 0x385f0000, op: AMADD_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
   837  	// AMADD_DB.D rd, rk, rj
   838  	{mask: 0xffff8000, value: 0x386a8000, op: AMADD_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   839  	// AMADD_DB.H rd, rk, rj
   840  	{mask: 0xffff8000, value: 0x385f8000, op: AMADD_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
   841  	// AMADD_DB.W rd, rk, rj
   842  	{mask: 0xffff8000, value: 0x386a0000, op: AMADD_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   843  	// AMADD.H rd, rk, rj
   844  	{mask: 0xffff8000, value: 0x385d8000, op: AMADD_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
   845  	// AMADD.W rd, rk, rj
   846  	{mask: 0xffff8000, value: 0x38610000, op: AMADD_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   847  	// AMAND.D rd, rk, rj
   848  	{mask: 0xffff8000, value: 0x38628000, op: AMAND_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   849  	// AMAND_DB.D rd, rk, rj
   850  	{mask: 0xffff8000, value: 0x386b8000, op: AMAND_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   851  	// AMAND_DB.W rd, rk, rj
   852  	{mask: 0xffff8000, value: 0x386b0000, op: AMAND_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   853  	// AMAND.W rd, rk, rj
   854  	{mask: 0xffff8000, value: 0x38620000, op: AMAND_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   855  	// AMCAS.B rd, rk, rj
   856  	{mask: 0xffff8000, value: 0x38580000, op: AMCAS_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
   857  	// AMCAS.D rd, rk, rj
   858  	{mask: 0xffff8000, value: 0x38598000, op: AMCAS_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   859  	// AMCAS_DB.B rd, rk, rj
   860  	{mask: 0xffff8000, value: 0x385a0000, op: AMCAS_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
   861  	// AMCAS_DB.D rd, rk, rj
   862  	{mask: 0xffff8000, value: 0x385b8000, op: AMCAS_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   863  	// AMCAS_DB.H rd, rk, rj
   864  	{mask: 0xffff8000, value: 0x385a8000, op: AMCAS_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
   865  	// AMCAS_DB.W rd, rk, rj
   866  	{mask: 0xffff8000, value: 0x385b0000, op: AMCAS_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   867  	// AMCAS.H rd, rk, rj
   868  	{mask: 0xffff8000, value: 0x38588000, op: AMCAS_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
   869  	// AMCAS.W rd, rk, rj
   870  	{mask: 0xffff8000, value: 0x38590000, op: AMCAS_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   871  	// AMMAX.D rd, rk, rj
   872  	{mask: 0xffff8000, value: 0x38658000, op: AMMAX_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   873  	// AMMAX_DB.D rd, rk, rj
   874  	{mask: 0xffff8000, value: 0x386e8000, op: AMMAX_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   875  	// AMMAX_DB.DU rd, rk, rj
   876  	{mask: 0xffff8000, value: 0x38708000, op: AMMAX_DB_DU, args: instArgs{arg_rd, arg_rk, arg_rj}},
   877  	// AMMAX_DB.W rd, rk, rj
   878  	{mask: 0xffff8000, value: 0x386e0000, op: AMMAX_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   879  	// AMMAX_DB.WU rd, rk, rj
   880  	{mask: 0xffff8000, value: 0x38700000, op: AMMAX_DB_WU, args: instArgs{arg_rd, arg_rk, arg_rj}},
   881  	// AMMAX.DU rd, rk, rj
   882  	{mask: 0xffff8000, value: 0x38678000, op: AMMAX_DU, args: instArgs{arg_rd, arg_rk, arg_rj}},
   883  	// AMMAX.W rd, rk, rj
   884  	{mask: 0xffff8000, value: 0x38650000, op: AMMAX_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   885  	// AMMAX.WU rd, rk, rj
   886  	{mask: 0xffff8000, value: 0x38670000, op: AMMAX_WU, args: instArgs{arg_rd, arg_rk, arg_rj}},
   887  	// AMMIN.D rd, rk, rj
   888  	{mask: 0xffff8000, value: 0x38668000, op: AMMIN_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   889  	// AMMIN_DB.D rd, rk, rj
   890  	{mask: 0xffff8000, value: 0x386f8000, op: AMMIN_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   891  	// AMMIN_DB.DU rd, rk, rj
   892  	{mask: 0xffff8000, value: 0x38718000, op: AMMIN_DB_DU, args: instArgs{arg_rd, arg_rk, arg_rj}},
   893  	// AMMIN_DB.W rd, rk, rj
   894  	{mask: 0xffff8000, value: 0x386f0000, op: AMMIN_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   895  	// AMMIN_DB.WU rd, rk, rj
   896  	{mask: 0xffff8000, value: 0x38710000, op: AMMIN_DB_WU, args: instArgs{arg_rd, arg_rk, arg_rj}},
   897  	// AMMIN.DU rd, rk, rj
   898  	{mask: 0xffff8000, value: 0x38688000, op: AMMIN_DU, args: instArgs{arg_rd, arg_rk, arg_rj}},
   899  	// AMMIN.W rd, rk, rj
   900  	{mask: 0xffff8000, value: 0x38660000, op: AMMIN_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   901  	// AMMIN.WU rd, rk, rj
   902  	{mask: 0xffff8000, value: 0x38680000, op: AMMIN_WU, args: instArgs{arg_rd, arg_rk, arg_rj}},
   903  	// AMOR.D rd, rk, rj
   904  	{mask: 0xffff8000, value: 0x38638000, op: AMOR_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   905  	// AMOR_DB.D rd, rk, rj
   906  	{mask: 0xffff8000, value: 0x386c8000, op: AMOR_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   907  	// AMOR_DB.W rd, rk, rj
   908  	{mask: 0xffff8000, value: 0x386c0000, op: AMOR_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   909  	// AMOR.W rd, rk, rj
   910  	{mask: 0xffff8000, value: 0x38630000, op: AMOR_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   911  	// AMSWAP.B rd, rk, rj
   912  	{mask: 0xffff8000, value: 0x385c0000, op: AMSWAP_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
   913  	// AMSWAP.D rd, rk, rj
   914  	{mask: 0xffff8000, value: 0x38608000, op: AMSWAP_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   915  	// AMSWAP_DB.B rd, rk, rj
   916  	{mask: 0xffff8000, value: 0x385e0000, op: AMSWAP_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}},
   917  	// AMSWAP_DB.D rd, rk, rj
   918  	{mask: 0xffff8000, value: 0x38698000, op: AMSWAP_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   919  	// AMSWAP_DB.H rd, rk, rj
   920  	{mask: 0xffff8000, value: 0x385e8000, op: AMSWAP_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
   921  	// AMSWAP_DB.W rd, rk, rj
   922  	{mask: 0xffff8000, value: 0x38690000, op: AMSWAP_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   923  	// AMSWAP.H rd, rk, rj
   924  	{mask: 0xffff8000, value: 0x385c8000, op: AMSWAP_H, args: instArgs{arg_rd, arg_rk, arg_rj}},
   925  	// AMSWAP.W rd, rk, rj
   926  	{mask: 0xffff8000, value: 0x38600000, op: AMSWAP_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   927  	// AMXOR.D rd, rk, rj
   928  	{mask: 0xffff8000, value: 0x38648000, op: AMXOR_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   929  	// AMXOR_DB.D rd, rk, rj
   930  	{mask: 0xffff8000, value: 0x386d8000, op: AMXOR_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}},
   931  	// AMXOR_DB.W rd, rk, rj
   932  	{mask: 0xffff8000, value: 0x386d0000, op: AMXOR_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   933  	// AMXOR.W rd, rk, rj
   934  	{mask: 0xffff8000, value: 0x38640000, op: AMXOR_W, args: instArgs{arg_rd, arg_rk, arg_rj}},
   935  	// AND rd, rj, rk
   936  	{mask: 0xffff8000, value: 0x00148000, op: AND, args: instArgs{arg_rd, arg_rj, arg_rk}},
   937  	// ANDI rd, rj, ui12
   938  	{mask: 0xffc00000, value: 0x03400000, op: ANDI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
   939  	// ANDN rd, rj, rk
   940  	{mask: 0xffff8000, value: 0x00168000, op: ANDN, args: instArgs{arg_rd, arg_rj, arg_rk}},
   941  	// ASRTGT.D rj, rk
   942  	{mask: 0xffff801f, value: 0x00018000, op: ASRTGT_D, args: instArgs{arg_rj, arg_rk}},
   943  	// ASRTLE.D rj, rk
   944  	{mask: 0xffff801f, value: 0x00010000, op: ASRTLE_D, args: instArgs{arg_rj, arg_rk}},
   945  	// B offs
   946  	{mask: 0xfc000000, value: 0x50000000, op: B, args: instArgs{arg_offset_25_0}},
   947  	// BCEQZ cj, offs
   948  	{mask: 0xfc000300, value: 0x48000000, op: BCEQZ, args: instArgs{arg_cj, arg_offset_20_0}},
   949  	// BCNEZ cj, offs
   950  	{mask: 0xfc000300, value: 0x48000100, op: BCNEZ, args: instArgs{arg_cj, arg_offset_20_0}},
   951  	// BEQ rj, rd, offs
   952  	{mask: 0xfc000000, value: 0x58000000, op: BEQ, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
   953  	// BEQZ rj, offs
   954  	{mask: 0xfc000000, value: 0x40000000, op: BEQZ, args: instArgs{arg_rj, arg_offset_20_0}},
   955  	// BGE rj, rd, offs
   956  	{mask: 0xfc000000, value: 0x64000000, op: BGE, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
   957  	// BGEU rj, rd, offs
   958  	{mask: 0xfc000000, value: 0x6c000000, op: BGEU, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
   959  	// BITREV.4B rd, rj
   960  	{mask: 0xfffffc00, value: 0x00004800, op: BITREV_4B, args: instArgs{arg_rd, arg_rj}},
   961  	// BITREV.8B rd, rj
   962  	{mask: 0xfffffc00, value: 0x00004c00, op: BITREV_8B, args: instArgs{arg_rd, arg_rj}},
   963  	// BITREV.D rd, rj
   964  	{mask: 0xfffffc00, value: 0x00005400, op: BITREV_D, args: instArgs{arg_rd, arg_rj}},
   965  	// BITREV.W rd, rj
   966  	{mask: 0xfffffc00, value: 0x00005000, op: BITREV_W, args: instArgs{arg_rd, arg_rj}},
   967  	// BL offs
   968  	{mask: 0xfc000000, value: 0x54000000, op: BL, args: instArgs{arg_offset_25_0}},
   969  	// BLT rj, rd, offs
   970  	{mask: 0xfc000000, value: 0x60000000, op: BLT, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
   971  	// BLTU rj, rd, offs
   972  	{mask: 0xfc000000, value: 0x68000000, op: BLTU, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
   973  	// BNE rj, rd, offs
   974  	{mask: 0xfc000000, value: 0x5c000000, op: BNE, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}},
   975  	// BNEZ rj, offs
   976  	{mask: 0xfc000000, value: 0x44000000, op: BNEZ, args: instArgs{arg_rj, arg_offset_20_0}},
   977  	// BREAK code
   978  	{mask: 0xffff8000, value: 0x002a0000, op: BREAK, args: instArgs{arg_code_14_0}},
   979  	// BSTRINS.D rd, rj, msbd, lsbd
   980  	{mask: 0xffc00000, value: 0x00800000, op: BSTRINS_D, args: instArgs{arg_rd, arg_rj, arg_msbd, arg_lsbd}},
   981  	// BSTRINS.W rd, rj, msbw, lsbw
   982  	{mask: 0xffe08000, value: 0x00600000, op: BSTRINS_W, args: instArgs{arg_rd, arg_rj, arg_msbw, arg_lsbw}},
   983  	// BSTRPICK.D rd, rj, msbd, lsbd
   984  	{mask: 0xffc00000, value: 0x00c00000, op: BSTRPICK_D, args: instArgs{arg_rd, arg_rj, arg_msbd, arg_lsbd}},
   985  	// BSTRPICK.W rd, rj, msbw, lsbw
   986  	{mask: 0xffe08000, value: 0x00608000, op: BSTRPICK_W, args: instArgs{arg_rd, arg_rj, arg_msbw, arg_lsbw}},
   987  	// BYTEPICK.D rd, rj, rk, sa3
   988  	{mask: 0xfffc0000, value: 0x000c0000, op: BYTEPICK_D, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa3_17_15}},
   989  	// BYTEPICK.W rd, rj, rk, sa2
   990  	{mask: 0xfffe0000, value: 0x00080000, op: BYTEPICK_W, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}},
   991  	// CACOP code, rj, si12
   992  	{mask: 0xffc00000, value: 0x06000000, op: CACOP, args: instArgs{arg_code_4_0, arg_rj, arg_si12_21_10}},
   993  	// CLO.D rd, rj
   994  	{mask: 0xfffffc00, value: 0x00002000, op: CLO_D, args: instArgs{arg_rd, arg_rj}},
   995  	// CLO.W rd, rj
   996  	{mask: 0xfffffc00, value: 0x00001000, op: CLO_W, args: instArgs{arg_rd, arg_rj}},
   997  	// CLZ.D rd, rj
   998  	{mask: 0xfffffc00, value: 0x00002400, op: CLZ_D, args: instArgs{arg_rd, arg_rj}},
   999  	// CLZ.W rd, rj
  1000  	{mask: 0xfffffc00, value: 0x00001400, op: CLZ_W, args: instArgs{arg_rd, arg_rj}},
  1001  	// CPUCFG rd, rj
  1002  	{mask: 0xfffffc00, value: 0x00006c00, op: CPUCFG, args: instArgs{arg_rd, arg_rj}},
  1003  	// CRCC.W.B.W rd, rj, rk
  1004  	{mask: 0xffff8000, value: 0x00260000, op: CRCC_W_B_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1005  	// CRCC.W.D.W rd, rj, rk
  1006  	{mask: 0xffff8000, value: 0x00278000, op: CRCC_W_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1007  	// CRCC.W.H.W rd, rj, rk
  1008  	{mask: 0xffff8000, value: 0x00268000, op: CRCC_W_H_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1009  	// CRCC.W.W.W rd, rj, rk
  1010  	{mask: 0xffff8000, value: 0x00270000, op: CRCC_W_W_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1011  	// CRC.W.B.W rd, rj, rk
  1012  	{mask: 0xffff8000, value: 0x00240000, op: CRC_W_B_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1013  	// CRC.W.D.W rd, rj, rk
  1014  	{mask: 0xffff8000, value: 0x00258000, op: CRC_W_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1015  	// CRC.W.H.W rd, rj, rk
  1016  	{mask: 0xffff8000, value: 0x00248000, op: CRC_W_H_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1017  	// CRC.W.W.W rd, rj, rk
  1018  	{mask: 0xffff8000, value: 0x00250000, op: CRC_W_W_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1019  	// CSRRD rd, csr
  1020  	{mask: 0xff0003e0, value: 0x04000000, op: CSRRD, args: instArgs{arg_rd, arg_csr_23_10}},
  1021  	// CSRWR rd, csr
  1022  	{mask: 0xff0003e0, value: 0x04000020, op: CSRWR, args: instArgs{arg_rd, arg_csr_23_10}},
  1023  	// CSRXCHG rd, rj, csr
  1024  	{mask: 0xff000000, value: 0x04000000, op: CSRXCHG, args: instArgs{arg_rd, arg_rj, arg_csr_23_10}},
  1025  	// CTO.D rd, rj
  1026  	{mask: 0xfffffc00, value: 0x00002800, op: CTO_D, args: instArgs{arg_rd, arg_rj}},
  1027  	// CTO.W rd, rj
  1028  	{mask: 0xfffffc00, value: 0x00001800, op: CTO_W, args: instArgs{arg_rd, arg_rj}},
  1029  	// CTZ.D rd, rj
  1030  	{mask: 0xfffffc00, value: 0x00002c00, op: CTZ_D, args: instArgs{arg_rd, arg_rj}},
  1031  	// CTZ.W rd, rj
  1032  	{mask: 0xfffffc00, value: 0x00001c00, op: CTZ_W, args: instArgs{arg_rd, arg_rj}},
  1033  	// DBAR hint
  1034  	{mask: 0xffff8000, value: 0x38720000, op: DBAR, args: instArgs{arg_hint_14_0}},
  1035  	// DBCL code
  1036  	{mask: 0xffff8000, value: 0x002a8000, op: DBCL, args: instArgs{arg_code_14_0}},
  1037  	// DIV.D rd, rj, rk
  1038  	{mask: 0xffff8000, value: 0x00220000, op: DIV_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1039  	// DIV.DU rd, rj, rk
  1040  	{mask: 0xffff8000, value: 0x00230000, op: DIV_DU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1041  	// DIV.W rd, rj, rk
  1042  	{mask: 0xffff8000, value: 0x00200000, op: DIV_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1043  	// DIV.WU rd, rj, rk
  1044  	{mask: 0xffff8000, value: 0x00210000, op: DIV_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1045  	// ERTN
  1046  	{mask: 0xffffffff, value: 0x06483800, op: ERTN, args: instArgs{}},
  1047  	// EXT.W.B rd, rj
  1048  	{mask: 0xfffffc00, value: 0x00005c00, op: EXT_W_B, args: instArgs{arg_rd, arg_rj}},
  1049  	// EXT.W.H rd, rj
  1050  	{mask: 0xfffffc00, value: 0x00005800, op: EXT_W_H, args: instArgs{arg_rd, arg_rj}},
  1051  	// FABS.D fd, fj
  1052  	{mask: 0xfffffc00, value: 0x01140800, op: FABS_D, args: instArgs{arg_fd, arg_fj}},
  1053  	// FABS.S fd, fj
  1054  	{mask: 0xfffffc00, value: 0x01140400, op: FABS_S, args: instArgs{arg_fd, arg_fj}},
  1055  	// FADD.D fd, fj, fk
  1056  	{mask: 0xffff8000, value: 0x01010000, op: FADD_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1057  	// FADD.S fd, fj, fk
  1058  	{mask: 0xffff8000, value: 0x01008000, op: FADD_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1059  	// FCLASS.D fd, fj
  1060  	{mask: 0xfffffc00, value: 0x01143800, op: FCLASS_D, args: instArgs{arg_fd, arg_fj}},
  1061  	// FCLASS.S fd, fj
  1062  	{mask: 0xfffffc00, value: 0x01143400, op: FCLASS_S, args: instArgs{arg_fd, arg_fj}},
  1063  	// FCMP.CAF.D cd, fj, fk
  1064  	{mask: 0xffff8018, value: 0x0c200000, op: FCMP_CAF_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1065  	// FCMP.CAF.S cd, fj, fk
  1066  	{mask: 0xffff8018, value: 0x0c100000, op: FCMP_CAF_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1067  	// FCMP.CEQ.D cd, fj, fk
  1068  	{mask: 0xffff8018, value: 0x0c220000, op: FCMP_CEQ_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1069  	// FCMP.CEQ.S cd, fj, fk
  1070  	{mask: 0xffff8018, value: 0x0c120000, op: FCMP_CEQ_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1071  	// FCMP.CLE.D cd, fj, fk
  1072  	{mask: 0xffff8018, value: 0x0c230000, op: FCMP_CLE_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1073  	// FCMP.CLE.S cd, fj, fk
  1074  	{mask: 0xffff8018, value: 0x0c130000, op: FCMP_CLE_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1075  	// FCMP.CLT.D cd, fj, fk
  1076  	{mask: 0xffff8018, value: 0x0c210000, op: FCMP_CLT_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1077  	// FCMP.CLT.S cd, fj, fk
  1078  	{mask: 0xffff8018, value: 0x0c110000, op: FCMP_CLT_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1079  	// FCMP.CNE.D cd, fj, fk
  1080  	{mask: 0xffff8018, value: 0x0c280000, op: FCMP_CNE_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1081  	// FCMP.CNE.S cd, fj, fk
  1082  	{mask: 0xffff8018, value: 0x0c180000, op: FCMP_CNE_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1083  	// FCMP.COR.D cd, fj, fk
  1084  	{mask: 0xffff8018, value: 0x0c2a0000, op: FCMP_COR_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1085  	// FCMP.COR.S cd, fj, fk
  1086  	{mask: 0xffff8018, value: 0x0c1a0000, op: FCMP_COR_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1087  	// FCMP.CUEQ.D cd, fj, fk
  1088  	{mask: 0xffff8018, value: 0x0c260000, op: FCMP_CUEQ_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1089  	// FCMP.CUEQ.S cd, fj, fk
  1090  	{mask: 0xffff8018, value: 0x0c160000, op: FCMP_CUEQ_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1091  	// FCMP.CULE.D cd, fj, fk
  1092  	{mask: 0xffff8018, value: 0x0c270000, op: FCMP_CULE_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1093  	// FCMP.CULE.S cd, fj, fk
  1094  	{mask: 0xffff8018, value: 0x0c170000, op: FCMP_CULE_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1095  	// FCMP.CULT.D cd, fj, fk
  1096  	{mask: 0xffff8018, value: 0x0c250000, op: FCMP_CULT_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1097  	// FCMP.CULT.S cd, fj, fk
  1098  	{mask: 0xffff8018, value: 0x0c150000, op: FCMP_CULT_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1099  	// FCMP.CUNE.D cd, fj, fk
  1100  	{mask: 0xffff8018, value: 0x0c2c0000, op: FCMP_CUNE_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1101  	// FCMP.CUNE.S cd, fj, fk
  1102  	{mask: 0xffff8018, value: 0x0c1c0000, op: FCMP_CUNE_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1103  	// FCMP.CUN.D cd, fj, fk
  1104  	{mask: 0xffff8018, value: 0x0c240000, op: FCMP_CUN_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1105  	// FCMP.CUN.S cd, fj, fk
  1106  	{mask: 0xffff8018, value: 0x0c140000, op: FCMP_CUN_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1107  	// FCMP.SAF.D cd, fj, fk
  1108  	{mask: 0xffff8018, value: 0x0c208000, op: FCMP_SAF_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1109  	// FCMP.SAF.S cd, fj, fk
  1110  	{mask: 0xffff8018, value: 0x0c108000, op: FCMP_SAF_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1111  	// FCMP.SEQ.D cd, fj, fk
  1112  	{mask: 0xffff8018, value: 0x0c228000, op: FCMP_SEQ_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1113  	// FCMP.SEQ.S cd, fj, fk
  1114  	{mask: 0xffff8018, value: 0x0c128000, op: FCMP_SEQ_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1115  	// FCMP.SLE.D cd, fj, fk
  1116  	{mask: 0xffff8018, value: 0x0c238000, op: FCMP_SLE_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1117  	// FCMP.SLE.S cd, fj, fk
  1118  	{mask: 0xffff8018, value: 0x0c138000, op: FCMP_SLE_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1119  	// FCMP.SLT.D cd, fj, fk
  1120  	{mask: 0xffff8018, value: 0x0c218000, op: FCMP_SLT_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1121  	// FCMP.SLT.S cd, fj, fk
  1122  	{mask: 0xffff8018, value: 0x0c118000, op: FCMP_SLT_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1123  	// FCMP.SNE.D cd, fj, fk
  1124  	{mask: 0xffff8018, value: 0x0c288000, op: FCMP_SNE_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1125  	// FCMP.SNE.S cd, fj, fk
  1126  	{mask: 0xffff8018, value: 0x0c188000, op: FCMP_SNE_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1127  	// FCMP.SOR.D cd, fj, fk
  1128  	{mask: 0xffff8018, value: 0x0c2a8000, op: FCMP_SOR_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1129  	// FCMP.SOR.S cd, fj, fk
  1130  	{mask: 0xffff8018, value: 0x0c1a8000, op: FCMP_SOR_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1131  	// FCMP.SUEQ.D cd, fj, fk
  1132  	{mask: 0xffff8018, value: 0x0c268000, op: FCMP_SUEQ_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1133  	// FCMP.SUEQ.S cd, fj, fk
  1134  	{mask: 0xffff8018, value: 0x0c168000, op: FCMP_SUEQ_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1135  	// FCMP.SULE.D cd, fj, fk
  1136  	{mask: 0xffff8018, value: 0x0c278000, op: FCMP_SULE_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1137  	// FCMP.SULE.S cd, fj, fk
  1138  	{mask: 0xffff8018, value: 0x0c178000, op: FCMP_SULE_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1139  	// FCMP.SULT.D cd, fj, fk
  1140  	{mask: 0xffff8018, value: 0x0c258000, op: FCMP_SULT_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1141  	// FCMP.SULT.S cd, fj, fk
  1142  	{mask: 0xffff8018, value: 0x0c158000, op: FCMP_SULT_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1143  	// FCMP.SUNE.D cd, fj, fk
  1144  	{mask: 0xffff8018, value: 0x0c2c8000, op: FCMP_SUNE_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1145  	// FCMP.SUNE.S cd, fj, fk
  1146  	{mask: 0xffff8018, value: 0x0c1c8000, op: FCMP_SUNE_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1147  	// FCMP.SUN.D cd, fj, fk
  1148  	{mask: 0xffff8018, value: 0x0c248000, op: FCMP_SUN_D, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1149  	// FCMP.SUN.S cd, fj, fk
  1150  	{mask: 0xffff8018, value: 0x0c148000, op: FCMP_SUN_S, args: instArgs{arg_cd, arg_fj, arg_fk}},
  1151  	// FCOPYSIGN.D fd, fj, fk
  1152  	{mask: 0xffff8000, value: 0x01130000, op: FCOPYSIGN_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1153  	// FCOPYSIGN.S fd, fj, fk
  1154  	{mask: 0xffff8000, value: 0x01128000, op: FCOPYSIGN_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1155  	// FCVT.D.S fd, fj
  1156  	{mask: 0xfffffc00, value: 0x01192400, op: FCVT_D_S, args: instArgs{arg_fd, arg_fj}},
  1157  	// FCVT.S.D fd, fj
  1158  	{mask: 0xfffffc00, value: 0x01191800, op: FCVT_S_D, args: instArgs{arg_fd, arg_fj}},
  1159  	// FDIV.D fd, fj, fk
  1160  	{mask: 0xffff8000, value: 0x01070000, op: FDIV_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1161  	// FDIV.S fd, fj, fk
  1162  	{mask: 0xffff8000, value: 0x01068000, op: FDIV_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1163  	// FFINT.D.L fd, fj
  1164  	{mask: 0xfffffc00, value: 0x011d2800, op: FFINT_D_L, args: instArgs{arg_fd, arg_fj}},
  1165  	// FFINT.D.W fd, fj
  1166  	{mask: 0xfffffc00, value: 0x011d2000, op: FFINT_D_W, args: instArgs{arg_fd, arg_fj}},
  1167  	// FFINT.S.L fd, fj
  1168  	{mask: 0xfffffc00, value: 0x011d1800, op: FFINT_S_L, args: instArgs{arg_fd, arg_fj}},
  1169  	// FFINT.S.W fd, fj
  1170  	{mask: 0xfffffc00, value: 0x011d1000, op: FFINT_S_W, args: instArgs{arg_fd, arg_fj}},
  1171  	// FLDGT.D fd, rj, rk
  1172  	{mask: 0xffff8000, value: 0x38748000, op: FLDGT_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1173  	// FLDGT.S fd, rj, rk
  1174  	{mask: 0xffff8000, value: 0x38740000, op: FLDGT_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1175  	// FLDLE.D fd, rj, rk
  1176  	{mask: 0xffff8000, value: 0x38758000, op: FLDLE_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1177  	// FLDLE.S fd, rj, rk
  1178  	{mask: 0xffff8000, value: 0x38750000, op: FLDLE_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1179  	// FLDX.D fd, rj, rk
  1180  	{mask: 0xffff8000, value: 0x38340000, op: FLDX_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1181  	// FLDX.S fd, rj, rk
  1182  	{mask: 0xffff8000, value: 0x38300000, op: FLDX_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1183  	// FLD.D fd, rj, si12
  1184  	{mask: 0xffc00000, value: 0x2b800000, op: FLD_D, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
  1185  	// FLD.S fd, rj, si12
  1186  	{mask: 0xffc00000, value: 0x2b000000, op: FLD_S, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
  1187  	// FLOGB.D fd, fj
  1188  	{mask: 0xfffffc00, value: 0x01142800, op: FLOGB_D, args: instArgs{arg_fd, arg_fj}},
  1189  	// FLOGB.S fd, fj
  1190  	{mask: 0xfffffc00, value: 0x01142400, op: FLOGB_S, args: instArgs{arg_fd, arg_fj}},
  1191  	// FMADD.D fd, fj, fk, fa
  1192  	{mask: 0xfff00000, value: 0x08200000, op: FMADD_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
  1193  	// FMADD.S fd, fj, fk, fa
  1194  	{mask: 0xfff00000, value: 0x08100000, op: FMADD_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
  1195  	// FMAXA.D fd, fj, fk
  1196  	{mask: 0xffff8000, value: 0x010d0000, op: FMAXA_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1197  	// FMAXA.S fd, fj, fk
  1198  	{mask: 0xffff8000, value: 0x010c8000, op: FMAXA_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1199  	// FMAX.D fd, fj, fk
  1200  	{mask: 0xffff8000, value: 0x01090000, op: FMAX_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1201  	// FMAX.S fd, fj, fk
  1202  	{mask: 0xffff8000, value: 0x01088000, op: FMAX_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1203  	// FMINA.D fd, fj, fk
  1204  	{mask: 0xffff8000, value: 0x010f0000, op: FMINA_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1205  	// FMINA.S fd, fj, fk
  1206  	{mask: 0xffff8000, value: 0x010e8000, op: FMINA_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1207  	// FMIN.D fd, fj, fk
  1208  	{mask: 0xffff8000, value: 0x010b0000, op: FMIN_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1209  	// FMIN.S fd, fj, fk
  1210  	{mask: 0xffff8000, value: 0x010a8000, op: FMIN_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1211  	// FMOV.D fd, fj
  1212  	{mask: 0xfffffc00, value: 0x01149800, op: FMOV_D, args: instArgs{arg_fd, arg_fj}},
  1213  	// FMOV.S fd, fj
  1214  	{mask: 0xfffffc00, value: 0x01149400, op: FMOV_S, args: instArgs{arg_fd, arg_fj}},
  1215  	// FMSUB.D fd, fj, fk, fa
  1216  	{mask: 0xfff00000, value: 0x08600000, op: FMSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
  1217  	// FMSUB.S fd, fj, fk, fa
  1218  	{mask: 0xfff00000, value: 0x08500000, op: FMSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
  1219  	// FMUL.D fd, fj, fk
  1220  	{mask: 0xffff8000, value: 0x01050000, op: FMUL_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1221  	// FMUL.S fd, fj, fk
  1222  	{mask: 0xffff8000, value: 0x01048000, op: FMUL_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1223  	// FNEG.D fd, fj
  1224  	{mask: 0xfffffc00, value: 0x01141800, op: FNEG_D, args: instArgs{arg_fd, arg_fj}},
  1225  	// FNEG.S fd, fj
  1226  	{mask: 0xfffffc00, value: 0x01141400, op: FNEG_S, args: instArgs{arg_fd, arg_fj}},
  1227  	// FNMADD.D fd, fj, fk, fa
  1228  	{mask: 0xfff00000, value: 0x08a00000, op: FNMADD_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
  1229  	// FNMADD.S fd, fj, fk, fa
  1230  	{mask: 0xfff00000, value: 0x08900000, op: FNMADD_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
  1231  	// FNMSUB.D fd, fj, fk, fa
  1232  	{mask: 0xfff00000, value: 0x08e00000, op: FNMSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
  1233  	// FNMSUB.S fd, fj, fk, fa
  1234  	{mask: 0xfff00000, value: 0x08d00000, op: FNMSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}},
  1235  	// FRECIPE.D fd, fj
  1236  	{mask: 0xfffffc00, value: 0x01147800, op: FRECIPE_D, args: instArgs{arg_fd, arg_fj}},
  1237  	// FRECIPE.S fd, fj
  1238  	{mask: 0xfffffc00, value: 0x01147400, op: FRECIPE_S, args: instArgs{arg_fd, arg_fj}},
  1239  	// FRECIP.D fd, fj
  1240  	{mask: 0xfffffc00, value: 0x01145800, op: FRECIP_D, args: instArgs{arg_fd, arg_fj}},
  1241  	// FRECIP.S fd, fj
  1242  	{mask: 0xfffffc00, value: 0x01145400, op: FRECIP_S, args: instArgs{arg_fd, arg_fj}},
  1243  	// FRINT.D fd, fj
  1244  	{mask: 0xfffffc00, value: 0x011e4800, op: FRINT_D, args: instArgs{arg_fd, arg_fj}},
  1245  	// FRINT.S fd, fj
  1246  	{mask: 0xfffffc00, value: 0x011e4400, op: FRINT_S, args: instArgs{arg_fd, arg_fj}},
  1247  	// FRSQRTE.D fd, fj
  1248  	{mask: 0xfffffc00, value: 0x01148800, op: FRSQRTE_D, args: instArgs{arg_fd, arg_fj}},
  1249  	// FRSQRTE.S fd, fj
  1250  	{mask: 0xfffffc00, value: 0x01148400, op: FRSQRTE_S, args: instArgs{arg_fd, arg_fj}},
  1251  	// FRSQRT.D fd, fj
  1252  	{mask: 0xfffffc00, value: 0x01146800, op: FRSQRT_D, args: instArgs{arg_fd, arg_fj}},
  1253  	// FRSQRT.S fd, fj
  1254  	{mask: 0xfffffc00, value: 0x01146400, op: FRSQRT_S, args: instArgs{arg_fd, arg_fj}},
  1255  	// FSCALEB.D fd, fj, fk
  1256  	{mask: 0xffff8000, value: 0x01110000, op: FSCALEB_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1257  	// FSCALEB.S fd, fj, fk
  1258  	{mask: 0xffff8000, value: 0x01108000, op: FSCALEB_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1259  	// FSEL fd, fj, fk, ca
  1260  	{mask: 0xfffc0000, value: 0x0d000000, op: FSEL, args: instArgs{arg_fd, arg_fj, arg_fk, arg_ca}},
  1261  	// FSQRT.D fd, fj
  1262  	{mask: 0xfffffc00, value: 0x01144800, op: FSQRT_D, args: instArgs{arg_fd, arg_fj}},
  1263  	// FSQRT.S fd, fj
  1264  	{mask: 0xfffffc00, value: 0x01144400, op: FSQRT_S, args: instArgs{arg_fd, arg_fj}},
  1265  	// FSTGT.D fd, rj, rk
  1266  	{mask: 0xffff8000, value: 0x38768000, op: FSTGT_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1267  	// FSTGT.S fd, rj, rk
  1268  	{mask: 0xffff8000, value: 0x38760000, op: FSTGT_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1269  	// FSTLE.D fd, rj, rk
  1270  	{mask: 0xffff8000, value: 0x38778000, op: FSTLE_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1271  	// FSTLE.S fd, rj, rk
  1272  	{mask: 0xffff8000, value: 0x38770000, op: FSTLE_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1273  	// FSTX.D fd, rj, rk
  1274  	{mask: 0xffff8000, value: 0x383c0000, op: FSTX_D, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1275  	// FSTX.S fd, rj, rk
  1276  	{mask: 0xffff8000, value: 0x38380000, op: FSTX_S, args: instArgs{arg_fd, arg_rj, arg_rk}},
  1277  	// FST.D fd, rj, si12
  1278  	{mask: 0xffc00000, value: 0x2bc00000, op: FST_D, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
  1279  	// FST.S fd, rj, si12
  1280  	{mask: 0xffc00000, value: 0x2b400000, op: FST_S, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}},
  1281  	// FSUB.D fd, fj, fk
  1282  	{mask: 0xffff8000, value: 0x01030000, op: FSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1283  	// FSUB.S fd, fj, fk
  1284  	{mask: 0xffff8000, value: 0x01028000, op: FSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk}},
  1285  	// FTINTRM.L.D fd, fj
  1286  	{mask: 0xfffffc00, value: 0x011a2800, op: FTINTRM_L_D, args: instArgs{arg_fd, arg_fj}},
  1287  	// FTINTRM.L.S fd, fj
  1288  	{mask: 0xfffffc00, value: 0x011a2400, op: FTINTRM_L_S, args: instArgs{arg_fd, arg_fj}},
  1289  	// FTINTRM.W.D fd, fj
  1290  	{mask: 0xfffffc00, value: 0x011a0800, op: FTINTRM_W_D, args: instArgs{arg_fd, arg_fj}},
  1291  	// FTINTRM.W.S fd, fj
  1292  	{mask: 0xfffffc00, value: 0x011a0400, op: FTINTRM_W_S, args: instArgs{arg_fd, arg_fj}},
  1293  	// FTINTRNE.L.D fd, fj
  1294  	{mask: 0xfffffc00, value: 0x011ae800, op: FTINTRNE_L_D, args: instArgs{arg_fd, arg_fj}},
  1295  	// FTINTRNE.L.S fd, fj
  1296  	{mask: 0xfffffc00, value: 0x011ae400, op: FTINTRNE_L_S, args: instArgs{arg_fd, arg_fj}},
  1297  	// FTINTRNE.W.D fd, fj
  1298  	{mask: 0xfffffc00, value: 0x011ac800, op: FTINTRNE_W_D, args: instArgs{arg_fd, arg_fj}},
  1299  	// FTINTRNE.W.S fd, fj
  1300  	{mask: 0xfffffc00, value: 0x011ac400, op: FTINTRNE_W_S, args: instArgs{arg_fd, arg_fj}},
  1301  	// FTINTRP.L.D fd, fj
  1302  	{mask: 0xfffffc00, value: 0x011a6800, op: FTINTRP_L_D, args: instArgs{arg_fd, arg_fj}},
  1303  	// FTINTRP.L.S fd, fj
  1304  	{mask: 0xfffffc00, value: 0x011a6400, op: FTINTRP_L_S, args: instArgs{arg_fd, arg_fj}},
  1305  	// FTINTRP.W.D fd, fj
  1306  	{mask: 0xfffffc00, value: 0x011a4800, op: FTINTRP_W_D, args: instArgs{arg_fd, arg_fj}},
  1307  	// FTINTRP.W.S fd, fj
  1308  	{mask: 0xfffffc00, value: 0x011a4400, op: FTINTRP_W_S, args: instArgs{arg_fd, arg_fj}},
  1309  	// FTINTRZ.L.D fd, fj
  1310  	{mask: 0xfffffc00, value: 0x011aa800, op: FTINTRZ_L_D, args: instArgs{arg_fd, arg_fj}},
  1311  	// FTINTRZ.L.S fd, fj
  1312  	{mask: 0xfffffc00, value: 0x011aa400, op: FTINTRZ_L_S, args: instArgs{arg_fd, arg_fj}},
  1313  	// FTINTRZ.W.D fd, fj
  1314  	{mask: 0xfffffc00, value: 0x011a8800, op: FTINTRZ_W_D, args: instArgs{arg_fd, arg_fj}},
  1315  	// FTINTRZ.W.S fd, fj
  1316  	{mask: 0xfffffc00, value: 0x011a8400, op: FTINTRZ_W_S, args: instArgs{arg_fd, arg_fj}},
  1317  	// FTINT.L.D fd, fj
  1318  	{mask: 0xfffffc00, value: 0x011b2800, op: FTINT_L_D, args: instArgs{arg_fd, arg_fj}},
  1319  	// FTINT.L.S fd, fj
  1320  	{mask: 0xfffffc00, value: 0x011b2400, op: FTINT_L_S, args: instArgs{arg_fd, arg_fj}},
  1321  	// FTINT.W.D fd, fj
  1322  	{mask: 0xfffffc00, value: 0x011b0800, op: FTINT_W_D, args: instArgs{arg_fd, arg_fj}},
  1323  	// FTINT.W.S fd, fj
  1324  	{mask: 0xfffffc00, value: 0x011b0400, op: FTINT_W_S, args: instArgs{arg_fd, arg_fj}},
  1325  	// IBAR hint
  1326  	{mask: 0xffff8000, value: 0x38728000, op: IBAR, args: instArgs{arg_hint_14_0}},
  1327  	// IDLE level
  1328  	{mask: 0xffff8000, value: 0x06488000, op: IDLE, args: instArgs{arg_level_14_0}},
  1329  	// INVTLB op, rj, rk
  1330  	{mask: 0xffff8000, value: 0x06498000, op: INVTLB, args: instArgs{arg_op_4_0, arg_rj, arg_rk}},
  1331  	// IOCSRRD.B rd, rj
  1332  	{mask: 0xfffffc00, value: 0x06480000, op: IOCSRRD_B, args: instArgs{arg_rd, arg_rj}},
  1333  	// IOCSRRD.D rd, rj
  1334  	{mask: 0xfffffc00, value: 0x06480c00, op: IOCSRRD_D, args: instArgs{arg_rd, arg_rj}},
  1335  	// IOCSRRD.H rd, rj
  1336  	{mask: 0xfffffc00, value: 0x06480400, op: IOCSRRD_H, args: instArgs{arg_rd, arg_rj}},
  1337  	// IOCSRRD.W rd, rj
  1338  	{mask: 0xfffffc00, value: 0x06480800, op: IOCSRRD_W, args: instArgs{arg_rd, arg_rj}},
  1339  	// IOCSRWR.B rd, rj
  1340  	{mask: 0xfffffc00, value: 0x06481000, op: IOCSRWR_B, args: instArgs{arg_rd, arg_rj}},
  1341  	// IOCSRWR.D rd, rj
  1342  	{mask: 0xfffffc00, value: 0x06481c00, op: IOCSRWR_D, args: instArgs{arg_rd, arg_rj}},
  1343  	// IOCSRWR.H rd, rj
  1344  	{mask: 0xfffffc00, value: 0x06481400, op: IOCSRWR_H, args: instArgs{arg_rd, arg_rj}},
  1345  	// IOCSRWR.W rd, rj
  1346  	{mask: 0xfffffc00, value: 0x06481800, op: IOCSRWR_W, args: instArgs{arg_rd, arg_rj}},
  1347  	// JIRL rd, rj, offs
  1348  	{mask: 0xfc000000, value: 0x4c000000, op: JIRL, args: instArgs{arg_rd, arg_rj, arg_offset_15_0}},
  1349  	// LDDIR rd, rj, level
  1350  	{mask: 0xfffc0000, value: 0x06400000, op: LDDIR, args: instArgs{arg_rd, arg_rj, arg_level_17_10}},
  1351  	// LDGT.B rd, rj, rk
  1352  	{mask: 0xffff8000, value: 0x38780000, op: LDGT_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1353  	// LDGT.D rd, rj, rk
  1354  	{mask: 0xffff8000, value: 0x38798000, op: LDGT_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1355  	// LDGT.H rd, rj, rk
  1356  	{mask: 0xffff8000, value: 0x38788000, op: LDGT_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1357  	// LDGT.W rd, rj, rk
  1358  	{mask: 0xffff8000, value: 0x38790000, op: LDGT_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1359  	// LDLE.B rd, rj, rk
  1360  	{mask: 0xffff8000, value: 0x387a0000, op: LDLE_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1361  	// LDLE.D rd, rj, rk
  1362  	{mask: 0xffff8000, value: 0x387b8000, op: LDLE_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1363  	// LDLE.H rd, rj, rk
  1364  	{mask: 0xffff8000, value: 0x387a8000, op: LDLE_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1365  	// LDLE.W rd, rj, rk
  1366  	{mask: 0xffff8000, value: 0x387b0000, op: LDLE_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1367  	// LDPTE rj, seq
  1368  	{mask: 0xfffc001f, value: 0x06440000, op: LDPTE, args: instArgs{arg_rj, arg_seq_17_10}},
  1369  	// LDPTR.D rd, rj, si14
  1370  	{mask: 0xff000000, value: 0x26000000, op: LDPTR_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
  1371  	// LDPTR.W rd, rj, si14
  1372  	{mask: 0xff000000, value: 0x24000000, op: LDPTR_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
  1373  	// LDX.B rd, rj, rk
  1374  	{mask: 0xffff8000, value: 0x38000000, op: LDX_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1375  	// LDX.BU rd, rj, rk
  1376  	{mask: 0xffff8000, value: 0x38200000, op: LDX_BU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1377  	// LDX.D rd, rj, rk
  1378  	{mask: 0xffff8000, value: 0x380c0000, op: LDX_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1379  	// LDX.H rd, rj, rk
  1380  	{mask: 0xffff8000, value: 0x38040000, op: LDX_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1381  	// LDX.HU rd, rj, rk
  1382  	{mask: 0xffff8000, value: 0x38240000, op: LDX_HU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1383  	// LDX.W rd, rj, rk
  1384  	{mask: 0xffff8000, value: 0x38080000, op: LDX_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1385  	// LDX.WU rd, rj, rk
  1386  	{mask: 0xffff8000, value: 0x38280000, op: LDX_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1387  	// LD.B rd, rj, si12
  1388  	{mask: 0xffc00000, value: 0x28000000, op: LD_B, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1389  	// LD.BU rd, rj, si12
  1390  	{mask: 0xffc00000, value: 0x2a000000, op: LD_BU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1391  	// LD.D rd, rj, si12
  1392  	{mask: 0xffc00000, value: 0x28c00000, op: LD_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1393  	// LD.H rd, rj, si12
  1394  	{mask: 0xffc00000, value: 0x28400000, op: LD_H, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1395  	// LD.HU rd, rj, si12
  1396  	{mask: 0xffc00000, value: 0x2a400000, op: LD_HU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1397  	// LD.W rd, rj, si12
  1398  	{mask: 0xffc00000, value: 0x28800000, op: LD_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1399  	// LD.WU rd, rj, si12
  1400  	{mask: 0xffc00000, value: 0x2a800000, op: LD_WU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1401  	// LLACQ.D rd, rj
  1402  	{mask: 0xfffffc00, value: 0x38578800, op: LLACQ_D, args: instArgs{arg_rd, arg_rj}},
  1403  	// LLACQ.W rd, rj
  1404  	{mask: 0xfffffc00, value: 0x38578000, op: LLACQ_W, args: instArgs{arg_rd, arg_rj}},
  1405  	// LL.D rd, rj, si14
  1406  	{mask: 0xff000000, value: 0x22000000, op: LL_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
  1407  	// LL.W rd, rj, si14
  1408  	{mask: 0xff000000, value: 0x20000000, op: LL_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
  1409  	// LU12I.W rd, si20
  1410  	{mask: 0xfe000000, value: 0x14000000, op: LU12I_W, args: instArgs{arg_rd, arg_si20_24_5}},
  1411  	// LU32I.D rd, si20
  1412  	{mask: 0xfe000000, value: 0x16000000, op: LU32I_D, args: instArgs{arg_rd, arg_si20_24_5}},
  1413  	// LU52I.D rd, rj, si12
  1414  	{mask: 0xffc00000, value: 0x03000000, op: LU52I_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1415  	// MASKEQZ rd, rj, rk
  1416  	{mask: 0xffff8000, value: 0x00130000, op: MASKEQZ, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1417  	// MASKNEZ rd, rj, rk
  1418  	{mask: 0xffff8000, value: 0x00138000, op: MASKNEZ, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1419  	// MOD.D rd, rj, rk
  1420  	{mask: 0xffff8000, value: 0x00228000, op: MOD_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1421  	// MOD.DU rd, rj, rk
  1422  	{mask: 0xffff8000, value: 0x00238000, op: MOD_DU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1423  	// MOD.W rd, rj, rk
  1424  	{mask: 0xffff8000, value: 0x00208000, op: MOD_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1425  	// MOD.WU rd, rj, rk
  1426  	{mask: 0xffff8000, value: 0x00218000, op: MOD_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1427  	// MOVCF2FR fd, cj
  1428  	{mask: 0xffffff00, value: 0x0114d400, op: MOVCF2FR, args: instArgs{arg_fd, arg_cj}},
  1429  	// MOVCF2GR rd, cj
  1430  	{mask: 0xffffff00, value: 0x0114dc00, op: MOVCF2GR, args: instArgs{arg_rd, arg_cj}},
  1431  	// MOVFCSR2GR rd, fcsr
  1432  	{mask: 0xfffffc00, value: 0x0114c800, op: MOVFCSR2GR, args: instArgs{arg_rd, arg_fcsr_9_5}},
  1433  	// MOVFR2CF cd, fj
  1434  	{mask: 0xfffffc18, value: 0x0114d000, op: MOVFR2CF, args: instArgs{arg_cd, arg_fj}},
  1435  	// MOVFR2GR.D rd, fj
  1436  	{mask: 0xfffffc00, value: 0x0114b800, op: MOVFR2GR_D, args: instArgs{arg_rd, arg_fj}},
  1437  	// MOVFR2GR.S rd, fj
  1438  	{mask: 0xfffffc00, value: 0x0114b400, op: MOVFR2GR_S, args: instArgs{arg_rd, arg_fj}},
  1439  	// MOVFRH2GR.S rd, fj
  1440  	{mask: 0xfffffc00, value: 0x0114bc00, op: MOVFRH2GR_S, args: instArgs{arg_rd, arg_fj}},
  1441  	// MOVGR2CF cd, rj
  1442  	{mask: 0xfffffc18, value: 0x0114d800, op: MOVGR2CF, args: instArgs{arg_cd, arg_rj}},
  1443  	// MOVGR2FCSR fcsr, rj
  1444  	{mask: 0xfffffc00, value: 0x0114c000, op: MOVGR2FCSR, args: instArgs{arg_fcsr_4_0, arg_rj}},
  1445  	// MOVGR2FRH.W fd, rj
  1446  	{mask: 0xfffffc00, value: 0x0114ac00, op: MOVGR2FRH_W, args: instArgs{arg_fd, arg_rj}},
  1447  	// MOVGR2FR.D fd, rj
  1448  	{mask: 0xfffffc00, value: 0x0114a800, op: MOVGR2FR_D, args: instArgs{arg_fd, arg_rj}},
  1449  	// MOVGR2FR.W fd, rj
  1450  	{mask: 0xfffffc00, value: 0x0114a400, op: MOVGR2FR_W, args: instArgs{arg_fd, arg_rj}},
  1451  	// MULH.D rd, rj, rk
  1452  	{mask: 0xffff8000, value: 0x001e0000, op: MULH_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1453  	// MULH.DU rd, rj, rk
  1454  	{mask: 0xffff8000, value: 0x001e8000, op: MULH_DU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1455  	// MULH.W rd, rj, rk
  1456  	{mask: 0xffff8000, value: 0x001c8000, op: MULH_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1457  	// MULH.WU rd, rj, rk
  1458  	{mask: 0xffff8000, value: 0x001d0000, op: MULH_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1459  	// MULW.D.W rd, rj, rk
  1460  	{mask: 0xffff8000, value: 0x001f0000, op: MULW_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1461  	// MULW.D.WU rd, rj, rk
  1462  	{mask: 0xffff8000, value: 0x001f8000, op: MULW_D_WU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1463  	// MUL.D rd, rj, rk
  1464  	{mask: 0xffff8000, value: 0x001d8000, op: MUL_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1465  	// MUL.W rd, rj, rk
  1466  	{mask: 0xffff8000, value: 0x001c0000, op: MUL_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1467  	// NOR rd, rj, rk
  1468  	{mask: 0xffff8000, value: 0x00140000, op: NOR, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1469  	// OR rd, rj, rk
  1470  	{mask: 0xffff8000, value: 0x00150000, op: OR, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1471  	// ORI rd, rj, ui12
  1472  	{mask: 0xffc00000, value: 0x03800000, op: ORI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
  1473  	// ORN rd, rj, rk
  1474  	{mask: 0xffff8000, value: 0x00160000, op: ORN, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1475  	// PCADDI rd, si20
  1476  	{mask: 0xfe000000, value: 0x18000000, op: PCADDI, args: instArgs{arg_rd, arg_si20_24_5}},
  1477  	// PCADDU12I rd, si20
  1478  	{mask: 0xfe000000, value: 0x1c000000, op: PCADDU12I, args: instArgs{arg_rd, arg_si20_24_5}},
  1479  	// PCADDU18I rd, si20
  1480  	{mask: 0xfe000000, value: 0x1e000000, op: PCADDU18I, args: instArgs{arg_rd, arg_si20_24_5}},
  1481  	// PCALAU12I rd, si20
  1482  	{mask: 0xfe000000, value: 0x1a000000, op: PCALAU12I, args: instArgs{arg_rd, arg_si20_24_5}},
  1483  	// PRELD hint, rj, si12
  1484  	{mask: 0xffc00000, value: 0x2ac00000, op: PRELD, args: instArgs{arg_hint_4_0, arg_rj, arg_si12_21_10}},
  1485  	// PRELDX hint, rj, rk
  1486  	{mask: 0xffff8000, value: 0x382c0000, op: PRELDX, args: instArgs{arg_hint_4_0, arg_rj, arg_rk}},
  1487  	// RDTIMEH.W rd, rj
  1488  	{mask: 0xfffffc00, value: 0x00006400, op: RDTIMEH_W, args: instArgs{arg_rd, arg_rj}},
  1489  	// RDTIMEL.W rd, rj
  1490  	{mask: 0xfffffc00, value: 0x00006000, op: RDTIMEL_W, args: instArgs{arg_rd, arg_rj}},
  1491  	// RDTIME.D rd, rj
  1492  	{mask: 0xfffffc00, value: 0x00006800, op: RDTIME_D, args: instArgs{arg_rd, arg_rj}},
  1493  	// REVB.2H rd, rj
  1494  	{mask: 0xfffffc00, value: 0x00003000, op: REVB_2H, args: instArgs{arg_rd, arg_rj}},
  1495  	// REVB.2W rd, rj
  1496  	{mask: 0xfffffc00, value: 0x00003800, op: REVB_2W, args: instArgs{arg_rd, arg_rj}},
  1497  	// REVB.4H rd, rj
  1498  	{mask: 0xfffffc00, value: 0x00003400, op: REVB_4H, args: instArgs{arg_rd, arg_rj}},
  1499  	// REVB.D rd, rj
  1500  	{mask: 0xfffffc00, value: 0x00003c00, op: REVB_D, args: instArgs{arg_rd, arg_rj}},
  1501  	// REVH.2W rd, rj
  1502  	{mask: 0xfffffc00, value: 0x00004000, op: REVH_2W, args: instArgs{arg_rd, arg_rj}},
  1503  	// REVH.D rd, rj
  1504  	{mask: 0xfffffc00, value: 0x00004400, op: REVH_D, args: instArgs{arg_rd, arg_rj}},
  1505  	// ROTRI.D rd, rj, ui6
  1506  	{mask: 0xffff0000, value: 0x004d0000, op: ROTRI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
  1507  	// ROTRI.W rd, rj, ui5
  1508  	{mask: 0xffff8000, value: 0x004c8000, op: ROTRI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
  1509  	// ROTR.D rd, rj, rk
  1510  	{mask: 0xffff8000, value: 0x001b8000, op: ROTR_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1511  	// ROTR.W rd, rj, rk
  1512  	{mask: 0xffff8000, value: 0x001b0000, op: ROTR_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1513  	// SCREL.D rd, rj
  1514  	{mask: 0xfffffc00, value: 0x38578c00, op: SCREL_D, args: instArgs{arg_rd, arg_rj}},
  1515  	// SCREL.W rd, rj
  1516  	{mask: 0xfffffc00, value: 0x38578400, op: SCREL_W, args: instArgs{arg_rd, arg_rj}},
  1517  	// SC.D rd, rj, si14
  1518  	{mask: 0xff000000, value: 0x23000000, op: SC_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
  1519  	// SC.Q rd, rk, rj
  1520  	{mask: 0xffff8000, value: 0x38570000, op: SC_Q, args: instArgs{arg_rd, arg_rk, arg_rj}},
  1521  	// SC.W rd, rj, si14
  1522  	{mask: 0xff000000, value: 0x21000000, op: SC_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
  1523  	// SLLI.D rd, rj, ui6
  1524  	{mask: 0xffff0000, value: 0x00410000, op: SLLI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
  1525  	// SLLI.W rd, rj, ui5
  1526  	{mask: 0xffff8000, value: 0x00408000, op: SLLI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
  1527  	// SLL.D rd, rj, rk
  1528  	{mask: 0xffff8000, value: 0x00188000, op: SLL_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1529  	// SLL.W rd, rj, rk
  1530  	{mask: 0xffff8000, value: 0x00170000, op: SLL_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1531  	// SLT rd, rj, rk
  1532  	{mask: 0xffff8000, value: 0x00120000, op: SLT, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1533  	// SLTI rd, rj, si12
  1534  	{mask: 0xffc00000, value: 0x02000000, op: SLTI, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1535  	// SLTU rd, rj, rk
  1536  	{mask: 0xffff8000, value: 0x00128000, op: SLTU, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1537  	// SLTUI rd, rj, si12
  1538  	{mask: 0xffc00000, value: 0x02400000, op: SLTUI, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1539  	// SRAI.D rd, rj, ui6
  1540  	{mask: 0xffff0000, value: 0x00490000, op: SRAI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
  1541  	// SRAI.W rd, rj, ui5
  1542  	{mask: 0xffff8000, value: 0x00488000, op: SRAI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
  1543  	// SRA.D rd, rj, rk
  1544  	{mask: 0xffff8000, value: 0x00198000, op: SRA_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1545  	// SRA.W rd, rj, rk
  1546  	{mask: 0xffff8000, value: 0x00180000, op: SRA_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1547  	// SRLI.D rd, rj, ui6
  1548  	{mask: 0xffff0000, value: 0x00450000, op: SRLI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}},
  1549  	// SRLI.W rd, rj, ui5
  1550  	{mask: 0xffff8000, value: 0x00448000, op: SRLI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}},
  1551  	// SRL.D rd, rj, rk
  1552  	{mask: 0xffff8000, value: 0x00190000, op: SRL_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1553  	// SRL.W rd, rj, rk
  1554  	{mask: 0xffff8000, value: 0x00178000, op: SRL_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1555  	// STGT.B rd, rj, rk
  1556  	{mask: 0xffff8000, value: 0x387c0000, op: STGT_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1557  	// STGT.D rd, rj, rk
  1558  	{mask: 0xffff8000, value: 0x387d8000, op: STGT_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1559  	// STGT.H rd, rj, rk
  1560  	{mask: 0xffff8000, value: 0x387c8000, op: STGT_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1561  	// STGT.W rd, rj, rk
  1562  	{mask: 0xffff8000, value: 0x387d0000, op: STGT_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1563  	// STLE.B rd, rj, rk
  1564  	{mask: 0xffff8000, value: 0x387e0000, op: STLE_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1565  	// STLE.D rd, rj, rk
  1566  	{mask: 0xffff8000, value: 0x387f8000, op: STLE_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1567  	// STLE.H rd, rj, rk
  1568  	{mask: 0xffff8000, value: 0x387e8000, op: STLE_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1569  	// STLE.W rd, rj, rk
  1570  	{mask: 0xffff8000, value: 0x387f0000, op: STLE_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1571  	// STPTR.D rd, rj, si14
  1572  	{mask: 0xff000000, value: 0x27000000, op: STPTR_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
  1573  	// STPTR.W rd, rj, si14
  1574  	{mask: 0xff000000, value: 0x25000000, op: STPTR_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}},
  1575  	// STX.B rd, rj, rk
  1576  	{mask: 0xffff8000, value: 0x38100000, op: STX_B, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1577  	// STX.D rd, rj, rk
  1578  	{mask: 0xffff8000, value: 0x381c0000, op: STX_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1579  	// STX.H rd, rj, rk
  1580  	{mask: 0xffff8000, value: 0x38140000, op: STX_H, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1581  	// STX.W rd, rj, rk
  1582  	{mask: 0xffff8000, value: 0x38180000, op: STX_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1583  	// ST.B rd, rj, si12
  1584  	{mask: 0xffc00000, value: 0x29000000, op: ST_B, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1585  	// ST.D rd, rj, si12
  1586  	{mask: 0xffc00000, value: 0x29c00000, op: ST_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1587  	// ST.H rd, rj, si12
  1588  	{mask: 0xffc00000, value: 0x29400000, op: ST_H, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1589  	// ST.W rd, rj, si12
  1590  	{mask: 0xffc00000, value: 0x29800000, op: ST_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}},
  1591  	// SUB.D rd, rj, rk
  1592  	{mask: 0xffff8000, value: 0x00118000, op: SUB_D, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1593  	// SUB.W rd, rj, rk
  1594  	{mask: 0xffff8000, value: 0x00110000, op: SUB_W, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1595  	// SYSCALL code
  1596  	{mask: 0xffff8000, value: 0x002b0000, op: SYSCALL, args: instArgs{arg_code_14_0}},
  1597  	// TLBCLR
  1598  	{mask: 0xffffffff, value: 0x06482000, op: TLBCLR, args: instArgs{}},
  1599  	// TLBFILL
  1600  	{mask: 0xffffffff, value: 0x06483400, op: TLBFILL, args: instArgs{}},
  1601  	// TLBFLUSH
  1602  	{mask: 0xffffffff, value: 0x06482400, op: TLBFLUSH, args: instArgs{}},
  1603  	// TLBRD
  1604  	{mask: 0xffffffff, value: 0x06482c00, op: TLBRD, args: instArgs{}},
  1605  	// TLBSRCH
  1606  	{mask: 0xffffffff, value: 0x06482800, op: TLBSRCH, args: instArgs{}},
  1607  	// TLBWR
  1608  	{mask: 0xffffffff, value: 0x06483000, op: TLBWR, args: instArgs{}},
  1609  	// XOR rd, rj, rk
  1610  	{mask: 0xffff8000, value: 0x00158000, op: XOR, args: instArgs{arg_rd, arg_rj, arg_rk}},
  1611  	// XORI rd, rj, ui12
  1612  	{mask: 0xffc00000, value: 0x03c00000, op: XORI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}},
  1613  }
  1614  

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