Source file src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/arg.go
1 // Copyright 2024 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 package riscv64asm 6 7 // Naming for Go decoder arguments: 8 // 9 // - arg_rd: a general purpose register rd encoded in rd[11:7] field 10 // 11 // - arg_rs1: a general purpose register rs1 encoded in rs1[19:15] field 12 // 13 // - arg_rs2: a general purpose register rs2 encoded in rs2[24:20] field 14 // 15 // - arg_rs3: a general purpose register rs3 encoded in rs3[31:27] field 16 // 17 // - arg_fd: a floating point register rd encoded in rd[11:7] field 18 // 19 // - arg_fs1: a floating point register rs1 encoded in rs1[19:15] field 20 // 21 // - arg_fs2: a floating point register rs2 encoded in rs2[24:20] field 22 // 23 // - arg_fs3: a floating point register rs3 encoded in rs3[31:27] field 24 // 25 // - arg_vd: a vector register vd encoded in vd[11:7] field 26 // 27 // - arg_vm: indicates the presence of the mask register, encoded in vm[25] field 28 // 29 // - arg_vs1: a vector register vs1 encoded in vs1[19:15] field 30 // 31 // - arg_vs2: a vector register vs3 encoded in vs2[20:24] field 32 // 33 // - arg_vs3: a vector register vs3 encoded in vs3[11:7] field 34 // 35 // - arg_csr: a control status register encoded in csr[31:20] field 36 // 37 // - arg_rs1_mem: source register with offset in load commands 38 // 39 // - arg_rs1_store: source register with offset in store commands 40 // 41 // - arg_rs1_ptr: source register used as an address with no offset in atomic and vector commands 42 // 43 // - arg_pred: predecessor memory ordering information encoded in pred[27:24] field 44 // For details, please refer to chapter 2.7 of ISA manual volume 1 45 // 46 // - arg_succ: successor memory ordering information encoded in succ[23:20] field 47 // For details, please refer to chapter 2.7 of ISA manual volume 1 48 // 49 // - arg_zimm: a unsigned immediate encoded in zimm[19:15] field 50 // 51 // - arg_imm12: an I-type immediate encoded in imm12[31:20] field 52 // 53 // - arg_simm12: a S-type immediate encoded in simm12[31:25|11:7] field 54 // 55 // - arg_bimm12: a B-type immediate encoded in bimm12[31:25|11:7] field 56 // 57 // - arg_imm20: an U-type immediate encoded in imm20[31:12] field 58 // 59 // - arg_simm5: a 5 bit signed immediate encoded in imm[19:15] field 60 // 61 // - arg_zimm5: a 5 bit unsigned immediate encoded in imm[19:15] field 62 // 63 // - arg_vtype_zimm10: a 10 bit unsigned immediate encoded in vtypei[29:20] field 64 // 65 // - arg_vtype_zimm11: an 11 bit unsigned immediate encoded in vtypei[30:20] field 66 // 67 // - arg_jimm20: a J-type immediate encoded in jimm20[31:12] field 68 // 69 // - arg_shamt5: a shift amount encoded in shamt5[24:20] field 70 // 71 // - arg_shamt6: a shift amount encoded in shamt6[25:20] field 72 // 73 74 type argType uint16 75 76 const ( 77 _ argType = iota 78 arg_rd 79 arg_rs1 80 arg_rs2 81 arg_rs3 82 arg_fd 83 arg_fs1 84 arg_fs2 85 arg_fs3 86 arg_vd 87 arg_vm 88 arg_vs1 89 arg_vs2 90 arg_vs3 91 arg_csr 92 93 arg_rs1_ptr 94 arg_rs1_mem 95 arg_rs1_store 96 97 arg_pred 98 arg_succ 99 100 arg_zimm 101 arg_imm12 102 arg_simm12 103 arg_simm5 104 arg_zimm5 105 arg_vtype_zimm10 106 arg_vtype_zimm11 107 arg_bimm12 108 arg_imm20 109 arg_jimm20 110 arg_shamt5 111 arg_shamt6 112 113 // RISC-V Compressed Extension Args 114 arg_rd_p 115 arg_fd_p 116 arg_rs1_p 117 arg_rd_rs1_p 118 arg_fs2_p 119 arg_rs2_p 120 arg_rd_n0 121 arg_rs1_n0 122 arg_rd_rs1_n0 123 arg_c_rs1_n0 124 arg_c_rs2_n0 125 arg_c_fs2 126 arg_c_rs2 127 arg_rd_n2 128 129 arg_c_imm6 130 arg_c_nzimm6 131 arg_c_nzuimm6 132 arg_c_uimm7 133 arg_c_uimm8 134 arg_c_uimm8sp_s 135 arg_c_uimm8sp 136 arg_c_uimm9sp_s 137 arg_c_uimm9sp 138 arg_c_bimm9 139 arg_c_nzimm10 140 arg_c_nzuimm10 141 arg_c_imm12 142 arg_c_nzimm18 143 ) 144