Source file src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/tables.go

     1  // Code generated by 'go run ../riscv64spec riscv-opcodes'; DO NOT EDIT.
     2  
     3  // Copyright 2024 The Go Authors. All rights reserved.
     4  // Use of this source code is governed by a BSD-style
     5  // license that can be found in the LICENSE file.
     6  
     7  package riscv64asm
     8  
     9  const (
    10  	_ Op = iota
    11  	ADD
    12  	ADDI
    13  	ADDIW
    14  	ADDW
    15  	ADD_UW
    16  	AMOADD_D
    17  	AMOADD_D_AQ
    18  	AMOADD_D_AQRL
    19  	AMOADD_D_RL
    20  	AMOADD_W
    21  	AMOADD_W_AQ
    22  	AMOADD_W_AQRL
    23  	AMOADD_W_RL
    24  	AMOAND_D
    25  	AMOAND_D_AQ
    26  	AMOAND_D_AQRL
    27  	AMOAND_D_RL
    28  	AMOAND_W
    29  	AMOAND_W_AQ
    30  	AMOAND_W_AQRL
    31  	AMOAND_W_RL
    32  	AMOMAXU_D
    33  	AMOMAXU_D_AQ
    34  	AMOMAXU_D_AQRL
    35  	AMOMAXU_D_RL
    36  	AMOMAXU_W
    37  	AMOMAXU_W_AQ
    38  	AMOMAXU_W_AQRL
    39  	AMOMAXU_W_RL
    40  	AMOMAX_D
    41  	AMOMAX_D_AQ
    42  	AMOMAX_D_AQRL
    43  	AMOMAX_D_RL
    44  	AMOMAX_W
    45  	AMOMAX_W_AQ
    46  	AMOMAX_W_AQRL
    47  	AMOMAX_W_RL
    48  	AMOMINU_D
    49  	AMOMINU_D_AQ
    50  	AMOMINU_D_AQRL
    51  	AMOMINU_D_RL
    52  	AMOMINU_W
    53  	AMOMINU_W_AQ
    54  	AMOMINU_W_AQRL
    55  	AMOMINU_W_RL
    56  	AMOMIN_D
    57  	AMOMIN_D_AQ
    58  	AMOMIN_D_AQRL
    59  	AMOMIN_D_RL
    60  	AMOMIN_W
    61  	AMOMIN_W_AQ
    62  	AMOMIN_W_AQRL
    63  	AMOMIN_W_RL
    64  	AMOOR_D
    65  	AMOOR_D_AQ
    66  	AMOOR_D_AQRL
    67  	AMOOR_D_RL
    68  	AMOOR_W
    69  	AMOOR_W_AQ
    70  	AMOOR_W_AQRL
    71  	AMOOR_W_RL
    72  	AMOSWAP_D
    73  	AMOSWAP_D_AQ
    74  	AMOSWAP_D_AQRL
    75  	AMOSWAP_D_RL
    76  	AMOSWAP_W
    77  	AMOSWAP_W_AQ
    78  	AMOSWAP_W_AQRL
    79  	AMOSWAP_W_RL
    80  	AMOXOR_D
    81  	AMOXOR_D_AQ
    82  	AMOXOR_D_AQRL
    83  	AMOXOR_D_RL
    84  	AMOXOR_W
    85  	AMOXOR_W_AQ
    86  	AMOXOR_W_AQRL
    87  	AMOXOR_W_RL
    88  	AND
    89  	ANDI
    90  	ANDN
    91  	AUIPC
    92  	BCLR
    93  	BCLRI
    94  	BEQ
    95  	BEXT
    96  	BEXTI
    97  	BGE
    98  	BGEU
    99  	BINV
   100  	BINVI
   101  	BLT
   102  	BLTU
   103  	BNE
   104  	BSET
   105  	BSETI
   106  	CBO_CLEAN
   107  	CBO_FLUSH
   108  	CBO_INVAL
   109  	CBO_ZERO
   110  	CLMUL
   111  	CLMULH
   112  	CLMULR
   113  	CLZ
   114  	CLZW
   115  	CPOP
   116  	CPOPW
   117  	CSRRC
   118  	CSRRCI
   119  	CSRRS
   120  	CSRRSI
   121  	CSRRW
   122  	CSRRWI
   123  	CTZ
   124  	CTZW
   125  	CZERO_EQZ
   126  	CZERO_NEZ
   127  	C_ADD
   128  	C_ADDI
   129  	C_ADDI16SP
   130  	C_ADDI4SPN
   131  	C_ADDIW
   132  	C_ADDW
   133  	C_AND
   134  	C_ANDI
   135  	C_BEQZ
   136  	C_BNEZ
   137  	C_EBREAK
   138  	C_FLD
   139  	C_FLDSP
   140  	C_FSD
   141  	C_FSDSP
   142  	C_J
   143  	C_JALR
   144  	C_JR
   145  	C_LD
   146  	C_LDSP
   147  	C_LI
   148  	C_LUI
   149  	C_LW
   150  	C_LWSP
   151  	C_MV
   152  	C_NOP
   153  	C_OR
   154  	C_SD
   155  	C_SDSP
   156  	C_SLLI
   157  	C_SRAI
   158  	C_SRLI
   159  	C_SUB
   160  	C_SUBW
   161  	C_SW
   162  	C_SWSP
   163  	C_UNIMP
   164  	C_XOR
   165  	DIV
   166  	DIVU
   167  	DIVUW
   168  	DIVW
   169  	EBREAK
   170  	ECALL
   171  	FADD_D
   172  	FADD_H
   173  	FADD_Q
   174  	FADD_S
   175  	FCLASS_D
   176  	FCLASS_H
   177  	FCLASS_Q
   178  	FCLASS_S
   179  	FCVT_D_L
   180  	FCVT_D_LU
   181  	FCVT_D_Q
   182  	FCVT_D_S
   183  	FCVT_D_W
   184  	FCVT_D_WU
   185  	FCVT_H_L
   186  	FCVT_H_LU
   187  	FCVT_H_S
   188  	FCVT_H_W
   189  	FCVT_H_WU
   190  	FCVT_LU_D
   191  	FCVT_LU_H
   192  	FCVT_LU_Q
   193  	FCVT_LU_S
   194  	FCVT_L_D
   195  	FCVT_L_H
   196  	FCVT_L_Q
   197  	FCVT_L_S
   198  	FCVT_Q_D
   199  	FCVT_Q_L
   200  	FCVT_Q_LU
   201  	FCVT_Q_S
   202  	FCVT_Q_W
   203  	FCVT_Q_WU
   204  	FCVT_S_D
   205  	FCVT_S_H
   206  	FCVT_S_L
   207  	FCVT_S_LU
   208  	FCVT_S_Q
   209  	FCVT_S_W
   210  	FCVT_S_WU
   211  	FCVT_WU_D
   212  	FCVT_WU_H
   213  	FCVT_WU_Q
   214  	FCVT_WU_S
   215  	FCVT_W_D
   216  	FCVT_W_H
   217  	FCVT_W_Q
   218  	FCVT_W_S
   219  	FDIV_D
   220  	FDIV_H
   221  	FDIV_Q
   222  	FDIV_S
   223  	FENCE
   224  	FENCE_I
   225  	FEQ_D
   226  	FEQ_H
   227  	FEQ_Q
   228  	FEQ_S
   229  	FLD
   230  	FLE_D
   231  	FLE_H
   232  	FLE_Q
   233  	FLE_S
   234  	FLH
   235  	FLQ
   236  	FLT_D
   237  	FLT_H
   238  	FLT_Q
   239  	FLT_S
   240  	FLW
   241  	FMADD_D
   242  	FMADD_H
   243  	FMADD_Q
   244  	FMADD_S
   245  	FMAX_D
   246  	FMAX_H
   247  	FMAX_Q
   248  	FMAX_S
   249  	FMIN_D
   250  	FMIN_H
   251  	FMIN_Q
   252  	FMIN_S
   253  	FMSUB_D
   254  	FMSUB_H
   255  	FMSUB_Q
   256  	FMSUB_S
   257  	FMUL_D
   258  	FMUL_H
   259  	FMUL_Q
   260  	FMUL_S
   261  	FMV_D_X
   262  	FMV_H_X
   263  	FMV_W_X
   264  	FMV_X_D
   265  	FMV_X_H
   266  	FMV_X_W
   267  	FNMADD_D
   268  	FNMADD_H
   269  	FNMADD_Q
   270  	FNMADD_S
   271  	FNMSUB_D
   272  	FNMSUB_H
   273  	FNMSUB_Q
   274  	FNMSUB_S
   275  	FSD
   276  	FSGNJN_D
   277  	FSGNJN_H
   278  	FSGNJN_Q
   279  	FSGNJN_S
   280  	FSGNJX_D
   281  	FSGNJX_H
   282  	FSGNJX_Q
   283  	FSGNJX_S
   284  	FSGNJ_D
   285  	FSGNJ_H
   286  	FSGNJ_Q
   287  	FSGNJ_S
   288  	FSH
   289  	FSQ
   290  	FSQRT_D
   291  	FSQRT_H
   292  	FSQRT_Q
   293  	FSQRT_S
   294  	FSUB_D
   295  	FSUB_H
   296  	FSUB_Q
   297  	FSUB_S
   298  	FSW
   299  	JAL
   300  	JALR
   301  	LB
   302  	LBU
   303  	LD
   304  	LH
   305  	LHU
   306  	LR_D
   307  	LR_D_AQ
   308  	LR_D_AQRL
   309  	LR_D_RL
   310  	LR_W
   311  	LR_W_AQ
   312  	LR_W_AQRL
   313  	LR_W_RL
   314  	LUI
   315  	LW
   316  	LWU
   317  	MAX
   318  	MAXU
   319  	MIN
   320  	MINU
   321  	MUL
   322  	MULH
   323  	MULHSU
   324  	MULHU
   325  	MULW
   326  	OR
   327  	ORC_B
   328  	ORI
   329  	ORN
   330  	REM
   331  	REMU
   332  	REMUW
   333  	REMW
   334  	REV8
   335  	ROL
   336  	ROLW
   337  	ROR
   338  	RORI
   339  	RORIW
   340  	RORW
   341  	SB
   342  	SC_D
   343  	SC_D_AQ
   344  	SC_D_AQRL
   345  	SC_D_RL
   346  	SC_W
   347  	SC_W_AQ
   348  	SC_W_AQRL
   349  	SC_W_RL
   350  	SD
   351  	SEXT_B
   352  	SEXT_H
   353  	SH
   354  	SH1ADD
   355  	SH1ADD_UW
   356  	SH2ADD
   357  	SH2ADD_UW
   358  	SH3ADD
   359  	SH3ADD_UW
   360  	SLL
   361  	SLLI
   362  	SLLIW
   363  	SLLI_UW
   364  	SLLW
   365  	SLT
   366  	SLTI
   367  	SLTIU
   368  	SLTU
   369  	SRA
   370  	SRAI
   371  	SRAIW
   372  	SRAW
   373  	SRL
   374  	SRLI
   375  	SRLIW
   376  	SRLW
   377  	SUB
   378  	SUBW
   379  	SW
   380  	VAADDU_VV
   381  	VAADDU_VX
   382  	VAADD_VV
   383  	VAADD_VX
   384  	VAESDF_VS
   385  	VAESDF_VV
   386  	VAESDM_VS
   387  	VAESDM_VV
   388  	VAESEF_VS
   389  	VAESEF_VV
   390  	VAESEM_VS
   391  	VAESEM_VV
   392  	VAESKF1_VI
   393  	VAESKF2_VI
   394  	VAESZ_VS
   395  	VGHSH_VV
   396  	VGMUL_VV
   397  	VSHA2CH_VV
   398  	VSHA2CL_VV
   399  	VSHA2MS_VV
   400  	VSM3C_VI
   401  	VSM3ME_VV
   402  	VSM4K_VI
   403  	VSM4R_VS
   404  	VSM4R_VV
   405  	VADC_VIM
   406  	VADC_VVM
   407  	VADC_VXM
   408  	VADD_VI
   409  	VADD_VV
   410  	VADD_VX
   411  	VAND_VI
   412  	VAND_VV
   413  	VAND_VX
   414  	VASUBU_VV
   415  	VASUBU_VX
   416  	VASUB_VV
   417  	VASUB_VX
   418  	VCOMPRESS_VM
   419  	VCPOP_M
   420  	VDIVU_VV
   421  	VDIVU_VX
   422  	VDIV_VV
   423  	VDIV_VX
   424  	VFADD_VF
   425  	VFADD_VV
   426  	VFCLASS_V
   427  	VFCVT_F_XU_V
   428  	VFCVT_F_X_V
   429  	VFCVT_RTZ_XU_F_V
   430  	VFCVT_RTZ_X_F_V
   431  	VFCVT_XU_F_V
   432  	VFCVT_X_F_V
   433  	VFDIV_VF
   434  	VFDIV_VV
   435  	VFIRST_M
   436  	VFMACC_VF
   437  	VFMACC_VV
   438  	VFMADD_VF
   439  	VFMADD_VV
   440  	VFMAX_VF
   441  	VFMAX_VV
   442  	VFMERGE_VFM
   443  	VFMIN_VF
   444  	VFMIN_VV
   445  	VFMSAC_VF
   446  	VFMSAC_VV
   447  	VFMSUB_VF
   448  	VFMSUB_VV
   449  	VFMUL_VF
   450  	VFMUL_VV
   451  	VFMV_F_S
   452  	VFMV_S_F
   453  	VFMV_V_F
   454  	VFNCVT_F_F_W
   455  	VFNCVT_F_XU_W
   456  	VFNCVT_F_X_W
   457  	VFNCVT_ROD_F_F_W
   458  	VFNCVT_RTZ_XU_F_W
   459  	VFNCVT_RTZ_X_F_W
   460  	VFNCVT_XU_F_W
   461  	VFNCVT_X_F_W
   462  	VFNMACC_VF
   463  	VFNMACC_VV
   464  	VFNMADD_VF
   465  	VFNMADD_VV
   466  	VFNMSAC_VF
   467  	VFNMSAC_VV
   468  	VFNMSUB_VF
   469  	VFNMSUB_VV
   470  	VFRDIV_VF
   471  	VFREC7_V
   472  	VFREDMAX_VS
   473  	VFREDMIN_VS
   474  	VFREDOSUM_VS
   475  	VFREDUSUM_VS
   476  	VFRSQRT7_V
   477  	VFRSUB_VF
   478  	VFSGNJN_VF
   479  	VFSGNJN_VV
   480  	VFSGNJX_VF
   481  	VFSGNJX_VV
   482  	VFSGNJ_VF
   483  	VFSGNJ_VV
   484  	VFSLIDE1DOWN_VF
   485  	VFSLIDE1UP_VF
   486  	VFSQRT_V
   487  	VFSUB_VF
   488  	VFSUB_VV
   489  	VFWADD_VF
   490  	VFWADD_VV
   491  	VFWADD_WF
   492  	VFWADD_WV
   493  	VFWCVT_F_F_V
   494  	VFWCVT_F_XU_V
   495  	VFWCVT_F_X_V
   496  	VFWCVT_RTZ_XU_F_V
   497  	VFWCVT_RTZ_X_F_V
   498  	VFWCVT_XU_F_V
   499  	VFWCVT_X_F_V
   500  	VFWMACC_VF
   501  	VFWMACC_VV
   502  	VFWMSAC_VF
   503  	VFWMSAC_VV
   504  	VFWMUL_VF
   505  	VFWMUL_VV
   506  	VFWNMACC_VF
   507  	VFWNMACC_VV
   508  	VFWNMSAC_VF
   509  	VFWNMSAC_VV
   510  	VFWREDOSUM_VS
   511  	VFWREDUSUM_VS
   512  	VFWSUB_VF
   513  	VFWSUB_VV
   514  	VFWSUB_WF
   515  	VFWSUB_WV
   516  	VID_V
   517  	VIOTA_M
   518  	VL1RE16_V
   519  	VL1RE32_V
   520  	VL1RE64_V
   521  	VL1RE8_V
   522  	VL2RE16_V
   523  	VL2RE32_V
   524  	VL2RE64_V
   525  	VL2RE8_V
   526  	VL4RE16_V
   527  	VL4RE32_V
   528  	VL4RE64_V
   529  	VL4RE8_V
   530  	VL8RE16_V
   531  	VL8RE32_V
   532  	VL8RE64_V
   533  	VL8RE8_V
   534  	VLE16FF_V
   535  	VLE16_V
   536  	VLE32FF_V
   537  	VLE32_V
   538  	VLE64FF_V
   539  	VLE64_V
   540  	VLE8FF_V
   541  	VLE8_V
   542  	VLM_V
   543  	VLOXEI16_V
   544  	VLOXEI32_V
   545  	VLOXEI64_V
   546  	VLOXEI8_V
   547  	VLOXSEG2EI16_V
   548  	VLOXSEG2EI32_V
   549  	VLOXSEG2EI64_V
   550  	VLOXSEG2EI8_V
   551  	VLOXSEG3EI16_V
   552  	VLOXSEG3EI32_V
   553  	VLOXSEG3EI64_V
   554  	VLOXSEG3EI8_V
   555  	VLOXSEG4EI16_V
   556  	VLOXSEG4EI32_V
   557  	VLOXSEG4EI64_V
   558  	VLOXSEG4EI8_V
   559  	VLOXSEG5EI16_V
   560  	VLOXSEG5EI32_V
   561  	VLOXSEG5EI64_V
   562  	VLOXSEG5EI8_V
   563  	VLOXSEG6EI16_V
   564  	VLOXSEG6EI32_V
   565  	VLOXSEG6EI64_V
   566  	VLOXSEG6EI8_V
   567  	VLOXSEG7EI16_V
   568  	VLOXSEG7EI32_V
   569  	VLOXSEG7EI64_V
   570  	VLOXSEG7EI8_V
   571  	VLOXSEG8EI16_V
   572  	VLOXSEG8EI32_V
   573  	VLOXSEG8EI64_V
   574  	VLOXSEG8EI8_V
   575  	VLSE16_V
   576  	VLSE32_V
   577  	VLSE64_V
   578  	VLSE8_V
   579  	VLSEG2E16FF_V
   580  	VLSEG2E16_V
   581  	VLSEG2E32FF_V
   582  	VLSEG2E32_V
   583  	VLSEG2E64FF_V
   584  	VLSEG2E64_V
   585  	VLSEG2E8FF_V
   586  	VLSEG2E8_V
   587  	VLSEG3E16FF_V
   588  	VLSEG3E16_V
   589  	VLSEG3E32FF_V
   590  	VLSEG3E32_V
   591  	VLSEG3E64FF_V
   592  	VLSEG3E64_V
   593  	VLSEG3E8FF_V
   594  	VLSEG3E8_V
   595  	VLSEG4E16FF_V
   596  	VLSEG4E16_V
   597  	VLSEG4E32FF_V
   598  	VLSEG4E32_V
   599  	VLSEG4E64FF_V
   600  	VLSEG4E64_V
   601  	VLSEG4E8FF_V
   602  	VLSEG4E8_V
   603  	VLSEG5E16FF_V
   604  	VLSEG5E16_V
   605  	VLSEG5E32FF_V
   606  	VLSEG5E32_V
   607  	VLSEG5E64FF_V
   608  	VLSEG5E64_V
   609  	VLSEG5E8FF_V
   610  	VLSEG5E8_V
   611  	VLSEG6E16FF_V
   612  	VLSEG6E16_V
   613  	VLSEG6E32FF_V
   614  	VLSEG6E32_V
   615  	VLSEG6E64FF_V
   616  	VLSEG6E64_V
   617  	VLSEG6E8FF_V
   618  	VLSEG6E8_V
   619  	VLSEG7E16FF_V
   620  	VLSEG7E16_V
   621  	VLSEG7E32FF_V
   622  	VLSEG7E32_V
   623  	VLSEG7E64FF_V
   624  	VLSEG7E64_V
   625  	VLSEG7E8FF_V
   626  	VLSEG7E8_V
   627  	VLSEG8E16FF_V
   628  	VLSEG8E16_V
   629  	VLSEG8E32FF_V
   630  	VLSEG8E32_V
   631  	VLSEG8E64FF_V
   632  	VLSEG8E64_V
   633  	VLSEG8E8FF_V
   634  	VLSEG8E8_V
   635  	VLSSEG2E16_V
   636  	VLSSEG2E32_V
   637  	VLSSEG2E64_V
   638  	VLSSEG2E8_V
   639  	VLSSEG3E16_V
   640  	VLSSEG3E32_V
   641  	VLSSEG3E64_V
   642  	VLSSEG3E8_V
   643  	VLSSEG4E16_V
   644  	VLSSEG4E32_V
   645  	VLSSEG4E64_V
   646  	VLSSEG4E8_V
   647  	VLSSEG5E16_V
   648  	VLSSEG5E32_V
   649  	VLSSEG5E64_V
   650  	VLSSEG5E8_V
   651  	VLSSEG6E16_V
   652  	VLSSEG6E32_V
   653  	VLSSEG6E64_V
   654  	VLSSEG6E8_V
   655  	VLSSEG7E16_V
   656  	VLSSEG7E32_V
   657  	VLSSEG7E64_V
   658  	VLSSEG7E8_V
   659  	VLSSEG8E16_V
   660  	VLSSEG8E32_V
   661  	VLSSEG8E64_V
   662  	VLSSEG8E8_V
   663  	VLUXEI16_V
   664  	VLUXEI32_V
   665  	VLUXEI64_V
   666  	VLUXEI8_V
   667  	VLUXSEG2EI16_V
   668  	VLUXSEG2EI32_V
   669  	VLUXSEG2EI64_V
   670  	VLUXSEG2EI8_V
   671  	VLUXSEG3EI16_V
   672  	VLUXSEG3EI32_V
   673  	VLUXSEG3EI64_V
   674  	VLUXSEG3EI8_V
   675  	VLUXSEG4EI16_V
   676  	VLUXSEG4EI32_V
   677  	VLUXSEG4EI64_V
   678  	VLUXSEG4EI8_V
   679  	VLUXSEG5EI16_V
   680  	VLUXSEG5EI32_V
   681  	VLUXSEG5EI64_V
   682  	VLUXSEG5EI8_V
   683  	VLUXSEG6EI16_V
   684  	VLUXSEG6EI32_V
   685  	VLUXSEG6EI64_V
   686  	VLUXSEG6EI8_V
   687  	VLUXSEG7EI16_V
   688  	VLUXSEG7EI32_V
   689  	VLUXSEG7EI64_V
   690  	VLUXSEG7EI8_V
   691  	VLUXSEG8EI16_V
   692  	VLUXSEG8EI32_V
   693  	VLUXSEG8EI64_V
   694  	VLUXSEG8EI8_V
   695  	VMACC_VV
   696  	VMACC_VX
   697  	VMADC_VI
   698  	VMADC_VIM
   699  	VMADC_VV
   700  	VMADC_VVM
   701  	VMADC_VX
   702  	VMADC_VXM
   703  	VMADD_VV
   704  	VMADD_VX
   705  	VMANDN_MM
   706  	VMAND_MM
   707  	VMAXU_VV
   708  	VMAXU_VX
   709  	VMAX_VV
   710  	VMAX_VX
   711  	VMERGE_VIM
   712  	VMERGE_VVM
   713  	VMERGE_VXM
   714  	VMFEQ_VF
   715  	VMFEQ_VV
   716  	VMFGE_VF
   717  	VMFGT_VF
   718  	VMFLE_VF
   719  	VMFLE_VV
   720  	VMFLT_VF
   721  	VMFLT_VV
   722  	VMFNE_VF
   723  	VMFNE_VV
   724  	VMINU_VV
   725  	VMINU_VX
   726  	VMIN_VV
   727  	VMIN_VX
   728  	VMNAND_MM
   729  	VMNOR_MM
   730  	VMORN_MM
   731  	VMOR_MM
   732  	VMSBC_VV
   733  	VMSBC_VVM
   734  	VMSBC_VX
   735  	VMSBC_VXM
   736  	VMSBF_M
   737  	VMSEQ_VI
   738  	VMSEQ_VV
   739  	VMSEQ_VX
   740  	VMSGTU_VI
   741  	VMSGTU_VX
   742  	VMSGT_VI
   743  	VMSGT_VX
   744  	VMSIF_M
   745  	VMSLEU_VI
   746  	VMSLEU_VV
   747  	VMSLEU_VX
   748  	VMSLE_VI
   749  	VMSLE_VV
   750  	VMSLE_VX
   751  	VMSLTU_VV
   752  	VMSLTU_VX
   753  	VMSLT_VV
   754  	VMSLT_VX
   755  	VMSNE_VI
   756  	VMSNE_VV
   757  	VMSNE_VX
   758  	VMSOF_M
   759  	VMULHSU_VV
   760  	VMULHSU_VX
   761  	VMULHU_VV
   762  	VMULHU_VX
   763  	VMULH_VV
   764  	VMULH_VX
   765  	VMUL_VV
   766  	VMUL_VX
   767  	VMV1R_V
   768  	VMV2R_V
   769  	VMV4R_V
   770  	VMV8R_V
   771  	VMV_S_X
   772  	VMV_V_I
   773  	VMV_V_V
   774  	VMV_V_X
   775  	VMV_X_S
   776  	VMXNOR_MM
   777  	VMXOR_MM
   778  	VNCLIPU_WI
   779  	VNCLIPU_WV
   780  	VNCLIPU_WX
   781  	VNCLIP_WI
   782  	VNCLIP_WV
   783  	VNCLIP_WX
   784  	VNMSAC_VV
   785  	VNMSAC_VX
   786  	VNMSUB_VV
   787  	VNMSUB_VX
   788  	VNSRA_WI
   789  	VNSRA_WV
   790  	VNSRA_WX
   791  	VNSRL_WI
   792  	VNSRL_WV
   793  	VNSRL_WX
   794  	VOR_VI
   795  	VOR_VV
   796  	VOR_VX
   797  	VREDAND_VS
   798  	VREDMAXU_VS
   799  	VREDMAX_VS
   800  	VREDMINU_VS
   801  	VREDMIN_VS
   802  	VREDOR_VS
   803  	VREDSUM_VS
   804  	VREDXOR_VS
   805  	VREMU_VV
   806  	VREMU_VX
   807  	VREM_VV
   808  	VREM_VX
   809  	VRGATHEREI16_VV
   810  	VRGATHER_VI
   811  	VRGATHER_VV
   812  	VRGATHER_VX
   813  	VRSUB_VI
   814  	VRSUB_VX
   815  	VS1R_V
   816  	VS2R_V
   817  	VS4R_V
   818  	VS8R_V
   819  	VSADDU_VI
   820  	VSADDU_VV
   821  	VSADDU_VX
   822  	VSADD_VI
   823  	VSADD_VV
   824  	VSADD_VX
   825  	VSBC_VVM
   826  	VSBC_VXM
   827  	VSE16_V
   828  	VSE32_V
   829  	VSE64_V
   830  	VSE8_V
   831  	VSETIVLI
   832  	VSETVL
   833  	VSETVLI
   834  	VSEXT_VF2
   835  	VSEXT_VF4
   836  	VSEXT_VF8
   837  	VSLIDE1DOWN_VX
   838  	VSLIDE1UP_VX
   839  	VSLIDEDOWN_VI
   840  	VSLIDEDOWN_VX
   841  	VSLIDEUP_VI
   842  	VSLIDEUP_VX
   843  	VSLL_VI
   844  	VSLL_VV
   845  	VSLL_VX
   846  	VSMUL_VV
   847  	VSMUL_VX
   848  	VSM_V
   849  	VSOXEI16_V
   850  	VSOXEI32_V
   851  	VSOXEI64_V
   852  	VSOXEI8_V
   853  	VSOXSEG2EI16_V
   854  	VSOXSEG2EI32_V
   855  	VSOXSEG2EI64_V
   856  	VSOXSEG2EI8_V
   857  	VSOXSEG3EI16_V
   858  	VSOXSEG3EI32_V
   859  	VSOXSEG3EI64_V
   860  	VSOXSEG3EI8_V
   861  	VSOXSEG4EI16_V
   862  	VSOXSEG4EI32_V
   863  	VSOXSEG4EI64_V
   864  	VSOXSEG4EI8_V
   865  	VSOXSEG5EI16_V
   866  	VSOXSEG5EI32_V
   867  	VSOXSEG5EI64_V
   868  	VSOXSEG5EI8_V
   869  	VSOXSEG6EI16_V
   870  	VSOXSEG6EI32_V
   871  	VSOXSEG6EI64_V
   872  	VSOXSEG6EI8_V
   873  	VSOXSEG7EI16_V
   874  	VSOXSEG7EI32_V
   875  	VSOXSEG7EI64_V
   876  	VSOXSEG7EI8_V
   877  	VSOXSEG8EI16_V
   878  	VSOXSEG8EI32_V
   879  	VSOXSEG8EI64_V
   880  	VSOXSEG8EI8_V
   881  	VSRA_VI
   882  	VSRA_VV
   883  	VSRA_VX
   884  	VSRL_VI
   885  	VSRL_VV
   886  	VSRL_VX
   887  	VSSE16_V
   888  	VSSE32_V
   889  	VSSE64_V
   890  	VSSE8_V
   891  	VSSEG2E16_V
   892  	VSSEG2E32_V
   893  	VSSEG2E64_V
   894  	VSSEG2E8_V
   895  	VSSEG3E16_V
   896  	VSSEG3E32_V
   897  	VSSEG3E64_V
   898  	VSSEG3E8_V
   899  	VSSEG4E16_V
   900  	VSSEG4E32_V
   901  	VSSEG4E64_V
   902  	VSSEG4E8_V
   903  	VSSEG5E16_V
   904  	VSSEG5E32_V
   905  	VSSEG5E64_V
   906  	VSSEG5E8_V
   907  	VSSEG6E16_V
   908  	VSSEG6E32_V
   909  	VSSEG6E64_V
   910  	VSSEG6E8_V
   911  	VSSEG7E16_V
   912  	VSSEG7E32_V
   913  	VSSEG7E64_V
   914  	VSSEG7E8_V
   915  	VSSEG8E16_V
   916  	VSSEG8E32_V
   917  	VSSEG8E64_V
   918  	VSSEG8E8_V
   919  	VSSRA_VI
   920  	VSSRA_VV
   921  	VSSRA_VX
   922  	VSSRL_VI
   923  	VSSRL_VV
   924  	VSSRL_VX
   925  	VSSSEG2E16_V
   926  	VSSSEG2E32_V
   927  	VSSSEG2E64_V
   928  	VSSSEG2E8_V
   929  	VSSSEG3E16_V
   930  	VSSSEG3E32_V
   931  	VSSSEG3E64_V
   932  	VSSSEG3E8_V
   933  	VSSSEG4E16_V
   934  	VSSSEG4E32_V
   935  	VSSSEG4E64_V
   936  	VSSSEG4E8_V
   937  	VSSSEG5E16_V
   938  	VSSSEG5E32_V
   939  	VSSSEG5E64_V
   940  	VSSSEG5E8_V
   941  	VSSSEG6E16_V
   942  	VSSSEG6E32_V
   943  	VSSSEG6E64_V
   944  	VSSSEG6E8_V
   945  	VSSSEG7E16_V
   946  	VSSSEG7E32_V
   947  	VSSSEG7E64_V
   948  	VSSSEG7E8_V
   949  	VSSSEG8E16_V
   950  	VSSSEG8E32_V
   951  	VSSSEG8E64_V
   952  	VSSSEG8E8_V
   953  	VSSUBU_VV
   954  	VSSUBU_VX
   955  	VSSUB_VV
   956  	VSSUB_VX
   957  	VSUB_VV
   958  	VSUB_VX
   959  	VSUXEI16_V
   960  	VSUXEI32_V
   961  	VSUXEI64_V
   962  	VSUXEI8_V
   963  	VSUXSEG2EI16_V
   964  	VSUXSEG2EI32_V
   965  	VSUXSEG2EI64_V
   966  	VSUXSEG2EI8_V
   967  	VSUXSEG3EI16_V
   968  	VSUXSEG3EI32_V
   969  	VSUXSEG3EI64_V
   970  	VSUXSEG3EI8_V
   971  	VSUXSEG4EI16_V
   972  	VSUXSEG4EI32_V
   973  	VSUXSEG4EI64_V
   974  	VSUXSEG4EI8_V
   975  	VSUXSEG5EI16_V
   976  	VSUXSEG5EI32_V
   977  	VSUXSEG5EI64_V
   978  	VSUXSEG5EI8_V
   979  	VSUXSEG6EI16_V
   980  	VSUXSEG6EI32_V
   981  	VSUXSEG6EI64_V
   982  	VSUXSEG6EI8_V
   983  	VSUXSEG7EI16_V
   984  	VSUXSEG7EI32_V
   985  	VSUXSEG7EI64_V
   986  	VSUXSEG7EI8_V
   987  	VSUXSEG8EI16_V
   988  	VSUXSEG8EI32_V
   989  	VSUXSEG8EI64_V
   990  	VSUXSEG8EI8_V
   991  	VWADDU_VV
   992  	VWADDU_VX
   993  	VWADDU_WV
   994  	VWADDU_WX
   995  	VWADD_VV
   996  	VWADD_VX
   997  	VWADD_WV
   998  	VWADD_WX
   999  	VWMACCSU_VV
  1000  	VWMACCSU_VX
  1001  	VWMACCUS_VX
  1002  	VWMACCU_VV
  1003  	VWMACCU_VX
  1004  	VWMACC_VV
  1005  	VWMACC_VX
  1006  	VWMULSU_VV
  1007  	VWMULSU_VX
  1008  	VWMULU_VV
  1009  	VWMULU_VX
  1010  	VWMUL_VV
  1011  	VWMUL_VX
  1012  	VWREDSUMU_VS
  1013  	VWREDSUM_VS
  1014  	VWSUBU_VV
  1015  	VWSUBU_VX
  1016  	VWSUBU_WV
  1017  	VWSUBU_WX
  1018  	VWSUB_VV
  1019  	VWSUB_VX
  1020  	VWSUB_WV
  1021  	VWSUB_WX
  1022  	VXOR_VI
  1023  	VXOR_VV
  1024  	VXOR_VX
  1025  	VZEXT_VF2
  1026  	VZEXT_VF4
  1027  	VZEXT_VF8
  1028  	XNOR
  1029  	XOR
  1030  	XORI
  1031  	ZEXT_H
  1032  )
  1033  
  1034  var opstr = [...]string{
  1035  	ADD:               "ADD",
  1036  	ADDI:              "ADDI",
  1037  	ADDIW:             "ADDIW",
  1038  	ADDW:              "ADDW",
  1039  	ADD_UW:            "ADD.UW",
  1040  	AMOADD_D:          "AMOADD.D",
  1041  	AMOADD_D_AQ:       "AMOADD.D.AQ",
  1042  	AMOADD_D_AQRL:     "AMOADD.D.AQRL",
  1043  	AMOADD_D_RL:       "AMOADD.D.RL",
  1044  	AMOADD_W:          "AMOADD.W",
  1045  	AMOADD_W_AQ:       "AMOADD.W.AQ",
  1046  	AMOADD_W_AQRL:     "AMOADD.W.AQRL",
  1047  	AMOADD_W_RL:       "AMOADD.W.RL",
  1048  	AMOAND_D:          "AMOAND.D",
  1049  	AMOAND_D_AQ:       "AMOAND.D.AQ",
  1050  	AMOAND_D_AQRL:     "AMOAND.D.AQRL",
  1051  	AMOAND_D_RL:       "AMOAND.D.RL",
  1052  	AMOAND_W:          "AMOAND.W",
  1053  	AMOAND_W_AQ:       "AMOAND.W.AQ",
  1054  	AMOAND_W_AQRL:     "AMOAND.W.AQRL",
  1055  	AMOAND_W_RL:       "AMOAND.W.RL",
  1056  	AMOMAXU_D:         "AMOMAXU.D",
  1057  	AMOMAXU_D_AQ:      "AMOMAXU.D.AQ",
  1058  	AMOMAXU_D_AQRL:    "AMOMAXU.D.AQRL",
  1059  	AMOMAXU_D_RL:      "AMOMAXU.D.RL",
  1060  	AMOMAXU_W:         "AMOMAXU.W",
  1061  	AMOMAXU_W_AQ:      "AMOMAXU.W.AQ",
  1062  	AMOMAXU_W_AQRL:    "AMOMAXU.W.AQRL",
  1063  	AMOMAXU_W_RL:      "AMOMAXU.W.RL",
  1064  	AMOMAX_D:          "AMOMAX.D",
  1065  	AMOMAX_D_AQ:       "AMOMAX.D.AQ",
  1066  	AMOMAX_D_AQRL:     "AMOMAX.D.AQRL",
  1067  	AMOMAX_D_RL:       "AMOMAX.D.RL",
  1068  	AMOMAX_W:          "AMOMAX.W",
  1069  	AMOMAX_W_AQ:       "AMOMAX.W.AQ",
  1070  	AMOMAX_W_AQRL:     "AMOMAX.W.AQRL",
  1071  	AMOMAX_W_RL:       "AMOMAX.W.RL",
  1072  	AMOMINU_D:         "AMOMINU.D",
  1073  	AMOMINU_D_AQ:      "AMOMINU.D.AQ",
  1074  	AMOMINU_D_AQRL:    "AMOMINU.D.AQRL",
  1075  	AMOMINU_D_RL:      "AMOMINU.D.RL",
  1076  	AMOMINU_W:         "AMOMINU.W",
  1077  	AMOMINU_W_AQ:      "AMOMINU.W.AQ",
  1078  	AMOMINU_W_AQRL:    "AMOMINU.W.AQRL",
  1079  	AMOMINU_W_RL:      "AMOMINU.W.RL",
  1080  	AMOMIN_D:          "AMOMIN.D",
  1081  	AMOMIN_D_AQ:       "AMOMIN.D.AQ",
  1082  	AMOMIN_D_AQRL:     "AMOMIN.D.AQRL",
  1083  	AMOMIN_D_RL:       "AMOMIN.D.RL",
  1084  	AMOMIN_W:          "AMOMIN.W",
  1085  	AMOMIN_W_AQ:       "AMOMIN.W.AQ",
  1086  	AMOMIN_W_AQRL:     "AMOMIN.W.AQRL",
  1087  	AMOMIN_W_RL:       "AMOMIN.W.RL",
  1088  	AMOOR_D:           "AMOOR.D",
  1089  	AMOOR_D_AQ:        "AMOOR.D.AQ",
  1090  	AMOOR_D_AQRL:      "AMOOR.D.AQRL",
  1091  	AMOOR_D_RL:        "AMOOR.D.RL",
  1092  	AMOOR_W:           "AMOOR.W",
  1093  	AMOOR_W_AQ:        "AMOOR.W.AQ",
  1094  	AMOOR_W_AQRL:      "AMOOR.W.AQRL",
  1095  	AMOOR_W_RL:        "AMOOR.W.RL",
  1096  	AMOSWAP_D:         "AMOSWAP.D",
  1097  	AMOSWAP_D_AQ:      "AMOSWAP.D.AQ",
  1098  	AMOSWAP_D_AQRL:    "AMOSWAP.D.AQRL",
  1099  	AMOSWAP_D_RL:      "AMOSWAP.D.RL",
  1100  	AMOSWAP_W:         "AMOSWAP.W",
  1101  	AMOSWAP_W_AQ:      "AMOSWAP.W.AQ",
  1102  	AMOSWAP_W_AQRL:    "AMOSWAP.W.AQRL",
  1103  	AMOSWAP_W_RL:      "AMOSWAP.W.RL",
  1104  	AMOXOR_D:          "AMOXOR.D",
  1105  	AMOXOR_D_AQ:       "AMOXOR.D.AQ",
  1106  	AMOXOR_D_AQRL:     "AMOXOR.D.AQRL",
  1107  	AMOXOR_D_RL:       "AMOXOR.D.RL",
  1108  	AMOXOR_W:          "AMOXOR.W",
  1109  	AMOXOR_W_AQ:       "AMOXOR.W.AQ",
  1110  	AMOXOR_W_AQRL:     "AMOXOR.W.AQRL",
  1111  	AMOXOR_W_RL:       "AMOXOR.W.RL",
  1112  	AND:               "AND",
  1113  	ANDI:              "ANDI",
  1114  	ANDN:              "ANDN",
  1115  	AUIPC:             "AUIPC",
  1116  	BCLR:              "BCLR",
  1117  	BCLRI:             "BCLRI",
  1118  	BEQ:               "BEQ",
  1119  	BEXT:              "BEXT",
  1120  	BEXTI:             "BEXTI",
  1121  	BGE:               "BGE",
  1122  	BGEU:              "BGEU",
  1123  	BINV:              "BINV",
  1124  	BINVI:             "BINVI",
  1125  	BLT:               "BLT",
  1126  	BLTU:              "BLTU",
  1127  	BNE:               "BNE",
  1128  	BSET:              "BSET",
  1129  	BSETI:             "BSETI",
  1130  	CBO_CLEAN:         "CBO.CLEAN",
  1131  	CBO_FLUSH:         "CBO.FLUSH",
  1132  	CBO_INVAL:         "CBO.INVAL",
  1133  	CBO_ZERO:          "CBO.ZERO",
  1134  	CLMUL:             "CLMUL",
  1135  	CLMULH:            "CLMULH",
  1136  	CLMULR:            "CLMULR",
  1137  	CLZ:               "CLZ",
  1138  	CLZW:              "CLZW",
  1139  	CPOP:              "CPOP",
  1140  	CPOPW:             "CPOPW",
  1141  	CSRRC:             "CSRRC",
  1142  	CSRRCI:            "CSRRCI",
  1143  	CSRRS:             "CSRRS",
  1144  	CSRRSI:            "CSRRSI",
  1145  	CSRRW:             "CSRRW",
  1146  	CSRRWI:            "CSRRWI",
  1147  	CTZ:               "CTZ",
  1148  	CTZW:              "CTZW",
  1149  	CZERO_EQZ:         "CZERO.EQZ",
  1150  	CZERO_NEZ:         "CZERO.NEZ",
  1151  	C_ADD:             "C.ADD",
  1152  	C_ADDI:            "C.ADDI",
  1153  	C_ADDI16SP:        "C.ADDI16SP",
  1154  	C_ADDI4SPN:        "C.ADDI4SPN",
  1155  	C_ADDIW:           "C.ADDIW",
  1156  	C_ADDW:            "C.ADDW",
  1157  	C_AND:             "C.AND",
  1158  	C_ANDI:            "C.ANDI",
  1159  	C_BEQZ:            "C.BEQZ",
  1160  	C_BNEZ:            "C.BNEZ",
  1161  	C_EBREAK:          "C.EBREAK",
  1162  	C_FLD:             "C.FLD",
  1163  	C_FLDSP:           "C.FLDSP",
  1164  	C_FSD:             "C.FSD",
  1165  	C_FSDSP:           "C.FSDSP",
  1166  	C_J:               "C.J",
  1167  	C_JALR:            "C.JALR",
  1168  	C_JR:              "C.JR",
  1169  	C_LD:              "C.LD",
  1170  	C_LDSP:            "C.LDSP",
  1171  	C_LI:              "C.LI",
  1172  	C_LUI:             "C.LUI",
  1173  	C_LW:              "C.LW",
  1174  	C_LWSP:            "C.LWSP",
  1175  	C_MV:              "C.MV",
  1176  	C_NOP:             "C.NOP",
  1177  	C_OR:              "C.OR",
  1178  	C_SD:              "C.SD",
  1179  	C_SDSP:            "C.SDSP",
  1180  	C_SLLI:            "C.SLLI",
  1181  	C_SRAI:            "C.SRAI",
  1182  	C_SRLI:            "C.SRLI",
  1183  	C_SUB:             "C.SUB",
  1184  	C_SUBW:            "C.SUBW",
  1185  	C_SW:              "C.SW",
  1186  	C_SWSP:            "C.SWSP",
  1187  	C_UNIMP:           "C.UNIMP",
  1188  	C_XOR:             "C.XOR",
  1189  	DIV:               "DIV",
  1190  	DIVU:              "DIVU",
  1191  	DIVUW:             "DIVUW",
  1192  	DIVW:              "DIVW",
  1193  	EBREAK:            "EBREAK",
  1194  	ECALL:             "ECALL",
  1195  	FADD_D:            "FADD.D",
  1196  	FADD_H:            "FADD.H",
  1197  	FADD_Q:            "FADD.Q",
  1198  	FADD_S:            "FADD.S",
  1199  	FCLASS_D:          "FCLASS.D",
  1200  	FCLASS_H:          "FCLASS.H",
  1201  	FCLASS_Q:          "FCLASS.Q",
  1202  	FCLASS_S:          "FCLASS.S",
  1203  	FCVT_D_L:          "FCVT.D.L",
  1204  	FCVT_D_LU:         "FCVT.D.LU",
  1205  	FCVT_D_Q:          "FCVT.D.Q",
  1206  	FCVT_D_S:          "FCVT.D.S",
  1207  	FCVT_D_W:          "FCVT.D.W",
  1208  	FCVT_D_WU:         "FCVT.D.WU",
  1209  	FCVT_H_L:          "FCVT.H.L",
  1210  	FCVT_H_LU:         "FCVT.H.LU",
  1211  	FCVT_H_S:          "FCVT.H.S",
  1212  	FCVT_H_W:          "FCVT.H.W",
  1213  	FCVT_H_WU:         "FCVT.H.WU",
  1214  	FCVT_LU_D:         "FCVT.LU.D",
  1215  	FCVT_LU_H:         "FCVT.LU.H",
  1216  	FCVT_LU_Q:         "FCVT.LU.Q",
  1217  	FCVT_LU_S:         "FCVT.LU.S",
  1218  	FCVT_L_D:          "FCVT.L.D",
  1219  	FCVT_L_H:          "FCVT.L.H",
  1220  	FCVT_L_Q:          "FCVT.L.Q",
  1221  	FCVT_L_S:          "FCVT.L.S",
  1222  	FCVT_Q_D:          "FCVT.Q.D",
  1223  	FCVT_Q_L:          "FCVT.Q.L",
  1224  	FCVT_Q_LU:         "FCVT.Q.LU",
  1225  	FCVT_Q_S:          "FCVT.Q.S",
  1226  	FCVT_Q_W:          "FCVT.Q.W",
  1227  	FCVT_Q_WU:         "FCVT.Q.WU",
  1228  	FCVT_S_D:          "FCVT.S.D",
  1229  	FCVT_S_H:          "FCVT.S.H",
  1230  	FCVT_S_L:          "FCVT.S.L",
  1231  	FCVT_S_LU:         "FCVT.S.LU",
  1232  	FCVT_S_Q:          "FCVT.S.Q",
  1233  	FCVT_S_W:          "FCVT.S.W",
  1234  	FCVT_S_WU:         "FCVT.S.WU",
  1235  	FCVT_WU_D:         "FCVT.WU.D",
  1236  	FCVT_WU_H:         "FCVT.WU.H",
  1237  	FCVT_WU_Q:         "FCVT.WU.Q",
  1238  	FCVT_WU_S:         "FCVT.WU.S",
  1239  	FCVT_W_D:          "FCVT.W.D",
  1240  	FCVT_W_H:          "FCVT.W.H",
  1241  	FCVT_W_Q:          "FCVT.W.Q",
  1242  	FCVT_W_S:          "FCVT.W.S",
  1243  	FDIV_D:            "FDIV.D",
  1244  	FDIV_H:            "FDIV.H",
  1245  	FDIV_Q:            "FDIV.Q",
  1246  	FDIV_S:            "FDIV.S",
  1247  	FENCE:             "FENCE",
  1248  	FENCE_I:           "FENCE.I",
  1249  	FEQ_D:             "FEQ.D",
  1250  	FEQ_H:             "FEQ.H",
  1251  	FEQ_Q:             "FEQ.Q",
  1252  	FEQ_S:             "FEQ.S",
  1253  	FLD:               "FLD",
  1254  	FLE_D:             "FLE.D",
  1255  	FLE_H:             "FLE.H",
  1256  	FLE_Q:             "FLE.Q",
  1257  	FLE_S:             "FLE.S",
  1258  	FLH:               "FLH",
  1259  	FLQ:               "FLQ",
  1260  	FLT_D:             "FLT.D",
  1261  	FLT_H:             "FLT.H",
  1262  	FLT_Q:             "FLT.Q",
  1263  	FLT_S:             "FLT.S",
  1264  	FLW:               "FLW",
  1265  	FMADD_D:           "FMADD.D",
  1266  	FMADD_H:           "FMADD.H",
  1267  	FMADD_Q:           "FMADD.Q",
  1268  	FMADD_S:           "FMADD.S",
  1269  	FMAX_D:            "FMAX.D",
  1270  	FMAX_H:            "FMAX.H",
  1271  	FMAX_Q:            "FMAX.Q",
  1272  	FMAX_S:            "FMAX.S",
  1273  	FMIN_D:            "FMIN.D",
  1274  	FMIN_H:            "FMIN.H",
  1275  	FMIN_Q:            "FMIN.Q",
  1276  	FMIN_S:            "FMIN.S",
  1277  	FMSUB_D:           "FMSUB.D",
  1278  	FMSUB_H:           "FMSUB.H",
  1279  	FMSUB_Q:           "FMSUB.Q",
  1280  	FMSUB_S:           "FMSUB.S",
  1281  	FMUL_D:            "FMUL.D",
  1282  	FMUL_H:            "FMUL.H",
  1283  	FMUL_Q:            "FMUL.Q",
  1284  	FMUL_S:            "FMUL.S",
  1285  	FMV_D_X:           "FMV.D.X",
  1286  	FMV_H_X:           "FMV.H.X",
  1287  	FMV_W_X:           "FMV.W.X",
  1288  	FMV_X_D:           "FMV.X.D",
  1289  	FMV_X_H:           "FMV.X.H",
  1290  	FMV_X_W:           "FMV.X.W",
  1291  	FNMADD_D:          "FNMADD.D",
  1292  	FNMADD_H:          "FNMADD.H",
  1293  	FNMADD_Q:          "FNMADD.Q",
  1294  	FNMADD_S:          "FNMADD.S",
  1295  	FNMSUB_D:          "FNMSUB.D",
  1296  	FNMSUB_H:          "FNMSUB.H",
  1297  	FNMSUB_Q:          "FNMSUB.Q",
  1298  	FNMSUB_S:          "FNMSUB.S",
  1299  	FSD:               "FSD",
  1300  	FSGNJN_D:          "FSGNJN.D",
  1301  	FSGNJN_H:          "FSGNJN.H",
  1302  	FSGNJN_Q:          "FSGNJN.Q",
  1303  	FSGNJN_S:          "FSGNJN.S",
  1304  	FSGNJX_D:          "FSGNJX.D",
  1305  	FSGNJX_H:          "FSGNJX.H",
  1306  	FSGNJX_Q:          "FSGNJX.Q",
  1307  	FSGNJX_S:          "FSGNJX.S",
  1308  	FSGNJ_D:           "FSGNJ.D",
  1309  	FSGNJ_H:           "FSGNJ.H",
  1310  	FSGNJ_Q:           "FSGNJ.Q",
  1311  	FSGNJ_S:           "FSGNJ.S",
  1312  	FSH:               "FSH",
  1313  	FSQ:               "FSQ",
  1314  	FSQRT_D:           "FSQRT.D",
  1315  	FSQRT_H:           "FSQRT.H",
  1316  	FSQRT_Q:           "FSQRT.Q",
  1317  	FSQRT_S:           "FSQRT.S",
  1318  	FSUB_D:            "FSUB.D",
  1319  	FSUB_H:            "FSUB.H",
  1320  	FSUB_Q:            "FSUB.Q",
  1321  	FSUB_S:            "FSUB.S",
  1322  	FSW:               "FSW",
  1323  	JAL:               "JAL",
  1324  	JALR:              "JALR",
  1325  	LB:                "LB",
  1326  	LBU:               "LBU",
  1327  	LD:                "LD",
  1328  	LH:                "LH",
  1329  	LHU:               "LHU",
  1330  	LR_D:              "LR.D",
  1331  	LR_D_AQ:           "LR.D.AQ",
  1332  	LR_D_AQRL:         "LR.D.AQRL",
  1333  	LR_D_RL:           "LR.D.RL",
  1334  	LR_W:              "LR.W",
  1335  	LR_W_AQ:           "LR.W.AQ",
  1336  	LR_W_AQRL:         "LR.W.AQRL",
  1337  	LR_W_RL:           "LR.W.RL",
  1338  	LUI:               "LUI",
  1339  	LW:                "LW",
  1340  	LWU:               "LWU",
  1341  	MAX:               "MAX",
  1342  	MAXU:              "MAXU",
  1343  	MIN:               "MIN",
  1344  	MINU:              "MINU",
  1345  	MUL:               "MUL",
  1346  	MULH:              "MULH",
  1347  	MULHSU:            "MULHSU",
  1348  	MULHU:             "MULHU",
  1349  	MULW:              "MULW",
  1350  	OR:                "OR",
  1351  	ORC_B:             "ORC.B",
  1352  	ORI:               "ORI",
  1353  	ORN:               "ORN",
  1354  	REM:               "REM",
  1355  	REMU:              "REMU",
  1356  	REMUW:             "REMUW",
  1357  	REMW:              "REMW",
  1358  	REV8:              "REV8",
  1359  	ROL:               "ROL",
  1360  	ROLW:              "ROLW",
  1361  	ROR:               "ROR",
  1362  	RORI:              "RORI",
  1363  	RORIW:             "RORIW",
  1364  	RORW:              "RORW",
  1365  	SB:                "SB",
  1366  	SC_D:              "SC.D",
  1367  	SC_D_AQ:           "SC.D.AQ",
  1368  	SC_D_AQRL:         "SC.D.AQRL",
  1369  	SC_D_RL:           "SC.D.RL",
  1370  	SC_W:              "SC.W",
  1371  	SC_W_AQ:           "SC.W.AQ",
  1372  	SC_W_AQRL:         "SC.W.AQRL",
  1373  	SC_W_RL:           "SC.W.RL",
  1374  	SD:                "SD",
  1375  	SEXT_B:            "SEXT.B",
  1376  	SEXT_H:            "SEXT.H",
  1377  	SH:                "SH",
  1378  	SH1ADD:            "SH1ADD",
  1379  	SH1ADD_UW:         "SH1ADD.UW",
  1380  	SH2ADD:            "SH2ADD",
  1381  	SH2ADD_UW:         "SH2ADD.UW",
  1382  	SH3ADD:            "SH3ADD",
  1383  	SH3ADD_UW:         "SH3ADD.UW",
  1384  	SLL:               "SLL",
  1385  	SLLI:              "SLLI",
  1386  	SLLIW:             "SLLIW",
  1387  	SLLI_UW:           "SLLI.UW",
  1388  	SLLW:              "SLLW",
  1389  	SLT:               "SLT",
  1390  	SLTI:              "SLTI",
  1391  	SLTIU:             "SLTIU",
  1392  	SLTU:              "SLTU",
  1393  	SRA:               "SRA",
  1394  	SRAI:              "SRAI",
  1395  	SRAIW:             "SRAIW",
  1396  	SRAW:              "SRAW",
  1397  	SRL:               "SRL",
  1398  	SRLI:              "SRLI",
  1399  	SRLIW:             "SRLIW",
  1400  	SRLW:              "SRLW",
  1401  	SUB:               "SUB",
  1402  	SUBW:              "SUBW",
  1403  	SW:                "SW",
  1404  	VAADDU_VV:         "VAADDU.VV",
  1405  	VAADDU_VX:         "VAADDU.VX",
  1406  	VAADD_VV:          "VAADD.VV",
  1407  	VAADD_VX:          "VAADD.VX",
  1408  	VAESDF_VS:         "VAESDF.VS",
  1409  	VAESDF_VV:         "VAESDF.VV",
  1410  	VAESDM_VS:         "VAESDM.VS",
  1411  	VAESDM_VV:         "VAESDM.VV",
  1412  	VAESEF_VS:         "VAESEF.VS",
  1413  	VAESEF_VV:         "VAESEF.VV",
  1414  	VAESEM_VS:         "VAESEM.VS",
  1415  	VAESEM_VV:         "VAESEM.VV",
  1416  	VAESKF1_VI:        "VAESKF1.VI",
  1417  	VAESKF2_VI:        "VAESKF2.VI",
  1418  	VAESZ_VS:          "VAESZ.VS",
  1419  	VGHSH_VV:          "VGHSH.VV",
  1420  	VGMUL_VV:          "VGMUL.VV",
  1421  	VSHA2CH_VV:        "VSHA2CH.VV",
  1422  	VSHA2CL_VV:        "VSHA2CL.VV",
  1423  	VSHA2MS_VV:        "VSHA2MS.VV",
  1424  	VSM3C_VI:          "VSM3C.VI",
  1425  	VSM3ME_VV:         "VSM3ME.VV",
  1426  	VSM4K_VI:          "VSM4K.VI",
  1427  	VSM4R_VS:          "VSM4R.VS",
  1428  	VSM4R_VV:          "VSM4R.VV",
  1429  	VADC_VIM:          "VADC.VIM",
  1430  	VADC_VVM:          "VADC.VVM",
  1431  	VADC_VXM:          "VADC.VXM",
  1432  	VADD_VI:           "VADD.VI",
  1433  	VADD_VV:           "VADD.VV",
  1434  	VADD_VX:           "VADD.VX",
  1435  	VAND_VI:           "VAND.VI",
  1436  	VAND_VV:           "VAND.VV",
  1437  	VAND_VX:           "VAND.VX",
  1438  	VASUBU_VV:         "VASUBU.VV",
  1439  	VASUBU_VX:         "VASUBU.VX",
  1440  	VASUB_VV:          "VASUB.VV",
  1441  	VASUB_VX:          "VASUB.VX",
  1442  	VCOMPRESS_VM:      "VCOMPRESS.VM",
  1443  	VCPOP_M:           "VCPOP.M",
  1444  	VDIVU_VV:          "VDIVU.VV",
  1445  	VDIVU_VX:          "VDIVU.VX",
  1446  	VDIV_VV:           "VDIV.VV",
  1447  	VDIV_VX:           "VDIV.VX",
  1448  	VFADD_VF:          "VFADD.VF",
  1449  	VFADD_VV:          "VFADD.VV",
  1450  	VFCLASS_V:         "VFCLASS.V",
  1451  	VFCVT_F_XU_V:      "VFCVT.F.XU.V",
  1452  	VFCVT_F_X_V:       "VFCVT.F.X.V",
  1453  	VFCVT_RTZ_XU_F_V:  "VFCVT.RTZ.XU.F.V",
  1454  	VFCVT_RTZ_X_F_V:   "VFCVT.RTZ.X.F.V",
  1455  	VFCVT_XU_F_V:      "VFCVT.XU.F.V",
  1456  	VFCVT_X_F_V:       "VFCVT.X.F.V",
  1457  	VFDIV_VF:          "VFDIV.VF",
  1458  	VFDIV_VV:          "VFDIV.VV",
  1459  	VFIRST_M:          "VFIRST.M",
  1460  	VFMACC_VF:         "VFMACC.VF",
  1461  	VFMACC_VV:         "VFMACC.VV",
  1462  	VFMADD_VF:         "VFMADD.VF",
  1463  	VFMADD_VV:         "VFMADD.VV",
  1464  	VFMAX_VF:          "VFMAX.VF",
  1465  	VFMAX_VV:          "VFMAX.VV",
  1466  	VFMERGE_VFM:       "VFMERGE.VFM",
  1467  	VFMIN_VF:          "VFMIN.VF",
  1468  	VFMIN_VV:          "VFMIN.VV",
  1469  	VFMSAC_VF:         "VFMSAC.VF",
  1470  	VFMSAC_VV:         "VFMSAC.VV",
  1471  	VFMSUB_VF:         "VFMSUB.VF",
  1472  	VFMSUB_VV:         "VFMSUB.VV",
  1473  	VFMUL_VF:          "VFMUL.VF",
  1474  	VFMUL_VV:          "VFMUL.VV",
  1475  	VFMV_F_S:          "VFMV.F.S",
  1476  	VFMV_S_F:          "VFMV.S.F",
  1477  	VFMV_V_F:          "VFMV.V.F",
  1478  	VFNCVT_F_F_W:      "VFNCVT.F.F.W",
  1479  	VFNCVT_F_XU_W:     "VFNCVT.F.XU.W",
  1480  	VFNCVT_F_X_W:      "VFNCVT.F.X.W",
  1481  	VFNCVT_ROD_F_F_W:  "VFNCVT.ROD.F.F.W",
  1482  	VFNCVT_RTZ_XU_F_W: "VFNCVT.RTZ.XU.F.W",
  1483  	VFNCVT_RTZ_X_F_W:  "VFNCVT.RTZ.X.F.W",
  1484  	VFNCVT_XU_F_W:     "VFNCVT.XU.F.W",
  1485  	VFNCVT_X_F_W:      "VFNCVT.X.F.W",
  1486  	VFNMACC_VF:        "VFNMACC.VF",
  1487  	VFNMACC_VV:        "VFNMACC.VV",
  1488  	VFNMADD_VF:        "VFNMADD.VF",
  1489  	VFNMADD_VV:        "VFNMADD.VV",
  1490  	VFNMSAC_VF:        "VFNMSAC.VF",
  1491  	VFNMSAC_VV:        "VFNMSAC.VV",
  1492  	VFNMSUB_VF:        "VFNMSUB.VF",
  1493  	VFNMSUB_VV:        "VFNMSUB.VV",
  1494  	VFRDIV_VF:         "VFRDIV.VF",
  1495  	VFREC7_V:          "VFREC7.V",
  1496  	VFREDMAX_VS:       "VFREDMAX.VS",
  1497  	VFREDMIN_VS:       "VFREDMIN.VS",
  1498  	VFREDOSUM_VS:      "VFREDOSUM.VS",
  1499  	VFREDUSUM_VS:      "VFREDUSUM.VS",
  1500  	VFRSQRT7_V:        "VFRSQRT7.V",
  1501  	VFRSUB_VF:         "VFRSUB.VF",
  1502  	VFSGNJN_VF:        "VFSGNJN.VF",
  1503  	VFSGNJN_VV:        "VFSGNJN.VV",
  1504  	VFSGNJX_VF:        "VFSGNJX.VF",
  1505  	VFSGNJX_VV:        "VFSGNJX.VV",
  1506  	VFSGNJ_VF:         "VFSGNJ.VF",
  1507  	VFSGNJ_VV:         "VFSGNJ.VV",
  1508  	VFSLIDE1DOWN_VF:   "VFSLIDE1DOWN.VF",
  1509  	VFSLIDE1UP_VF:     "VFSLIDE1UP.VF",
  1510  	VFSQRT_V:          "VFSQRT.V",
  1511  	VFSUB_VF:          "VFSUB.VF",
  1512  	VFSUB_VV:          "VFSUB.VV",
  1513  	VFWADD_VF:         "VFWADD.VF",
  1514  	VFWADD_VV:         "VFWADD.VV",
  1515  	VFWADD_WF:         "VFWADD.WF",
  1516  	VFWADD_WV:         "VFWADD.WV",
  1517  	VFWCVT_F_F_V:      "VFWCVT.F.F.V",
  1518  	VFWCVT_F_XU_V:     "VFWCVT.F.XU.V",
  1519  	VFWCVT_F_X_V:      "VFWCVT.F.X.V",
  1520  	VFWCVT_RTZ_XU_F_V: "VFWCVT.RTZ.XU.F.V",
  1521  	VFWCVT_RTZ_X_F_V:  "VFWCVT.RTZ.X.F.V",
  1522  	VFWCVT_XU_F_V:     "VFWCVT.XU.F.V",
  1523  	VFWCVT_X_F_V:      "VFWCVT.X.F.V",
  1524  	VFWMACC_VF:        "VFWMACC.VF",
  1525  	VFWMACC_VV:        "VFWMACC.VV",
  1526  	VFWMSAC_VF:        "VFWMSAC.VF",
  1527  	VFWMSAC_VV:        "VFWMSAC.VV",
  1528  	VFWMUL_VF:         "VFWMUL.VF",
  1529  	VFWMUL_VV:         "VFWMUL.VV",
  1530  	VFWNMACC_VF:       "VFWNMACC.VF",
  1531  	VFWNMACC_VV:       "VFWNMACC.VV",
  1532  	VFWNMSAC_VF:       "VFWNMSAC.VF",
  1533  	VFWNMSAC_VV:       "VFWNMSAC.VV",
  1534  	VFWREDOSUM_VS:     "VFWREDOSUM.VS",
  1535  	VFWREDUSUM_VS:     "VFWREDUSUM.VS",
  1536  	VFWSUB_VF:         "VFWSUB.VF",
  1537  	VFWSUB_VV:         "VFWSUB.VV",
  1538  	VFWSUB_WF:         "VFWSUB.WF",
  1539  	VFWSUB_WV:         "VFWSUB.WV",
  1540  	VID_V:             "VID.V",
  1541  	VIOTA_M:           "VIOTA.M",
  1542  	VL1RE16_V:         "VL1RE16.V",
  1543  	VL1RE32_V:         "VL1RE32.V",
  1544  	VL1RE64_V:         "VL1RE64.V",
  1545  	VL1RE8_V:          "VL1RE8.V",
  1546  	VL2RE16_V:         "VL2RE16.V",
  1547  	VL2RE32_V:         "VL2RE32.V",
  1548  	VL2RE64_V:         "VL2RE64.V",
  1549  	VL2RE8_V:          "VL2RE8.V",
  1550  	VL4RE16_V:         "VL4RE16.V",
  1551  	VL4RE32_V:         "VL4RE32.V",
  1552  	VL4RE64_V:         "VL4RE64.V",
  1553  	VL4RE8_V:          "VL4RE8.V",
  1554  	VL8RE16_V:         "VL8RE16.V",
  1555  	VL8RE32_V:         "VL8RE32.V",
  1556  	VL8RE64_V:         "VL8RE64.V",
  1557  	VL8RE8_V:          "VL8RE8.V",
  1558  	VLE16FF_V:         "VLE16FF.V",
  1559  	VLE16_V:           "VLE16.V",
  1560  	VLE32FF_V:         "VLE32FF.V",
  1561  	VLE32_V:           "VLE32.V",
  1562  	VLE64FF_V:         "VLE64FF.V",
  1563  	VLE64_V:           "VLE64.V",
  1564  	VLE8FF_V:          "VLE8FF.V",
  1565  	VLE8_V:            "VLE8.V",
  1566  	VLM_V:             "VLM.V",
  1567  	VLOXEI16_V:        "VLOXEI16.V",
  1568  	VLOXEI32_V:        "VLOXEI32.V",
  1569  	VLOXEI64_V:        "VLOXEI64.V",
  1570  	VLOXEI8_V:         "VLOXEI8.V",
  1571  	VLOXSEG2EI16_V:    "VLOXSEG2EI16.V",
  1572  	VLOXSEG2EI32_V:    "VLOXSEG2EI32.V",
  1573  	VLOXSEG2EI64_V:    "VLOXSEG2EI64.V",
  1574  	VLOXSEG2EI8_V:     "VLOXSEG2EI8.V",
  1575  	VLOXSEG3EI16_V:    "VLOXSEG3EI16.V",
  1576  	VLOXSEG3EI32_V:    "VLOXSEG3EI32.V",
  1577  	VLOXSEG3EI64_V:    "VLOXSEG3EI64.V",
  1578  	VLOXSEG3EI8_V:     "VLOXSEG3EI8.V",
  1579  	VLOXSEG4EI16_V:    "VLOXSEG4EI16.V",
  1580  	VLOXSEG4EI32_V:    "VLOXSEG4EI32.V",
  1581  	VLOXSEG4EI64_V:    "VLOXSEG4EI64.V",
  1582  	VLOXSEG4EI8_V:     "VLOXSEG4EI8.V",
  1583  	VLOXSEG5EI16_V:    "VLOXSEG5EI16.V",
  1584  	VLOXSEG5EI32_V:    "VLOXSEG5EI32.V",
  1585  	VLOXSEG5EI64_V:    "VLOXSEG5EI64.V",
  1586  	VLOXSEG5EI8_V:     "VLOXSEG5EI8.V",
  1587  	VLOXSEG6EI16_V:    "VLOXSEG6EI16.V",
  1588  	VLOXSEG6EI32_V:    "VLOXSEG6EI32.V",
  1589  	VLOXSEG6EI64_V:    "VLOXSEG6EI64.V",
  1590  	VLOXSEG6EI8_V:     "VLOXSEG6EI8.V",
  1591  	VLOXSEG7EI16_V:    "VLOXSEG7EI16.V",
  1592  	VLOXSEG7EI32_V:    "VLOXSEG7EI32.V",
  1593  	VLOXSEG7EI64_V:    "VLOXSEG7EI64.V",
  1594  	VLOXSEG7EI8_V:     "VLOXSEG7EI8.V",
  1595  	VLOXSEG8EI16_V:    "VLOXSEG8EI16.V",
  1596  	VLOXSEG8EI32_V:    "VLOXSEG8EI32.V",
  1597  	VLOXSEG8EI64_V:    "VLOXSEG8EI64.V",
  1598  	VLOXSEG8EI8_V:     "VLOXSEG8EI8.V",
  1599  	VLSE16_V:          "VLSE16.V",
  1600  	VLSE32_V:          "VLSE32.V",
  1601  	VLSE64_V:          "VLSE64.V",
  1602  	VLSE8_V:           "VLSE8.V",
  1603  	VLSEG2E16FF_V:     "VLSEG2E16FF.V",
  1604  	VLSEG2E16_V:       "VLSEG2E16.V",
  1605  	VLSEG2E32FF_V:     "VLSEG2E32FF.V",
  1606  	VLSEG2E32_V:       "VLSEG2E32.V",
  1607  	VLSEG2E64FF_V:     "VLSEG2E64FF.V",
  1608  	VLSEG2E64_V:       "VLSEG2E64.V",
  1609  	VLSEG2E8FF_V:      "VLSEG2E8FF.V",
  1610  	VLSEG2E8_V:        "VLSEG2E8.V",
  1611  	VLSEG3E16FF_V:     "VLSEG3E16FF.V",
  1612  	VLSEG3E16_V:       "VLSEG3E16.V",
  1613  	VLSEG3E32FF_V:     "VLSEG3E32FF.V",
  1614  	VLSEG3E32_V:       "VLSEG3E32.V",
  1615  	VLSEG3E64FF_V:     "VLSEG3E64FF.V",
  1616  	VLSEG3E64_V:       "VLSEG3E64.V",
  1617  	VLSEG3E8FF_V:      "VLSEG3E8FF.V",
  1618  	VLSEG3E8_V:        "VLSEG3E8.V",
  1619  	VLSEG4E16FF_V:     "VLSEG4E16FF.V",
  1620  	VLSEG4E16_V:       "VLSEG4E16.V",
  1621  	VLSEG4E32FF_V:     "VLSEG4E32FF.V",
  1622  	VLSEG4E32_V:       "VLSEG4E32.V",
  1623  	VLSEG4E64FF_V:     "VLSEG4E64FF.V",
  1624  	VLSEG4E64_V:       "VLSEG4E64.V",
  1625  	VLSEG4E8FF_V:      "VLSEG4E8FF.V",
  1626  	VLSEG4E8_V:        "VLSEG4E8.V",
  1627  	VLSEG5E16FF_V:     "VLSEG5E16FF.V",
  1628  	VLSEG5E16_V:       "VLSEG5E16.V",
  1629  	VLSEG5E32FF_V:     "VLSEG5E32FF.V",
  1630  	VLSEG5E32_V:       "VLSEG5E32.V",
  1631  	VLSEG5E64FF_V:     "VLSEG5E64FF.V",
  1632  	VLSEG5E64_V:       "VLSEG5E64.V",
  1633  	VLSEG5E8FF_V:      "VLSEG5E8FF.V",
  1634  	VLSEG5E8_V:        "VLSEG5E8.V",
  1635  	VLSEG6E16FF_V:     "VLSEG6E16FF.V",
  1636  	VLSEG6E16_V:       "VLSEG6E16.V",
  1637  	VLSEG6E32FF_V:     "VLSEG6E32FF.V",
  1638  	VLSEG6E32_V:       "VLSEG6E32.V",
  1639  	VLSEG6E64FF_V:     "VLSEG6E64FF.V",
  1640  	VLSEG6E64_V:       "VLSEG6E64.V",
  1641  	VLSEG6E8FF_V:      "VLSEG6E8FF.V",
  1642  	VLSEG6E8_V:        "VLSEG6E8.V",
  1643  	VLSEG7E16FF_V:     "VLSEG7E16FF.V",
  1644  	VLSEG7E16_V:       "VLSEG7E16.V",
  1645  	VLSEG7E32FF_V:     "VLSEG7E32FF.V",
  1646  	VLSEG7E32_V:       "VLSEG7E32.V",
  1647  	VLSEG7E64FF_V:     "VLSEG7E64FF.V",
  1648  	VLSEG7E64_V:       "VLSEG7E64.V",
  1649  	VLSEG7E8FF_V:      "VLSEG7E8FF.V",
  1650  	VLSEG7E8_V:        "VLSEG7E8.V",
  1651  	VLSEG8E16FF_V:     "VLSEG8E16FF.V",
  1652  	VLSEG8E16_V:       "VLSEG8E16.V",
  1653  	VLSEG8E32FF_V:     "VLSEG8E32FF.V",
  1654  	VLSEG8E32_V:       "VLSEG8E32.V",
  1655  	VLSEG8E64FF_V:     "VLSEG8E64FF.V",
  1656  	VLSEG8E64_V:       "VLSEG8E64.V",
  1657  	VLSEG8E8FF_V:      "VLSEG8E8FF.V",
  1658  	VLSEG8E8_V:        "VLSEG8E8.V",
  1659  	VLSSEG2E16_V:      "VLSSEG2E16.V",
  1660  	VLSSEG2E32_V:      "VLSSEG2E32.V",
  1661  	VLSSEG2E64_V:      "VLSSEG2E64.V",
  1662  	VLSSEG2E8_V:       "VLSSEG2E8.V",
  1663  	VLSSEG3E16_V:      "VLSSEG3E16.V",
  1664  	VLSSEG3E32_V:      "VLSSEG3E32.V",
  1665  	VLSSEG3E64_V:      "VLSSEG3E64.V",
  1666  	VLSSEG3E8_V:       "VLSSEG3E8.V",
  1667  	VLSSEG4E16_V:      "VLSSEG4E16.V",
  1668  	VLSSEG4E32_V:      "VLSSEG4E32.V",
  1669  	VLSSEG4E64_V:      "VLSSEG4E64.V",
  1670  	VLSSEG4E8_V:       "VLSSEG4E8.V",
  1671  	VLSSEG5E16_V:      "VLSSEG5E16.V",
  1672  	VLSSEG5E32_V:      "VLSSEG5E32.V",
  1673  	VLSSEG5E64_V:      "VLSSEG5E64.V",
  1674  	VLSSEG5E8_V:       "VLSSEG5E8.V",
  1675  	VLSSEG6E16_V:      "VLSSEG6E16.V",
  1676  	VLSSEG6E32_V:      "VLSSEG6E32.V",
  1677  	VLSSEG6E64_V:      "VLSSEG6E64.V",
  1678  	VLSSEG6E8_V:       "VLSSEG6E8.V",
  1679  	VLSSEG7E16_V:      "VLSSEG7E16.V",
  1680  	VLSSEG7E32_V:      "VLSSEG7E32.V",
  1681  	VLSSEG7E64_V:      "VLSSEG7E64.V",
  1682  	VLSSEG7E8_V:       "VLSSEG7E8.V",
  1683  	VLSSEG8E16_V:      "VLSSEG8E16.V",
  1684  	VLSSEG8E32_V:      "VLSSEG8E32.V",
  1685  	VLSSEG8E64_V:      "VLSSEG8E64.V",
  1686  	VLSSEG8E8_V:       "VLSSEG8E8.V",
  1687  	VLUXEI16_V:        "VLUXEI16.V",
  1688  	VLUXEI32_V:        "VLUXEI32.V",
  1689  	VLUXEI64_V:        "VLUXEI64.V",
  1690  	VLUXEI8_V:         "VLUXEI8.V",
  1691  	VLUXSEG2EI16_V:    "VLUXSEG2EI16.V",
  1692  	VLUXSEG2EI32_V:    "VLUXSEG2EI32.V",
  1693  	VLUXSEG2EI64_V:    "VLUXSEG2EI64.V",
  1694  	VLUXSEG2EI8_V:     "VLUXSEG2EI8.V",
  1695  	VLUXSEG3EI16_V:    "VLUXSEG3EI16.V",
  1696  	VLUXSEG3EI32_V:    "VLUXSEG3EI32.V",
  1697  	VLUXSEG3EI64_V:    "VLUXSEG3EI64.V",
  1698  	VLUXSEG3EI8_V:     "VLUXSEG3EI8.V",
  1699  	VLUXSEG4EI16_V:    "VLUXSEG4EI16.V",
  1700  	VLUXSEG4EI32_V:    "VLUXSEG4EI32.V",
  1701  	VLUXSEG4EI64_V:    "VLUXSEG4EI64.V",
  1702  	VLUXSEG4EI8_V:     "VLUXSEG4EI8.V",
  1703  	VLUXSEG5EI16_V:    "VLUXSEG5EI16.V",
  1704  	VLUXSEG5EI32_V:    "VLUXSEG5EI32.V",
  1705  	VLUXSEG5EI64_V:    "VLUXSEG5EI64.V",
  1706  	VLUXSEG5EI8_V:     "VLUXSEG5EI8.V",
  1707  	VLUXSEG6EI16_V:    "VLUXSEG6EI16.V",
  1708  	VLUXSEG6EI32_V:    "VLUXSEG6EI32.V",
  1709  	VLUXSEG6EI64_V:    "VLUXSEG6EI64.V",
  1710  	VLUXSEG6EI8_V:     "VLUXSEG6EI8.V",
  1711  	VLUXSEG7EI16_V:    "VLUXSEG7EI16.V",
  1712  	VLUXSEG7EI32_V:    "VLUXSEG7EI32.V",
  1713  	VLUXSEG7EI64_V:    "VLUXSEG7EI64.V",
  1714  	VLUXSEG7EI8_V:     "VLUXSEG7EI8.V",
  1715  	VLUXSEG8EI16_V:    "VLUXSEG8EI16.V",
  1716  	VLUXSEG8EI32_V:    "VLUXSEG8EI32.V",
  1717  	VLUXSEG8EI64_V:    "VLUXSEG8EI64.V",
  1718  	VLUXSEG8EI8_V:     "VLUXSEG8EI8.V",
  1719  	VMACC_VV:          "VMACC.VV",
  1720  	VMACC_VX:          "VMACC.VX",
  1721  	VMADC_VI:          "VMADC.VI",
  1722  	VMADC_VIM:         "VMADC.VIM",
  1723  	VMADC_VV:          "VMADC.VV",
  1724  	VMADC_VVM:         "VMADC.VVM",
  1725  	VMADC_VX:          "VMADC.VX",
  1726  	VMADC_VXM:         "VMADC.VXM",
  1727  	VMADD_VV:          "VMADD.VV",
  1728  	VMADD_VX:          "VMADD.VX",
  1729  	VMANDN_MM:         "VMANDN.MM",
  1730  	VMAND_MM:          "VMAND.MM",
  1731  	VMAXU_VV:          "VMAXU.VV",
  1732  	VMAXU_VX:          "VMAXU.VX",
  1733  	VMAX_VV:           "VMAX.VV",
  1734  	VMAX_VX:           "VMAX.VX",
  1735  	VMERGE_VIM:        "VMERGE.VIM",
  1736  	VMERGE_VVM:        "VMERGE.VVM",
  1737  	VMERGE_VXM:        "VMERGE.VXM",
  1738  	VMFEQ_VF:          "VMFEQ.VF",
  1739  	VMFEQ_VV:          "VMFEQ.VV",
  1740  	VMFGE_VF:          "VMFGE.VF",
  1741  	VMFGT_VF:          "VMFGT.VF",
  1742  	VMFLE_VF:          "VMFLE.VF",
  1743  	VMFLE_VV:          "VMFLE.VV",
  1744  	VMFLT_VF:          "VMFLT.VF",
  1745  	VMFLT_VV:          "VMFLT.VV",
  1746  	VMFNE_VF:          "VMFNE.VF",
  1747  	VMFNE_VV:          "VMFNE.VV",
  1748  	VMINU_VV:          "VMINU.VV",
  1749  	VMINU_VX:          "VMINU.VX",
  1750  	VMIN_VV:           "VMIN.VV",
  1751  	VMIN_VX:           "VMIN.VX",
  1752  	VMNAND_MM:         "VMNAND.MM",
  1753  	VMNOR_MM:          "VMNOR.MM",
  1754  	VMORN_MM:          "VMORN.MM",
  1755  	VMOR_MM:           "VMOR.MM",
  1756  	VMSBC_VV:          "VMSBC.VV",
  1757  	VMSBC_VVM:         "VMSBC.VVM",
  1758  	VMSBC_VX:          "VMSBC.VX",
  1759  	VMSBC_VXM:         "VMSBC.VXM",
  1760  	VMSBF_M:           "VMSBF.M",
  1761  	VMSEQ_VI:          "VMSEQ.VI",
  1762  	VMSEQ_VV:          "VMSEQ.VV",
  1763  	VMSEQ_VX:          "VMSEQ.VX",
  1764  	VMSGTU_VI:         "VMSGTU.VI",
  1765  	VMSGTU_VX:         "VMSGTU.VX",
  1766  	VMSGT_VI:          "VMSGT.VI",
  1767  	VMSGT_VX:          "VMSGT.VX",
  1768  	VMSIF_M:           "VMSIF.M",
  1769  	VMSLEU_VI:         "VMSLEU.VI",
  1770  	VMSLEU_VV:         "VMSLEU.VV",
  1771  	VMSLEU_VX:         "VMSLEU.VX",
  1772  	VMSLE_VI:          "VMSLE.VI",
  1773  	VMSLE_VV:          "VMSLE.VV",
  1774  	VMSLE_VX:          "VMSLE.VX",
  1775  	VMSLTU_VV:         "VMSLTU.VV",
  1776  	VMSLTU_VX:         "VMSLTU.VX",
  1777  	VMSLT_VV:          "VMSLT.VV",
  1778  	VMSLT_VX:          "VMSLT.VX",
  1779  	VMSNE_VI:          "VMSNE.VI",
  1780  	VMSNE_VV:          "VMSNE.VV",
  1781  	VMSNE_VX:          "VMSNE.VX",
  1782  	VMSOF_M:           "VMSOF.M",
  1783  	VMULHSU_VV:        "VMULHSU.VV",
  1784  	VMULHSU_VX:        "VMULHSU.VX",
  1785  	VMULHU_VV:         "VMULHU.VV",
  1786  	VMULHU_VX:         "VMULHU.VX",
  1787  	VMULH_VV:          "VMULH.VV",
  1788  	VMULH_VX:          "VMULH.VX",
  1789  	VMUL_VV:           "VMUL.VV",
  1790  	VMUL_VX:           "VMUL.VX",
  1791  	VMV1R_V:           "VMV1R.V",
  1792  	VMV2R_V:           "VMV2R.V",
  1793  	VMV4R_V:           "VMV4R.V",
  1794  	VMV8R_V:           "VMV8R.V",
  1795  	VMV_S_X:           "VMV.S.X",
  1796  	VMV_V_I:           "VMV.V.I",
  1797  	VMV_V_V:           "VMV.V.V",
  1798  	VMV_V_X:           "VMV.V.X",
  1799  	VMV_X_S:           "VMV.X.S",
  1800  	VMXNOR_MM:         "VMXNOR.MM",
  1801  	VMXOR_MM:          "VMXOR.MM",
  1802  	VNCLIPU_WI:        "VNCLIPU.WI",
  1803  	VNCLIPU_WV:        "VNCLIPU.WV",
  1804  	VNCLIPU_WX:        "VNCLIPU.WX",
  1805  	VNCLIP_WI:         "VNCLIP.WI",
  1806  	VNCLIP_WV:         "VNCLIP.WV",
  1807  	VNCLIP_WX:         "VNCLIP.WX",
  1808  	VNMSAC_VV:         "VNMSAC.VV",
  1809  	VNMSAC_VX:         "VNMSAC.VX",
  1810  	VNMSUB_VV:         "VNMSUB.VV",
  1811  	VNMSUB_VX:         "VNMSUB.VX",
  1812  	VNSRA_WI:          "VNSRA.WI",
  1813  	VNSRA_WV:          "VNSRA.WV",
  1814  	VNSRA_WX:          "VNSRA.WX",
  1815  	VNSRL_WI:          "VNSRL.WI",
  1816  	VNSRL_WV:          "VNSRL.WV",
  1817  	VNSRL_WX:          "VNSRL.WX",
  1818  	VOR_VI:            "VOR.VI",
  1819  	VOR_VV:            "VOR.VV",
  1820  	VOR_VX:            "VOR.VX",
  1821  	VREDAND_VS:        "VREDAND.VS",
  1822  	VREDMAXU_VS:       "VREDMAXU.VS",
  1823  	VREDMAX_VS:        "VREDMAX.VS",
  1824  	VREDMINU_VS:       "VREDMINU.VS",
  1825  	VREDMIN_VS:        "VREDMIN.VS",
  1826  	VREDOR_VS:         "VREDOR.VS",
  1827  	VREDSUM_VS:        "VREDSUM.VS",
  1828  	VREDXOR_VS:        "VREDXOR.VS",
  1829  	VREMU_VV:          "VREMU.VV",
  1830  	VREMU_VX:          "VREMU.VX",
  1831  	VREM_VV:           "VREM.VV",
  1832  	VREM_VX:           "VREM.VX",
  1833  	VRGATHEREI16_VV:   "VRGATHEREI16.VV",
  1834  	VRGATHER_VI:       "VRGATHER.VI",
  1835  	VRGATHER_VV:       "VRGATHER.VV",
  1836  	VRGATHER_VX:       "VRGATHER.VX",
  1837  	VRSUB_VI:          "VRSUB.VI",
  1838  	VRSUB_VX:          "VRSUB.VX",
  1839  	VS1R_V:            "VS1R.V",
  1840  	VS2R_V:            "VS2R.V",
  1841  	VS4R_V:            "VS4R.V",
  1842  	VS8R_V:            "VS8R.V",
  1843  	VSADDU_VI:         "VSADDU.VI",
  1844  	VSADDU_VV:         "VSADDU.VV",
  1845  	VSADDU_VX:         "VSADDU.VX",
  1846  	VSADD_VI:          "VSADD.VI",
  1847  	VSADD_VV:          "VSADD.VV",
  1848  	VSADD_VX:          "VSADD.VX",
  1849  	VSBC_VVM:          "VSBC.VVM",
  1850  	VSBC_VXM:          "VSBC.VXM",
  1851  	VSE16_V:           "VSE16.V",
  1852  	VSE32_V:           "VSE32.V",
  1853  	VSE64_V:           "VSE64.V",
  1854  	VSE8_V:            "VSE8.V",
  1855  	VSETIVLI:          "VSETIVLI",
  1856  	VSETVL:            "VSETVL",
  1857  	VSETVLI:           "VSETVLI",
  1858  	VSEXT_VF2:         "VSEXT.VF2",
  1859  	VSEXT_VF4:         "VSEXT.VF4",
  1860  	VSEXT_VF8:         "VSEXT.VF8",
  1861  	VSLIDE1DOWN_VX:    "VSLIDE1DOWN.VX",
  1862  	VSLIDE1UP_VX:      "VSLIDE1UP.VX",
  1863  	VSLIDEDOWN_VI:     "VSLIDEDOWN.VI",
  1864  	VSLIDEDOWN_VX:     "VSLIDEDOWN.VX",
  1865  	VSLIDEUP_VI:       "VSLIDEUP.VI",
  1866  	VSLIDEUP_VX:       "VSLIDEUP.VX",
  1867  	VSLL_VI:           "VSLL.VI",
  1868  	VSLL_VV:           "VSLL.VV",
  1869  	VSLL_VX:           "VSLL.VX",
  1870  	VSMUL_VV:          "VSMUL.VV",
  1871  	VSMUL_VX:          "VSMUL.VX",
  1872  	VSM_V:             "VSM.V",
  1873  	VSOXEI16_V:        "VSOXEI16.V",
  1874  	VSOXEI32_V:        "VSOXEI32.V",
  1875  	VSOXEI64_V:        "VSOXEI64.V",
  1876  	VSOXEI8_V:         "VSOXEI8.V",
  1877  	VSOXSEG2EI16_V:    "VSOXSEG2EI16.V",
  1878  	VSOXSEG2EI32_V:    "VSOXSEG2EI32.V",
  1879  	VSOXSEG2EI64_V:    "VSOXSEG2EI64.V",
  1880  	VSOXSEG2EI8_V:     "VSOXSEG2EI8.V",
  1881  	VSOXSEG3EI16_V:    "VSOXSEG3EI16.V",
  1882  	VSOXSEG3EI32_V:    "VSOXSEG3EI32.V",
  1883  	VSOXSEG3EI64_V:    "VSOXSEG3EI64.V",
  1884  	VSOXSEG3EI8_V:     "VSOXSEG3EI8.V",
  1885  	VSOXSEG4EI16_V:    "VSOXSEG4EI16.V",
  1886  	VSOXSEG4EI32_V:    "VSOXSEG4EI32.V",
  1887  	VSOXSEG4EI64_V:    "VSOXSEG4EI64.V",
  1888  	VSOXSEG4EI8_V:     "VSOXSEG4EI8.V",
  1889  	VSOXSEG5EI16_V:    "VSOXSEG5EI16.V",
  1890  	VSOXSEG5EI32_V:    "VSOXSEG5EI32.V",
  1891  	VSOXSEG5EI64_V:    "VSOXSEG5EI64.V",
  1892  	VSOXSEG5EI8_V:     "VSOXSEG5EI8.V",
  1893  	VSOXSEG6EI16_V:    "VSOXSEG6EI16.V",
  1894  	VSOXSEG6EI32_V:    "VSOXSEG6EI32.V",
  1895  	VSOXSEG6EI64_V:    "VSOXSEG6EI64.V",
  1896  	VSOXSEG6EI8_V:     "VSOXSEG6EI8.V",
  1897  	VSOXSEG7EI16_V:    "VSOXSEG7EI16.V",
  1898  	VSOXSEG7EI32_V:    "VSOXSEG7EI32.V",
  1899  	VSOXSEG7EI64_V:    "VSOXSEG7EI64.V",
  1900  	VSOXSEG7EI8_V:     "VSOXSEG7EI8.V",
  1901  	VSOXSEG8EI16_V:    "VSOXSEG8EI16.V",
  1902  	VSOXSEG8EI32_V:    "VSOXSEG8EI32.V",
  1903  	VSOXSEG8EI64_V:    "VSOXSEG8EI64.V",
  1904  	VSOXSEG8EI8_V:     "VSOXSEG8EI8.V",
  1905  	VSRA_VI:           "VSRA.VI",
  1906  	VSRA_VV:           "VSRA.VV",
  1907  	VSRA_VX:           "VSRA.VX",
  1908  	VSRL_VI:           "VSRL.VI",
  1909  	VSRL_VV:           "VSRL.VV",
  1910  	VSRL_VX:           "VSRL.VX",
  1911  	VSSE16_V:          "VSSE16.V",
  1912  	VSSE32_V:          "VSSE32.V",
  1913  	VSSE64_V:          "VSSE64.V",
  1914  	VSSE8_V:           "VSSE8.V",
  1915  	VSSEG2E16_V:       "VSSEG2E16.V",
  1916  	VSSEG2E32_V:       "VSSEG2E32.V",
  1917  	VSSEG2E64_V:       "VSSEG2E64.V",
  1918  	VSSEG2E8_V:        "VSSEG2E8.V",
  1919  	VSSEG3E16_V:       "VSSEG3E16.V",
  1920  	VSSEG3E32_V:       "VSSEG3E32.V",
  1921  	VSSEG3E64_V:       "VSSEG3E64.V",
  1922  	VSSEG3E8_V:        "VSSEG3E8.V",
  1923  	VSSEG4E16_V:       "VSSEG4E16.V",
  1924  	VSSEG4E32_V:       "VSSEG4E32.V",
  1925  	VSSEG4E64_V:       "VSSEG4E64.V",
  1926  	VSSEG4E8_V:        "VSSEG4E8.V",
  1927  	VSSEG5E16_V:       "VSSEG5E16.V",
  1928  	VSSEG5E32_V:       "VSSEG5E32.V",
  1929  	VSSEG5E64_V:       "VSSEG5E64.V",
  1930  	VSSEG5E8_V:        "VSSEG5E8.V",
  1931  	VSSEG6E16_V:       "VSSEG6E16.V",
  1932  	VSSEG6E32_V:       "VSSEG6E32.V",
  1933  	VSSEG6E64_V:       "VSSEG6E64.V",
  1934  	VSSEG6E8_V:        "VSSEG6E8.V",
  1935  	VSSEG7E16_V:       "VSSEG7E16.V",
  1936  	VSSEG7E32_V:       "VSSEG7E32.V",
  1937  	VSSEG7E64_V:       "VSSEG7E64.V",
  1938  	VSSEG7E8_V:        "VSSEG7E8.V",
  1939  	VSSEG8E16_V:       "VSSEG8E16.V",
  1940  	VSSEG8E32_V:       "VSSEG8E32.V",
  1941  	VSSEG8E64_V:       "VSSEG8E64.V",
  1942  	VSSEG8E8_V:        "VSSEG8E8.V",
  1943  	VSSRA_VI:          "VSSRA.VI",
  1944  	VSSRA_VV:          "VSSRA.VV",
  1945  	VSSRA_VX:          "VSSRA.VX",
  1946  	VSSRL_VI:          "VSSRL.VI",
  1947  	VSSRL_VV:          "VSSRL.VV",
  1948  	VSSRL_VX:          "VSSRL.VX",
  1949  	VSSSEG2E16_V:      "VSSSEG2E16.V",
  1950  	VSSSEG2E32_V:      "VSSSEG2E32.V",
  1951  	VSSSEG2E64_V:      "VSSSEG2E64.V",
  1952  	VSSSEG2E8_V:       "VSSSEG2E8.V",
  1953  	VSSSEG3E16_V:      "VSSSEG3E16.V",
  1954  	VSSSEG3E32_V:      "VSSSEG3E32.V",
  1955  	VSSSEG3E64_V:      "VSSSEG3E64.V",
  1956  	VSSSEG3E8_V:       "VSSSEG3E8.V",
  1957  	VSSSEG4E16_V:      "VSSSEG4E16.V",
  1958  	VSSSEG4E32_V:      "VSSSEG4E32.V",
  1959  	VSSSEG4E64_V:      "VSSSEG4E64.V",
  1960  	VSSSEG4E8_V:       "VSSSEG4E8.V",
  1961  	VSSSEG5E16_V:      "VSSSEG5E16.V",
  1962  	VSSSEG5E32_V:      "VSSSEG5E32.V",
  1963  	VSSSEG5E64_V:      "VSSSEG5E64.V",
  1964  	VSSSEG5E8_V:       "VSSSEG5E8.V",
  1965  	VSSSEG6E16_V:      "VSSSEG6E16.V",
  1966  	VSSSEG6E32_V:      "VSSSEG6E32.V",
  1967  	VSSSEG6E64_V:      "VSSSEG6E64.V",
  1968  	VSSSEG6E8_V:       "VSSSEG6E8.V",
  1969  	VSSSEG7E16_V:      "VSSSEG7E16.V",
  1970  	VSSSEG7E32_V:      "VSSSEG7E32.V",
  1971  	VSSSEG7E64_V:      "VSSSEG7E64.V",
  1972  	VSSSEG7E8_V:       "VSSSEG7E8.V",
  1973  	VSSSEG8E16_V:      "VSSSEG8E16.V",
  1974  	VSSSEG8E32_V:      "VSSSEG8E32.V",
  1975  	VSSSEG8E64_V:      "VSSSEG8E64.V",
  1976  	VSSSEG8E8_V:       "VSSSEG8E8.V",
  1977  	VSSUBU_VV:         "VSSUBU.VV",
  1978  	VSSUBU_VX:         "VSSUBU.VX",
  1979  	VSSUB_VV:          "VSSUB.VV",
  1980  	VSSUB_VX:          "VSSUB.VX",
  1981  	VSUB_VV:           "VSUB.VV",
  1982  	VSUB_VX:           "VSUB.VX",
  1983  	VSUXEI16_V:        "VSUXEI16.V",
  1984  	VSUXEI32_V:        "VSUXEI32.V",
  1985  	VSUXEI64_V:        "VSUXEI64.V",
  1986  	VSUXEI8_V:         "VSUXEI8.V",
  1987  	VSUXSEG2EI16_V:    "VSUXSEG2EI16.V",
  1988  	VSUXSEG2EI32_V:    "VSUXSEG2EI32.V",
  1989  	VSUXSEG2EI64_V:    "VSUXSEG2EI64.V",
  1990  	VSUXSEG2EI8_V:     "VSUXSEG2EI8.V",
  1991  	VSUXSEG3EI16_V:    "VSUXSEG3EI16.V",
  1992  	VSUXSEG3EI32_V:    "VSUXSEG3EI32.V",
  1993  	VSUXSEG3EI64_V:    "VSUXSEG3EI64.V",
  1994  	VSUXSEG3EI8_V:     "VSUXSEG3EI8.V",
  1995  	VSUXSEG4EI16_V:    "VSUXSEG4EI16.V",
  1996  	VSUXSEG4EI32_V:    "VSUXSEG4EI32.V",
  1997  	VSUXSEG4EI64_V:    "VSUXSEG4EI64.V",
  1998  	VSUXSEG4EI8_V:     "VSUXSEG4EI8.V",
  1999  	VSUXSEG5EI16_V:    "VSUXSEG5EI16.V",
  2000  	VSUXSEG5EI32_V:    "VSUXSEG5EI32.V",
  2001  	VSUXSEG5EI64_V:    "VSUXSEG5EI64.V",
  2002  	VSUXSEG5EI8_V:     "VSUXSEG5EI8.V",
  2003  	VSUXSEG6EI16_V:    "VSUXSEG6EI16.V",
  2004  	VSUXSEG6EI32_V:    "VSUXSEG6EI32.V",
  2005  	VSUXSEG6EI64_V:    "VSUXSEG6EI64.V",
  2006  	VSUXSEG6EI8_V:     "VSUXSEG6EI8.V",
  2007  	VSUXSEG7EI16_V:    "VSUXSEG7EI16.V",
  2008  	VSUXSEG7EI32_V:    "VSUXSEG7EI32.V",
  2009  	VSUXSEG7EI64_V:    "VSUXSEG7EI64.V",
  2010  	VSUXSEG7EI8_V:     "VSUXSEG7EI8.V",
  2011  	VSUXSEG8EI16_V:    "VSUXSEG8EI16.V",
  2012  	VSUXSEG8EI32_V:    "VSUXSEG8EI32.V",
  2013  	VSUXSEG8EI64_V:    "VSUXSEG8EI64.V",
  2014  	VSUXSEG8EI8_V:     "VSUXSEG8EI8.V",
  2015  	VWADDU_VV:         "VWADDU.VV",
  2016  	VWADDU_VX:         "VWADDU.VX",
  2017  	VWADDU_WV:         "VWADDU.WV",
  2018  	VWADDU_WX:         "VWADDU.WX",
  2019  	VWADD_VV:          "VWADD.VV",
  2020  	VWADD_VX:          "VWADD.VX",
  2021  	VWADD_WV:          "VWADD.WV",
  2022  	VWADD_WX:          "VWADD.WX",
  2023  	VWMACCSU_VV:       "VWMACCSU.VV",
  2024  	VWMACCSU_VX:       "VWMACCSU.VX",
  2025  	VWMACCUS_VX:       "VWMACCUS.VX",
  2026  	VWMACCU_VV:        "VWMACCU.VV",
  2027  	VWMACCU_VX:        "VWMACCU.VX",
  2028  	VWMACC_VV:         "VWMACC.VV",
  2029  	VWMACC_VX:         "VWMACC.VX",
  2030  	VWMULSU_VV:        "VWMULSU.VV",
  2031  	VWMULSU_VX:        "VWMULSU.VX",
  2032  	VWMULU_VV:         "VWMULU.VV",
  2033  	VWMULU_VX:         "VWMULU.VX",
  2034  	VWMUL_VV:          "VWMUL.VV",
  2035  	VWMUL_VX:          "VWMUL.VX",
  2036  	VWREDSUMU_VS:      "VWREDSUMU.VS",
  2037  	VWREDSUM_VS:       "VWREDSUM.VS",
  2038  	VWSUBU_VV:         "VWSUBU.VV",
  2039  	VWSUBU_VX:         "VWSUBU.VX",
  2040  	VWSUBU_WV:         "VWSUBU.WV",
  2041  	VWSUBU_WX:         "VWSUBU.WX",
  2042  	VWSUB_VV:          "VWSUB.VV",
  2043  	VWSUB_VX:          "VWSUB.VX",
  2044  	VWSUB_WV:          "VWSUB.WV",
  2045  	VWSUB_WX:          "VWSUB.WX",
  2046  	VXOR_VI:           "VXOR.VI",
  2047  	VXOR_VV:           "VXOR.VV",
  2048  	VXOR_VX:           "VXOR.VX",
  2049  	VZEXT_VF2:         "VZEXT.VF2",
  2050  	VZEXT_VF4:         "VZEXT.VF4",
  2051  	VZEXT_VF8:         "VZEXT.VF8",
  2052  	XNOR:              "XNOR",
  2053  	XOR:               "XOR",
  2054  	XORI:              "XORI",
  2055  	ZEXT_H:            "ZEXT.H",
  2056  }
  2057  
  2058  var instFormats = [...]instFormat{
  2059  	// ADD rd, rs1, rs2
  2060  	{mask: 0xfe00707f, value: 0x00000033, op: ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2061  	// ADDI rd, rs1, imm12
  2062  	{mask: 0x0000707f, value: 0x00000013, op: ADDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2063  	// ADDIW rd, rs1, imm12
  2064  	{mask: 0x0000707f, value: 0x0000001b, op: ADDIW, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2065  	// ADDW rd, rs1, rs2
  2066  	{mask: 0xfe00707f, value: 0x0000003b, op: ADDW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2067  	// ADD.UW rd, rs1, rs2
  2068  	{mask: 0xfe00707f, value: 0x0800003b, op: ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2069  	// AMOADD.D rd, rs2, rs1_ptr
  2070  	{mask: 0xfe00707f, value: 0x0000302f, op: AMOADD_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2071  	// AMOADD.D.AQ rd, rs2, rs1_ptr
  2072  	{mask: 0xfe00707f, value: 0x0400302f, op: AMOADD_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2073  	// AMOADD.D.AQRL rd, rs2, rs1_ptr
  2074  	{mask: 0xfe00707f, value: 0x0600302f, op: AMOADD_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2075  	// AMOADD.D.RL rd, rs2, rs1_ptr
  2076  	{mask: 0xfe00707f, value: 0x0200302f, op: AMOADD_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2077  	// AMOADD.W rd, rs2, rs1_ptr
  2078  	{mask: 0xfe00707f, value: 0x0000202f, op: AMOADD_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2079  	// AMOADD.W.AQ rd, rs2, rs1_ptr
  2080  	{mask: 0xfe00707f, value: 0x0400202f, op: AMOADD_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2081  	// AMOADD.W.AQRL rd, rs2, rs1_ptr
  2082  	{mask: 0xfe00707f, value: 0x0600202f, op: AMOADD_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2083  	// AMOADD.W.RL rd, rs2, rs1_ptr
  2084  	{mask: 0xfe00707f, value: 0x0200202f, op: AMOADD_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2085  	// AMOAND.D rd, rs2, rs1_ptr
  2086  	{mask: 0xfe00707f, value: 0x6000302f, op: AMOAND_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2087  	// AMOAND.D.AQ rd, rs2, rs1_ptr
  2088  	{mask: 0xfe00707f, value: 0x6400302f, op: AMOAND_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2089  	// AMOAND.D.AQRL rd, rs2, rs1_ptr
  2090  	{mask: 0xfe00707f, value: 0x6600302f, op: AMOAND_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2091  	// AMOAND.D.RL rd, rs2, rs1_ptr
  2092  	{mask: 0xfe00707f, value: 0x6200302f, op: AMOAND_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2093  	// AMOAND.W rd, rs2, rs1_ptr
  2094  	{mask: 0xfe00707f, value: 0x6000202f, op: AMOAND_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2095  	// AMOAND.W.AQ rd, rs2, rs1_ptr
  2096  	{mask: 0xfe00707f, value: 0x6400202f, op: AMOAND_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2097  	// AMOAND.W.AQRL rd, rs2, rs1_ptr
  2098  	{mask: 0xfe00707f, value: 0x6600202f, op: AMOAND_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2099  	// AMOAND.W.RL rd, rs2, rs1_ptr
  2100  	{mask: 0xfe00707f, value: 0x6200202f, op: AMOAND_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2101  	// AMOMAXU.D rd, rs2, rs1_ptr
  2102  	{mask: 0xfe00707f, value: 0xe000302f, op: AMOMAXU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2103  	// AMOMAXU.D.AQ rd, rs2, rs1_ptr
  2104  	{mask: 0xfe00707f, value: 0xe400302f, op: AMOMAXU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2105  	// AMOMAXU.D.AQRL rd, rs2, rs1_ptr
  2106  	{mask: 0xfe00707f, value: 0xe600302f, op: AMOMAXU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2107  	// AMOMAXU.D.RL rd, rs2, rs1_ptr
  2108  	{mask: 0xfe00707f, value: 0xe200302f, op: AMOMAXU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2109  	// AMOMAXU.W rd, rs2, rs1_ptr
  2110  	{mask: 0xfe00707f, value: 0xe000202f, op: AMOMAXU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2111  	// AMOMAXU.W.AQ rd, rs2, rs1_ptr
  2112  	{mask: 0xfe00707f, value: 0xe400202f, op: AMOMAXU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2113  	// AMOMAXU.W.AQRL rd, rs2, rs1_ptr
  2114  	{mask: 0xfe00707f, value: 0xe600202f, op: AMOMAXU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2115  	// AMOMAXU.W.RL rd, rs2, rs1_ptr
  2116  	{mask: 0xfe00707f, value: 0xe200202f, op: AMOMAXU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2117  	// AMOMAX.D rd, rs2, rs1_ptr
  2118  	{mask: 0xfe00707f, value: 0xa000302f, op: AMOMAX_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2119  	// AMOMAX.D.AQ rd, rs2, rs1_ptr
  2120  	{mask: 0xfe00707f, value: 0xa400302f, op: AMOMAX_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2121  	// AMOMAX.D.AQRL rd, rs2, rs1_ptr
  2122  	{mask: 0xfe00707f, value: 0xa600302f, op: AMOMAX_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2123  	// AMOMAX.D.RL rd, rs2, rs1_ptr
  2124  	{mask: 0xfe00707f, value: 0xa200302f, op: AMOMAX_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2125  	// AMOMAX.W rd, rs2, rs1_ptr
  2126  	{mask: 0xfe00707f, value: 0xa000202f, op: AMOMAX_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2127  	// AMOMAX.W.AQ rd, rs2, rs1_ptr
  2128  	{mask: 0xfe00707f, value: 0xa400202f, op: AMOMAX_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2129  	// AMOMAX.W.AQRL rd, rs2, rs1_ptr
  2130  	{mask: 0xfe00707f, value: 0xa600202f, op: AMOMAX_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2131  	// AMOMAX.W.RL rd, rs2, rs1_ptr
  2132  	{mask: 0xfe00707f, value: 0xa200202f, op: AMOMAX_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2133  	// AMOMINU.D rd, rs2, rs1_ptr
  2134  	{mask: 0xfe00707f, value: 0xc000302f, op: AMOMINU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2135  	// AMOMINU.D.AQ rd, rs2, rs1_ptr
  2136  	{mask: 0xfe00707f, value: 0xc400302f, op: AMOMINU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2137  	// AMOMINU.D.AQRL rd, rs2, rs1_ptr
  2138  	{mask: 0xfe00707f, value: 0xc600302f, op: AMOMINU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2139  	// AMOMINU.D.RL rd, rs2, rs1_ptr
  2140  	{mask: 0xfe00707f, value: 0xc200302f, op: AMOMINU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2141  	// AMOMINU.W rd, rs2, rs1_ptr
  2142  	{mask: 0xfe00707f, value: 0xc000202f, op: AMOMINU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2143  	// AMOMINU.W.AQ rd, rs2, rs1_ptr
  2144  	{mask: 0xfe00707f, value: 0xc400202f, op: AMOMINU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2145  	// AMOMINU.W.AQRL rd, rs2, rs1_ptr
  2146  	{mask: 0xfe00707f, value: 0xc600202f, op: AMOMINU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2147  	// AMOMINU.W.RL rd, rs2, rs1_ptr
  2148  	{mask: 0xfe00707f, value: 0xc200202f, op: AMOMINU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2149  	// AMOMIN.D rd, rs2, rs1_ptr
  2150  	{mask: 0xfe00707f, value: 0x8000302f, op: AMOMIN_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2151  	// AMOMIN.D.AQ rd, rs2, rs1_ptr
  2152  	{mask: 0xfe00707f, value: 0x8400302f, op: AMOMIN_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2153  	// AMOMIN.D.AQRL rd, rs2, rs1_ptr
  2154  	{mask: 0xfe00707f, value: 0x8600302f, op: AMOMIN_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2155  	// AMOMIN.D.RL rd, rs2, rs1_ptr
  2156  	{mask: 0xfe00707f, value: 0x8200302f, op: AMOMIN_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2157  	// AMOMIN.W rd, rs2, rs1_ptr
  2158  	{mask: 0xfe00707f, value: 0x8000202f, op: AMOMIN_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2159  	// AMOMIN.W.AQ rd, rs2, rs1_ptr
  2160  	{mask: 0xfe00707f, value: 0x8400202f, op: AMOMIN_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2161  	// AMOMIN.W.AQRL rd, rs2, rs1_ptr
  2162  	{mask: 0xfe00707f, value: 0x8600202f, op: AMOMIN_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2163  	// AMOMIN.W.RL rd, rs2, rs1_ptr
  2164  	{mask: 0xfe00707f, value: 0x8200202f, op: AMOMIN_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2165  	// AMOOR.D rd, rs2, rs1_ptr
  2166  	{mask: 0xfe00707f, value: 0x4000302f, op: AMOOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2167  	// AMOOR.D.AQ rd, rs2, rs1_ptr
  2168  	{mask: 0xfe00707f, value: 0x4400302f, op: AMOOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2169  	// AMOOR.D.AQRL rd, rs2, rs1_ptr
  2170  	{mask: 0xfe00707f, value: 0x4600302f, op: AMOOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2171  	// AMOOR.D.RL rd, rs2, rs1_ptr
  2172  	{mask: 0xfe00707f, value: 0x4200302f, op: AMOOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2173  	// AMOOR.W rd, rs2, rs1_ptr
  2174  	{mask: 0xfe00707f, value: 0x4000202f, op: AMOOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2175  	// AMOOR.W.AQ rd, rs2, rs1_ptr
  2176  	{mask: 0xfe00707f, value: 0x4400202f, op: AMOOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2177  	// AMOOR.W.AQRL rd, rs2, rs1_ptr
  2178  	{mask: 0xfe00707f, value: 0x4600202f, op: AMOOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2179  	// AMOOR.W.RL rd, rs2, rs1_ptr
  2180  	{mask: 0xfe00707f, value: 0x4200202f, op: AMOOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2181  	// AMOSWAP.D rd, rs2, rs1_ptr
  2182  	{mask: 0xfe00707f, value: 0x0800302f, op: AMOSWAP_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2183  	// AMOSWAP.D.AQ rd, rs2, rs1_ptr
  2184  	{mask: 0xfe00707f, value: 0x0c00302f, op: AMOSWAP_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2185  	// AMOSWAP.D.AQRL rd, rs2, rs1_ptr
  2186  	{mask: 0xfe00707f, value: 0x0e00302f, op: AMOSWAP_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2187  	// AMOSWAP.D.RL rd, rs2, rs1_ptr
  2188  	{mask: 0xfe00707f, value: 0x0a00302f, op: AMOSWAP_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2189  	// AMOSWAP.W rd, rs2, rs1_ptr
  2190  	{mask: 0xfe00707f, value: 0x0800202f, op: AMOSWAP_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2191  	// AMOSWAP.W.AQ rd, rs2, rs1_ptr
  2192  	{mask: 0xfe00707f, value: 0x0c00202f, op: AMOSWAP_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2193  	// AMOSWAP.W.AQRL rd, rs2, rs1_ptr
  2194  	{mask: 0xfe00707f, value: 0x0e00202f, op: AMOSWAP_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2195  	// AMOSWAP.W.RL rd, rs2, rs1_ptr
  2196  	{mask: 0xfe00707f, value: 0x0a00202f, op: AMOSWAP_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2197  	// AMOXOR.D rd, rs2, rs1_ptr
  2198  	{mask: 0xfe00707f, value: 0x2000302f, op: AMOXOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2199  	// AMOXOR.D.AQ rd, rs2, rs1_ptr
  2200  	{mask: 0xfe00707f, value: 0x2400302f, op: AMOXOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2201  	// AMOXOR.D.AQRL rd, rs2, rs1_ptr
  2202  	{mask: 0xfe00707f, value: 0x2600302f, op: AMOXOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2203  	// AMOXOR.D.RL rd, rs2, rs1_ptr
  2204  	{mask: 0xfe00707f, value: 0x2200302f, op: AMOXOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2205  	// AMOXOR.W rd, rs2, rs1_ptr
  2206  	{mask: 0xfe00707f, value: 0x2000202f, op: AMOXOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2207  	// AMOXOR.W.AQ rd, rs2, rs1_ptr
  2208  	{mask: 0xfe00707f, value: 0x2400202f, op: AMOXOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2209  	// AMOXOR.W.AQRL rd, rs2, rs1_ptr
  2210  	{mask: 0xfe00707f, value: 0x2600202f, op: AMOXOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2211  	// AMOXOR.W.RL rd, rs2, rs1_ptr
  2212  	{mask: 0xfe00707f, value: 0x2200202f, op: AMOXOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2213  	// AND rd, rs1, rs2
  2214  	{mask: 0xfe00707f, value: 0x00007033, op: AND, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2215  	// ANDI rd, rs1, imm12
  2216  	{mask: 0x0000707f, value: 0x00007013, op: ANDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2217  	// ANDN rd, rs1, rs2
  2218  	{mask: 0xfe00707f, value: 0x40007033, op: ANDN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2219  	// AUIPC rd, imm20
  2220  	{mask: 0x0000007f, value: 0x00000017, op: AUIPC, args: argTypeList{arg_rd, arg_imm20}},
  2221  	// BCLR rd, rs1, rs2
  2222  	{mask: 0xfe00707f, value: 0x48001033, op: BCLR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2223  	// BCLRI rd, rs1, shamt6
  2224  	{mask: 0xfc00707f, value: 0x48001013, op: BCLRI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2225  	// BEQ rs1, rs2, bimm12
  2226  	{mask: 0x0000707f, value: 0x00000063, op: BEQ, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2227  	// BEXT rd, rs1, rs2
  2228  	{mask: 0xfe00707f, value: 0x48005033, op: BEXT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2229  	// BEXTI rd, rs1, shamt6
  2230  	{mask: 0xfc00707f, value: 0x48005013, op: BEXTI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2231  	// BGE rs1, rs2, bimm12
  2232  	{mask: 0x0000707f, value: 0x00005063, op: BGE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2233  	// BGEU rs1, rs2, bimm12
  2234  	{mask: 0x0000707f, value: 0x00007063, op: BGEU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2235  	// BINV rd, rs1, rs2
  2236  	{mask: 0xfe00707f, value: 0x68001033, op: BINV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2237  	// BINVI rd, rs1, shamt6
  2238  	{mask: 0xfc00707f, value: 0x68001013, op: BINVI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2239  	// BLT rs1, rs2, bimm12
  2240  	{mask: 0x0000707f, value: 0x00004063, op: BLT, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2241  	// BLTU rs1, rs2, bimm12
  2242  	{mask: 0x0000707f, value: 0x00006063, op: BLTU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2243  	// BNE rs1, rs2, bimm12
  2244  	{mask: 0x0000707f, value: 0x00001063, op: BNE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2245  	// BSET rd, rs1, rs2
  2246  	{mask: 0xfe00707f, value: 0x28001033, op: BSET, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2247  	// BSETI rd, rs1, shamt6
  2248  	{mask: 0xfc00707f, value: 0x28001013, op: BSETI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2249  	// CBO.CLEAN rs1_ptr
  2250  	{mask: 0xfff07fff, value: 0x0010200f, op: CBO_CLEAN, args: argTypeList{arg_rs1_ptr}},
  2251  	// CBO.FLUSH rs1_ptr
  2252  	{mask: 0xfff07fff, value: 0x0020200f, op: CBO_FLUSH, args: argTypeList{arg_rs1_ptr}},
  2253  	// CBO.INVAL rs1_ptr
  2254  	{mask: 0xfff07fff, value: 0x0000200f, op: CBO_INVAL, args: argTypeList{arg_rs1_ptr}},
  2255  	// CBO.ZERO rs1_ptr
  2256  	{mask: 0xfff07fff, value: 0x0040200f, op: CBO_ZERO, args: argTypeList{arg_rs1_ptr}},
  2257  	// CLMUL rd, rs1, rs2
  2258  	{mask: 0xfe00707f, value: 0x0a001033, op: CLMUL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2259  	// CLMULH rd, rs1, rs2
  2260  	{mask: 0xfe00707f, value: 0x0a003033, op: CLMULH, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2261  	// CLMULR rd, rs1, rs2
  2262  	{mask: 0xfe00707f, value: 0x0a002033, op: CLMULR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2263  	// CLZ rd, rs1
  2264  	{mask: 0xfff0707f, value: 0x60001013, op: CLZ, args: argTypeList{arg_rd, arg_rs1}},
  2265  	// CLZW rd, rs1
  2266  	{mask: 0xfff0707f, value: 0x6000101b, op: CLZW, args: argTypeList{arg_rd, arg_rs1}},
  2267  	// CPOP rd, rs1
  2268  	{mask: 0xfff0707f, value: 0x60201013, op: CPOP, args: argTypeList{arg_rd, arg_rs1}},
  2269  	// CPOPW rd, rs1
  2270  	{mask: 0xfff0707f, value: 0x6020101b, op: CPOPW, args: argTypeList{arg_rd, arg_rs1}},
  2271  	// CSRRC rd, csr, rs1
  2272  	{mask: 0x0000707f, value: 0x00003073, op: CSRRC, args: argTypeList{arg_rd, arg_csr, arg_rs1}},
  2273  	// CSRRCI rd, csr, zimm
  2274  	{mask: 0x0000707f, value: 0x00007073, op: CSRRCI, args: argTypeList{arg_rd, arg_csr, arg_zimm}},
  2275  	// CSRRS rd, csr, rs1
  2276  	{mask: 0x0000707f, value: 0x00002073, op: CSRRS, args: argTypeList{arg_rd, arg_csr, arg_rs1}},
  2277  	// CSRRSI rd, csr, zimm
  2278  	{mask: 0x0000707f, value: 0x00006073, op: CSRRSI, args: argTypeList{arg_rd, arg_csr, arg_zimm}},
  2279  	// CSRRW rd, csr, rs1
  2280  	{mask: 0x0000707f, value: 0x00001073, op: CSRRW, args: argTypeList{arg_rd, arg_csr, arg_rs1}},
  2281  	// CSRRWI rd, csr, zimm
  2282  	{mask: 0x0000707f, value: 0x00005073, op: CSRRWI, args: argTypeList{arg_rd, arg_csr, arg_zimm}},
  2283  	// CTZ rd, rs1
  2284  	{mask: 0xfff0707f, value: 0x60101013, op: CTZ, args: argTypeList{arg_rd, arg_rs1}},
  2285  	// CTZW rd, rs1
  2286  	{mask: 0xfff0707f, value: 0x6010101b, op: CTZW, args: argTypeList{arg_rd, arg_rs1}},
  2287  	// CZERO.EQZ rd, rs1, rs2
  2288  	{mask: 0xfe00707f, value: 0x0e005033, op: CZERO_EQZ, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2289  	// CZERO.NEZ rd, rs1, rs2
  2290  	{mask: 0xfe00707f, value: 0x0e007033, op: CZERO_NEZ, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2291  	// C.ADD rd_rs1_n0, c_rs2_n0
  2292  	{mask: 0x0000f003, value: 0x00009002, op: C_ADD, args: argTypeList{arg_rd_rs1_n0, arg_c_rs2_n0}},
  2293  	// C.ADDI rd_rs1_n0, c_nzimm6
  2294  	{mask: 0x0000e003, value: 0x00000001, op: C_ADDI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzimm6}},
  2295  	// C.ADDI16SP c_nzimm10
  2296  	{mask: 0x0000ef83, value: 0x00006101, op: C_ADDI16SP, args: argTypeList{arg_c_nzimm10}},
  2297  	// C.ADDI4SPN rd_p, c_nzuimm10
  2298  	{mask: 0x0000e003, value: 0x00000000, op: C_ADDI4SPN, args: argTypeList{arg_rd_p, arg_c_nzuimm10}},
  2299  	// C.ADDIW rd_rs1_n0, c_imm6
  2300  	{mask: 0x0000e003, value: 0x00002001, op: C_ADDIW, args: argTypeList{arg_rd_rs1_n0, arg_c_imm6}},
  2301  	// C.ADDW rd_rs1_p, rs2_p
  2302  	{mask: 0x0000fc63, value: 0x00009c21, op: C_ADDW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2303  	// C.AND rd_rs1_p, rs2_p
  2304  	{mask: 0x0000fc63, value: 0x00008c61, op: C_AND, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2305  	// C.ANDI rd_rs1_p, c_imm6
  2306  	{mask: 0x0000ec03, value: 0x00008801, op: C_ANDI, args: argTypeList{arg_rd_rs1_p, arg_c_imm6}},
  2307  	// C.BEQZ rs1_p, c_bimm9
  2308  	{mask: 0x0000e003, value: 0x0000c001, op: C_BEQZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}},
  2309  	// C.BNEZ rs1_p, c_bimm9
  2310  	{mask: 0x0000e003, value: 0x0000e001, op: C_BNEZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}},
  2311  	// C.EBREAK
  2312  	{mask: 0x0000ffff, value: 0x00009002, op: C_EBREAK, args: argTypeList{}},
  2313  	// C.FLD fd_p, rs1_p, c_uimm8
  2314  	{mask: 0x0000e003, value: 0x00002000, op: C_FLD, args: argTypeList{arg_fd_p, arg_rs1_p, arg_c_uimm8}},
  2315  	// C.FLDSP fd, c_uimm9sp
  2316  	{mask: 0x0000e003, value: 0x00002002, op: C_FLDSP, args: argTypeList{arg_fd, arg_c_uimm9sp}},
  2317  	// C.FSD rs1_p, fs2_p, c_uimm8
  2318  	{mask: 0x0000e003, value: 0x0000a000, op: C_FSD, args: argTypeList{arg_rs1_p, arg_fs2_p, arg_c_uimm8}},
  2319  	// C.FSDSP c_fs2, c_uimm9sp_s
  2320  	{mask: 0x0000e003, value: 0x0000a002, op: C_FSDSP, args: argTypeList{arg_c_fs2, arg_c_uimm9sp_s}},
  2321  	// C.J c_imm12
  2322  	{mask: 0x0000e003, value: 0x0000a001, op: C_J, args: argTypeList{arg_c_imm12}},
  2323  	// C.JALR c_rs1_n0
  2324  	{mask: 0x0000f07f, value: 0x00009002, op: C_JALR, args: argTypeList{arg_c_rs1_n0}},
  2325  	// C.JR rs1_n0
  2326  	{mask: 0x0000f07f, value: 0x00008002, op: C_JR, args: argTypeList{arg_rs1_n0}},
  2327  	// C.LD rd_p, rs1_p, c_uimm8
  2328  	{mask: 0x0000e003, value: 0x00006000, op: C_LD, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm8}},
  2329  	// C.LDSP rd_n0, c_uimm9sp
  2330  	{mask: 0x0000e003, value: 0x00006002, op: C_LDSP, args: argTypeList{arg_rd_n0, arg_c_uimm9sp}},
  2331  	// C.LI rd_n0, c_imm6
  2332  	{mask: 0x0000e003, value: 0x00004001, op: C_LI, args: argTypeList{arg_rd_n0, arg_c_imm6}},
  2333  	// C.LUI rd_n2, c_nzimm18
  2334  	{mask: 0x0000e003, value: 0x00006001, op: C_LUI, args: argTypeList{arg_rd_n2, arg_c_nzimm18}},
  2335  	// C.LW rd_p, rs1_p, c_uimm7
  2336  	{mask: 0x0000e003, value: 0x00004000, op: C_LW, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm7}},
  2337  	// C.LWSP rd_n0, c_uimm8sp
  2338  	{mask: 0x0000e003, value: 0x00004002, op: C_LWSP, args: argTypeList{arg_rd_n0, arg_c_uimm8sp}},
  2339  	// C.MV rd_n0, c_rs2_n0
  2340  	{mask: 0x0000f003, value: 0x00008002, op: C_MV, args: argTypeList{arg_rd_n0, arg_c_rs2_n0}},
  2341  	// C.NOP c_nzimm6
  2342  	{mask: 0x0000ef83, value: 0x00000001, op: C_NOP, args: argTypeList{arg_c_nzimm6}},
  2343  	// C.OR rd_rs1_p, rs2_p
  2344  	{mask: 0x0000fc63, value: 0x00008c41, op: C_OR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2345  	// C.SD rs1_p, rs2_p, c_uimm8
  2346  	{mask: 0x0000e003, value: 0x0000e000, op: C_SD, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm8}},
  2347  	// C.SDSP c_rs2, c_uimm9sp_s
  2348  	{mask: 0x0000e003, value: 0x0000e002, op: C_SDSP, args: argTypeList{arg_c_rs2, arg_c_uimm9sp_s}},
  2349  	// C.SLLI rd_rs1_n0, c_nzuimm6
  2350  	{mask: 0x0000e003, value: 0x00000002, op: C_SLLI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzuimm6}},
  2351  	// C.SRAI rd_rs1_p, c_nzuimm6
  2352  	{mask: 0x0000ec03, value: 0x00008401, op: C_SRAI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}},
  2353  	// C.SRLI rd_rs1_p, c_nzuimm6
  2354  	{mask: 0x0000ec03, value: 0x00008001, op: C_SRLI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}},
  2355  	// C.SUB rd_rs1_p, rs2_p
  2356  	{mask: 0x0000fc63, value: 0x00008c01, op: C_SUB, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2357  	// C.SUBW rd_rs1_p, rs2_p
  2358  	{mask: 0x0000fc63, value: 0x00009c01, op: C_SUBW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2359  	// C.SW rs1_p, rs2_p, c_uimm7
  2360  	{mask: 0x0000e003, value: 0x0000c000, op: C_SW, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm7}},
  2361  	// C.SWSP c_rs2, c_uimm8sp_s
  2362  	{mask: 0x0000e003, value: 0x0000c002, op: C_SWSP, args: argTypeList{arg_c_rs2, arg_c_uimm8sp_s}},
  2363  	// C.UNIMP
  2364  	{mask: 0x0000ffff, value: 0x00000000, op: C_UNIMP, args: argTypeList{}},
  2365  	// C.XOR rd_rs1_p, rs2_p
  2366  	{mask: 0x0000fc63, value: 0x00008c21, op: C_XOR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2367  	// DIV rd, rs1, rs2
  2368  	{mask: 0xfe00707f, value: 0x02004033, op: DIV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2369  	// DIVU rd, rs1, rs2
  2370  	{mask: 0xfe00707f, value: 0x02005033, op: DIVU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2371  	// DIVUW rd, rs1, rs2
  2372  	{mask: 0xfe00707f, value: 0x0200503b, op: DIVUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2373  	// DIVW rd, rs1, rs2
  2374  	{mask: 0xfe00707f, value: 0x0200403b, op: DIVW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2375  	// EBREAK
  2376  	{mask: 0xffffffff, value: 0x00100073, op: EBREAK, args: argTypeList{}},
  2377  	// ECALL
  2378  	{mask: 0xffffffff, value: 0x00000073, op: ECALL, args: argTypeList{}},
  2379  	// FADD.D fd, fs1, fs2
  2380  	{mask: 0xfe00007f, value: 0x02000053, op: FADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2381  	// FADD.H fd, fs1, fs2
  2382  	{mask: 0xfe00007f, value: 0x04000053, op: FADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2383  	// FADD.Q fd, fs1, fs2
  2384  	{mask: 0xfe00007f, value: 0x06000053, op: FADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2385  	// FADD.S fd, fs1, fs2
  2386  	{mask: 0xfe00007f, value: 0x00000053, op: FADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2387  	// FCLASS.D rd, fs1
  2388  	{mask: 0xfff0707f, value: 0xe2001053, op: FCLASS_D, args: argTypeList{arg_rd, arg_fs1}},
  2389  	// FCLASS.H rd, fs1
  2390  	{mask: 0xfff0707f, value: 0xe4001053, op: FCLASS_H, args: argTypeList{arg_rd, arg_fs1}},
  2391  	// FCLASS.Q rd, fs1
  2392  	{mask: 0xfff0707f, value: 0xe6001053, op: FCLASS_Q, args: argTypeList{arg_rd, arg_fs1}},
  2393  	// FCLASS.S rd, fs1
  2394  	{mask: 0xfff0707f, value: 0xe0001053, op: FCLASS_S, args: argTypeList{arg_rd, arg_fs1}},
  2395  	// FCVT.D.L fd, rs1
  2396  	{mask: 0xfff0007f, value: 0xd2200053, op: FCVT_D_L, args: argTypeList{arg_fd, arg_rs1}},
  2397  	// FCVT.D.LU fd, rs1
  2398  	{mask: 0xfff0007f, value: 0xd2300053, op: FCVT_D_LU, args: argTypeList{arg_fd, arg_rs1}},
  2399  	// FCVT.D.Q fd, fs1
  2400  	{mask: 0xfff0007f, value: 0x42300053, op: FCVT_D_Q, args: argTypeList{arg_fd, arg_fs1}},
  2401  	// FCVT.D.S fd, fs1
  2402  	{mask: 0xfff0007f, value: 0x42000053, op: FCVT_D_S, args: argTypeList{arg_fd, arg_fs1}},
  2403  	// FCVT.D.W fd, rs1
  2404  	{mask: 0xfff0007f, value: 0xd2000053, op: FCVT_D_W, args: argTypeList{arg_fd, arg_rs1}},
  2405  	// FCVT.D.WU fd, rs1
  2406  	{mask: 0xfff0007f, value: 0xd2100053, op: FCVT_D_WU, args: argTypeList{arg_fd, arg_rs1}},
  2407  	// FCVT.H.L fd, rs1
  2408  	{mask: 0xfff0007f, value: 0xd4200053, op: FCVT_H_L, args: argTypeList{arg_fd, arg_rs1}},
  2409  	// FCVT.H.LU fd, rs1
  2410  	{mask: 0xfff0007f, value: 0xd4300053, op: FCVT_H_LU, args: argTypeList{arg_fd, arg_rs1}},
  2411  	// FCVT.H.S fd, fs1
  2412  	{mask: 0xfff0007f, value: 0x44000053, op: FCVT_H_S, args: argTypeList{arg_fd, arg_fs1}},
  2413  	// FCVT.H.W fd, rs1
  2414  	{mask: 0xfff0007f, value: 0xd4000053, op: FCVT_H_W, args: argTypeList{arg_fd, arg_rs1}},
  2415  	// FCVT.H.WU fd, rs1
  2416  	{mask: 0xfff0007f, value: 0xd4100053, op: FCVT_H_WU, args: argTypeList{arg_fd, arg_rs1}},
  2417  	// FCVT.LU.D rd, fs1
  2418  	{mask: 0xfff0007f, value: 0xc2300053, op: FCVT_LU_D, args: argTypeList{arg_rd, arg_fs1}},
  2419  	// FCVT.LU.H rd, fs1
  2420  	{mask: 0xfff0007f, value: 0xc4300053, op: FCVT_LU_H, args: argTypeList{arg_rd, arg_fs1}},
  2421  	// FCVT.LU.Q rd, fs1
  2422  	{mask: 0xfff0007f, value: 0xc6300053, op: FCVT_LU_Q, args: argTypeList{arg_rd, arg_fs1}},
  2423  	// FCVT.LU.S rd, fs1
  2424  	{mask: 0xfff0007f, value: 0xc0300053, op: FCVT_LU_S, args: argTypeList{arg_rd, arg_fs1}},
  2425  	// FCVT.L.D rd, fs1
  2426  	{mask: 0xfff0007f, value: 0xc2200053, op: FCVT_L_D, args: argTypeList{arg_rd, arg_fs1}},
  2427  	// FCVT.L.H rd, fs1
  2428  	{mask: 0xfff0007f, value: 0xc4200053, op: FCVT_L_H, args: argTypeList{arg_rd, arg_fs1}},
  2429  	// FCVT.L.Q rd, fs1
  2430  	{mask: 0xfff0007f, value: 0xc6200053, op: FCVT_L_Q, args: argTypeList{arg_rd, arg_fs1}},
  2431  	// FCVT.L.S rd, fs1
  2432  	{mask: 0xfff0007f, value: 0xc0200053, op: FCVT_L_S, args: argTypeList{arg_rd, arg_fs1}},
  2433  	// FCVT.Q.D fd, fs1
  2434  	{mask: 0xfff0007f, value: 0x46100053, op: FCVT_Q_D, args: argTypeList{arg_fd, arg_fs1}},
  2435  	// FCVT.Q.L fd, rs1
  2436  	{mask: 0xfff0007f, value: 0xd6200053, op: FCVT_Q_L, args: argTypeList{arg_fd, arg_rs1}},
  2437  	// FCVT.Q.LU fd, rs1
  2438  	{mask: 0xfff0007f, value: 0xd6300053, op: FCVT_Q_LU, args: argTypeList{arg_fd, arg_rs1}},
  2439  	// FCVT.Q.S fd, fs1
  2440  	{mask: 0xfff0007f, value: 0x46000053, op: FCVT_Q_S, args: argTypeList{arg_fd, arg_fs1}},
  2441  	// FCVT.Q.W fd, rs1
  2442  	{mask: 0xfff0007f, value: 0xd6000053, op: FCVT_Q_W, args: argTypeList{arg_fd, arg_rs1}},
  2443  	// FCVT.Q.WU fd, rs1
  2444  	{mask: 0xfff0007f, value: 0xd6100053, op: FCVT_Q_WU, args: argTypeList{arg_fd, arg_rs1}},
  2445  	// FCVT.S.D fd, fs1
  2446  	{mask: 0xfff0007f, value: 0x40100053, op: FCVT_S_D, args: argTypeList{arg_fd, arg_fs1}},
  2447  	// FCVT.S.H fd, fs1
  2448  	{mask: 0xfff0007f, value: 0x40200053, op: FCVT_S_H, args: argTypeList{arg_fd, arg_fs1}},
  2449  	// FCVT.S.L fd, rs1
  2450  	{mask: 0xfff0007f, value: 0xd0200053, op: FCVT_S_L, args: argTypeList{arg_fd, arg_rs1}},
  2451  	// FCVT.S.LU fd, rs1
  2452  	{mask: 0xfff0007f, value: 0xd0300053, op: FCVT_S_LU, args: argTypeList{arg_fd, arg_rs1}},
  2453  	// FCVT.S.Q fd, fs1
  2454  	{mask: 0xfff0007f, value: 0x40300053, op: FCVT_S_Q, args: argTypeList{arg_fd, arg_fs1}},
  2455  	// FCVT.S.W fd, rs1
  2456  	{mask: 0xfff0007f, value: 0xd0000053, op: FCVT_S_W, args: argTypeList{arg_fd, arg_rs1}},
  2457  	// FCVT.S.WU fd, rs1
  2458  	{mask: 0xfff0007f, value: 0xd0100053, op: FCVT_S_WU, args: argTypeList{arg_fd, arg_rs1}},
  2459  	// FCVT.WU.D rd, fs1
  2460  	{mask: 0xfff0007f, value: 0xc2100053, op: FCVT_WU_D, args: argTypeList{arg_rd, arg_fs1}},
  2461  	// FCVT.WU.H rd, fs1
  2462  	{mask: 0xfff0007f, value: 0xc4100053, op: FCVT_WU_H, args: argTypeList{arg_rd, arg_fs1}},
  2463  	// FCVT.WU.Q rd, fs1
  2464  	{mask: 0xfff0007f, value: 0xc6100053, op: FCVT_WU_Q, args: argTypeList{arg_rd, arg_fs1}},
  2465  	// FCVT.WU.S rd, fs1
  2466  	{mask: 0xfff0007f, value: 0xc0100053, op: FCVT_WU_S, args: argTypeList{arg_rd, arg_fs1}},
  2467  	// FCVT.W.D rd, fs1
  2468  	{mask: 0xfff0007f, value: 0xc2000053, op: FCVT_W_D, args: argTypeList{arg_rd, arg_fs1}},
  2469  	// FCVT.W.H rd, fs1
  2470  	{mask: 0xfff0007f, value: 0xc4000053, op: FCVT_W_H, args: argTypeList{arg_rd, arg_fs1}},
  2471  	// FCVT.W.Q rd, fs1
  2472  	{mask: 0xfff0007f, value: 0xc6000053, op: FCVT_W_Q, args: argTypeList{arg_rd, arg_fs1}},
  2473  	// FCVT.W.S rd, fs1
  2474  	{mask: 0xfff0007f, value: 0xc0000053, op: FCVT_W_S, args: argTypeList{arg_rd, arg_fs1}},
  2475  	// FDIV.D fd, fs1, fs2
  2476  	{mask: 0xfe00007f, value: 0x1a000053, op: FDIV_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2477  	// FDIV.H fd, fs1, fs2
  2478  	{mask: 0xfe00007f, value: 0x1c000053, op: FDIV_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2479  	// FDIV.Q fd, fs1, fs2
  2480  	{mask: 0xfe00007f, value: 0x1e000053, op: FDIV_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2481  	// FDIV.S fd, fs1, fs2
  2482  	{mask: 0xfe00007f, value: 0x18000053, op: FDIV_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2483  	// FENCE pred, succ
  2484  	{mask: 0x0000707f, value: 0x0000000f, op: FENCE, args: argTypeList{arg_pred, arg_succ}},
  2485  	// FENCE.I
  2486  	{mask: 0x0000707f, value: 0x0000100f, op: FENCE_I, args: argTypeList{}},
  2487  	// FEQ.D rd, fs1, fs2
  2488  	{mask: 0xfe00707f, value: 0xa2002053, op: FEQ_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2489  	// FEQ.H rd, fs1, fs2
  2490  	{mask: 0xfe00707f, value: 0xa4002053, op: FEQ_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2491  	// FEQ.Q rd, fs1, fs2
  2492  	{mask: 0xfe00707f, value: 0xa6002053, op: FEQ_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2493  	// FEQ.S rd, fs1, fs2
  2494  	{mask: 0xfe00707f, value: 0xa0002053, op: FEQ_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2495  	// FLD fd, rs1_mem
  2496  	{mask: 0x0000707f, value: 0x00003007, op: FLD, args: argTypeList{arg_fd, arg_rs1_mem}},
  2497  	// FLE.D rd, fs1, fs2
  2498  	{mask: 0xfe00707f, value: 0xa2000053, op: FLE_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2499  	// FLE.H rd, fs1, fs2
  2500  	{mask: 0xfe00707f, value: 0xa4000053, op: FLE_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2501  	// FLE.Q rd, fs1, fs2
  2502  	{mask: 0xfe00707f, value: 0xa6000053, op: FLE_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2503  	// FLE.S rd, fs1, fs2
  2504  	{mask: 0xfe00707f, value: 0xa0000053, op: FLE_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2505  	// FLH fd, rs1_mem
  2506  	{mask: 0x0000707f, value: 0x00001007, op: FLH, args: argTypeList{arg_fd, arg_rs1_mem}},
  2507  	// FLQ fd, rs1_mem
  2508  	{mask: 0x0000707f, value: 0x00004007, op: FLQ, args: argTypeList{arg_fd, arg_rs1_mem}},
  2509  	// FLT.D rd, fs1, fs2
  2510  	{mask: 0xfe00707f, value: 0xa2001053, op: FLT_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2511  	// FLT.H rd, fs1, fs2
  2512  	{mask: 0xfe00707f, value: 0xa4001053, op: FLT_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2513  	// FLT.Q rd, fs1, fs2
  2514  	{mask: 0xfe00707f, value: 0xa6001053, op: FLT_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2515  	// FLT.S rd, fs1, fs2
  2516  	{mask: 0xfe00707f, value: 0xa0001053, op: FLT_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2517  	// FLW fd, rs1_mem
  2518  	{mask: 0x0000707f, value: 0x00002007, op: FLW, args: argTypeList{arg_fd, arg_rs1_mem}},
  2519  	// FMADD.D fd, fs1, fs2, fs3
  2520  	{mask: 0x0600007f, value: 0x02000043, op: FMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2521  	// FMADD.H fd, fs1, fs2, fs3
  2522  	{mask: 0x0600007f, value: 0x04000043, op: FMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2523  	// FMADD.Q fd, fs1, fs2, fs3
  2524  	{mask: 0x0600007f, value: 0x06000043, op: FMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2525  	// FMADD.S fd, fs1, fs2, fs3
  2526  	{mask: 0x0600007f, value: 0x00000043, op: FMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2527  	// FMAX.D fd, fs1, fs2
  2528  	{mask: 0xfe00707f, value: 0x2a001053, op: FMAX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2529  	// FMAX.H fd, fs1, fs2
  2530  	{mask: 0xfe00707f, value: 0x2c001053, op: FMAX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2531  	// FMAX.Q fd, fs1, fs2
  2532  	{mask: 0xfe00707f, value: 0x2e001053, op: FMAX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2533  	// FMAX.S fd, fs1, fs2
  2534  	{mask: 0xfe00707f, value: 0x28001053, op: FMAX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2535  	// FMIN.D fd, fs1, fs2
  2536  	{mask: 0xfe00707f, value: 0x2a000053, op: FMIN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2537  	// FMIN.H fd, fs1, fs2
  2538  	{mask: 0xfe00707f, value: 0x2c000053, op: FMIN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2539  	// FMIN.Q fd, fs1, fs2
  2540  	{mask: 0xfe00707f, value: 0x2e000053, op: FMIN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2541  	// FMIN.S fd, fs1, fs2
  2542  	{mask: 0xfe00707f, value: 0x28000053, op: FMIN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2543  	// FMSUB.D fd, fs1, fs2, fs3
  2544  	{mask: 0x0600007f, value: 0x02000047, op: FMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2545  	// FMSUB.H fd, fs1, fs2, fs3
  2546  	{mask: 0x0600007f, value: 0x04000047, op: FMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2547  	// FMSUB.Q fd, fs1, fs2, fs3
  2548  	{mask: 0x0600007f, value: 0x06000047, op: FMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2549  	// FMSUB.S fd, fs1, fs2, fs3
  2550  	{mask: 0x0600007f, value: 0x00000047, op: FMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2551  	// FMUL.D fd, fs1, fs2
  2552  	{mask: 0xfe00007f, value: 0x12000053, op: FMUL_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2553  	// FMUL.H fd, fs1, fs2
  2554  	{mask: 0xfe00007f, value: 0x14000053, op: FMUL_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2555  	// FMUL.Q fd, fs1, fs2
  2556  	{mask: 0xfe00007f, value: 0x16000053, op: FMUL_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2557  	// FMUL.S fd, fs1, fs2
  2558  	{mask: 0xfe00007f, value: 0x10000053, op: FMUL_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2559  	// FMV.D.X fd, rs1
  2560  	{mask: 0xfff0707f, value: 0xf2000053, op: FMV_D_X, args: argTypeList{arg_fd, arg_rs1}},
  2561  	// FMV.H.X fd, rs1
  2562  	{mask: 0xfff0707f, value: 0xf4000053, op: FMV_H_X, args: argTypeList{arg_fd, arg_rs1}},
  2563  	// FMV.W.X fd, rs1
  2564  	{mask: 0xfff0707f, value: 0xf0000053, op: FMV_W_X, args: argTypeList{arg_fd, arg_rs1}},
  2565  	// FMV.X.D rd, fs1
  2566  	{mask: 0xfff0707f, value: 0xe2000053, op: FMV_X_D, args: argTypeList{arg_rd, arg_fs1}},
  2567  	// FMV.X.H rd, fs1
  2568  	{mask: 0xfff0707f, value: 0xe4000053, op: FMV_X_H, args: argTypeList{arg_rd, arg_fs1}},
  2569  	// FMV.X.W rd, fs1
  2570  	{mask: 0xfff0707f, value: 0xe0000053, op: FMV_X_W, args: argTypeList{arg_rd, arg_fs1}},
  2571  	// FNMADD.D fd, fs1, fs2, fs3
  2572  	{mask: 0x0600007f, value: 0x0200004f, op: FNMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2573  	// FNMADD.H fd, fs1, fs2, fs3
  2574  	{mask: 0x0600007f, value: 0x0400004f, op: FNMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2575  	// FNMADD.Q fd, fs1, fs2, fs3
  2576  	{mask: 0x0600007f, value: 0x0600004f, op: FNMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2577  	// FNMADD.S fd, fs1, fs2, fs3
  2578  	{mask: 0x0600007f, value: 0x0000004f, op: FNMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2579  	// FNMSUB.D fd, fs1, fs2, fs3
  2580  	{mask: 0x0600007f, value: 0x0200004b, op: FNMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2581  	// FNMSUB.H fd, fs1, fs2, fs3
  2582  	{mask: 0x0600007f, value: 0x0400004b, op: FNMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2583  	// FNMSUB.Q fd, fs1, fs2, fs3
  2584  	{mask: 0x0600007f, value: 0x0600004b, op: FNMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2585  	// FNMSUB.S fd, fs1, fs2, fs3
  2586  	{mask: 0x0600007f, value: 0x0000004b, op: FNMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2587  	// FSD fs2, rs1_store
  2588  	{mask: 0x0000707f, value: 0x00003027, op: FSD, args: argTypeList{arg_fs2, arg_rs1_store}},
  2589  	// FSGNJN.D fd, fs1, fs2
  2590  	{mask: 0xfe00707f, value: 0x22001053, op: FSGNJN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2591  	// FSGNJN.H fd, fs1, fs2
  2592  	{mask: 0xfe00707f, value: 0x24001053, op: FSGNJN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2593  	// FSGNJN.Q fd, fs1, fs2
  2594  	{mask: 0xfe00707f, value: 0x26001053, op: FSGNJN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2595  	// FSGNJN.S fd, fs1, fs2
  2596  	{mask: 0xfe00707f, value: 0x20001053, op: FSGNJN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2597  	// FSGNJX.D fd, fs1, fs2
  2598  	{mask: 0xfe00707f, value: 0x22002053, op: FSGNJX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2599  	// FSGNJX.H fd, fs1, fs2
  2600  	{mask: 0xfe00707f, value: 0x24002053, op: FSGNJX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2601  	// FSGNJX.Q fd, fs1, fs2
  2602  	{mask: 0xfe00707f, value: 0x26002053, op: FSGNJX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2603  	// FSGNJX.S fd, fs1, fs2
  2604  	{mask: 0xfe00707f, value: 0x20002053, op: FSGNJX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2605  	// FSGNJ.D fd, fs1, fs2
  2606  	{mask: 0xfe00707f, value: 0x22000053, op: FSGNJ_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2607  	// FSGNJ.H fd, fs1, fs2
  2608  	{mask: 0xfe00707f, value: 0x24000053, op: FSGNJ_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2609  	// FSGNJ.Q fd, fs1, fs2
  2610  	{mask: 0xfe00707f, value: 0x26000053, op: FSGNJ_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2611  	// FSGNJ.S fd, fs1, fs2
  2612  	{mask: 0xfe00707f, value: 0x20000053, op: FSGNJ_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2613  	// FSH fs2, rs1_store
  2614  	{mask: 0x0000707f, value: 0x00001027, op: FSH, args: argTypeList{arg_fs2, arg_rs1_store}},
  2615  	// FSQ fs2, rs1_store
  2616  	{mask: 0x0000707f, value: 0x00004027, op: FSQ, args: argTypeList{arg_fs2, arg_rs1_store}},
  2617  	// FSQRT.D fd, fs1
  2618  	{mask: 0xfff0007f, value: 0x5a000053, op: FSQRT_D, args: argTypeList{arg_fd, arg_fs1}},
  2619  	// FSQRT.H fd, fs1
  2620  	{mask: 0xfff0007f, value: 0x5c000053, op: FSQRT_H, args: argTypeList{arg_fd, arg_fs1}},
  2621  	// FSQRT.Q fd, fs1
  2622  	{mask: 0xfff0007f, value: 0x5e000053, op: FSQRT_Q, args: argTypeList{arg_fd, arg_fs1}},
  2623  	// FSQRT.S fd, fs1
  2624  	{mask: 0xfff0007f, value: 0x58000053, op: FSQRT_S, args: argTypeList{arg_fd, arg_fs1}},
  2625  	// FSUB.D fd, fs1, fs2
  2626  	{mask: 0xfe00007f, value: 0x0a000053, op: FSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2627  	// FSUB.H fd, fs1, fs2
  2628  	{mask: 0xfe00007f, value: 0x0c000053, op: FSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2629  	// FSUB.Q fd, fs1, fs2
  2630  	{mask: 0xfe00007f, value: 0x0e000053, op: FSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2631  	// FSUB.S fd, fs1, fs2
  2632  	{mask: 0xfe00007f, value: 0x08000053, op: FSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2633  	// FSW fs2, rs1_store
  2634  	{mask: 0x0000707f, value: 0x00002027, op: FSW, args: argTypeList{arg_fs2, arg_rs1_store}},
  2635  	// JAL rd, jimm20
  2636  	{mask: 0x0000007f, value: 0x0000006f, op: JAL, args: argTypeList{arg_rd, arg_jimm20}},
  2637  	// JALR rd, rs1_mem
  2638  	{mask: 0x0000707f, value: 0x00000067, op: JALR, args: argTypeList{arg_rd, arg_rs1_mem}},
  2639  	// LB rd, rs1_mem
  2640  	{mask: 0x0000707f, value: 0x00000003, op: LB, args: argTypeList{arg_rd, arg_rs1_mem}},
  2641  	// LBU rd, rs1_mem
  2642  	{mask: 0x0000707f, value: 0x00004003, op: LBU, args: argTypeList{arg_rd, arg_rs1_mem}},
  2643  	// LD rd, rs1_mem
  2644  	{mask: 0x0000707f, value: 0x00003003, op: LD, args: argTypeList{arg_rd, arg_rs1_mem}},
  2645  	// LH rd, rs1_mem
  2646  	{mask: 0x0000707f, value: 0x00001003, op: LH, args: argTypeList{arg_rd, arg_rs1_mem}},
  2647  	// LHU rd, rs1_mem
  2648  	{mask: 0x0000707f, value: 0x00005003, op: LHU, args: argTypeList{arg_rd, arg_rs1_mem}},
  2649  	// LR.D rd, rs1_ptr
  2650  	{mask: 0xfff0707f, value: 0x1000302f, op: LR_D, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2651  	// LR.D.AQ rd, rs1_ptr
  2652  	{mask: 0xfff0707f, value: 0x1400302f, op: LR_D_AQ, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2653  	// LR.D.AQRL rd, rs1_ptr
  2654  	{mask: 0xfff0707f, value: 0x1600302f, op: LR_D_AQRL, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2655  	// LR.D.RL rd, rs1_ptr
  2656  	{mask: 0xfff0707f, value: 0x1200302f, op: LR_D_RL, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2657  	// LR.W rd, rs1_ptr
  2658  	{mask: 0xfff0707f, value: 0x1000202f, op: LR_W, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2659  	// LR.W.AQ rd, rs1_ptr
  2660  	{mask: 0xfff0707f, value: 0x1400202f, op: LR_W_AQ, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2661  	// LR.W.AQRL rd, rs1_ptr
  2662  	{mask: 0xfff0707f, value: 0x1600202f, op: LR_W_AQRL, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2663  	// LR.W.RL rd, rs1_ptr
  2664  	{mask: 0xfff0707f, value: 0x1200202f, op: LR_W_RL, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2665  	// LUI rd, imm20
  2666  	{mask: 0x0000007f, value: 0x00000037, op: LUI, args: argTypeList{arg_rd, arg_imm20}},
  2667  	// LW rd, rs1_mem
  2668  	{mask: 0x0000707f, value: 0x00002003, op: LW, args: argTypeList{arg_rd, arg_rs1_mem}},
  2669  	// LWU rd, rs1_mem
  2670  	{mask: 0x0000707f, value: 0x00006003, op: LWU, args: argTypeList{arg_rd, arg_rs1_mem}},
  2671  	// MAX rd, rs1, rs2
  2672  	{mask: 0xfe00707f, value: 0x0a006033, op: MAX, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2673  	// MAXU rd, rs1, rs2
  2674  	{mask: 0xfe00707f, value: 0x0a007033, op: MAXU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2675  	// MIN rd, rs1, rs2
  2676  	{mask: 0xfe00707f, value: 0x0a004033, op: MIN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2677  	// MINU rd, rs1, rs2
  2678  	{mask: 0xfe00707f, value: 0x0a005033, op: MINU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2679  	// MUL rd, rs1, rs2
  2680  	{mask: 0xfe00707f, value: 0x02000033, op: MUL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2681  	// MULH rd, rs1, rs2
  2682  	{mask: 0xfe00707f, value: 0x02001033, op: MULH, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2683  	// MULHSU rd, rs1, rs2
  2684  	{mask: 0xfe00707f, value: 0x02002033, op: MULHSU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2685  	// MULHU rd, rs1, rs2
  2686  	{mask: 0xfe00707f, value: 0x02003033, op: MULHU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2687  	// MULW rd, rs1, rs2
  2688  	{mask: 0xfe00707f, value: 0x0200003b, op: MULW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2689  	// OR rd, rs1, rs2
  2690  	{mask: 0xfe00707f, value: 0x00006033, op: OR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2691  	// ORC.B rd, rs1
  2692  	{mask: 0xfff0707f, value: 0x28705013, op: ORC_B, args: argTypeList{arg_rd, arg_rs1}},
  2693  	// ORI rd, rs1, imm12
  2694  	{mask: 0x0000707f, value: 0x00006013, op: ORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2695  	// ORN rd, rs1, rs2
  2696  	{mask: 0xfe00707f, value: 0x40006033, op: ORN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2697  	// REM rd, rs1, rs2
  2698  	{mask: 0xfe00707f, value: 0x02006033, op: REM, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2699  	// REMU rd, rs1, rs2
  2700  	{mask: 0xfe00707f, value: 0x02007033, op: REMU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2701  	// REMUW rd, rs1, rs2
  2702  	{mask: 0xfe00707f, value: 0x0200703b, op: REMUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2703  	// REMW rd, rs1, rs2
  2704  	{mask: 0xfe00707f, value: 0x0200603b, op: REMW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2705  	// REV8 rd, rs1
  2706  	{mask: 0xfff0707f, value: 0x6b805013, op: REV8, args: argTypeList{arg_rd, arg_rs1}},
  2707  	// ROL rd, rs1, rs2
  2708  	{mask: 0xfe00707f, value: 0x60001033, op: ROL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2709  	// ROLW rd, rs1, rs2
  2710  	{mask: 0xfe00707f, value: 0x6000103b, op: ROLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2711  	// ROR rd, rs1, rs2
  2712  	{mask: 0xfe00707f, value: 0x60005033, op: ROR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2713  	// RORI rd, rs1, shamt6
  2714  	{mask: 0xfc00707f, value: 0x60005013, op: RORI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2715  	// RORIW rd, rs1, shamt5
  2716  	{mask: 0xfe00707f, value: 0x6000501b, op: RORIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}},
  2717  	// RORW rd, rs1, rs2
  2718  	{mask: 0xfe00707f, value: 0x6000503b, op: RORW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2719  	// SB rs2, rs1_store
  2720  	{mask: 0x0000707f, value: 0x00000023, op: SB, args: argTypeList{arg_rs2, arg_rs1_store}},
  2721  	// SC.D rd, rs2, rs1_ptr
  2722  	{mask: 0xfe00707f, value: 0x1800302f, op: SC_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2723  	// SC.D.AQ rd, rs2, rs1_ptr
  2724  	{mask: 0xfe00707f, value: 0x1c00302f, op: SC_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2725  	// SC.D.AQRL rd, rs2, rs1_ptr
  2726  	{mask: 0xfe00707f, value: 0x1e00302f, op: SC_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2727  	// SC.D.RL rd, rs2, rs1_ptr
  2728  	{mask: 0xfe00707f, value: 0x1a00302f, op: SC_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2729  	// SC.W rd, rs2, rs1_ptr
  2730  	{mask: 0xfe00707f, value: 0x1800202f, op: SC_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2731  	// SC.W.AQ rd, rs2, rs1_ptr
  2732  	{mask: 0xfe00707f, value: 0x1c00202f, op: SC_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2733  	// SC.W.AQRL rd, rs2, rs1_ptr
  2734  	{mask: 0xfe00707f, value: 0x1e00202f, op: SC_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2735  	// SC.W.RL rd, rs2, rs1_ptr
  2736  	{mask: 0xfe00707f, value: 0x1a00202f, op: SC_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2737  	// SD rs2, rs1_store
  2738  	{mask: 0x0000707f, value: 0x00003023, op: SD, args: argTypeList{arg_rs2, arg_rs1_store}},
  2739  	// SEXT.B rd, rs1
  2740  	{mask: 0xfff0707f, value: 0x60401013, op: SEXT_B, args: argTypeList{arg_rd, arg_rs1}},
  2741  	// SEXT.H rd, rs1
  2742  	{mask: 0xfff0707f, value: 0x60501013, op: SEXT_H, args: argTypeList{arg_rd, arg_rs1}},
  2743  	// SH rs2, rs1_store
  2744  	{mask: 0x0000707f, value: 0x00001023, op: SH, args: argTypeList{arg_rs2, arg_rs1_store}},
  2745  	// SH1ADD rd, rs1, rs2
  2746  	{mask: 0xfe00707f, value: 0x20002033, op: SH1ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2747  	// SH1ADD.UW rd, rs1, rs2
  2748  	{mask: 0xfe00707f, value: 0x2000203b, op: SH1ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2749  	// SH2ADD rd, rs1, rs2
  2750  	{mask: 0xfe00707f, value: 0x20004033, op: SH2ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2751  	// SH2ADD.UW rd, rs1, rs2
  2752  	{mask: 0xfe00707f, value: 0x2000403b, op: SH2ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2753  	// SH3ADD rd, rs1, rs2
  2754  	{mask: 0xfe00707f, value: 0x20006033, op: SH3ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2755  	// SH3ADD.UW rd, rs1, rs2
  2756  	{mask: 0xfe00707f, value: 0x2000603b, op: SH3ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2757  	// SLL rd, rs1, rs2
  2758  	{mask: 0xfe00707f, value: 0x00001033, op: SLL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2759  	// SLLI rd, rs1, shamt6
  2760  	{mask: 0xfc00707f, value: 0x00001013, op: SLLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2761  	// SLLIW rd, rs1, shamt5
  2762  	{mask: 0xfe00707f, value: 0x0000101b, op: SLLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}},
  2763  	// SLLI.UW rd, rs1, shamt6
  2764  	{mask: 0xfc00707f, value: 0x0800101b, op: SLLI_UW, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2765  	// SLLW rd, rs1, rs2
  2766  	{mask: 0xfe00707f, value: 0x0000103b, op: SLLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2767  	// SLT rd, rs1, rs2
  2768  	{mask: 0xfe00707f, value: 0x00002033, op: SLT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2769  	// SLTI rd, rs1, imm12
  2770  	{mask: 0x0000707f, value: 0x00002013, op: SLTI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2771  	// SLTIU rd, rs1, imm12
  2772  	{mask: 0x0000707f, value: 0x00003013, op: SLTIU, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2773  	// SLTU rd, rs1, rs2
  2774  	{mask: 0xfe00707f, value: 0x00003033, op: SLTU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2775  	// SRA rd, rs1, rs2
  2776  	{mask: 0xfe00707f, value: 0x40005033, op: SRA, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2777  	// SRAI rd, rs1, shamt6
  2778  	{mask: 0xfc00707f, value: 0x40005013, op: SRAI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2779  	// SRAIW rd, rs1, shamt5
  2780  	{mask: 0xfe00707f, value: 0x4000501b, op: SRAIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}},
  2781  	// SRAW rd, rs1, rs2
  2782  	{mask: 0xfe00707f, value: 0x4000503b, op: SRAW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2783  	// SRL rd, rs1, rs2
  2784  	{mask: 0xfe00707f, value: 0x00005033, op: SRL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2785  	// SRLI rd, rs1, shamt6
  2786  	{mask: 0xfc00707f, value: 0x00005013, op: SRLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2787  	// SRLIW rd, rs1, shamt5
  2788  	{mask: 0xfe00707f, value: 0x0000501b, op: SRLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}},
  2789  	// SRLW rd, rs1, rs2
  2790  	{mask: 0xfe00707f, value: 0x0000503b, op: SRLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2791  	// SUB rd, rs1, rs2
  2792  	{mask: 0xfe00707f, value: 0x40000033, op: SUB, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2793  	// SUBW rd, rs1, rs2
  2794  	{mask: 0xfe00707f, value: 0x4000003b, op: SUBW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2795  	// SW rs2, rs1_store
  2796  	{mask: 0x0000707f, value: 0x00002023, op: SW, args: argTypeList{arg_rs2, arg_rs1_store}},
  2797  	// VAADDU.VV vm, vs2, vs1, vd
  2798  	{mask: 0xfc00707f, value: 0x20002057, op: VAADDU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2799  	// VAADDU.VX vm, vs2, rs1, vd
  2800  	{mask: 0xfc00707f, value: 0x20006057, op: VAADDU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2801  	// VAADD.VV vm, vs2, vs1, vd
  2802  	{mask: 0xfc00707f, value: 0x24002057, op: VAADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2803  	// VAADD.VX vm, vs2, rs1, vd
  2804  	{mask: 0xfc00707f, value: 0x24006057, op: VAADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2805  	// VAESDF.VS vs2, vd
  2806  	{mask: 0xfe0ff07f, value: 0xa600a077, op: VAESDF_VS, args: argTypeList{arg_vs2, arg_vd}},
  2807  	// VAESDF.VV vs2, vd
  2808  	{mask: 0xfe0ff07f, value: 0xa200a077, op: VAESDF_VV, args: argTypeList{arg_vs2, arg_vd}},
  2809  	// VAESDM.VS vs2, vd
  2810  	{mask: 0xfe0ff07f, value: 0xa6002077, op: VAESDM_VS, args: argTypeList{arg_vs2, arg_vd}},
  2811  	// VAESDM.VV vs2, vd
  2812  	{mask: 0xfe0ff07f, value: 0xa2002077, op: VAESDM_VV, args: argTypeList{arg_vs2, arg_vd}},
  2813  	// VAESEF.VS vs2, vd
  2814  	{mask: 0xfe0ff07f, value: 0xa601a077, op: VAESEF_VS, args: argTypeList{arg_vs2, arg_vd}},
  2815  	// VAESEF.VV vs2, vd
  2816  	{mask: 0xfe0ff07f, value: 0xa201a077, op: VAESEF_VV, args: argTypeList{arg_vs2, arg_vd}},
  2817  	// VAESEM.VS vs2, vd
  2818  	{mask: 0xfe0ff07f, value: 0xa6012077, op: VAESEM_VS, args: argTypeList{arg_vs2, arg_vd}},
  2819  	// VAESEM.VV vs2, vd
  2820  	{mask: 0xfe0ff07f, value: 0xa2012077, op: VAESEM_VV, args: argTypeList{arg_vs2, arg_vd}},
  2821  	// VAESKF1.VI vs2, zimm, vd
  2822  	{mask: 0xfe00707f, value: 0x8a002077, op: VAESKF1_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
  2823  	// VAESKF2.VI vs2, zimm, vd
  2824  	{mask: 0xfe00707f, value: 0xaa002077, op: VAESKF2_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
  2825  	// VAESZ.VS vs2, vd
  2826  	{mask: 0xfe0ff07f, value: 0xa603a077, op: VAESZ_VS, args: argTypeList{arg_vs2, arg_vd}},
  2827  	// VGHSH.VV vs2, vs1, vd
  2828  	{mask: 0xfe00707f, value: 0xb2002077, op: VGHSH_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2829  	// VGMUL.VV vs2, vd
  2830  	{mask: 0xfe0ff07f, value: 0xa208a077, op: VGMUL_VV, args: argTypeList{arg_vs2, arg_vd}},
  2831  	// VSHA2CH.VV vs2, vs1, vd
  2832  	{mask: 0xfe00707f, value: 0xba002077, op: VSHA2CH_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2833  	// VSHA2CL.VV vs2, vs1, vd
  2834  	{mask: 0xfe00707f, value: 0xbe002077, op: VSHA2CL_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2835  	// VSHA2MS.VV vs2, vs1, vd
  2836  	{mask: 0xfe00707f, value: 0xb6002077, op: VSHA2MS_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2837  	// VSM3C.VI vs2, zimm, vd
  2838  	{mask: 0xfe00707f, value: 0xae002077, op: VSM3C_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
  2839  	// VSM3ME.VV vs2, vs1, vd
  2840  	{mask: 0xfe00707f, value: 0x82002077, op: VSM3ME_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2841  	// VSM4K.VI vs2, zimm, vd
  2842  	{mask: 0xfe00707f, value: 0x86002077, op: VSM4K_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
  2843  	// VSM4R.VS vs2, vd
  2844  	{mask: 0xfe0ff07f, value: 0xa6082077, op: VSM4R_VS, args: argTypeList{arg_vs2, arg_vd}},
  2845  	// VSM4R.VV vs2, vd
  2846  	{mask: 0xfe0ff07f, value: 0xa2082077, op: VSM4R_VV, args: argTypeList{arg_vs2, arg_vd}},
  2847  	// VADC.VIM vs2, simm5, vd
  2848  	{mask: 0xfe00707f, value: 0x40003057, op: VADC_VIM, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
  2849  	// VADC.VVM vs2, vs1, vd
  2850  	{mask: 0xfe00707f, value: 0x40000057, op: VADC_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2851  	// VADC.VXM vs2, rs1, vd
  2852  	{mask: 0xfe00707f, value: 0x40004057, op: VADC_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  2853  	// VADD.VI vm, vs2, simm5, vd
  2854  	{mask: 0xfc00707f, value: 0x00003057, op: VADD_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  2855  	// VADD.VV vm, vs2, vs1, vd
  2856  	{mask: 0xfc00707f, value: 0x00000057, op: VADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2857  	// VADD.VX vm, vs2, rs1, vd
  2858  	{mask: 0xfc00707f, value: 0x00004057, op: VADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2859  	// VAND.VI vm, vs2, simm5, vd
  2860  	{mask: 0xfc00707f, value: 0x24003057, op: VAND_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  2861  	// VAND.VV vm, vs2, vs1, vd
  2862  	{mask: 0xfc00707f, value: 0x24000057, op: VAND_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2863  	// VAND.VX vm, vs2, rs1, vd
  2864  	{mask: 0xfc00707f, value: 0x24004057, op: VAND_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2865  	// VASUBU.VV vm, vs2, vs1, vd
  2866  	{mask: 0xfc00707f, value: 0x28002057, op: VASUBU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2867  	// VASUBU.VX vm, vs2, rs1, vd
  2868  	{mask: 0xfc00707f, value: 0x28006057, op: VASUBU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2869  	// VASUB.VV vm, vs2, vs1, vd
  2870  	{mask: 0xfc00707f, value: 0x2c002057, op: VASUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2871  	// VASUB.VX vm, vs2, rs1, vd
  2872  	{mask: 0xfc00707f, value: 0x2c006057, op: VASUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2873  	// VCOMPRESS.VM vs2, vs1, vd
  2874  	{mask: 0xfe00707f, value: 0x5e002057, op: VCOMPRESS_VM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2875  	// VCPOP.M vm, vs2, rd
  2876  	{mask: 0xfc0ff07f, value: 0x40082057, op: VCPOP_M, args: argTypeList{arg_vm, arg_vs2, arg_rd}},
  2877  	// VDIVU.VV vm, vs2, vs1, vd
  2878  	{mask: 0xfc00707f, value: 0x80002057, op: VDIVU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2879  	// VDIVU.VX vm, vs2, rs1, vd
  2880  	{mask: 0xfc00707f, value: 0x80006057, op: VDIVU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2881  	// VDIV.VV vm, vs2, vs1, vd
  2882  	{mask: 0xfc00707f, value: 0x84002057, op: VDIV_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2883  	// VDIV.VX vm, vs2, rs1, vd
  2884  	{mask: 0xfc00707f, value: 0x84006057, op: VDIV_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2885  	// VFADD.VF vm, vs2, fs1, vd
  2886  	{mask: 0xfc00707f, value: 0x00005057, op: VFADD_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2887  	// VFADD.VV vm, vs2, vs1, vd
  2888  	{mask: 0xfc00707f, value: 0x00001057, op: VFADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2889  	// VFCLASS.V vm, vs2, vd
  2890  	{mask: 0xfc0ff07f, value: 0x4c081057, op: VFCLASS_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2891  	// VFCVT.F.XU.V vm, vs2, vd
  2892  	{mask: 0xfc0ff07f, value: 0x48011057, op: VFCVT_F_XU_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2893  	// VFCVT.F.X.V vm, vs2, vd
  2894  	{mask: 0xfc0ff07f, value: 0x48019057, op: VFCVT_F_X_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2895  	// VFCVT.RTZ.XU.F.V vm, vs2, vd
  2896  	{mask: 0xfc0ff07f, value: 0x48031057, op: VFCVT_RTZ_XU_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2897  	// VFCVT.RTZ.X.F.V vm, vs2, vd
  2898  	{mask: 0xfc0ff07f, value: 0x48039057, op: VFCVT_RTZ_X_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2899  	// VFCVT.XU.F.V vm, vs2, vd
  2900  	{mask: 0xfc0ff07f, value: 0x48001057, op: VFCVT_XU_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2901  	// VFCVT.X.F.V vm, vs2, vd
  2902  	{mask: 0xfc0ff07f, value: 0x48009057, op: VFCVT_X_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2903  	// VFDIV.VF vm, vs2, fs1, vd
  2904  	{mask: 0xfc00707f, value: 0x80005057, op: VFDIV_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2905  	// VFDIV.VV vm, vs2, vs1, vd
  2906  	{mask: 0xfc00707f, value: 0x80001057, op: VFDIV_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2907  	// VFIRST.M vm, vs2, rd
  2908  	{mask: 0xfc0ff07f, value: 0x4008a057, op: VFIRST_M, args: argTypeList{arg_vm, arg_vs2, arg_rd}},
  2909  	// VFMACC.VF vm, vs2, fs1, vd
  2910  	{mask: 0xfc00707f, value: 0xb0005057, op: VFMACC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2911  	// VFMACC.VV vm, vs2, vs1, vd
  2912  	{mask: 0xfc00707f, value: 0xb0001057, op: VFMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2913  	// VFMADD.VF vm, vs2, fs1, vd
  2914  	{mask: 0xfc00707f, value: 0xa0005057, op: VFMADD_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2915  	// VFMADD.VV vm, vs2, vs1, vd
  2916  	{mask: 0xfc00707f, value: 0xa0001057, op: VFMADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2917  	// VFMAX.VF vm, vs2, fs1, vd
  2918  	{mask: 0xfc00707f, value: 0x18005057, op: VFMAX_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2919  	// VFMAX.VV vm, vs2, vs1, vd
  2920  	{mask: 0xfc00707f, value: 0x18001057, op: VFMAX_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2921  	// VFMERGE.VFM vs2, fs1, vd
  2922  	{mask: 0xfe00707f, value: 0x5c005057, op: VFMERGE_VFM, args: argTypeList{arg_vs2, arg_fs1, arg_vd}},
  2923  	// VFMIN.VF vm, vs2, fs1, vd
  2924  	{mask: 0xfc00707f, value: 0x10005057, op: VFMIN_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2925  	// VFMIN.VV vm, vs2, vs1, vd
  2926  	{mask: 0xfc00707f, value: 0x10001057, op: VFMIN_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2927  	// VFMSAC.VF vm, vs2, fs1, vd
  2928  	{mask: 0xfc00707f, value: 0xb8005057, op: VFMSAC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2929  	// VFMSAC.VV vm, vs2, vs1, vd
  2930  	{mask: 0xfc00707f, value: 0xb8001057, op: VFMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2931  	// VFMSUB.VF vm, vs2, fs1, vd
  2932  	{mask: 0xfc00707f, value: 0xa8005057, op: VFMSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2933  	// VFMSUB.VV vm, vs2, vs1, vd
  2934  	{mask: 0xfc00707f, value: 0xa8001057, op: VFMSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2935  	// VFMUL.VF vm, vs2, fs1, vd
  2936  	{mask: 0xfc00707f, value: 0x90005057, op: VFMUL_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2937  	// VFMUL.VV vm, vs2, vs1, vd
  2938  	{mask: 0xfc00707f, value: 0x90001057, op: VFMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2939  	// VFMV.F.S vs2, fd
  2940  	{mask: 0xfe0ff07f, value: 0x42001057, op: VFMV_F_S, args: argTypeList{arg_vs2, arg_fd}},
  2941  	// VFMV.S.F fs1, vd
  2942  	{mask: 0xfff0707f, value: 0x42005057, op: VFMV_S_F, args: argTypeList{arg_fs1, arg_vd}},
  2943  	// VFMV.V.F fs1, vd
  2944  	{mask: 0xfff0707f, value: 0x5e005057, op: VFMV_V_F, args: argTypeList{arg_fs1, arg_vd}},
  2945  	// VFNCVT.F.F.W vm, vs2, vd
  2946  	{mask: 0xfc0ff07f, value: 0x480a1057, op: VFNCVT_F_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2947  	// VFNCVT.F.XU.W vm, vs2, vd
  2948  	{mask: 0xfc0ff07f, value: 0x48091057, op: VFNCVT_F_XU_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2949  	// VFNCVT.F.X.W vm, vs2, vd
  2950  	{mask: 0xfc0ff07f, value: 0x48099057, op: VFNCVT_F_X_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2951  	// VFNCVT.ROD.F.F.W vm, vs2, vd
  2952  	{mask: 0xfc0ff07f, value: 0x480a9057, op: VFNCVT_ROD_F_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2953  	// VFNCVT.RTZ.XU.F.W vm, vs2, vd
  2954  	{mask: 0xfc0ff07f, value: 0x480b1057, op: VFNCVT_RTZ_XU_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2955  	// VFNCVT.RTZ.X.F.W vm, vs2, vd
  2956  	{mask: 0xfc0ff07f, value: 0x480b9057, op: VFNCVT_RTZ_X_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2957  	// VFNCVT.XU.F.W vm, vs2, vd
  2958  	{mask: 0xfc0ff07f, value: 0x48081057, op: VFNCVT_XU_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2959  	// VFNCVT.X.F.W vm, vs2, vd
  2960  	{mask: 0xfc0ff07f, value: 0x48089057, op: VFNCVT_X_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2961  	// VFNMACC.VF vm, vs2, fs1, vd
  2962  	{mask: 0xfc00707f, value: 0xb4005057, op: VFNMACC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2963  	// VFNMACC.VV vm, vs2, vs1, vd
  2964  	{mask: 0xfc00707f, value: 0xb4001057, op: VFNMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2965  	// VFNMADD.VF vm, vs2, fs1, vd
  2966  	{mask: 0xfc00707f, value: 0xa4005057, op: VFNMADD_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2967  	// VFNMADD.VV vm, vs2, vs1, vd
  2968  	{mask: 0xfc00707f, value: 0xa4001057, op: VFNMADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2969  	// VFNMSAC.VF vm, vs2, fs1, vd
  2970  	{mask: 0xfc00707f, value: 0xbc005057, op: VFNMSAC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2971  	// VFNMSAC.VV vm, vs2, vs1, vd
  2972  	{mask: 0xfc00707f, value: 0xbc001057, op: VFNMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2973  	// VFNMSUB.VF vm, vs2, fs1, vd
  2974  	{mask: 0xfc00707f, value: 0xac005057, op: VFNMSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2975  	// VFNMSUB.VV vm, vs2, vs1, vd
  2976  	{mask: 0xfc00707f, value: 0xac001057, op: VFNMSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2977  	// VFRDIV.VF vm, vs2, fs1, vd
  2978  	{mask: 0xfc00707f, value: 0x84005057, op: VFRDIV_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2979  	// VFREC7.V vm, vs2, vd
  2980  	{mask: 0xfc0ff07f, value: 0x4c029057, op: VFREC7_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2981  	// VFREDMAX.VS vm, vs2, vs1, vd
  2982  	{mask: 0xfc00707f, value: 0x1c001057, op: VFREDMAX_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2983  	// VFREDMIN.VS vm, vs2, vs1, vd
  2984  	{mask: 0xfc00707f, value: 0x14001057, op: VFREDMIN_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2985  	// VFREDOSUM.VS vm, vs2, vs1, vd
  2986  	{mask: 0xfc00707f, value: 0x0c001057, op: VFREDOSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2987  	// VFREDUSUM.VS vm, vs2, vs1, vd
  2988  	{mask: 0xfc00707f, value: 0x04001057, op: VFREDUSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2989  	// VFRSQRT7.V vm, vs2, vd
  2990  	{mask: 0xfc0ff07f, value: 0x4c021057, op: VFRSQRT7_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2991  	// VFRSUB.VF vm, vs2, fs1, vd
  2992  	{mask: 0xfc00707f, value: 0x9c005057, op: VFRSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2993  	// VFSGNJN.VF vm, vs2, fs1, vd
  2994  	{mask: 0xfc00707f, value: 0x24005057, op: VFSGNJN_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2995  	// VFSGNJN.VV vm, vs2, vs1, vd
  2996  	{mask: 0xfc00707f, value: 0x24001057, op: VFSGNJN_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2997  	// VFSGNJX.VF vm, vs2, fs1, vd
  2998  	{mask: 0xfc00707f, value: 0x28005057, op: VFSGNJX_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2999  	// VFSGNJX.VV vm, vs2, vs1, vd
  3000  	{mask: 0xfc00707f, value: 0x28001057, op: VFSGNJX_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3001  	// VFSGNJ.VF vm, vs2, fs1, vd
  3002  	{mask: 0xfc00707f, value: 0x20005057, op: VFSGNJ_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3003  	// VFSGNJ.VV vm, vs2, vs1, vd
  3004  	{mask: 0xfc00707f, value: 0x20001057, op: VFSGNJ_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3005  	// VFSLIDE1DOWN.VF vm, vs2, fs1, vd
  3006  	{mask: 0xfc00707f, value: 0x3c005057, op: VFSLIDE1DOWN_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3007  	// VFSLIDE1UP.VF vm, vs2, fs1, vd
  3008  	{mask: 0xfc00707f, value: 0x38005057, op: VFSLIDE1UP_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3009  	// VFSQRT.V vm, vs2, vd
  3010  	{mask: 0xfc0ff07f, value: 0x4c001057, op: VFSQRT_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3011  	// VFSUB.VF vm, vs2, fs1, vd
  3012  	{mask: 0xfc00707f, value: 0x08005057, op: VFSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3013  	// VFSUB.VV vm, vs2, vs1, vd
  3014  	{mask: 0xfc00707f, value: 0x08001057, op: VFSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3015  	// VFWADD.VF vm, vs2, fs1, vd
  3016  	{mask: 0xfc00707f, value: 0xc0005057, op: VFWADD_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3017  	// VFWADD.VV vm, vs2, vs1, vd
  3018  	{mask: 0xfc00707f, value: 0xc0001057, op: VFWADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3019  	// VFWADD.WF vm, vs2, fs1, vd
  3020  	{mask: 0xfc00707f, value: 0xd0005057, op: VFWADD_WF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3021  	// VFWADD.WV vm, vs2, vs1, vd
  3022  	{mask: 0xfc00707f, value: 0xd0001057, op: VFWADD_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3023  	// VFWCVT.F.F.V vm, vs2, vd
  3024  	{mask: 0xfc0ff07f, value: 0x48061057, op: VFWCVT_F_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3025  	// VFWCVT.F.XU.V vm, vs2, vd
  3026  	{mask: 0xfc0ff07f, value: 0x48051057, op: VFWCVT_F_XU_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3027  	// VFWCVT.F.X.V vm, vs2, vd
  3028  	{mask: 0xfc0ff07f, value: 0x48059057, op: VFWCVT_F_X_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3029  	// VFWCVT.RTZ.XU.F.V vm, vs2, vd
  3030  	{mask: 0xfc0ff07f, value: 0x48071057, op: VFWCVT_RTZ_XU_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3031  	// VFWCVT.RTZ.X.F.V vm, vs2, vd
  3032  	{mask: 0xfc0ff07f, value: 0x48079057, op: VFWCVT_RTZ_X_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3033  	// VFWCVT.XU.F.V vm, vs2, vd
  3034  	{mask: 0xfc0ff07f, value: 0x48041057, op: VFWCVT_XU_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3035  	// VFWCVT.X.F.V vm, vs2, vd
  3036  	{mask: 0xfc0ff07f, value: 0x48049057, op: VFWCVT_X_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3037  	// VFWMACC.VF vm, vs2, fs1, vd
  3038  	{mask: 0xfc00707f, value: 0xf0005057, op: VFWMACC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3039  	// VFWMACC.VV vm, vs2, vs1, vd
  3040  	{mask: 0xfc00707f, value: 0xf0001057, op: VFWMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3041  	// VFWMSAC.VF vm, vs2, fs1, vd
  3042  	{mask: 0xfc00707f, value: 0xf8005057, op: VFWMSAC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3043  	// VFWMSAC.VV vm, vs2, vs1, vd
  3044  	{mask: 0xfc00707f, value: 0xf8001057, op: VFWMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3045  	// VFWMUL.VF vm, vs2, fs1, vd
  3046  	{mask: 0xfc00707f, value: 0xe0005057, op: VFWMUL_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3047  	// VFWMUL.VV vm, vs2, vs1, vd
  3048  	{mask: 0xfc00707f, value: 0xe0001057, op: VFWMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3049  	// VFWNMACC.VF vm, vs2, fs1, vd
  3050  	{mask: 0xfc00707f, value: 0xf4005057, op: VFWNMACC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3051  	// VFWNMACC.VV vm, vs2, vs1, vd
  3052  	{mask: 0xfc00707f, value: 0xf4001057, op: VFWNMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3053  	// VFWNMSAC.VF vm, vs2, fs1, vd
  3054  	{mask: 0xfc00707f, value: 0xfc005057, op: VFWNMSAC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3055  	// VFWNMSAC.VV vm, vs2, vs1, vd
  3056  	{mask: 0xfc00707f, value: 0xfc001057, op: VFWNMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3057  	// VFWREDOSUM.VS vm, vs2, vs1, vd
  3058  	{mask: 0xfc00707f, value: 0xcc001057, op: VFWREDOSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3059  	// VFWREDUSUM.VS vm, vs2, vs1, vd
  3060  	{mask: 0xfc00707f, value: 0xc4001057, op: VFWREDUSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3061  	// VFWSUB.VF vm, vs2, fs1, vd
  3062  	{mask: 0xfc00707f, value: 0xc8005057, op: VFWSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3063  	// VFWSUB.VV vm, vs2, vs1, vd
  3064  	{mask: 0xfc00707f, value: 0xc8001057, op: VFWSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3065  	// VFWSUB.WF vm, vs2, fs1, vd
  3066  	{mask: 0xfc00707f, value: 0xd8005057, op: VFWSUB_WF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3067  	// VFWSUB.WV vm, vs2, vs1, vd
  3068  	{mask: 0xfc00707f, value: 0xd8001057, op: VFWSUB_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3069  	// VID.V vm, vd
  3070  	{mask: 0xfdfff07f, value: 0x5008a057, op: VID_V, args: argTypeList{arg_vm, arg_vd}},
  3071  	// VIOTA.M vm, vs2, vd
  3072  	{mask: 0xfc0ff07f, value: 0x50082057, op: VIOTA_M, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3073  	// VL1RE16.V rs1_ptr, vd
  3074  	{mask: 0xfff0707f, value: 0x02805007, op: VL1RE16_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3075  	// VL1RE32.V rs1_ptr, vd
  3076  	{mask: 0xfff0707f, value: 0x02806007, op: VL1RE32_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3077  	// VL1RE64.V rs1_ptr, vd
  3078  	{mask: 0xfff0707f, value: 0x02807007, op: VL1RE64_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3079  	// VL1RE8.V rs1_ptr, vd
  3080  	{mask: 0xfff0707f, value: 0x02800007, op: VL1RE8_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3081  	// VL2RE16.V rs1_ptr, vd
  3082  	{mask: 0xfff0707f, value: 0x22805007, op: VL2RE16_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3083  	// VL2RE32.V rs1_ptr, vd
  3084  	{mask: 0xfff0707f, value: 0x22806007, op: VL2RE32_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3085  	// VL2RE64.V rs1_ptr, vd
  3086  	{mask: 0xfff0707f, value: 0x22807007, op: VL2RE64_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3087  	// VL2RE8.V rs1_ptr, vd
  3088  	{mask: 0xfff0707f, value: 0x22800007, op: VL2RE8_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3089  	// VL4RE16.V rs1_ptr, vd
  3090  	{mask: 0xfff0707f, value: 0x62805007, op: VL4RE16_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3091  	// VL4RE32.V rs1_ptr, vd
  3092  	{mask: 0xfff0707f, value: 0x62806007, op: VL4RE32_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3093  	// VL4RE64.V rs1_ptr, vd
  3094  	{mask: 0xfff0707f, value: 0x62807007, op: VL4RE64_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3095  	// VL4RE8.V rs1_ptr, vd
  3096  	{mask: 0xfff0707f, value: 0x62800007, op: VL4RE8_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3097  	// VL8RE16.V rs1_ptr, vd
  3098  	{mask: 0xfff0707f, value: 0xe2805007, op: VL8RE16_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3099  	// VL8RE32.V rs1_ptr, vd
  3100  	{mask: 0xfff0707f, value: 0xe2806007, op: VL8RE32_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3101  	// VL8RE64.V rs1_ptr, vd
  3102  	{mask: 0xfff0707f, value: 0xe2807007, op: VL8RE64_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3103  	// VL8RE8.V rs1_ptr, vd
  3104  	{mask: 0xfff0707f, value: 0xe2800007, op: VL8RE8_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3105  	// VLE16FF.V vm, rs1_ptr, vd
  3106  	{mask: 0xfdf0707f, value: 0x01005007, op: VLE16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3107  	// VLE16.V vm, rs1_ptr, vd
  3108  	{mask: 0xfdf0707f, value: 0x00005007, op: VLE16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3109  	// VLE32FF.V vm, rs1_ptr, vd
  3110  	{mask: 0xfdf0707f, value: 0x01006007, op: VLE32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3111  	// VLE32.V vm, rs1_ptr, vd
  3112  	{mask: 0xfdf0707f, value: 0x00006007, op: VLE32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3113  	// VLE64FF.V vm, rs1_ptr, vd
  3114  	{mask: 0xfdf0707f, value: 0x01007007, op: VLE64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3115  	// VLE64.V vm, rs1_ptr, vd
  3116  	{mask: 0xfdf0707f, value: 0x00007007, op: VLE64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3117  	// VLE8FF.V vm, rs1_ptr, vd
  3118  	{mask: 0xfdf0707f, value: 0x01000007, op: VLE8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3119  	// VLE8.V vm, rs1_ptr, vd
  3120  	{mask: 0xfdf0707f, value: 0x00000007, op: VLE8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3121  	// VLM.V rs1_ptr, vd
  3122  	{mask: 0xfff0707f, value: 0x02b00007, op: VLM_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3123  	// VLOXEI16.V vm, vs2, rs1_ptr, vd
  3124  	{mask: 0xfc00707f, value: 0x0c005007, op: VLOXEI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3125  	// VLOXEI32.V vm, vs2, rs1_ptr, vd
  3126  	{mask: 0xfc00707f, value: 0x0c006007, op: VLOXEI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3127  	// VLOXEI64.V vm, vs2, rs1_ptr, vd
  3128  	{mask: 0xfc00707f, value: 0x0c007007, op: VLOXEI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3129  	// VLOXEI8.V vm, vs2, rs1_ptr, vd
  3130  	{mask: 0xfc00707f, value: 0x0c000007, op: VLOXEI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3131  	// VLOXSEG2EI16.V vm, vs2, rs1_ptr, vd
  3132  	{mask: 0xfc00707f, value: 0x2c005007, op: VLOXSEG2EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3133  	// VLOXSEG2EI32.V vm, vs2, rs1_ptr, vd
  3134  	{mask: 0xfc00707f, value: 0x2c006007, op: VLOXSEG2EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3135  	// VLOXSEG2EI64.V vm, vs2, rs1_ptr, vd
  3136  	{mask: 0xfc00707f, value: 0x2c007007, op: VLOXSEG2EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3137  	// VLOXSEG2EI8.V vm, vs2, rs1_ptr, vd
  3138  	{mask: 0xfc00707f, value: 0x2c000007, op: VLOXSEG2EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3139  	// VLOXSEG3EI16.V vm, vs2, rs1_ptr, vd
  3140  	{mask: 0xfc00707f, value: 0x4c005007, op: VLOXSEG3EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3141  	// VLOXSEG3EI32.V vm, vs2, rs1_ptr, vd
  3142  	{mask: 0xfc00707f, value: 0x4c006007, op: VLOXSEG3EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3143  	// VLOXSEG3EI64.V vm, vs2, rs1_ptr, vd
  3144  	{mask: 0xfc00707f, value: 0x4c007007, op: VLOXSEG3EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3145  	// VLOXSEG3EI8.V vm, vs2, rs1_ptr, vd
  3146  	{mask: 0xfc00707f, value: 0x4c000007, op: VLOXSEG3EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3147  	// VLOXSEG4EI16.V vm, vs2, rs1_ptr, vd
  3148  	{mask: 0xfc00707f, value: 0x6c005007, op: VLOXSEG4EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3149  	// VLOXSEG4EI32.V vm, vs2, rs1_ptr, vd
  3150  	{mask: 0xfc00707f, value: 0x6c006007, op: VLOXSEG4EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3151  	// VLOXSEG4EI64.V vm, vs2, rs1_ptr, vd
  3152  	{mask: 0xfc00707f, value: 0x6c007007, op: VLOXSEG4EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3153  	// VLOXSEG4EI8.V vm, vs2, rs1_ptr, vd
  3154  	{mask: 0xfc00707f, value: 0x6c000007, op: VLOXSEG4EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3155  	// VLOXSEG5EI16.V vm, vs2, rs1_ptr, vd
  3156  	{mask: 0xfc00707f, value: 0x8c005007, op: VLOXSEG5EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3157  	// VLOXSEG5EI32.V vm, vs2, rs1_ptr, vd
  3158  	{mask: 0xfc00707f, value: 0x8c006007, op: VLOXSEG5EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3159  	// VLOXSEG5EI64.V vm, vs2, rs1_ptr, vd
  3160  	{mask: 0xfc00707f, value: 0x8c007007, op: VLOXSEG5EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3161  	// VLOXSEG5EI8.V vm, vs2, rs1_ptr, vd
  3162  	{mask: 0xfc00707f, value: 0x8c000007, op: VLOXSEG5EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3163  	// VLOXSEG6EI16.V vm, vs2, rs1_ptr, vd
  3164  	{mask: 0xfc00707f, value: 0xac005007, op: VLOXSEG6EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3165  	// VLOXSEG6EI32.V vm, vs2, rs1_ptr, vd
  3166  	{mask: 0xfc00707f, value: 0xac006007, op: VLOXSEG6EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3167  	// VLOXSEG6EI64.V vm, vs2, rs1_ptr, vd
  3168  	{mask: 0xfc00707f, value: 0xac007007, op: VLOXSEG6EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3169  	// VLOXSEG6EI8.V vm, vs2, rs1_ptr, vd
  3170  	{mask: 0xfc00707f, value: 0xac000007, op: VLOXSEG6EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3171  	// VLOXSEG7EI16.V vm, vs2, rs1_ptr, vd
  3172  	{mask: 0xfc00707f, value: 0xcc005007, op: VLOXSEG7EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3173  	// VLOXSEG7EI32.V vm, vs2, rs1_ptr, vd
  3174  	{mask: 0xfc00707f, value: 0xcc006007, op: VLOXSEG7EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3175  	// VLOXSEG7EI64.V vm, vs2, rs1_ptr, vd
  3176  	{mask: 0xfc00707f, value: 0xcc007007, op: VLOXSEG7EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3177  	// VLOXSEG7EI8.V vm, vs2, rs1_ptr, vd
  3178  	{mask: 0xfc00707f, value: 0xcc000007, op: VLOXSEG7EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3179  	// VLOXSEG8EI16.V vm, vs2, rs1_ptr, vd
  3180  	{mask: 0xfc00707f, value: 0xec005007, op: VLOXSEG8EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3181  	// VLOXSEG8EI32.V vm, vs2, rs1_ptr, vd
  3182  	{mask: 0xfc00707f, value: 0xec006007, op: VLOXSEG8EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3183  	// VLOXSEG8EI64.V vm, vs2, rs1_ptr, vd
  3184  	{mask: 0xfc00707f, value: 0xec007007, op: VLOXSEG8EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3185  	// VLOXSEG8EI8.V vm, vs2, rs1_ptr, vd
  3186  	{mask: 0xfc00707f, value: 0xec000007, op: VLOXSEG8EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3187  	// VLSE16.V vm, rs2, rs1_ptr, vd
  3188  	{mask: 0xfc00707f, value: 0x08005007, op: VLSE16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3189  	// VLSE32.V vm, rs2, rs1_ptr, vd
  3190  	{mask: 0xfc00707f, value: 0x08006007, op: VLSE32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3191  	// VLSE64.V vm, rs2, rs1_ptr, vd
  3192  	{mask: 0xfc00707f, value: 0x08007007, op: VLSE64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3193  	// VLSE8.V vm, rs2, rs1_ptr, vd
  3194  	{mask: 0xfc00707f, value: 0x08000007, op: VLSE8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3195  	// VLSEG2E16FF.V vm, rs1_ptr, vd
  3196  	{mask: 0xfdf0707f, value: 0x21005007, op: VLSEG2E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3197  	// VLSEG2E16.V vm, rs1_ptr, vd
  3198  	{mask: 0xfdf0707f, value: 0x20005007, op: VLSEG2E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3199  	// VLSEG2E32FF.V vm, rs1_ptr, vd
  3200  	{mask: 0xfdf0707f, value: 0x21006007, op: VLSEG2E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3201  	// VLSEG2E32.V vm, rs1_ptr, vd
  3202  	{mask: 0xfdf0707f, value: 0x20006007, op: VLSEG2E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3203  	// VLSEG2E64FF.V vm, rs1_ptr, vd
  3204  	{mask: 0xfdf0707f, value: 0x21007007, op: VLSEG2E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3205  	// VLSEG2E64.V vm, rs1_ptr, vd
  3206  	{mask: 0xfdf0707f, value: 0x20007007, op: VLSEG2E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3207  	// VLSEG2E8FF.V vm, rs1_ptr, vd
  3208  	{mask: 0xfdf0707f, value: 0x21000007, op: VLSEG2E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3209  	// VLSEG2E8.V vm, rs1_ptr, vd
  3210  	{mask: 0xfdf0707f, value: 0x20000007, op: VLSEG2E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3211  	// VLSEG3E16FF.V vm, rs1_ptr, vd
  3212  	{mask: 0xfdf0707f, value: 0x41005007, op: VLSEG3E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3213  	// VLSEG3E16.V vm, rs1_ptr, vd
  3214  	{mask: 0xfdf0707f, value: 0x40005007, op: VLSEG3E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3215  	// VLSEG3E32FF.V vm, rs1_ptr, vd
  3216  	{mask: 0xfdf0707f, value: 0x41006007, op: VLSEG3E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3217  	// VLSEG3E32.V vm, rs1_ptr, vd
  3218  	{mask: 0xfdf0707f, value: 0x40006007, op: VLSEG3E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3219  	// VLSEG3E64FF.V vm, rs1_ptr, vd
  3220  	{mask: 0xfdf0707f, value: 0x41007007, op: VLSEG3E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3221  	// VLSEG3E64.V vm, rs1_ptr, vd
  3222  	{mask: 0xfdf0707f, value: 0x40007007, op: VLSEG3E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3223  	// VLSEG3E8FF.V vm, rs1_ptr, vd
  3224  	{mask: 0xfdf0707f, value: 0x41000007, op: VLSEG3E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3225  	// VLSEG3E8.V vm, rs1_ptr, vd
  3226  	{mask: 0xfdf0707f, value: 0x40000007, op: VLSEG3E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3227  	// VLSEG4E16FF.V vm, rs1_ptr, vd
  3228  	{mask: 0xfdf0707f, value: 0x61005007, op: VLSEG4E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3229  	// VLSEG4E16.V vm, rs1_ptr, vd
  3230  	{mask: 0xfdf0707f, value: 0x60005007, op: VLSEG4E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3231  	// VLSEG4E32FF.V vm, rs1_ptr, vd
  3232  	{mask: 0xfdf0707f, value: 0x61006007, op: VLSEG4E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3233  	// VLSEG4E32.V vm, rs1_ptr, vd
  3234  	{mask: 0xfdf0707f, value: 0x60006007, op: VLSEG4E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3235  	// VLSEG4E64FF.V vm, rs1_ptr, vd
  3236  	{mask: 0xfdf0707f, value: 0x61007007, op: VLSEG4E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3237  	// VLSEG4E64.V vm, rs1_ptr, vd
  3238  	{mask: 0xfdf0707f, value: 0x60007007, op: VLSEG4E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3239  	// VLSEG4E8FF.V vm, rs1_ptr, vd
  3240  	{mask: 0xfdf0707f, value: 0x61000007, op: VLSEG4E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3241  	// VLSEG4E8.V vm, rs1_ptr, vd
  3242  	{mask: 0xfdf0707f, value: 0x60000007, op: VLSEG4E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3243  	// VLSEG5E16FF.V vm, rs1_ptr, vd
  3244  	{mask: 0xfdf0707f, value: 0x81005007, op: VLSEG5E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3245  	// VLSEG5E16.V vm, rs1_ptr, vd
  3246  	{mask: 0xfdf0707f, value: 0x80005007, op: VLSEG5E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3247  	// VLSEG5E32FF.V vm, rs1_ptr, vd
  3248  	{mask: 0xfdf0707f, value: 0x81006007, op: VLSEG5E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3249  	// VLSEG5E32.V vm, rs1_ptr, vd
  3250  	{mask: 0xfdf0707f, value: 0x80006007, op: VLSEG5E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3251  	// VLSEG5E64FF.V vm, rs1_ptr, vd
  3252  	{mask: 0xfdf0707f, value: 0x81007007, op: VLSEG5E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3253  	// VLSEG5E64.V vm, rs1_ptr, vd
  3254  	{mask: 0xfdf0707f, value: 0x80007007, op: VLSEG5E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3255  	// VLSEG5E8FF.V vm, rs1_ptr, vd
  3256  	{mask: 0xfdf0707f, value: 0x81000007, op: VLSEG5E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3257  	// VLSEG5E8.V vm, rs1_ptr, vd
  3258  	{mask: 0xfdf0707f, value: 0x80000007, op: VLSEG5E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3259  	// VLSEG6E16FF.V vm, rs1_ptr, vd
  3260  	{mask: 0xfdf0707f, value: 0xa1005007, op: VLSEG6E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3261  	// VLSEG6E16.V vm, rs1_ptr, vd
  3262  	{mask: 0xfdf0707f, value: 0xa0005007, op: VLSEG6E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3263  	// VLSEG6E32FF.V vm, rs1_ptr, vd
  3264  	{mask: 0xfdf0707f, value: 0xa1006007, op: VLSEG6E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3265  	// VLSEG6E32.V vm, rs1_ptr, vd
  3266  	{mask: 0xfdf0707f, value: 0xa0006007, op: VLSEG6E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3267  	// VLSEG6E64FF.V vm, rs1_ptr, vd
  3268  	{mask: 0xfdf0707f, value: 0xa1007007, op: VLSEG6E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3269  	// VLSEG6E64.V vm, rs1_ptr, vd
  3270  	{mask: 0xfdf0707f, value: 0xa0007007, op: VLSEG6E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3271  	// VLSEG6E8FF.V vm, rs1_ptr, vd
  3272  	{mask: 0xfdf0707f, value: 0xa1000007, op: VLSEG6E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3273  	// VLSEG6E8.V vm, rs1_ptr, vd
  3274  	{mask: 0xfdf0707f, value: 0xa0000007, op: VLSEG6E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3275  	// VLSEG7E16FF.V vm, rs1_ptr, vd
  3276  	{mask: 0xfdf0707f, value: 0xc1005007, op: VLSEG7E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3277  	// VLSEG7E16.V vm, rs1_ptr, vd
  3278  	{mask: 0xfdf0707f, value: 0xc0005007, op: VLSEG7E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3279  	// VLSEG7E32FF.V vm, rs1_ptr, vd
  3280  	{mask: 0xfdf0707f, value: 0xc1006007, op: VLSEG7E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3281  	// VLSEG7E32.V vm, rs1_ptr, vd
  3282  	{mask: 0xfdf0707f, value: 0xc0006007, op: VLSEG7E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3283  	// VLSEG7E64FF.V vm, rs1_ptr, vd
  3284  	{mask: 0xfdf0707f, value: 0xc1007007, op: VLSEG7E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3285  	// VLSEG7E64.V vm, rs1_ptr, vd
  3286  	{mask: 0xfdf0707f, value: 0xc0007007, op: VLSEG7E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3287  	// VLSEG7E8FF.V vm, rs1_ptr, vd
  3288  	{mask: 0xfdf0707f, value: 0xc1000007, op: VLSEG7E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3289  	// VLSEG7E8.V vm, rs1_ptr, vd
  3290  	{mask: 0xfdf0707f, value: 0xc0000007, op: VLSEG7E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3291  	// VLSEG8E16FF.V vm, rs1_ptr, vd
  3292  	{mask: 0xfdf0707f, value: 0xe1005007, op: VLSEG8E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3293  	// VLSEG8E16.V vm, rs1_ptr, vd
  3294  	{mask: 0xfdf0707f, value: 0xe0005007, op: VLSEG8E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3295  	// VLSEG8E32FF.V vm, rs1_ptr, vd
  3296  	{mask: 0xfdf0707f, value: 0xe1006007, op: VLSEG8E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3297  	// VLSEG8E32.V vm, rs1_ptr, vd
  3298  	{mask: 0xfdf0707f, value: 0xe0006007, op: VLSEG8E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3299  	// VLSEG8E64FF.V vm, rs1_ptr, vd
  3300  	{mask: 0xfdf0707f, value: 0xe1007007, op: VLSEG8E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3301  	// VLSEG8E64.V vm, rs1_ptr, vd
  3302  	{mask: 0xfdf0707f, value: 0xe0007007, op: VLSEG8E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3303  	// VLSEG8E8FF.V vm, rs1_ptr, vd
  3304  	{mask: 0xfdf0707f, value: 0xe1000007, op: VLSEG8E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3305  	// VLSEG8E8.V vm, rs1_ptr, vd
  3306  	{mask: 0xfdf0707f, value: 0xe0000007, op: VLSEG8E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3307  	// VLSSEG2E16.V vm, rs2, rs1_ptr, vd
  3308  	{mask: 0xfc00707f, value: 0x28005007, op: VLSSEG2E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3309  	// VLSSEG2E32.V vm, rs2, rs1_ptr, vd
  3310  	{mask: 0xfc00707f, value: 0x28006007, op: VLSSEG2E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3311  	// VLSSEG2E64.V vm, rs2, rs1_ptr, vd
  3312  	{mask: 0xfc00707f, value: 0x28007007, op: VLSSEG2E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3313  	// VLSSEG2E8.V vm, rs2, rs1_ptr, vd
  3314  	{mask: 0xfc00707f, value: 0x28000007, op: VLSSEG2E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3315  	// VLSSEG3E16.V vm, rs2, rs1_ptr, vd
  3316  	{mask: 0xfc00707f, value: 0x48005007, op: VLSSEG3E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3317  	// VLSSEG3E32.V vm, rs2, rs1_ptr, vd
  3318  	{mask: 0xfc00707f, value: 0x48006007, op: VLSSEG3E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3319  	// VLSSEG3E64.V vm, rs2, rs1_ptr, vd
  3320  	{mask: 0xfc00707f, value: 0x48007007, op: VLSSEG3E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3321  	// VLSSEG3E8.V vm, rs2, rs1_ptr, vd
  3322  	{mask: 0xfc00707f, value: 0x48000007, op: VLSSEG3E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3323  	// VLSSEG4E16.V vm, rs2, rs1_ptr, vd
  3324  	{mask: 0xfc00707f, value: 0x68005007, op: VLSSEG4E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3325  	// VLSSEG4E32.V vm, rs2, rs1_ptr, vd
  3326  	{mask: 0xfc00707f, value: 0x68006007, op: VLSSEG4E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3327  	// VLSSEG4E64.V vm, rs2, rs1_ptr, vd
  3328  	{mask: 0xfc00707f, value: 0x68007007, op: VLSSEG4E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3329  	// VLSSEG4E8.V vm, rs2, rs1_ptr, vd
  3330  	{mask: 0xfc00707f, value: 0x68000007, op: VLSSEG4E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3331  	// VLSSEG5E16.V vm, rs2, rs1_ptr, vd
  3332  	{mask: 0xfc00707f, value: 0x88005007, op: VLSSEG5E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3333  	// VLSSEG5E32.V vm, rs2, rs1_ptr, vd
  3334  	{mask: 0xfc00707f, value: 0x88006007, op: VLSSEG5E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3335  	// VLSSEG5E64.V vm, rs2, rs1_ptr, vd
  3336  	{mask: 0xfc00707f, value: 0x88007007, op: VLSSEG5E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3337  	// VLSSEG5E8.V vm, rs2, rs1_ptr, vd
  3338  	{mask: 0xfc00707f, value: 0x88000007, op: VLSSEG5E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3339  	// VLSSEG6E16.V vm, rs2, rs1_ptr, vd
  3340  	{mask: 0xfc00707f, value: 0xa8005007, op: VLSSEG6E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3341  	// VLSSEG6E32.V vm, rs2, rs1_ptr, vd
  3342  	{mask: 0xfc00707f, value: 0xa8006007, op: VLSSEG6E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3343  	// VLSSEG6E64.V vm, rs2, rs1_ptr, vd
  3344  	{mask: 0xfc00707f, value: 0xa8007007, op: VLSSEG6E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3345  	// VLSSEG6E8.V vm, rs2, rs1_ptr, vd
  3346  	{mask: 0xfc00707f, value: 0xa8000007, op: VLSSEG6E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3347  	// VLSSEG7E16.V vm, rs2, rs1_ptr, vd
  3348  	{mask: 0xfc00707f, value: 0xc8005007, op: VLSSEG7E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3349  	// VLSSEG7E32.V vm, rs2, rs1_ptr, vd
  3350  	{mask: 0xfc00707f, value: 0xc8006007, op: VLSSEG7E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3351  	// VLSSEG7E64.V vm, rs2, rs1_ptr, vd
  3352  	{mask: 0xfc00707f, value: 0xc8007007, op: VLSSEG7E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3353  	// VLSSEG7E8.V vm, rs2, rs1_ptr, vd
  3354  	{mask: 0xfc00707f, value: 0xc8000007, op: VLSSEG7E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3355  	// VLSSEG8E16.V vm, rs2, rs1_ptr, vd
  3356  	{mask: 0xfc00707f, value: 0xe8005007, op: VLSSEG8E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3357  	// VLSSEG8E32.V vm, rs2, rs1_ptr, vd
  3358  	{mask: 0xfc00707f, value: 0xe8006007, op: VLSSEG8E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3359  	// VLSSEG8E64.V vm, rs2, rs1_ptr, vd
  3360  	{mask: 0xfc00707f, value: 0xe8007007, op: VLSSEG8E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3361  	// VLSSEG8E8.V vm, rs2, rs1_ptr, vd
  3362  	{mask: 0xfc00707f, value: 0xe8000007, op: VLSSEG8E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3363  	// VLUXEI16.V vm, vs2, rs1_ptr, vd
  3364  	{mask: 0xfc00707f, value: 0x04005007, op: VLUXEI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3365  	// VLUXEI32.V vm, vs2, rs1_ptr, vd
  3366  	{mask: 0xfc00707f, value: 0x04006007, op: VLUXEI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3367  	// VLUXEI64.V vm, vs2, rs1_ptr, vd
  3368  	{mask: 0xfc00707f, value: 0x04007007, op: VLUXEI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3369  	// VLUXEI8.V vm, vs2, rs1_ptr, vd
  3370  	{mask: 0xfc00707f, value: 0x04000007, op: VLUXEI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3371  	// VLUXSEG2EI16.V vm, vs2, rs1_ptr, vd
  3372  	{mask: 0xfc00707f, value: 0x24005007, op: VLUXSEG2EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3373  	// VLUXSEG2EI32.V vm, vs2, rs1_ptr, vd
  3374  	{mask: 0xfc00707f, value: 0x24006007, op: VLUXSEG2EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3375  	// VLUXSEG2EI64.V vm, vs2, rs1_ptr, vd
  3376  	{mask: 0xfc00707f, value: 0x24007007, op: VLUXSEG2EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3377  	// VLUXSEG2EI8.V vm, vs2, rs1_ptr, vd
  3378  	{mask: 0xfc00707f, value: 0x24000007, op: VLUXSEG2EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3379  	// VLUXSEG3EI16.V vm, vs2, rs1_ptr, vd
  3380  	{mask: 0xfc00707f, value: 0x44005007, op: VLUXSEG3EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3381  	// VLUXSEG3EI32.V vm, vs2, rs1_ptr, vd
  3382  	{mask: 0xfc00707f, value: 0x44006007, op: VLUXSEG3EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3383  	// VLUXSEG3EI64.V vm, vs2, rs1_ptr, vd
  3384  	{mask: 0xfc00707f, value: 0x44007007, op: VLUXSEG3EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3385  	// VLUXSEG3EI8.V vm, vs2, rs1_ptr, vd
  3386  	{mask: 0xfc00707f, value: 0x44000007, op: VLUXSEG3EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3387  	// VLUXSEG4EI16.V vm, vs2, rs1_ptr, vd
  3388  	{mask: 0xfc00707f, value: 0x64005007, op: VLUXSEG4EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3389  	// VLUXSEG4EI32.V vm, vs2, rs1_ptr, vd
  3390  	{mask: 0xfc00707f, value: 0x64006007, op: VLUXSEG4EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3391  	// VLUXSEG4EI64.V vm, vs2, rs1_ptr, vd
  3392  	{mask: 0xfc00707f, value: 0x64007007, op: VLUXSEG4EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3393  	// VLUXSEG4EI8.V vm, vs2, rs1_ptr, vd
  3394  	{mask: 0xfc00707f, value: 0x64000007, op: VLUXSEG4EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3395  	// VLUXSEG5EI16.V vm, vs2, rs1_ptr, vd
  3396  	{mask: 0xfc00707f, value: 0x84005007, op: VLUXSEG5EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3397  	// VLUXSEG5EI32.V vm, vs2, rs1_ptr, vd
  3398  	{mask: 0xfc00707f, value: 0x84006007, op: VLUXSEG5EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3399  	// VLUXSEG5EI64.V vm, vs2, rs1_ptr, vd
  3400  	{mask: 0xfc00707f, value: 0x84007007, op: VLUXSEG5EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3401  	// VLUXSEG5EI8.V vm, vs2, rs1_ptr, vd
  3402  	{mask: 0xfc00707f, value: 0x84000007, op: VLUXSEG5EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3403  	// VLUXSEG6EI16.V vm, vs2, rs1_ptr, vd
  3404  	{mask: 0xfc00707f, value: 0xa4005007, op: VLUXSEG6EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3405  	// VLUXSEG6EI32.V vm, vs2, rs1_ptr, vd
  3406  	{mask: 0xfc00707f, value: 0xa4006007, op: VLUXSEG6EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3407  	// VLUXSEG6EI64.V vm, vs2, rs1_ptr, vd
  3408  	{mask: 0xfc00707f, value: 0xa4007007, op: VLUXSEG6EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3409  	// VLUXSEG6EI8.V vm, vs2, rs1_ptr, vd
  3410  	{mask: 0xfc00707f, value: 0xa4000007, op: VLUXSEG6EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3411  	// VLUXSEG7EI16.V vm, vs2, rs1_ptr, vd
  3412  	{mask: 0xfc00707f, value: 0xc4005007, op: VLUXSEG7EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3413  	// VLUXSEG7EI32.V vm, vs2, rs1_ptr, vd
  3414  	{mask: 0xfc00707f, value: 0xc4006007, op: VLUXSEG7EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3415  	// VLUXSEG7EI64.V vm, vs2, rs1_ptr, vd
  3416  	{mask: 0xfc00707f, value: 0xc4007007, op: VLUXSEG7EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3417  	// VLUXSEG7EI8.V vm, vs2, rs1_ptr, vd
  3418  	{mask: 0xfc00707f, value: 0xc4000007, op: VLUXSEG7EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3419  	// VLUXSEG8EI16.V vm, vs2, rs1_ptr, vd
  3420  	{mask: 0xfc00707f, value: 0xe4005007, op: VLUXSEG8EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3421  	// VLUXSEG8EI32.V vm, vs2, rs1_ptr, vd
  3422  	{mask: 0xfc00707f, value: 0xe4006007, op: VLUXSEG8EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3423  	// VLUXSEG8EI64.V vm, vs2, rs1_ptr, vd
  3424  	{mask: 0xfc00707f, value: 0xe4007007, op: VLUXSEG8EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3425  	// VLUXSEG8EI8.V vm, vs2, rs1_ptr, vd
  3426  	{mask: 0xfc00707f, value: 0xe4000007, op: VLUXSEG8EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3427  	// VMACC.VV vm, vs2, vs1, vd
  3428  	{mask: 0xfc00707f, value: 0xb4002057, op: VMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3429  	// VMACC.VX vm, vs2, rs1, vd
  3430  	{mask: 0xfc00707f, value: 0xb4006057, op: VMACC_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3431  	// VMADC.VI vs2, simm5, vd
  3432  	{mask: 0xfe00707f, value: 0x46003057, op: VMADC_VI, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
  3433  	// VMADC.VIM vs2, simm5, vd
  3434  	{mask: 0xfe00707f, value: 0x44003057, op: VMADC_VIM, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
  3435  	// VMADC.VV vs2, vs1, vd
  3436  	{mask: 0xfe00707f, value: 0x46000057, op: VMADC_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3437  	// VMADC.VVM vs2, vs1, vd
  3438  	{mask: 0xfe00707f, value: 0x44000057, op: VMADC_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3439  	// VMADC.VX vs2, rs1, vd
  3440  	{mask: 0xfe00707f, value: 0x46004057, op: VMADC_VX, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3441  	// VMADC.VXM vs2, rs1, vd
  3442  	{mask: 0xfe00707f, value: 0x44004057, op: VMADC_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3443  	// VMADD.VV vm, vs2, vs1, vd
  3444  	{mask: 0xfc00707f, value: 0xa4002057, op: VMADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3445  	// VMADD.VX vm, vs2, rs1, vd
  3446  	{mask: 0xfc00707f, value: 0xa4006057, op: VMADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3447  	// VMANDN.MM vs2, vs1, vd
  3448  	{mask: 0xfe00707f, value: 0x62002057, op: VMANDN_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3449  	// VMAND.MM vs2, vs1, vd
  3450  	{mask: 0xfe00707f, value: 0x66002057, op: VMAND_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3451  	// VMAXU.VV vm, vs2, vs1, vd
  3452  	{mask: 0xfc00707f, value: 0x18000057, op: VMAXU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3453  	// VMAXU.VX vm, vs2, rs1, vd
  3454  	{mask: 0xfc00707f, value: 0x18004057, op: VMAXU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3455  	// VMAX.VV vm, vs2, vs1, vd
  3456  	{mask: 0xfc00707f, value: 0x1c000057, op: VMAX_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3457  	// VMAX.VX vm, vs2, rs1, vd
  3458  	{mask: 0xfc00707f, value: 0x1c004057, op: VMAX_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3459  	// VMERGE.VIM vs2, simm5, vd
  3460  	{mask: 0xfe00707f, value: 0x5c003057, op: VMERGE_VIM, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
  3461  	// VMERGE.VVM vs2, vs1, vd
  3462  	{mask: 0xfe00707f, value: 0x5c000057, op: VMERGE_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3463  	// VMERGE.VXM vs2, rs1, vd
  3464  	{mask: 0xfe00707f, value: 0x5c004057, op: VMERGE_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3465  	// VMFEQ.VF vm, vs2, fs1, vd
  3466  	{mask: 0xfc00707f, value: 0x60005057, op: VMFEQ_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3467  	// VMFEQ.VV vm, vs2, vs1, vd
  3468  	{mask: 0xfc00707f, value: 0x60001057, op: VMFEQ_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3469  	// VMFGE.VF vm, vs2, fs1, vd
  3470  	{mask: 0xfc00707f, value: 0x7c005057, op: VMFGE_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3471  	// VMFGT.VF vm, vs2, fs1, vd
  3472  	{mask: 0xfc00707f, value: 0x74005057, op: VMFGT_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3473  	// VMFLE.VF vm, vs2, fs1, vd
  3474  	{mask: 0xfc00707f, value: 0x64005057, op: VMFLE_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3475  	// VMFLE.VV vm, vs2, vs1, vd
  3476  	{mask: 0xfc00707f, value: 0x64001057, op: VMFLE_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3477  	// VMFLT.VF vm, vs2, fs1, vd
  3478  	{mask: 0xfc00707f, value: 0x6c005057, op: VMFLT_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3479  	// VMFLT.VV vm, vs2, vs1, vd
  3480  	{mask: 0xfc00707f, value: 0x6c001057, op: VMFLT_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3481  	// VMFNE.VF vm, vs2, fs1, vd
  3482  	{mask: 0xfc00707f, value: 0x70005057, op: VMFNE_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3483  	// VMFNE.VV vm, vs2, vs1, vd
  3484  	{mask: 0xfc00707f, value: 0x70001057, op: VMFNE_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3485  	// VMINU.VV vm, vs2, vs1, vd
  3486  	{mask: 0xfc00707f, value: 0x10000057, op: VMINU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3487  	// VMINU.VX vm, vs2, rs1, vd
  3488  	{mask: 0xfc00707f, value: 0x10004057, op: VMINU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3489  	// VMIN.VV vm, vs2, vs1, vd
  3490  	{mask: 0xfc00707f, value: 0x14000057, op: VMIN_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3491  	// VMIN.VX vm, vs2, rs1, vd
  3492  	{mask: 0xfc00707f, value: 0x14004057, op: VMIN_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3493  	// VMNAND.MM vs2, vs1, vd
  3494  	{mask: 0xfe00707f, value: 0x76002057, op: VMNAND_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3495  	// VMNOR.MM vs2, vs1, vd
  3496  	{mask: 0xfe00707f, value: 0x7a002057, op: VMNOR_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3497  	// VMORN.MM vs2, vs1, vd
  3498  	{mask: 0xfe00707f, value: 0x72002057, op: VMORN_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3499  	// VMOR.MM vs2, vs1, vd
  3500  	{mask: 0xfe00707f, value: 0x6a002057, op: VMOR_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3501  	// VMSBC.VV vs2, vs1, vd
  3502  	{mask: 0xfe00707f, value: 0x4e000057, op: VMSBC_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3503  	// VMSBC.VVM vs2, vs1, vd
  3504  	{mask: 0xfe00707f, value: 0x4c000057, op: VMSBC_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3505  	// VMSBC.VX vs2, rs1, vd
  3506  	{mask: 0xfe00707f, value: 0x4e004057, op: VMSBC_VX, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3507  	// VMSBC.VXM vs2, rs1, vd
  3508  	{mask: 0xfe00707f, value: 0x4c004057, op: VMSBC_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3509  	// VMSBF.M vm, vs2, vd
  3510  	{mask: 0xfc0ff07f, value: 0x5000a057, op: VMSBF_M, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3511  	// VMSEQ.VI vm, vs2, simm5, vd
  3512  	{mask: 0xfc00707f, value: 0x60003057, op: VMSEQ_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3513  	// VMSEQ.VV vm, vs2, vs1, vd
  3514  	{mask: 0xfc00707f, value: 0x60000057, op: VMSEQ_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3515  	// VMSEQ.VX vm, vs2, rs1, vd
  3516  	{mask: 0xfc00707f, value: 0x60004057, op: VMSEQ_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3517  	// VMSGTU.VI vm, vs2, simm5, vd
  3518  	{mask: 0xfc00707f, value: 0x78003057, op: VMSGTU_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3519  	// VMSGTU.VX vm, vs2, rs1, vd
  3520  	{mask: 0xfc00707f, value: 0x78004057, op: VMSGTU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3521  	// VMSGT.VI vm, vs2, simm5, vd
  3522  	{mask: 0xfc00707f, value: 0x7c003057, op: VMSGT_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3523  	// VMSGT.VX vm, vs2, rs1, vd
  3524  	{mask: 0xfc00707f, value: 0x7c004057, op: VMSGT_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3525  	// VMSIF.M vm, vs2, vd
  3526  	{mask: 0xfc0ff07f, value: 0x5001a057, op: VMSIF_M, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3527  	// VMSLEU.VI vm, vs2, simm5, vd
  3528  	{mask: 0xfc00707f, value: 0x70003057, op: VMSLEU_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3529  	// VMSLEU.VV vm, vs2, vs1, vd
  3530  	{mask: 0xfc00707f, value: 0x70000057, op: VMSLEU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3531  	// VMSLEU.VX vm, vs2, rs1, vd
  3532  	{mask: 0xfc00707f, value: 0x70004057, op: VMSLEU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3533  	// VMSLE.VI vm, vs2, simm5, vd
  3534  	{mask: 0xfc00707f, value: 0x74003057, op: VMSLE_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3535  	// VMSLE.VV vm, vs2, vs1, vd
  3536  	{mask: 0xfc00707f, value: 0x74000057, op: VMSLE_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3537  	// VMSLE.VX vm, vs2, rs1, vd
  3538  	{mask: 0xfc00707f, value: 0x74004057, op: VMSLE_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3539  	// VMSLTU.VV vm, vs2, vs1, vd
  3540  	{mask: 0xfc00707f, value: 0x68000057, op: VMSLTU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3541  	// VMSLTU.VX vm, vs2, rs1, vd
  3542  	{mask: 0xfc00707f, value: 0x68004057, op: VMSLTU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3543  	// VMSLT.VV vm, vs2, vs1, vd
  3544  	{mask: 0xfc00707f, value: 0x6c000057, op: VMSLT_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3545  	// VMSLT.VX vm, vs2, rs1, vd
  3546  	{mask: 0xfc00707f, value: 0x6c004057, op: VMSLT_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3547  	// VMSNE.VI vm, vs2, simm5, vd
  3548  	{mask: 0xfc00707f, value: 0x64003057, op: VMSNE_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3549  	// VMSNE.VV vm, vs2, vs1, vd
  3550  	{mask: 0xfc00707f, value: 0x64000057, op: VMSNE_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3551  	// VMSNE.VX vm, vs2, rs1, vd
  3552  	{mask: 0xfc00707f, value: 0x64004057, op: VMSNE_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3553  	// VMSOF.M vm, vs2, vd
  3554  	{mask: 0xfc0ff07f, value: 0x50012057, op: VMSOF_M, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3555  	// VMULHSU.VV vm, vs2, vs1, vd
  3556  	{mask: 0xfc00707f, value: 0x98002057, op: VMULHSU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3557  	// VMULHSU.VX vm, vs2, rs1, vd
  3558  	{mask: 0xfc00707f, value: 0x98006057, op: VMULHSU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3559  	// VMULHU.VV vm, vs2, vs1, vd
  3560  	{mask: 0xfc00707f, value: 0x90002057, op: VMULHU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3561  	// VMULHU.VX vm, vs2, rs1, vd
  3562  	{mask: 0xfc00707f, value: 0x90006057, op: VMULHU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3563  	// VMULH.VV vm, vs2, vs1, vd
  3564  	{mask: 0xfc00707f, value: 0x9c002057, op: VMULH_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3565  	// VMULH.VX vm, vs2, rs1, vd
  3566  	{mask: 0xfc00707f, value: 0x9c006057, op: VMULH_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3567  	// VMUL.VV vm, vs2, vs1, vd
  3568  	{mask: 0xfc00707f, value: 0x94002057, op: VMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3569  	// VMUL.VX vm, vs2, rs1, vd
  3570  	{mask: 0xfc00707f, value: 0x94006057, op: VMUL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3571  	// VMV1R.V vs2, vd
  3572  	{mask: 0xfe0ff07f, value: 0x9e003057, op: VMV1R_V, args: argTypeList{arg_vs2, arg_vd}},
  3573  	// VMV2R.V vs2, vd
  3574  	{mask: 0xfe0ff07f, value: 0x9e00b057, op: VMV2R_V, args: argTypeList{arg_vs2, arg_vd}},
  3575  	// VMV4R.V vs2, vd
  3576  	{mask: 0xfe0ff07f, value: 0x9e01b057, op: VMV4R_V, args: argTypeList{arg_vs2, arg_vd}},
  3577  	// VMV8R.V vs2, vd
  3578  	{mask: 0xfe0ff07f, value: 0x9e03b057, op: VMV8R_V, args: argTypeList{arg_vs2, arg_vd}},
  3579  	// VMV.S.X rs1, vd
  3580  	{mask: 0xfff0707f, value: 0x42006057, op: VMV_S_X, args: argTypeList{arg_rs1, arg_vd}},
  3581  	// VMV.V.I simm5, vd
  3582  	{mask: 0xfff0707f, value: 0x5e003057, op: VMV_V_I, args: argTypeList{arg_simm5, arg_vd}},
  3583  	// VMV.V.V vs1, vd
  3584  	{mask: 0xfff0707f, value: 0x5e000057, op: VMV_V_V, args: argTypeList{arg_vs1, arg_vd}},
  3585  	// VMV.V.X rs1, vd
  3586  	{mask: 0xfff0707f, value: 0x5e004057, op: VMV_V_X, args: argTypeList{arg_rs1, arg_vd}},
  3587  	// VMV.X.S vs2, rd
  3588  	{mask: 0xfe0ff07f, value: 0x42002057, op: VMV_X_S, args: argTypeList{arg_vs2, arg_rd}},
  3589  	// VMXNOR.MM vs2, vs1, vd
  3590  	{mask: 0xfe00707f, value: 0x7e002057, op: VMXNOR_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3591  	// VMXOR.MM vs2, vs1, vd
  3592  	{mask: 0xfe00707f, value: 0x6e002057, op: VMXOR_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3593  	// VNCLIPU.WI vm, vs2, zimm5, vd
  3594  	{mask: 0xfc00707f, value: 0xb8003057, op: VNCLIPU_WI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3595  	// VNCLIPU.WV vm, vs2, vs1, vd
  3596  	{mask: 0xfc00707f, value: 0xb8000057, op: VNCLIPU_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3597  	// VNCLIPU.WX vm, vs2, rs1, vd
  3598  	{mask: 0xfc00707f, value: 0xb8004057, op: VNCLIPU_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3599  	// VNCLIP.WI vm, vs2, zimm5, vd
  3600  	{mask: 0xfc00707f, value: 0xbc003057, op: VNCLIP_WI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3601  	// VNCLIP.WV vm, vs2, vs1, vd
  3602  	{mask: 0xfc00707f, value: 0xbc000057, op: VNCLIP_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3603  	// VNCLIP.WX vm, vs2, rs1, vd
  3604  	{mask: 0xfc00707f, value: 0xbc004057, op: VNCLIP_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3605  	// VNMSAC.VV vm, vs2, vs1, vd
  3606  	{mask: 0xfc00707f, value: 0xbc002057, op: VNMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3607  	// VNMSAC.VX vm, vs2, rs1, vd
  3608  	{mask: 0xfc00707f, value: 0xbc006057, op: VNMSAC_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3609  	// VNMSUB.VV vm, vs2, vs1, vd
  3610  	{mask: 0xfc00707f, value: 0xac002057, op: VNMSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3611  	// VNMSUB.VX vm, vs2, rs1, vd
  3612  	{mask: 0xfc00707f, value: 0xac006057, op: VNMSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3613  	// VNSRA.WI vm, vs2, zimm5, vd
  3614  	{mask: 0xfc00707f, value: 0xb4003057, op: VNSRA_WI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3615  	// VNSRA.WV vm, vs2, vs1, vd
  3616  	{mask: 0xfc00707f, value: 0xb4000057, op: VNSRA_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3617  	// VNSRA.WX vm, vs2, rs1, vd
  3618  	{mask: 0xfc00707f, value: 0xb4004057, op: VNSRA_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3619  	// VNSRL.WI vm, vs2, zimm5, vd
  3620  	{mask: 0xfc00707f, value: 0xb0003057, op: VNSRL_WI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3621  	// VNSRL.WV vm, vs2, vs1, vd
  3622  	{mask: 0xfc00707f, value: 0xb0000057, op: VNSRL_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3623  	// VNSRL.WX vm, vs2, rs1, vd
  3624  	{mask: 0xfc00707f, value: 0xb0004057, op: VNSRL_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3625  	// VOR.VI vm, vs2, simm5, vd
  3626  	{mask: 0xfc00707f, value: 0x28003057, op: VOR_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3627  	// VOR.VV vm, vs2, vs1, vd
  3628  	{mask: 0xfc00707f, value: 0x28000057, op: VOR_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3629  	// VOR.VX vm, vs2, rs1, vd
  3630  	{mask: 0xfc00707f, value: 0x28004057, op: VOR_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3631  	// VREDAND.VS vm, vs2, vs1, vd
  3632  	{mask: 0xfc00707f, value: 0x04002057, op: VREDAND_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3633  	// VREDMAXU.VS vm, vs2, vs1, vd
  3634  	{mask: 0xfc00707f, value: 0x18002057, op: VREDMAXU_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3635  	// VREDMAX.VS vm, vs2, vs1, vd
  3636  	{mask: 0xfc00707f, value: 0x1c002057, op: VREDMAX_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3637  	// VREDMINU.VS vm, vs2, vs1, vd
  3638  	{mask: 0xfc00707f, value: 0x10002057, op: VREDMINU_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3639  	// VREDMIN.VS vm, vs2, vs1, vd
  3640  	{mask: 0xfc00707f, value: 0x14002057, op: VREDMIN_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3641  	// VREDOR.VS vm, vs2, vs1, vd
  3642  	{mask: 0xfc00707f, value: 0x08002057, op: VREDOR_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3643  	// VREDSUM.VS vm, vs2, vs1, vd
  3644  	{mask: 0xfc00707f, value: 0x00002057, op: VREDSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3645  	// VREDXOR.VS vm, vs2, vs1, vd
  3646  	{mask: 0xfc00707f, value: 0x0c002057, op: VREDXOR_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3647  	// VREMU.VV vm, vs2, vs1, vd
  3648  	{mask: 0xfc00707f, value: 0x88002057, op: VREMU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3649  	// VREMU.VX vm, vs2, rs1, vd
  3650  	{mask: 0xfc00707f, value: 0x88006057, op: VREMU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3651  	// VREM.VV vm, vs2, vs1, vd
  3652  	{mask: 0xfc00707f, value: 0x8c002057, op: VREM_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3653  	// VREM.VX vm, vs2, rs1, vd
  3654  	{mask: 0xfc00707f, value: 0x8c006057, op: VREM_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3655  	// VRGATHEREI16.VV vm, vs2, vs1, vd
  3656  	{mask: 0xfc00707f, value: 0x38000057, op: VRGATHEREI16_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3657  	// VRGATHER.VI vm, vs2, zimm5, vd
  3658  	{mask: 0xfc00707f, value: 0x30003057, op: VRGATHER_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3659  	// VRGATHER.VV vm, vs2, vs1, vd
  3660  	{mask: 0xfc00707f, value: 0x30000057, op: VRGATHER_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3661  	// VRGATHER.VX vm, vs2, rs1, vd
  3662  	{mask: 0xfc00707f, value: 0x30004057, op: VRGATHER_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3663  	// VRSUB.VI vm, vs2, simm5, vd
  3664  	{mask: 0xfc00707f, value: 0x0c003057, op: VRSUB_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3665  	// VRSUB.VX vm, vs2, rs1, vd
  3666  	{mask: 0xfc00707f, value: 0x0c004057, op: VRSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3667  	// VS1R.V rs1_ptr, vs3
  3668  	{mask: 0xfff0707f, value: 0x02800027, op: VS1R_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3669  	// VS2R.V rs1_ptr, vs3
  3670  	{mask: 0xfff0707f, value: 0x22800027, op: VS2R_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3671  	// VS4R.V rs1_ptr, vs3
  3672  	{mask: 0xfff0707f, value: 0x62800027, op: VS4R_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3673  	// VS8R.V rs1_ptr, vs3
  3674  	{mask: 0xfff0707f, value: 0xe2800027, op: VS8R_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3675  	// VSADDU.VI vm, vs2, simm5, vd
  3676  	{mask: 0xfc00707f, value: 0x80003057, op: VSADDU_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3677  	// VSADDU.VV vm, vs2, vs1, vd
  3678  	{mask: 0xfc00707f, value: 0x80000057, op: VSADDU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3679  	// VSADDU.VX vm, vs2, rs1, vd
  3680  	{mask: 0xfc00707f, value: 0x80004057, op: VSADDU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3681  	// VSADD.VI vm, vs2, simm5, vd
  3682  	{mask: 0xfc00707f, value: 0x84003057, op: VSADD_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3683  	// VSADD.VV vm, vs2, vs1, vd
  3684  	{mask: 0xfc00707f, value: 0x84000057, op: VSADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3685  	// VSADD.VX vm, vs2, rs1, vd
  3686  	{mask: 0xfc00707f, value: 0x84004057, op: VSADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3687  	// VSBC.VVM vs2, vs1, vd
  3688  	{mask: 0xfe00707f, value: 0x48000057, op: VSBC_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3689  	// VSBC.VXM vs2, rs1, vd
  3690  	{mask: 0xfe00707f, value: 0x48004057, op: VSBC_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3691  	// VSE16.V vm, rs1_ptr, vs3
  3692  	{mask: 0xfdf0707f, value: 0x00005027, op: VSE16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3693  	// VSE32.V vm, rs1_ptr, vs3
  3694  	{mask: 0xfdf0707f, value: 0x00006027, op: VSE32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3695  	// VSE64.V vm, rs1_ptr, vs3
  3696  	{mask: 0xfdf0707f, value: 0x00007027, op: VSE64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3697  	// VSE8.V vm, rs1_ptr, vs3
  3698  	{mask: 0xfdf0707f, value: 0x00000027, op: VSE8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3699  	// VSETIVLI vtype_zimm10, zimm, rd
  3700  	{mask: 0xc000707f, value: 0xc0007057, op: VSETIVLI, args: argTypeList{arg_vtype_zimm10, arg_zimm, arg_rd}},
  3701  	// VSETVL rs2, rs1, rd
  3702  	{mask: 0xfe00707f, value: 0x80007057, op: VSETVL, args: argTypeList{arg_rs2, arg_rs1, arg_rd}},
  3703  	// VSETVLI vtype_zimm11, rs1, rd
  3704  	{mask: 0x8000707f, value: 0x00007057, op: VSETVLI, args: argTypeList{arg_vtype_zimm11, arg_rs1, arg_rd}},
  3705  	// VSEXT.VF2 vm, vs2, vd
  3706  	{mask: 0xfc0ff07f, value: 0x4803a057, op: VSEXT_VF2, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3707  	// VSEXT.VF4 vm, vs2, vd
  3708  	{mask: 0xfc0ff07f, value: 0x4802a057, op: VSEXT_VF4, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3709  	// VSEXT.VF8 vm, vs2, vd
  3710  	{mask: 0xfc0ff07f, value: 0x4801a057, op: VSEXT_VF8, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3711  	// VSLIDE1DOWN.VX vm, vs2, rs1, vd
  3712  	{mask: 0xfc00707f, value: 0x3c006057, op: VSLIDE1DOWN_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3713  	// VSLIDE1UP.VX vm, vs2, rs1, vd
  3714  	{mask: 0xfc00707f, value: 0x38006057, op: VSLIDE1UP_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3715  	// VSLIDEDOWN.VI vm, vs2, zimm5, vd
  3716  	{mask: 0xfc00707f, value: 0x3c003057, op: VSLIDEDOWN_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3717  	// VSLIDEDOWN.VX vm, vs2, rs1, vd
  3718  	{mask: 0xfc00707f, value: 0x3c004057, op: VSLIDEDOWN_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3719  	// VSLIDEUP.VI vm, vs2, zimm5, vd
  3720  	{mask: 0xfc00707f, value: 0x38003057, op: VSLIDEUP_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3721  	// VSLIDEUP.VX vm, vs2, rs1, vd
  3722  	{mask: 0xfc00707f, value: 0x38004057, op: VSLIDEUP_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3723  	// VSLL.VI vm, vs2, zimm5, vd
  3724  	{mask: 0xfc00707f, value: 0x94003057, op: VSLL_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3725  	// VSLL.VV vm, vs2, vs1, vd
  3726  	{mask: 0xfc00707f, value: 0x94000057, op: VSLL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3727  	// VSLL.VX vm, vs2, rs1, vd
  3728  	{mask: 0xfc00707f, value: 0x94004057, op: VSLL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3729  	// VSMUL.VV vm, vs2, vs1, vd
  3730  	{mask: 0xfc00707f, value: 0x9c000057, op: VSMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3731  	// VSMUL.VX vm, vs2, rs1, vd
  3732  	{mask: 0xfc00707f, value: 0x9c004057, op: VSMUL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3733  	// VSM.V rs1_ptr, vs3
  3734  	{mask: 0xfff0707f, value: 0x02b00027, op: VSM_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3735  	// VSOXEI16.V vm, vs2, rs1_ptr, vs3
  3736  	{mask: 0xfc00707f, value: 0x0c005027, op: VSOXEI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3737  	// VSOXEI32.V vm, vs2, rs1_ptr, vs3
  3738  	{mask: 0xfc00707f, value: 0x0c006027, op: VSOXEI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3739  	// VSOXEI64.V vm, vs2, rs1_ptr, vs3
  3740  	{mask: 0xfc00707f, value: 0x0c007027, op: VSOXEI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3741  	// VSOXEI8.V vm, vs2, rs1_ptr, vs3
  3742  	{mask: 0xfc00707f, value: 0x0c000027, op: VSOXEI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3743  	// VSOXSEG2EI16.V vm, vs2, rs1_ptr, vs3
  3744  	{mask: 0xfc00707f, value: 0x2c005027, op: VSOXSEG2EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3745  	// VSOXSEG2EI32.V vm, vs2, rs1_ptr, vs3
  3746  	{mask: 0xfc00707f, value: 0x2c006027, op: VSOXSEG2EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3747  	// VSOXSEG2EI64.V vm, vs2, rs1_ptr, vs3
  3748  	{mask: 0xfc00707f, value: 0x2c007027, op: VSOXSEG2EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3749  	// VSOXSEG2EI8.V vm, vs2, rs1_ptr, vs3
  3750  	{mask: 0xfc00707f, value: 0x2c000027, op: VSOXSEG2EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3751  	// VSOXSEG3EI16.V vm, vs2, rs1_ptr, vs3
  3752  	{mask: 0xfc00707f, value: 0x4c005027, op: VSOXSEG3EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3753  	// VSOXSEG3EI32.V vm, vs2, rs1_ptr, vs3
  3754  	{mask: 0xfc00707f, value: 0x4c006027, op: VSOXSEG3EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3755  	// VSOXSEG3EI64.V vm, vs2, rs1_ptr, vs3
  3756  	{mask: 0xfc00707f, value: 0x4c007027, op: VSOXSEG3EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3757  	// VSOXSEG3EI8.V vm, vs2, rs1_ptr, vs3
  3758  	{mask: 0xfc00707f, value: 0x4c000027, op: VSOXSEG3EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3759  	// VSOXSEG4EI16.V vm, vs2, rs1_ptr, vs3
  3760  	{mask: 0xfc00707f, value: 0x6c005027, op: VSOXSEG4EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3761  	// VSOXSEG4EI32.V vm, vs2, rs1_ptr, vs3
  3762  	{mask: 0xfc00707f, value: 0x6c006027, op: VSOXSEG4EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3763  	// VSOXSEG4EI64.V vm, vs2, rs1_ptr, vs3
  3764  	{mask: 0xfc00707f, value: 0x6c007027, op: VSOXSEG4EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3765  	// VSOXSEG4EI8.V vm, vs2, rs1_ptr, vs3
  3766  	{mask: 0xfc00707f, value: 0x6c000027, op: VSOXSEG4EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3767  	// VSOXSEG5EI16.V vm, vs2, rs1_ptr, vs3
  3768  	{mask: 0xfc00707f, value: 0x8c005027, op: VSOXSEG5EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3769  	// VSOXSEG5EI32.V vm, vs2, rs1_ptr, vs3
  3770  	{mask: 0xfc00707f, value: 0x8c006027, op: VSOXSEG5EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3771  	// VSOXSEG5EI64.V vm, vs2, rs1_ptr, vs3
  3772  	{mask: 0xfc00707f, value: 0x8c007027, op: VSOXSEG5EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3773  	// VSOXSEG5EI8.V vm, vs2, rs1_ptr, vs3
  3774  	{mask: 0xfc00707f, value: 0x8c000027, op: VSOXSEG5EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3775  	// VSOXSEG6EI16.V vm, vs2, rs1_ptr, vs3
  3776  	{mask: 0xfc00707f, value: 0xac005027, op: VSOXSEG6EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3777  	// VSOXSEG6EI32.V vm, vs2, rs1_ptr, vs3
  3778  	{mask: 0xfc00707f, value: 0xac006027, op: VSOXSEG6EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3779  	// VSOXSEG6EI64.V vm, vs2, rs1_ptr, vs3
  3780  	{mask: 0xfc00707f, value: 0xac007027, op: VSOXSEG6EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3781  	// VSOXSEG6EI8.V vm, vs2, rs1_ptr, vs3
  3782  	{mask: 0xfc00707f, value: 0xac000027, op: VSOXSEG6EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3783  	// VSOXSEG7EI16.V vm, vs2, rs1_ptr, vs3
  3784  	{mask: 0xfc00707f, value: 0xcc005027, op: VSOXSEG7EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3785  	// VSOXSEG7EI32.V vm, vs2, rs1_ptr, vs3
  3786  	{mask: 0xfc00707f, value: 0xcc006027, op: VSOXSEG7EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3787  	// VSOXSEG7EI64.V vm, vs2, rs1_ptr, vs3
  3788  	{mask: 0xfc00707f, value: 0xcc007027, op: VSOXSEG7EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3789  	// VSOXSEG7EI8.V vm, vs2, rs1_ptr, vs3
  3790  	{mask: 0xfc00707f, value: 0xcc000027, op: VSOXSEG7EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3791  	// VSOXSEG8EI16.V vm, vs2, rs1_ptr, vs3
  3792  	{mask: 0xfc00707f, value: 0xec005027, op: VSOXSEG8EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3793  	// VSOXSEG8EI32.V vm, vs2, rs1_ptr, vs3
  3794  	{mask: 0xfc00707f, value: 0xec006027, op: VSOXSEG8EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3795  	// VSOXSEG8EI64.V vm, vs2, rs1_ptr, vs3
  3796  	{mask: 0xfc00707f, value: 0xec007027, op: VSOXSEG8EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3797  	// VSOXSEG8EI8.V vm, vs2, rs1_ptr, vs3
  3798  	{mask: 0xfc00707f, value: 0xec000027, op: VSOXSEG8EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3799  	// VSRA.VI vm, vs2, zimm5, vd
  3800  	{mask: 0xfc00707f, value: 0xa4003057, op: VSRA_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3801  	// VSRA.VV vm, vs2, vs1, vd
  3802  	{mask: 0xfc00707f, value: 0xa4000057, op: VSRA_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3803  	// VSRA.VX vm, vs2, rs1, vd
  3804  	{mask: 0xfc00707f, value: 0xa4004057, op: VSRA_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3805  	// VSRL.VI vm, vs2, zimm5, vd
  3806  	{mask: 0xfc00707f, value: 0xa0003057, op: VSRL_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3807  	// VSRL.VV vm, vs2, vs1, vd
  3808  	{mask: 0xfc00707f, value: 0xa0000057, op: VSRL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3809  	// VSRL.VX vm, vs2, rs1, vd
  3810  	{mask: 0xfc00707f, value: 0xa0004057, op: VSRL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3811  	// VSSE16.V vm, rs2, rs1_ptr, vs3
  3812  	{mask: 0xfc00707f, value: 0x08005027, op: VSSE16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3813  	// VSSE32.V vm, rs2, rs1_ptr, vs3
  3814  	{mask: 0xfc00707f, value: 0x08006027, op: VSSE32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3815  	// VSSE64.V vm, rs2, rs1_ptr, vs3
  3816  	{mask: 0xfc00707f, value: 0x08007027, op: VSSE64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3817  	// VSSE8.V vm, rs2, rs1_ptr, vs3
  3818  	{mask: 0xfc00707f, value: 0x08000027, op: VSSE8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3819  	// VSSEG2E16.V vm, rs1_ptr, vs3
  3820  	{mask: 0xfdf0707f, value: 0x20005027, op: VSSEG2E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3821  	// VSSEG2E32.V vm, rs1_ptr, vs3
  3822  	{mask: 0xfdf0707f, value: 0x20006027, op: VSSEG2E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3823  	// VSSEG2E64.V vm, rs1_ptr, vs3
  3824  	{mask: 0xfdf0707f, value: 0x20007027, op: VSSEG2E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3825  	// VSSEG2E8.V vm, rs1_ptr, vs3
  3826  	{mask: 0xfdf0707f, value: 0x20000027, op: VSSEG2E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3827  	// VSSEG3E16.V vm, rs1_ptr, vs3
  3828  	{mask: 0xfdf0707f, value: 0x40005027, op: VSSEG3E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3829  	// VSSEG3E32.V vm, rs1_ptr, vs3
  3830  	{mask: 0xfdf0707f, value: 0x40006027, op: VSSEG3E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3831  	// VSSEG3E64.V vm, rs1_ptr, vs3
  3832  	{mask: 0xfdf0707f, value: 0x40007027, op: VSSEG3E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3833  	// VSSEG3E8.V vm, rs1_ptr, vs3
  3834  	{mask: 0xfdf0707f, value: 0x40000027, op: VSSEG3E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3835  	// VSSEG4E16.V vm, rs1_ptr, vs3
  3836  	{mask: 0xfdf0707f, value: 0x60005027, op: VSSEG4E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3837  	// VSSEG4E32.V vm, rs1_ptr, vs3
  3838  	{mask: 0xfdf0707f, value: 0x60006027, op: VSSEG4E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3839  	// VSSEG4E64.V vm, rs1_ptr, vs3
  3840  	{mask: 0xfdf0707f, value: 0x60007027, op: VSSEG4E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3841  	// VSSEG4E8.V vm, rs1_ptr, vs3
  3842  	{mask: 0xfdf0707f, value: 0x60000027, op: VSSEG4E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3843  	// VSSEG5E16.V vm, rs1_ptr, vs3
  3844  	{mask: 0xfdf0707f, value: 0x80005027, op: VSSEG5E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3845  	// VSSEG5E32.V vm, rs1_ptr, vs3
  3846  	{mask: 0xfdf0707f, value: 0x80006027, op: VSSEG5E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3847  	// VSSEG5E64.V vm, rs1_ptr, vs3
  3848  	{mask: 0xfdf0707f, value: 0x80007027, op: VSSEG5E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3849  	// VSSEG5E8.V vm, rs1_ptr, vs3
  3850  	{mask: 0xfdf0707f, value: 0x80000027, op: VSSEG5E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3851  	// VSSEG6E16.V vm, rs1_ptr, vs3
  3852  	{mask: 0xfdf0707f, value: 0xa0005027, op: VSSEG6E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3853  	// VSSEG6E32.V vm, rs1_ptr, vs3
  3854  	{mask: 0xfdf0707f, value: 0xa0006027, op: VSSEG6E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3855  	// VSSEG6E64.V vm, rs1_ptr, vs3
  3856  	{mask: 0xfdf0707f, value: 0xa0007027, op: VSSEG6E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3857  	// VSSEG6E8.V vm, rs1_ptr, vs3
  3858  	{mask: 0xfdf0707f, value: 0xa0000027, op: VSSEG6E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3859  	// VSSEG7E16.V vm, rs1_ptr, vs3
  3860  	{mask: 0xfdf0707f, value: 0xc0005027, op: VSSEG7E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3861  	// VSSEG7E32.V vm, rs1_ptr, vs3
  3862  	{mask: 0xfdf0707f, value: 0xc0006027, op: VSSEG7E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3863  	// VSSEG7E64.V vm, rs1_ptr, vs3
  3864  	{mask: 0xfdf0707f, value: 0xc0007027, op: VSSEG7E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3865  	// VSSEG7E8.V vm, rs1_ptr, vs3
  3866  	{mask: 0xfdf0707f, value: 0xc0000027, op: VSSEG7E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3867  	// VSSEG8E16.V vm, rs1_ptr, vs3
  3868  	{mask: 0xfdf0707f, value: 0xe0005027, op: VSSEG8E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3869  	// VSSEG8E32.V vm, rs1_ptr, vs3
  3870  	{mask: 0xfdf0707f, value: 0xe0006027, op: VSSEG8E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3871  	// VSSEG8E64.V vm, rs1_ptr, vs3
  3872  	{mask: 0xfdf0707f, value: 0xe0007027, op: VSSEG8E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3873  	// VSSEG8E8.V vm, rs1_ptr, vs3
  3874  	{mask: 0xfdf0707f, value: 0xe0000027, op: VSSEG8E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3875  	// VSSRA.VI vm, vs2, zimm5, vd
  3876  	{mask: 0xfc00707f, value: 0xac003057, op: VSSRA_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3877  	// VSSRA.VV vm, vs2, vs1, vd
  3878  	{mask: 0xfc00707f, value: 0xac000057, op: VSSRA_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3879  	// VSSRA.VX vm, vs2, rs1, vd
  3880  	{mask: 0xfc00707f, value: 0xac004057, op: VSSRA_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3881  	// VSSRL.VI vm, vs2, zimm5, vd
  3882  	{mask: 0xfc00707f, value: 0xa8003057, op: VSSRL_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3883  	// VSSRL.VV vm, vs2, vs1, vd
  3884  	{mask: 0xfc00707f, value: 0xa8000057, op: VSSRL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3885  	// VSSRL.VX vm, vs2, rs1, vd
  3886  	{mask: 0xfc00707f, value: 0xa8004057, op: VSSRL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3887  	// VSSSEG2E16.V vm, rs2, rs1_ptr, vs3
  3888  	{mask: 0xfc00707f, value: 0x28005027, op: VSSSEG2E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3889  	// VSSSEG2E32.V vm, rs2, rs1_ptr, vs3
  3890  	{mask: 0xfc00707f, value: 0x28006027, op: VSSSEG2E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3891  	// VSSSEG2E64.V vm, rs2, rs1_ptr, vs3
  3892  	{mask: 0xfc00707f, value: 0x28007027, op: VSSSEG2E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3893  	// VSSSEG2E8.V vm, rs2, rs1_ptr, vs3
  3894  	{mask: 0xfc00707f, value: 0x28000027, op: VSSSEG2E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3895  	// VSSSEG3E16.V vm, rs2, rs1_ptr, vs3
  3896  	{mask: 0xfc00707f, value: 0x48005027, op: VSSSEG3E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3897  	// VSSSEG3E32.V vm, rs2, rs1_ptr, vs3
  3898  	{mask: 0xfc00707f, value: 0x48006027, op: VSSSEG3E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3899  	// VSSSEG3E64.V vm, rs2, rs1_ptr, vs3
  3900  	{mask: 0xfc00707f, value: 0x48007027, op: VSSSEG3E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3901  	// VSSSEG3E8.V vm, rs2, rs1_ptr, vs3
  3902  	{mask: 0xfc00707f, value: 0x48000027, op: VSSSEG3E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3903  	// VSSSEG4E16.V vm, rs2, rs1_ptr, vs3
  3904  	{mask: 0xfc00707f, value: 0x68005027, op: VSSSEG4E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3905  	// VSSSEG4E32.V vm, rs2, rs1_ptr, vs3
  3906  	{mask: 0xfc00707f, value: 0x68006027, op: VSSSEG4E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3907  	// VSSSEG4E64.V vm, rs2, rs1_ptr, vs3
  3908  	{mask: 0xfc00707f, value: 0x68007027, op: VSSSEG4E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3909  	// VSSSEG4E8.V vm, rs2, rs1_ptr, vs3
  3910  	{mask: 0xfc00707f, value: 0x68000027, op: VSSSEG4E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3911  	// VSSSEG5E16.V vm, rs2, rs1_ptr, vs3
  3912  	{mask: 0xfc00707f, value: 0x88005027, op: VSSSEG5E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3913  	// VSSSEG5E32.V vm, rs2, rs1_ptr, vs3
  3914  	{mask: 0xfc00707f, value: 0x88006027, op: VSSSEG5E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3915  	// VSSSEG5E64.V vm, rs2, rs1_ptr, vs3
  3916  	{mask: 0xfc00707f, value: 0x88007027, op: VSSSEG5E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3917  	// VSSSEG5E8.V vm, rs2, rs1_ptr, vs3
  3918  	{mask: 0xfc00707f, value: 0x88000027, op: VSSSEG5E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3919  	// VSSSEG6E16.V vm, rs2, rs1_ptr, vs3
  3920  	{mask: 0xfc00707f, value: 0xa8005027, op: VSSSEG6E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3921  	// VSSSEG6E32.V vm, rs2, rs1_ptr, vs3
  3922  	{mask: 0xfc00707f, value: 0xa8006027, op: VSSSEG6E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3923  	// VSSSEG6E64.V vm, rs2, rs1_ptr, vs3
  3924  	{mask: 0xfc00707f, value: 0xa8007027, op: VSSSEG6E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3925  	// VSSSEG6E8.V vm, rs2, rs1_ptr, vs3
  3926  	{mask: 0xfc00707f, value: 0xa8000027, op: VSSSEG6E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3927  	// VSSSEG7E16.V vm, rs2, rs1_ptr, vs3
  3928  	{mask: 0xfc00707f, value: 0xc8005027, op: VSSSEG7E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3929  	// VSSSEG7E32.V vm, rs2, rs1_ptr, vs3
  3930  	{mask: 0xfc00707f, value: 0xc8006027, op: VSSSEG7E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3931  	// VSSSEG7E64.V vm, rs2, rs1_ptr, vs3
  3932  	{mask: 0xfc00707f, value: 0xc8007027, op: VSSSEG7E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3933  	// VSSSEG7E8.V vm, rs2, rs1_ptr, vs3
  3934  	{mask: 0xfc00707f, value: 0xc8000027, op: VSSSEG7E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3935  	// VSSSEG8E16.V vm, rs2, rs1_ptr, vs3
  3936  	{mask: 0xfc00707f, value: 0xe8005027, op: VSSSEG8E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3937  	// VSSSEG8E32.V vm, rs2, rs1_ptr, vs3
  3938  	{mask: 0xfc00707f, value: 0xe8006027, op: VSSSEG8E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3939  	// VSSSEG8E64.V vm, rs2, rs1_ptr, vs3
  3940  	{mask: 0xfc00707f, value: 0xe8007027, op: VSSSEG8E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3941  	// VSSSEG8E8.V vm, rs2, rs1_ptr, vs3
  3942  	{mask: 0xfc00707f, value: 0xe8000027, op: VSSSEG8E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3943  	// VSSUBU.VV vm, vs2, vs1, vd
  3944  	{mask: 0xfc00707f, value: 0x88000057, op: VSSUBU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3945  	// VSSUBU.VX vm, vs2, rs1, vd
  3946  	{mask: 0xfc00707f, value: 0x88004057, op: VSSUBU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3947  	// VSSUB.VV vm, vs2, vs1, vd
  3948  	{mask: 0xfc00707f, value: 0x8c000057, op: VSSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3949  	// VSSUB.VX vm, vs2, rs1, vd
  3950  	{mask: 0xfc00707f, value: 0x8c004057, op: VSSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3951  	// VSUB.VV vm, vs2, vs1, vd
  3952  	{mask: 0xfc00707f, value: 0x08000057, op: VSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3953  	// VSUB.VX vm, vs2, rs1, vd
  3954  	{mask: 0xfc00707f, value: 0x08004057, op: VSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3955  	// VSUXEI16.V vm, vs2, rs1_ptr, vs3
  3956  	{mask: 0xfc00707f, value: 0x04005027, op: VSUXEI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3957  	// VSUXEI32.V vm, vs2, rs1_ptr, vs3
  3958  	{mask: 0xfc00707f, value: 0x04006027, op: VSUXEI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3959  	// VSUXEI64.V vm, vs2, rs1_ptr, vs3
  3960  	{mask: 0xfc00707f, value: 0x04007027, op: VSUXEI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3961  	// VSUXEI8.V vm, vs2, rs1_ptr, vs3
  3962  	{mask: 0xfc00707f, value: 0x04000027, op: VSUXEI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3963  	// VSUXSEG2EI16.V vm, vs2, rs1_ptr, vs3
  3964  	{mask: 0xfc00707f, value: 0x24005027, op: VSUXSEG2EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3965  	// VSUXSEG2EI32.V vm, vs2, rs1_ptr, vs3
  3966  	{mask: 0xfc00707f, value: 0x24006027, op: VSUXSEG2EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3967  	// VSUXSEG2EI64.V vm, vs2, rs1_ptr, vs3
  3968  	{mask: 0xfc00707f, value: 0x24007027, op: VSUXSEG2EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3969  	// VSUXSEG2EI8.V vm, vs2, rs1_ptr, vs3
  3970  	{mask: 0xfc00707f, value: 0x24000027, op: VSUXSEG2EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3971  	// VSUXSEG3EI16.V vm, vs2, rs1_ptr, vs3
  3972  	{mask: 0xfc00707f, value: 0x44005027, op: VSUXSEG3EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3973  	// VSUXSEG3EI32.V vm, vs2, rs1_ptr, vs3
  3974  	{mask: 0xfc00707f, value: 0x44006027, op: VSUXSEG3EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3975  	// VSUXSEG3EI64.V vm, vs2, rs1_ptr, vs3
  3976  	{mask: 0xfc00707f, value: 0x44007027, op: VSUXSEG3EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3977  	// VSUXSEG3EI8.V vm, vs2, rs1_ptr, vs3
  3978  	{mask: 0xfc00707f, value: 0x44000027, op: VSUXSEG3EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3979  	// VSUXSEG4EI16.V vm, vs2, rs1_ptr, vs3
  3980  	{mask: 0xfc00707f, value: 0x64005027, op: VSUXSEG4EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3981  	// VSUXSEG4EI32.V vm, vs2, rs1_ptr, vs3
  3982  	{mask: 0xfc00707f, value: 0x64006027, op: VSUXSEG4EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3983  	// VSUXSEG4EI64.V vm, vs2, rs1_ptr, vs3
  3984  	{mask: 0xfc00707f, value: 0x64007027, op: VSUXSEG4EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3985  	// VSUXSEG4EI8.V vm, vs2, rs1_ptr, vs3
  3986  	{mask: 0xfc00707f, value: 0x64000027, op: VSUXSEG4EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3987  	// VSUXSEG5EI16.V vm, vs2, rs1_ptr, vs3
  3988  	{mask: 0xfc00707f, value: 0x84005027, op: VSUXSEG5EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3989  	// VSUXSEG5EI32.V vm, vs2, rs1_ptr, vs3
  3990  	{mask: 0xfc00707f, value: 0x84006027, op: VSUXSEG5EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3991  	// VSUXSEG5EI64.V vm, vs2, rs1_ptr, vs3
  3992  	{mask: 0xfc00707f, value: 0x84007027, op: VSUXSEG5EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3993  	// VSUXSEG5EI8.V vm, vs2, rs1_ptr, vs3
  3994  	{mask: 0xfc00707f, value: 0x84000027, op: VSUXSEG5EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3995  	// VSUXSEG6EI16.V vm, vs2, rs1_ptr, vs3
  3996  	{mask: 0xfc00707f, value: 0xa4005027, op: VSUXSEG6EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3997  	// VSUXSEG6EI32.V vm, vs2, rs1_ptr, vs3
  3998  	{mask: 0xfc00707f, value: 0xa4006027, op: VSUXSEG6EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3999  	// VSUXSEG6EI64.V vm, vs2, rs1_ptr, vs3
  4000  	{mask: 0xfc00707f, value: 0xa4007027, op: VSUXSEG6EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4001  	// VSUXSEG6EI8.V vm, vs2, rs1_ptr, vs3
  4002  	{mask: 0xfc00707f, value: 0xa4000027, op: VSUXSEG6EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4003  	// VSUXSEG7EI16.V vm, vs2, rs1_ptr, vs3
  4004  	{mask: 0xfc00707f, value: 0xc4005027, op: VSUXSEG7EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4005  	// VSUXSEG7EI32.V vm, vs2, rs1_ptr, vs3
  4006  	{mask: 0xfc00707f, value: 0xc4006027, op: VSUXSEG7EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4007  	// VSUXSEG7EI64.V vm, vs2, rs1_ptr, vs3
  4008  	{mask: 0xfc00707f, value: 0xc4007027, op: VSUXSEG7EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4009  	// VSUXSEG7EI8.V vm, vs2, rs1_ptr, vs3
  4010  	{mask: 0xfc00707f, value: 0xc4000027, op: VSUXSEG7EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4011  	// VSUXSEG8EI16.V vm, vs2, rs1_ptr, vs3
  4012  	{mask: 0xfc00707f, value: 0xe4005027, op: VSUXSEG8EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4013  	// VSUXSEG8EI32.V vm, vs2, rs1_ptr, vs3
  4014  	{mask: 0xfc00707f, value: 0xe4006027, op: VSUXSEG8EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4015  	// VSUXSEG8EI64.V vm, vs2, rs1_ptr, vs3
  4016  	{mask: 0xfc00707f, value: 0xe4007027, op: VSUXSEG8EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4017  	// VSUXSEG8EI8.V vm, vs2, rs1_ptr, vs3
  4018  	{mask: 0xfc00707f, value: 0xe4000027, op: VSUXSEG8EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  4019  	// VWADDU.VV vm, vs2, vs1, vd
  4020  	{mask: 0xfc00707f, value: 0xc0002057, op: VWADDU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4021  	// VWADDU.VX vm, vs2, rs1, vd
  4022  	{mask: 0xfc00707f, value: 0xc0006057, op: VWADDU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4023  	// VWADDU.WV vm, vs2, vs1, vd
  4024  	{mask: 0xfc00707f, value: 0xd0002057, op: VWADDU_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4025  	// VWADDU.WX vm, vs2, rs1, vd
  4026  	{mask: 0xfc00707f, value: 0xd0006057, op: VWADDU_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4027  	// VWADD.VV vm, vs2, vs1, vd
  4028  	{mask: 0xfc00707f, value: 0xc4002057, op: VWADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4029  	// VWADD.VX vm, vs2, rs1, vd
  4030  	{mask: 0xfc00707f, value: 0xc4006057, op: VWADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4031  	// VWADD.WV vm, vs2, vs1, vd
  4032  	{mask: 0xfc00707f, value: 0xd4002057, op: VWADD_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4033  	// VWADD.WX vm, vs2, rs1, vd
  4034  	{mask: 0xfc00707f, value: 0xd4006057, op: VWADD_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4035  	// VWMACCSU.VV vm, vs2, vs1, vd
  4036  	{mask: 0xfc00707f, value: 0xfc002057, op: VWMACCSU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4037  	// VWMACCSU.VX vm, vs2, rs1, vd
  4038  	{mask: 0xfc00707f, value: 0xfc006057, op: VWMACCSU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4039  	// VWMACCUS.VX vm, vs2, rs1, vd
  4040  	{mask: 0xfc00707f, value: 0xf8006057, op: VWMACCUS_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4041  	// VWMACCU.VV vm, vs2, vs1, vd
  4042  	{mask: 0xfc00707f, value: 0xf0002057, op: VWMACCU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4043  	// VWMACCU.VX vm, vs2, rs1, vd
  4044  	{mask: 0xfc00707f, value: 0xf0006057, op: VWMACCU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4045  	// VWMACC.VV vm, vs2, vs1, vd
  4046  	{mask: 0xfc00707f, value: 0xf4002057, op: VWMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4047  	// VWMACC.VX vm, vs2, rs1, vd
  4048  	{mask: 0xfc00707f, value: 0xf4006057, op: VWMACC_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4049  	// VWMULSU.VV vm, vs2, vs1, vd
  4050  	{mask: 0xfc00707f, value: 0xe8002057, op: VWMULSU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4051  	// VWMULSU.VX vm, vs2, rs1, vd
  4052  	{mask: 0xfc00707f, value: 0xe8006057, op: VWMULSU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4053  	// VWMULU.VV vm, vs2, vs1, vd
  4054  	{mask: 0xfc00707f, value: 0xe0002057, op: VWMULU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4055  	// VWMULU.VX vm, vs2, rs1, vd
  4056  	{mask: 0xfc00707f, value: 0xe0006057, op: VWMULU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4057  	// VWMUL.VV vm, vs2, vs1, vd
  4058  	{mask: 0xfc00707f, value: 0xec002057, op: VWMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4059  	// VWMUL.VX vm, vs2, rs1, vd
  4060  	{mask: 0xfc00707f, value: 0xec006057, op: VWMUL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4061  	// VWREDSUMU.VS vm, vs2, vs1, vd
  4062  	{mask: 0xfc00707f, value: 0xc0000057, op: VWREDSUMU_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4063  	// VWREDSUM.VS vm, vs2, vs1, vd
  4064  	{mask: 0xfc00707f, value: 0xc4000057, op: VWREDSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4065  	// VWSUBU.VV vm, vs2, vs1, vd
  4066  	{mask: 0xfc00707f, value: 0xc8002057, op: VWSUBU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4067  	// VWSUBU.VX vm, vs2, rs1, vd
  4068  	{mask: 0xfc00707f, value: 0xc8006057, op: VWSUBU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4069  	// VWSUBU.WV vm, vs2, vs1, vd
  4070  	{mask: 0xfc00707f, value: 0xd8002057, op: VWSUBU_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4071  	// VWSUBU.WX vm, vs2, rs1, vd
  4072  	{mask: 0xfc00707f, value: 0xd8006057, op: VWSUBU_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4073  	// VWSUB.VV vm, vs2, vs1, vd
  4074  	{mask: 0xfc00707f, value: 0xcc002057, op: VWSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4075  	// VWSUB.VX vm, vs2, rs1, vd
  4076  	{mask: 0xfc00707f, value: 0xcc006057, op: VWSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4077  	// VWSUB.WV vm, vs2, vs1, vd
  4078  	{mask: 0xfc00707f, value: 0xdc002057, op: VWSUB_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4079  	// VWSUB.WX vm, vs2, rs1, vd
  4080  	{mask: 0xfc00707f, value: 0xdc006057, op: VWSUB_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4081  	// VXOR.VI vm, vs2, simm5, vd
  4082  	{mask: 0xfc00707f, value: 0x2c003057, op: VXOR_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  4083  	// VXOR.VV vm, vs2, vs1, vd
  4084  	{mask: 0xfc00707f, value: 0x2c000057, op: VXOR_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  4085  	// VXOR.VX vm, vs2, rs1, vd
  4086  	{mask: 0xfc00707f, value: 0x2c004057, op: VXOR_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  4087  	// VZEXT.VF2 vm, vs2, vd
  4088  	{mask: 0xfc0ff07f, value: 0x48032057, op: VZEXT_VF2, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  4089  	// VZEXT.VF4 vm, vs2, vd
  4090  	{mask: 0xfc0ff07f, value: 0x48022057, op: VZEXT_VF4, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  4091  	// VZEXT.VF8 vm, vs2, vd
  4092  	{mask: 0xfc0ff07f, value: 0x48012057, op: VZEXT_VF8, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  4093  	// XNOR rd, rs1, rs2
  4094  	{mask: 0xfe00707f, value: 0x40004033, op: XNOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  4095  	// XOR rd, rs1, rs2
  4096  	{mask: 0xfe00707f, value: 0x00004033, op: XOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  4097  	// XORI rd, rs1, imm12
  4098  	{mask: 0x0000707f, value: 0x00004013, op: XORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  4099  	// ZEXT.H rd, rs1
  4100  	{mask: 0xfff0707f, value: 0x0800403b, op: ZEXT_H, args: argTypeList{arg_rd, arg_rs1}},
  4101  }
  4102  

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