Source file src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/tables.go

     1  // Code generated by riscv64spec riscv-opcodes
     2  // DO NOT EDIT
     3  
     4  // Copyright 2024 The Go Authors. All rights reserved.
     5  // Use of this source code is governed by a BSD-style
     6  // license that can be found in the LICENSE file.
     7  
     8  package riscv64asm
     9  
    10  const (
    11  	_ Op = iota
    12  	ADD
    13  	ADDI
    14  	ADDIW
    15  	ADDW
    16  	ADD_UW
    17  	AMOADD_D
    18  	AMOADD_D_AQ
    19  	AMOADD_D_AQRL
    20  	AMOADD_D_RL
    21  	AMOADD_W
    22  	AMOADD_W_AQ
    23  	AMOADD_W_AQRL
    24  	AMOADD_W_RL
    25  	AMOAND_D
    26  	AMOAND_D_AQ
    27  	AMOAND_D_AQRL
    28  	AMOAND_D_RL
    29  	AMOAND_W
    30  	AMOAND_W_AQ
    31  	AMOAND_W_AQRL
    32  	AMOAND_W_RL
    33  	AMOMAXU_D
    34  	AMOMAXU_D_AQ
    35  	AMOMAXU_D_AQRL
    36  	AMOMAXU_D_RL
    37  	AMOMAXU_W
    38  	AMOMAXU_W_AQ
    39  	AMOMAXU_W_AQRL
    40  	AMOMAXU_W_RL
    41  	AMOMAX_D
    42  	AMOMAX_D_AQ
    43  	AMOMAX_D_AQRL
    44  	AMOMAX_D_RL
    45  	AMOMAX_W
    46  	AMOMAX_W_AQ
    47  	AMOMAX_W_AQRL
    48  	AMOMAX_W_RL
    49  	AMOMINU_D
    50  	AMOMINU_D_AQ
    51  	AMOMINU_D_AQRL
    52  	AMOMINU_D_RL
    53  	AMOMINU_W
    54  	AMOMINU_W_AQ
    55  	AMOMINU_W_AQRL
    56  	AMOMINU_W_RL
    57  	AMOMIN_D
    58  	AMOMIN_D_AQ
    59  	AMOMIN_D_AQRL
    60  	AMOMIN_D_RL
    61  	AMOMIN_W
    62  	AMOMIN_W_AQ
    63  	AMOMIN_W_AQRL
    64  	AMOMIN_W_RL
    65  	AMOOR_D
    66  	AMOOR_D_AQ
    67  	AMOOR_D_AQRL
    68  	AMOOR_D_RL
    69  	AMOOR_W
    70  	AMOOR_W_AQ
    71  	AMOOR_W_AQRL
    72  	AMOOR_W_RL
    73  	AMOSWAP_D
    74  	AMOSWAP_D_AQ
    75  	AMOSWAP_D_AQRL
    76  	AMOSWAP_D_RL
    77  	AMOSWAP_W
    78  	AMOSWAP_W_AQ
    79  	AMOSWAP_W_AQRL
    80  	AMOSWAP_W_RL
    81  	AMOXOR_D
    82  	AMOXOR_D_AQ
    83  	AMOXOR_D_AQRL
    84  	AMOXOR_D_RL
    85  	AMOXOR_W
    86  	AMOXOR_W_AQ
    87  	AMOXOR_W_AQRL
    88  	AMOXOR_W_RL
    89  	AND
    90  	ANDI
    91  	ANDN
    92  	AUIPC
    93  	BCLR
    94  	BCLRI
    95  	BEQ
    96  	BEXT
    97  	BEXTI
    98  	BGE
    99  	BGEU
   100  	BINV
   101  	BINVI
   102  	BLT
   103  	BLTU
   104  	BNE
   105  	BSET
   106  	BSETI
   107  	CLZ
   108  	CLZW
   109  	CPOP
   110  	CPOPW
   111  	CSRRC
   112  	CSRRCI
   113  	CSRRS
   114  	CSRRSI
   115  	CSRRW
   116  	CSRRWI
   117  	CTZ
   118  	CTZW
   119  	CZERO_EQZ
   120  	CZERO_NEZ
   121  	C_ADD
   122  	C_ADDI
   123  	C_ADDI16SP
   124  	C_ADDI4SPN
   125  	C_ADDIW
   126  	C_ADDW
   127  	C_AND
   128  	C_ANDI
   129  	C_BEQZ
   130  	C_BNEZ
   131  	C_EBREAK
   132  	C_FLD
   133  	C_FLDSP
   134  	C_FSD
   135  	C_FSDSP
   136  	C_J
   137  	C_JALR
   138  	C_JR
   139  	C_LD
   140  	C_LDSP
   141  	C_LI
   142  	C_LUI
   143  	C_LW
   144  	C_LWSP
   145  	C_MV
   146  	C_NOP
   147  	C_OR
   148  	C_SD
   149  	C_SDSP
   150  	C_SLLI
   151  	C_SRAI
   152  	C_SRLI
   153  	C_SUB
   154  	C_SUBW
   155  	C_SW
   156  	C_SWSP
   157  	C_UNIMP
   158  	C_XOR
   159  	DIV
   160  	DIVU
   161  	DIVUW
   162  	DIVW
   163  	EBREAK
   164  	ECALL
   165  	FADD_D
   166  	FADD_H
   167  	FADD_Q
   168  	FADD_S
   169  	FCLASS_D
   170  	FCLASS_H
   171  	FCLASS_Q
   172  	FCLASS_S
   173  	FCVT_D_L
   174  	FCVT_D_LU
   175  	FCVT_D_Q
   176  	FCVT_D_S
   177  	FCVT_D_W
   178  	FCVT_D_WU
   179  	FCVT_H_L
   180  	FCVT_H_LU
   181  	FCVT_H_S
   182  	FCVT_H_W
   183  	FCVT_H_WU
   184  	FCVT_LU_D
   185  	FCVT_LU_H
   186  	FCVT_LU_Q
   187  	FCVT_LU_S
   188  	FCVT_L_D
   189  	FCVT_L_H
   190  	FCVT_L_Q
   191  	FCVT_L_S
   192  	FCVT_Q_D
   193  	FCVT_Q_L
   194  	FCVT_Q_LU
   195  	FCVT_Q_S
   196  	FCVT_Q_W
   197  	FCVT_Q_WU
   198  	FCVT_S_D
   199  	FCVT_S_H
   200  	FCVT_S_L
   201  	FCVT_S_LU
   202  	FCVT_S_Q
   203  	FCVT_S_W
   204  	FCVT_S_WU
   205  	FCVT_WU_D
   206  	FCVT_WU_H
   207  	FCVT_WU_Q
   208  	FCVT_WU_S
   209  	FCVT_W_D
   210  	FCVT_W_H
   211  	FCVT_W_Q
   212  	FCVT_W_S
   213  	FDIV_D
   214  	FDIV_H
   215  	FDIV_Q
   216  	FDIV_S
   217  	FENCE
   218  	FENCE_I
   219  	FEQ_D
   220  	FEQ_H
   221  	FEQ_Q
   222  	FEQ_S
   223  	FLD
   224  	FLE_D
   225  	FLE_H
   226  	FLE_Q
   227  	FLE_S
   228  	FLH
   229  	FLQ
   230  	FLT_D
   231  	FLT_H
   232  	FLT_Q
   233  	FLT_S
   234  	FLW
   235  	FMADD_D
   236  	FMADD_H
   237  	FMADD_Q
   238  	FMADD_S
   239  	FMAX_D
   240  	FMAX_H
   241  	FMAX_Q
   242  	FMAX_S
   243  	FMIN_D
   244  	FMIN_H
   245  	FMIN_Q
   246  	FMIN_S
   247  	FMSUB_D
   248  	FMSUB_H
   249  	FMSUB_Q
   250  	FMSUB_S
   251  	FMUL_D
   252  	FMUL_H
   253  	FMUL_Q
   254  	FMUL_S
   255  	FMV_D_X
   256  	FMV_H_X
   257  	FMV_W_X
   258  	FMV_X_D
   259  	FMV_X_H
   260  	FMV_X_W
   261  	FNMADD_D
   262  	FNMADD_H
   263  	FNMADD_Q
   264  	FNMADD_S
   265  	FNMSUB_D
   266  	FNMSUB_H
   267  	FNMSUB_Q
   268  	FNMSUB_S
   269  	FSD
   270  	FSGNJN_D
   271  	FSGNJN_H
   272  	FSGNJN_Q
   273  	FSGNJN_S
   274  	FSGNJX_D
   275  	FSGNJX_H
   276  	FSGNJX_Q
   277  	FSGNJX_S
   278  	FSGNJ_D
   279  	FSGNJ_H
   280  	FSGNJ_Q
   281  	FSGNJ_S
   282  	FSH
   283  	FSQ
   284  	FSQRT_D
   285  	FSQRT_H
   286  	FSQRT_Q
   287  	FSQRT_S
   288  	FSUB_D
   289  	FSUB_H
   290  	FSUB_Q
   291  	FSUB_S
   292  	FSW
   293  	JAL
   294  	JALR
   295  	LB
   296  	LBU
   297  	LD
   298  	LH
   299  	LHU
   300  	LR_D
   301  	LR_D_AQ
   302  	LR_D_AQRL
   303  	LR_D_RL
   304  	LR_W
   305  	LR_W_AQ
   306  	LR_W_AQRL
   307  	LR_W_RL
   308  	LUI
   309  	LW
   310  	LWU
   311  	MAX
   312  	MAXU
   313  	MIN
   314  	MINU
   315  	MUL
   316  	MULH
   317  	MULHSU
   318  	MULHU
   319  	MULW
   320  	OR
   321  	ORC_B
   322  	ORI
   323  	ORN
   324  	REM
   325  	REMU
   326  	REMUW
   327  	REMW
   328  	REV8
   329  	ROL
   330  	ROLW
   331  	ROR
   332  	RORI
   333  	RORIW
   334  	RORW
   335  	SB
   336  	SC_D
   337  	SC_D_AQ
   338  	SC_D_AQRL
   339  	SC_D_RL
   340  	SC_W
   341  	SC_W_AQ
   342  	SC_W_AQRL
   343  	SC_W_RL
   344  	SD
   345  	SEXT_B
   346  	SEXT_H
   347  	SH
   348  	SH1ADD
   349  	SH1ADD_UW
   350  	SH2ADD
   351  	SH2ADD_UW
   352  	SH3ADD
   353  	SH3ADD_UW
   354  	SLL
   355  	SLLI
   356  	SLLIW
   357  	SLLI_UW
   358  	SLLW
   359  	SLT
   360  	SLTI
   361  	SLTIU
   362  	SLTU
   363  	SRA
   364  	SRAI
   365  	SRAIW
   366  	SRAW
   367  	SRL
   368  	SRLI
   369  	SRLIW
   370  	SRLW
   371  	SUB
   372  	SUBW
   373  	SW
   374  	VAADDU_VV
   375  	VAADDU_VX
   376  	VAADD_VV
   377  	VAADD_VX
   378  	VADC_VIM
   379  	VADC_VVM
   380  	VADC_VXM
   381  	VADD_VI
   382  	VADD_VV
   383  	VADD_VX
   384  	VAND_VI
   385  	VAND_VV
   386  	VAND_VX
   387  	VASUBU_VV
   388  	VASUBU_VX
   389  	VASUB_VV
   390  	VASUB_VX
   391  	VCOMPRESS_VM
   392  	VCPOP_M
   393  	VDIVU_VV
   394  	VDIVU_VX
   395  	VDIV_VV
   396  	VDIV_VX
   397  	VFADD_VF
   398  	VFADD_VV
   399  	VFCLASS_V
   400  	VFCVT_F_XU_V
   401  	VFCVT_F_X_V
   402  	VFCVT_RTZ_XU_F_V
   403  	VFCVT_RTZ_X_F_V
   404  	VFCVT_XU_F_V
   405  	VFCVT_X_F_V
   406  	VFDIV_VF
   407  	VFDIV_VV
   408  	VFIRST_M
   409  	VFMACC_VF
   410  	VFMACC_VV
   411  	VFMADD_VF
   412  	VFMADD_VV
   413  	VFMAX_VF
   414  	VFMAX_VV
   415  	VFMERGE_VFM
   416  	VFMIN_VF
   417  	VFMIN_VV
   418  	VFMSAC_VF
   419  	VFMSAC_VV
   420  	VFMSUB_VF
   421  	VFMSUB_VV
   422  	VFMUL_VF
   423  	VFMUL_VV
   424  	VFMV_F_S
   425  	VFMV_S_F
   426  	VFMV_V_F
   427  	VFNCVT_F_F_W
   428  	VFNCVT_F_XU_W
   429  	VFNCVT_F_X_W
   430  	VFNCVT_ROD_F_F_W
   431  	VFNCVT_RTZ_XU_F_W
   432  	VFNCVT_RTZ_X_F_W
   433  	VFNCVT_XU_F_W
   434  	VFNCVT_X_F_W
   435  	VFNMACC_VF
   436  	VFNMACC_VV
   437  	VFNMADD_VF
   438  	VFNMADD_VV
   439  	VFNMSAC_VF
   440  	VFNMSAC_VV
   441  	VFNMSUB_VF
   442  	VFNMSUB_VV
   443  	VFRDIV_VF
   444  	VFREC7_V
   445  	VFREDMAX_VS
   446  	VFREDMIN_VS
   447  	VFREDOSUM_VS
   448  	VFREDUSUM_VS
   449  	VFRSQRT7_V
   450  	VFRSUB_VF
   451  	VFSGNJN_VF
   452  	VFSGNJN_VV
   453  	VFSGNJX_VF
   454  	VFSGNJX_VV
   455  	VFSGNJ_VF
   456  	VFSGNJ_VV
   457  	VFSLIDE1DOWN_VF
   458  	VFSLIDE1UP_VF
   459  	VFSQRT_V
   460  	VFSUB_VF
   461  	VFSUB_VV
   462  	VFWADD_VF
   463  	VFWADD_VV
   464  	VFWADD_WF
   465  	VFWADD_WV
   466  	VFWCVT_F_F_V
   467  	VFWCVT_F_XU_V
   468  	VFWCVT_F_X_V
   469  	VFWCVT_RTZ_XU_F_V
   470  	VFWCVT_RTZ_X_F_V
   471  	VFWCVT_XU_F_V
   472  	VFWCVT_X_F_V
   473  	VFWMACC_VF
   474  	VFWMACC_VV
   475  	VFWMSAC_VF
   476  	VFWMSAC_VV
   477  	VFWMUL_VF
   478  	VFWMUL_VV
   479  	VFWNMACC_VF
   480  	VFWNMACC_VV
   481  	VFWNMSAC_VF
   482  	VFWNMSAC_VV
   483  	VFWREDOSUM_VS
   484  	VFWREDUSUM_VS
   485  	VFWSUB_VF
   486  	VFWSUB_VV
   487  	VFWSUB_WF
   488  	VFWSUB_WV
   489  	VID_V
   490  	VIOTA_M
   491  	VL1RE16_V
   492  	VL1RE32_V
   493  	VL1RE64_V
   494  	VL1RE8_V
   495  	VL2RE16_V
   496  	VL2RE32_V
   497  	VL2RE64_V
   498  	VL2RE8_V
   499  	VL4RE16_V
   500  	VL4RE32_V
   501  	VL4RE64_V
   502  	VL4RE8_V
   503  	VL8RE16_V
   504  	VL8RE32_V
   505  	VL8RE64_V
   506  	VL8RE8_V
   507  	VLE16FF_V
   508  	VLE16_V
   509  	VLE32FF_V
   510  	VLE32_V
   511  	VLE64FF_V
   512  	VLE64_V
   513  	VLE8FF_V
   514  	VLE8_V
   515  	VLM_V
   516  	VLOXEI16_V
   517  	VLOXEI32_V
   518  	VLOXEI64_V
   519  	VLOXEI8_V
   520  	VLOXSEG2EI16_V
   521  	VLOXSEG2EI32_V
   522  	VLOXSEG2EI64_V
   523  	VLOXSEG2EI8_V
   524  	VLOXSEG3EI16_V
   525  	VLOXSEG3EI32_V
   526  	VLOXSEG3EI64_V
   527  	VLOXSEG3EI8_V
   528  	VLOXSEG4EI16_V
   529  	VLOXSEG4EI32_V
   530  	VLOXSEG4EI64_V
   531  	VLOXSEG4EI8_V
   532  	VLOXSEG5EI16_V
   533  	VLOXSEG5EI32_V
   534  	VLOXSEG5EI64_V
   535  	VLOXSEG5EI8_V
   536  	VLOXSEG6EI16_V
   537  	VLOXSEG6EI32_V
   538  	VLOXSEG6EI64_V
   539  	VLOXSEG6EI8_V
   540  	VLOXSEG7EI16_V
   541  	VLOXSEG7EI32_V
   542  	VLOXSEG7EI64_V
   543  	VLOXSEG7EI8_V
   544  	VLOXSEG8EI16_V
   545  	VLOXSEG8EI32_V
   546  	VLOXSEG8EI64_V
   547  	VLOXSEG8EI8_V
   548  	VLSE16_V
   549  	VLSE32_V
   550  	VLSE64_V
   551  	VLSE8_V
   552  	VLSEG2E16FF_V
   553  	VLSEG2E16_V
   554  	VLSEG2E32FF_V
   555  	VLSEG2E32_V
   556  	VLSEG2E64FF_V
   557  	VLSEG2E64_V
   558  	VLSEG2E8FF_V
   559  	VLSEG2E8_V
   560  	VLSEG3E16FF_V
   561  	VLSEG3E16_V
   562  	VLSEG3E32FF_V
   563  	VLSEG3E32_V
   564  	VLSEG3E64FF_V
   565  	VLSEG3E64_V
   566  	VLSEG3E8FF_V
   567  	VLSEG3E8_V
   568  	VLSEG4E16FF_V
   569  	VLSEG4E16_V
   570  	VLSEG4E32FF_V
   571  	VLSEG4E32_V
   572  	VLSEG4E64FF_V
   573  	VLSEG4E64_V
   574  	VLSEG4E8FF_V
   575  	VLSEG4E8_V
   576  	VLSEG5E16FF_V
   577  	VLSEG5E16_V
   578  	VLSEG5E32FF_V
   579  	VLSEG5E32_V
   580  	VLSEG5E64FF_V
   581  	VLSEG5E64_V
   582  	VLSEG5E8FF_V
   583  	VLSEG5E8_V
   584  	VLSEG6E16FF_V
   585  	VLSEG6E16_V
   586  	VLSEG6E32FF_V
   587  	VLSEG6E32_V
   588  	VLSEG6E64FF_V
   589  	VLSEG6E64_V
   590  	VLSEG6E8FF_V
   591  	VLSEG6E8_V
   592  	VLSEG7E16FF_V
   593  	VLSEG7E16_V
   594  	VLSEG7E32FF_V
   595  	VLSEG7E32_V
   596  	VLSEG7E64FF_V
   597  	VLSEG7E64_V
   598  	VLSEG7E8FF_V
   599  	VLSEG7E8_V
   600  	VLSEG8E16FF_V
   601  	VLSEG8E16_V
   602  	VLSEG8E32FF_V
   603  	VLSEG8E32_V
   604  	VLSEG8E64FF_V
   605  	VLSEG8E64_V
   606  	VLSEG8E8FF_V
   607  	VLSEG8E8_V
   608  	VLSSEG2E16_V
   609  	VLSSEG2E32_V
   610  	VLSSEG2E64_V
   611  	VLSSEG2E8_V
   612  	VLSSEG3E16_V
   613  	VLSSEG3E32_V
   614  	VLSSEG3E64_V
   615  	VLSSEG3E8_V
   616  	VLSSEG4E16_V
   617  	VLSSEG4E32_V
   618  	VLSSEG4E64_V
   619  	VLSSEG4E8_V
   620  	VLSSEG5E16_V
   621  	VLSSEG5E32_V
   622  	VLSSEG5E64_V
   623  	VLSSEG5E8_V
   624  	VLSSEG6E16_V
   625  	VLSSEG6E32_V
   626  	VLSSEG6E64_V
   627  	VLSSEG6E8_V
   628  	VLSSEG7E16_V
   629  	VLSSEG7E32_V
   630  	VLSSEG7E64_V
   631  	VLSSEG7E8_V
   632  	VLSSEG8E16_V
   633  	VLSSEG8E32_V
   634  	VLSSEG8E64_V
   635  	VLSSEG8E8_V
   636  	VLUXEI16_V
   637  	VLUXEI32_V
   638  	VLUXEI64_V
   639  	VLUXEI8_V
   640  	VLUXSEG2EI16_V
   641  	VLUXSEG2EI32_V
   642  	VLUXSEG2EI64_V
   643  	VLUXSEG2EI8_V
   644  	VLUXSEG3EI16_V
   645  	VLUXSEG3EI32_V
   646  	VLUXSEG3EI64_V
   647  	VLUXSEG3EI8_V
   648  	VLUXSEG4EI16_V
   649  	VLUXSEG4EI32_V
   650  	VLUXSEG4EI64_V
   651  	VLUXSEG4EI8_V
   652  	VLUXSEG5EI16_V
   653  	VLUXSEG5EI32_V
   654  	VLUXSEG5EI64_V
   655  	VLUXSEG5EI8_V
   656  	VLUXSEG6EI16_V
   657  	VLUXSEG6EI32_V
   658  	VLUXSEG6EI64_V
   659  	VLUXSEG6EI8_V
   660  	VLUXSEG7EI16_V
   661  	VLUXSEG7EI32_V
   662  	VLUXSEG7EI64_V
   663  	VLUXSEG7EI8_V
   664  	VLUXSEG8EI16_V
   665  	VLUXSEG8EI32_V
   666  	VLUXSEG8EI64_V
   667  	VLUXSEG8EI8_V
   668  	VMACC_VV
   669  	VMACC_VX
   670  	VMADC_VI
   671  	VMADC_VIM
   672  	VMADC_VV
   673  	VMADC_VVM
   674  	VMADC_VX
   675  	VMADC_VXM
   676  	VMADD_VV
   677  	VMADD_VX
   678  	VMANDN_MM
   679  	VMAND_MM
   680  	VMAXU_VV
   681  	VMAXU_VX
   682  	VMAX_VV
   683  	VMAX_VX
   684  	VMERGE_VIM
   685  	VMERGE_VVM
   686  	VMERGE_VXM
   687  	VMFEQ_VF
   688  	VMFEQ_VV
   689  	VMFGE_VF
   690  	VMFGT_VF
   691  	VMFLE_VF
   692  	VMFLE_VV
   693  	VMFLT_VF
   694  	VMFLT_VV
   695  	VMFNE_VF
   696  	VMFNE_VV
   697  	VMINU_VV
   698  	VMINU_VX
   699  	VMIN_VV
   700  	VMIN_VX
   701  	VMNAND_MM
   702  	VMNOR_MM
   703  	VMORN_MM
   704  	VMOR_MM
   705  	VMSBC_VV
   706  	VMSBC_VVM
   707  	VMSBC_VX
   708  	VMSBC_VXM
   709  	VMSBF_M
   710  	VMSEQ_VI
   711  	VMSEQ_VV
   712  	VMSEQ_VX
   713  	VMSGTU_VI
   714  	VMSGTU_VX
   715  	VMSGT_VI
   716  	VMSGT_VX
   717  	VMSIF_M
   718  	VMSLEU_VI
   719  	VMSLEU_VV
   720  	VMSLEU_VX
   721  	VMSLE_VI
   722  	VMSLE_VV
   723  	VMSLE_VX
   724  	VMSLTU_VV
   725  	VMSLTU_VX
   726  	VMSLT_VV
   727  	VMSLT_VX
   728  	VMSNE_VI
   729  	VMSNE_VV
   730  	VMSNE_VX
   731  	VMSOF_M
   732  	VMULHSU_VV
   733  	VMULHSU_VX
   734  	VMULHU_VV
   735  	VMULHU_VX
   736  	VMULH_VV
   737  	VMULH_VX
   738  	VMUL_VV
   739  	VMUL_VX
   740  	VMV1R_V
   741  	VMV2R_V
   742  	VMV4R_V
   743  	VMV8R_V
   744  	VMV_S_X
   745  	VMV_V_I
   746  	VMV_V_V
   747  	VMV_V_X
   748  	VMV_X_S
   749  	VMXNOR_MM
   750  	VMXOR_MM
   751  	VNCLIPU_WI
   752  	VNCLIPU_WV
   753  	VNCLIPU_WX
   754  	VNCLIP_WI
   755  	VNCLIP_WV
   756  	VNCLIP_WX
   757  	VNMSAC_VV
   758  	VNMSAC_VX
   759  	VNMSUB_VV
   760  	VNMSUB_VX
   761  	VNSRA_WI
   762  	VNSRA_WV
   763  	VNSRA_WX
   764  	VNSRL_WI
   765  	VNSRL_WV
   766  	VNSRL_WX
   767  	VOR_VI
   768  	VOR_VV
   769  	VOR_VX
   770  	VREDAND_VS
   771  	VREDMAXU_VS
   772  	VREDMAX_VS
   773  	VREDMINU_VS
   774  	VREDMIN_VS
   775  	VREDOR_VS
   776  	VREDSUM_VS
   777  	VREDXOR_VS
   778  	VREMU_VV
   779  	VREMU_VX
   780  	VREM_VV
   781  	VREM_VX
   782  	VRGATHEREI16_VV
   783  	VRGATHER_VI
   784  	VRGATHER_VV
   785  	VRGATHER_VX
   786  	VRSUB_VI
   787  	VRSUB_VX
   788  	VS1R_V
   789  	VS2R_V
   790  	VS4R_V
   791  	VS8R_V
   792  	VSADDU_VI
   793  	VSADDU_VV
   794  	VSADDU_VX
   795  	VSADD_VI
   796  	VSADD_VV
   797  	VSADD_VX
   798  	VSBC_VVM
   799  	VSBC_VXM
   800  	VSE16_V
   801  	VSE32_V
   802  	VSE64_V
   803  	VSE8_V
   804  	VSETIVLI
   805  	VSETVL
   806  	VSETVLI
   807  	VSEXT_VF2
   808  	VSEXT_VF4
   809  	VSEXT_VF8
   810  	VSLIDE1DOWN_VX
   811  	VSLIDE1UP_VX
   812  	VSLIDEDOWN_VI
   813  	VSLIDEDOWN_VX
   814  	VSLIDEUP_VI
   815  	VSLIDEUP_VX
   816  	VSLL_VI
   817  	VSLL_VV
   818  	VSLL_VX
   819  	VSMUL_VV
   820  	VSMUL_VX
   821  	VSM_V
   822  	VSOXEI16_V
   823  	VSOXEI32_V
   824  	VSOXEI64_V
   825  	VSOXEI8_V
   826  	VSOXSEG2EI16_V
   827  	VSOXSEG2EI32_V
   828  	VSOXSEG2EI64_V
   829  	VSOXSEG2EI8_V
   830  	VSOXSEG3EI16_V
   831  	VSOXSEG3EI32_V
   832  	VSOXSEG3EI64_V
   833  	VSOXSEG3EI8_V
   834  	VSOXSEG4EI16_V
   835  	VSOXSEG4EI32_V
   836  	VSOXSEG4EI64_V
   837  	VSOXSEG4EI8_V
   838  	VSOXSEG5EI16_V
   839  	VSOXSEG5EI32_V
   840  	VSOXSEG5EI64_V
   841  	VSOXSEG5EI8_V
   842  	VSOXSEG6EI16_V
   843  	VSOXSEG6EI32_V
   844  	VSOXSEG6EI64_V
   845  	VSOXSEG6EI8_V
   846  	VSOXSEG7EI16_V
   847  	VSOXSEG7EI32_V
   848  	VSOXSEG7EI64_V
   849  	VSOXSEG7EI8_V
   850  	VSOXSEG8EI16_V
   851  	VSOXSEG8EI32_V
   852  	VSOXSEG8EI64_V
   853  	VSOXSEG8EI8_V
   854  	VSRA_VI
   855  	VSRA_VV
   856  	VSRA_VX
   857  	VSRL_VI
   858  	VSRL_VV
   859  	VSRL_VX
   860  	VSSE16_V
   861  	VSSE32_V
   862  	VSSE64_V
   863  	VSSE8_V
   864  	VSSEG2E16_V
   865  	VSSEG2E32_V
   866  	VSSEG2E64_V
   867  	VSSEG2E8_V
   868  	VSSEG3E16_V
   869  	VSSEG3E32_V
   870  	VSSEG3E64_V
   871  	VSSEG3E8_V
   872  	VSSEG4E16_V
   873  	VSSEG4E32_V
   874  	VSSEG4E64_V
   875  	VSSEG4E8_V
   876  	VSSEG5E16_V
   877  	VSSEG5E32_V
   878  	VSSEG5E64_V
   879  	VSSEG5E8_V
   880  	VSSEG6E16_V
   881  	VSSEG6E32_V
   882  	VSSEG6E64_V
   883  	VSSEG6E8_V
   884  	VSSEG7E16_V
   885  	VSSEG7E32_V
   886  	VSSEG7E64_V
   887  	VSSEG7E8_V
   888  	VSSEG8E16_V
   889  	VSSEG8E32_V
   890  	VSSEG8E64_V
   891  	VSSEG8E8_V
   892  	VSSRA_VI
   893  	VSSRA_VV
   894  	VSSRA_VX
   895  	VSSRL_VI
   896  	VSSRL_VV
   897  	VSSRL_VX
   898  	VSSSEG2E16_V
   899  	VSSSEG2E32_V
   900  	VSSSEG2E64_V
   901  	VSSSEG2E8_V
   902  	VSSSEG3E16_V
   903  	VSSSEG3E32_V
   904  	VSSSEG3E64_V
   905  	VSSSEG3E8_V
   906  	VSSSEG4E16_V
   907  	VSSSEG4E32_V
   908  	VSSSEG4E64_V
   909  	VSSSEG4E8_V
   910  	VSSSEG5E16_V
   911  	VSSSEG5E32_V
   912  	VSSSEG5E64_V
   913  	VSSSEG5E8_V
   914  	VSSSEG6E16_V
   915  	VSSSEG6E32_V
   916  	VSSSEG6E64_V
   917  	VSSSEG6E8_V
   918  	VSSSEG7E16_V
   919  	VSSSEG7E32_V
   920  	VSSSEG7E64_V
   921  	VSSSEG7E8_V
   922  	VSSSEG8E16_V
   923  	VSSSEG8E32_V
   924  	VSSSEG8E64_V
   925  	VSSSEG8E8_V
   926  	VSSUBU_VV
   927  	VSSUBU_VX
   928  	VSSUB_VV
   929  	VSSUB_VX
   930  	VSUB_VV
   931  	VSUB_VX
   932  	VSUXEI16_V
   933  	VSUXEI32_V
   934  	VSUXEI64_V
   935  	VSUXEI8_V
   936  	VSUXSEG2EI16_V
   937  	VSUXSEG2EI32_V
   938  	VSUXSEG2EI64_V
   939  	VSUXSEG2EI8_V
   940  	VSUXSEG3EI16_V
   941  	VSUXSEG3EI32_V
   942  	VSUXSEG3EI64_V
   943  	VSUXSEG3EI8_V
   944  	VSUXSEG4EI16_V
   945  	VSUXSEG4EI32_V
   946  	VSUXSEG4EI64_V
   947  	VSUXSEG4EI8_V
   948  	VSUXSEG5EI16_V
   949  	VSUXSEG5EI32_V
   950  	VSUXSEG5EI64_V
   951  	VSUXSEG5EI8_V
   952  	VSUXSEG6EI16_V
   953  	VSUXSEG6EI32_V
   954  	VSUXSEG6EI64_V
   955  	VSUXSEG6EI8_V
   956  	VSUXSEG7EI16_V
   957  	VSUXSEG7EI32_V
   958  	VSUXSEG7EI64_V
   959  	VSUXSEG7EI8_V
   960  	VSUXSEG8EI16_V
   961  	VSUXSEG8EI32_V
   962  	VSUXSEG8EI64_V
   963  	VSUXSEG8EI8_V
   964  	VWADDU_VV
   965  	VWADDU_VX
   966  	VWADDU_WV
   967  	VWADDU_WX
   968  	VWADD_VV
   969  	VWADD_VX
   970  	VWADD_WV
   971  	VWADD_WX
   972  	VWMACCSU_VV
   973  	VWMACCSU_VX
   974  	VWMACCUS_VX
   975  	VWMACCU_VV
   976  	VWMACCU_VX
   977  	VWMACC_VV
   978  	VWMACC_VX
   979  	VWMULSU_VV
   980  	VWMULSU_VX
   981  	VWMULU_VV
   982  	VWMULU_VX
   983  	VWMUL_VV
   984  	VWMUL_VX
   985  	VWREDSUMU_VS
   986  	VWREDSUM_VS
   987  	VWSUBU_VV
   988  	VWSUBU_VX
   989  	VWSUBU_WV
   990  	VWSUBU_WX
   991  	VWSUB_VV
   992  	VWSUB_VX
   993  	VWSUB_WV
   994  	VWSUB_WX
   995  	VXOR_VI
   996  	VXOR_VV
   997  	VXOR_VX
   998  	VZEXT_VF2
   999  	VZEXT_VF4
  1000  	VZEXT_VF8
  1001  	XNOR
  1002  	XOR
  1003  	XORI
  1004  	ZEXT_H
  1005  )
  1006  
  1007  var opstr = [...]string{
  1008  	ADD:               "ADD",
  1009  	ADDI:              "ADDI",
  1010  	ADDIW:             "ADDIW",
  1011  	ADDW:              "ADDW",
  1012  	ADD_UW:            "ADD.UW",
  1013  	AMOADD_D:          "AMOADD.D",
  1014  	AMOADD_D_AQ:       "AMOADD.D.AQ",
  1015  	AMOADD_D_AQRL:     "AMOADD.D.AQRL",
  1016  	AMOADD_D_RL:       "AMOADD.D.RL",
  1017  	AMOADD_W:          "AMOADD.W",
  1018  	AMOADD_W_AQ:       "AMOADD.W.AQ",
  1019  	AMOADD_W_AQRL:     "AMOADD.W.AQRL",
  1020  	AMOADD_W_RL:       "AMOADD.W.RL",
  1021  	AMOAND_D:          "AMOAND.D",
  1022  	AMOAND_D_AQ:       "AMOAND.D.AQ",
  1023  	AMOAND_D_AQRL:     "AMOAND.D.AQRL",
  1024  	AMOAND_D_RL:       "AMOAND.D.RL",
  1025  	AMOAND_W:          "AMOAND.W",
  1026  	AMOAND_W_AQ:       "AMOAND.W.AQ",
  1027  	AMOAND_W_AQRL:     "AMOAND.W.AQRL",
  1028  	AMOAND_W_RL:       "AMOAND.W.RL",
  1029  	AMOMAXU_D:         "AMOMAXU.D",
  1030  	AMOMAXU_D_AQ:      "AMOMAXU.D.AQ",
  1031  	AMOMAXU_D_AQRL:    "AMOMAXU.D.AQRL",
  1032  	AMOMAXU_D_RL:      "AMOMAXU.D.RL",
  1033  	AMOMAXU_W:         "AMOMAXU.W",
  1034  	AMOMAXU_W_AQ:      "AMOMAXU.W.AQ",
  1035  	AMOMAXU_W_AQRL:    "AMOMAXU.W.AQRL",
  1036  	AMOMAXU_W_RL:      "AMOMAXU.W.RL",
  1037  	AMOMAX_D:          "AMOMAX.D",
  1038  	AMOMAX_D_AQ:       "AMOMAX.D.AQ",
  1039  	AMOMAX_D_AQRL:     "AMOMAX.D.AQRL",
  1040  	AMOMAX_D_RL:       "AMOMAX.D.RL",
  1041  	AMOMAX_W:          "AMOMAX.W",
  1042  	AMOMAX_W_AQ:       "AMOMAX.W.AQ",
  1043  	AMOMAX_W_AQRL:     "AMOMAX.W.AQRL",
  1044  	AMOMAX_W_RL:       "AMOMAX.W.RL",
  1045  	AMOMINU_D:         "AMOMINU.D",
  1046  	AMOMINU_D_AQ:      "AMOMINU.D.AQ",
  1047  	AMOMINU_D_AQRL:    "AMOMINU.D.AQRL",
  1048  	AMOMINU_D_RL:      "AMOMINU.D.RL",
  1049  	AMOMINU_W:         "AMOMINU.W",
  1050  	AMOMINU_W_AQ:      "AMOMINU.W.AQ",
  1051  	AMOMINU_W_AQRL:    "AMOMINU.W.AQRL",
  1052  	AMOMINU_W_RL:      "AMOMINU.W.RL",
  1053  	AMOMIN_D:          "AMOMIN.D",
  1054  	AMOMIN_D_AQ:       "AMOMIN.D.AQ",
  1055  	AMOMIN_D_AQRL:     "AMOMIN.D.AQRL",
  1056  	AMOMIN_D_RL:       "AMOMIN.D.RL",
  1057  	AMOMIN_W:          "AMOMIN.W",
  1058  	AMOMIN_W_AQ:       "AMOMIN.W.AQ",
  1059  	AMOMIN_W_AQRL:     "AMOMIN.W.AQRL",
  1060  	AMOMIN_W_RL:       "AMOMIN.W.RL",
  1061  	AMOOR_D:           "AMOOR.D",
  1062  	AMOOR_D_AQ:        "AMOOR.D.AQ",
  1063  	AMOOR_D_AQRL:      "AMOOR.D.AQRL",
  1064  	AMOOR_D_RL:        "AMOOR.D.RL",
  1065  	AMOOR_W:           "AMOOR.W",
  1066  	AMOOR_W_AQ:        "AMOOR.W.AQ",
  1067  	AMOOR_W_AQRL:      "AMOOR.W.AQRL",
  1068  	AMOOR_W_RL:        "AMOOR.W.RL",
  1069  	AMOSWAP_D:         "AMOSWAP.D",
  1070  	AMOSWAP_D_AQ:      "AMOSWAP.D.AQ",
  1071  	AMOSWAP_D_AQRL:    "AMOSWAP.D.AQRL",
  1072  	AMOSWAP_D_RL:      "AMOSWAP.D.RL",
  1073  	AMOSWAP_W:         "AMOSWAP.W",
  1074  	AMOSWAP_W_AQ:      "AMOSWAP.W.AQ",
  1075  	AMOSWAP_W_AQRL:    "AMOSWAP.W.AQRL",
  1076  	AMOSWAP_W_RL:      "AMOSWAP.W.RL",
  1077  	AMOXOR_D:          "AMOXOR.D",
  1078  	AMOXOR_D_AQ:       "AMOXOR.D.AQ",
  1079  	AMOXOR_D_AQRL:     "AMOXOR.D.AQRL",
  1080  	AMOXOR_D_RL:       "AMOXOR.D.RL",
  1081  	AMOXOR_W:          "AMOXOR.W",
  1082  	AMOXOR_W_AQ:       "AMOXOR.W.AQ",
  1083  	AMOXOR_W_AQRL:     "AMOXOR.W.AQRL",
  1084  	AMOXOR_W_RL:       "AMOXOR.W.RL",
  1085  	AND:               "AND",
  1086  	ANDI:              "ANDI",
  1087  	ANDN:              "ANDN",
  1088  	AUIPC:             "AUIPC",
  1089  	BCLR:              "BCLR",
  1090  	BCLRI:             "BCLRI",
  1091  	BEQ:               "BEQ",
  1092  	BEXT:              "BEXT",
  1093  	BEXTI:             "BEXTI",
  1094  	BGE:               "BGE",
  1095  	BGEU:              "BGEU",
  1096  	BINV:              "BINV",
  1097  	BINVI:             "BINVI",
  1098  	BLT:               "BLT",
  1099  	BLTU:              "BLTU",
  1100  	BNE:               "BNE",
  1101  	BSET:              "BSET",
  1102  	BSETI:             "BSETI",
  1103  	CLZ:               "CLZ",
  1104  	CLZW:              "CLZW",
  1105  	CPOP:              "CPOP",
  1106  	CPOPW:             "CPOPW",
  1107  	CSRRC:             "CSRRC",
  1108  	CSRRCI:            "CSRRCI",
  1109  	CSRRS:             "CSRRS",
  1110  	CSRRSI:            "CSRRSI",
  1111  	CSRRW:             "CSRRW",
  1112  	CSRRWI:            "CSRRWI",
  1113  	CTZ:               "CTZ",
  1114  	CTZW:              "CTZW",
  1115  	CZERO_EQZ:         "CZERO.EQZ",
  1116  	CZERO_NEZ:         "CZERO.NEZ",
  1117  	C_ADD:             "C.ADD",
  1118  	C_ADDI:            "C.ADDI",
  1119  	C_ADDI16SP:        "C.ADDI16SP",
  1120  	C_ADDI4SPN:        "C.ADDI4SPN",
  1121  	C_ADDIW:           "C.ADDIW",
  1122  	C_ADDW:            "C.ADDW",
  1123  	C_AND:             "C.AND",
  1124  	C_ANDI:            "C.ANDI",
  1125  	C_BEQZ:            "C.BEQZ",
  1126  	C_BNEZ:            "C.BNEZ",
  1127  	C_EBREAK:          "C.EBREAK",
  1128  	C_FLD:             "C.FLD",
  1129  	C_FLDSP:           "C.FLDSP",
  1130  	C_FSD:             "C.FSD",
  1131  	C_FSDSP:           "C.FSDSP",
  1132  	C_J:               "C.J",
  1133  	C_JALR:            "C.JALR",
  1134  	C_JR:              "C.JR",
  1135  	C_LD:              "C.LD",
  1136  	C_LDSP:            "C.LDSP",
  1137  	C_LI:              "C.LI",
  1138  	C_LUI:             "C.LUI",
  1139  	C_LW:              "C.LW",
  1140  	C_LWSP:            "C.LWSP",
  1141  	C_MV:              "C.MV",
  1142  	C_NOP:             "C.NOP",
  1143  	C_OR:              "C.OR",
  1144  	C_SD:              "C.SD",
  1145  	C_SDSP:            "C.SDSP",
  1146  	C_SLLI:            "C.SLLI",
  1147  	C_SRAI:            "C.SRAI",
  1148  	C_SRLI:            "C.SRLI",
  1149  	C_SUB:             "C.SUB",
  1150  	C_SUBW:            "C.SUBW",
  1151  	C_SW:              "C.SW",
  1152  	C_SWSP:            "C.SWSP",
  1153  	C_UNIMP:           "C.UNIMP",
  1154  	C_XOR:             "C.XOR",
  1155  	DIV:               "DIV",
  1156  	DIVU:              "DIVU",
  1157  	DIVUW:             "DIVUW",
  1158  	DIVW:              "DIVW",
  1159  	EBREAK:            "EBREAK",
  1160  	ECALL:             "ECALL",
  1161  	FADD_D:            "FADD.D",
  1162  	FADD_H:            "FADD.H",
  1163  	FADD_Q:            "FADD.Q",
  1164  	FADD_S:            "FADD.S",
  1165  	FCLASS_D:          "FCLASS.D",
  1166  	FCLASS_H:          "FCLASS.H",
  1167  	FCLASS_Q:          "FCLASS.Q",
  1168  	FCLASS_S:          "FCLASS.S",
  1169  	FCVT_D_L:          "FCVT.D.L",
  1170  	FCVT_D_LU:         "FCVT.D.LU",
  1171  	FCVT_D_Q:          "FCVT.D.Q",
  1172  	FCVT_D_S:          "FCVT.D.S",
  1173  	FCVT_D_W:          "FCVT.D.W",
  1174  	FCVT_D_WU:         "FCVT.D.WU",
  1175  	FCVT_H_L:          "FCVT.H.L",
  1176  	FCVT_H_LU:         "FCVT.H.LU",
  1177  	FCVT_H_S:          "FCVT.H.S",
  1178  	FCVT_H_W:          "FCVT.H.W",
  1179  	FCVT_H_WU:         "FCVT.H.WU",
  1180  	FCVT_LU_D:         "FCVT.LU.D",
  1181  	FCVT_LU_H:         "FCVT.LU.H",
  1182  	FCVT_LU_Q:         "FCVT.LU.Q",
  1183  	FCVT_LU_S:         "FCVT.LU.S",
  1184  	FCVT_L_D:          "FCVT.L.D",
  1185  	FCVT_L_H:          "FCVT.L.H",
  1186  	FCVT_L_Q:          "FCVT.L.Q",
  1187  	FCVT_L_S:          "FCVT.L.S",
  1188  	FCVT_Q_D:          "FCVT.Q.D",
  1189  	FCVT_Q_L:          "FCVT.Q.L",
  1190  	FCVT_Q_LU:         "FCVT.Q.LU",
  1191  	FCVT_Q_S:          "FCVT.Q.S",
  1192  	FCVT_Q_W:          "FCVT.Q.W",
  1193  	FCVT_Q_WU:         "FCVT.Q.WU",
  1194  	FCVT_S_D:          "FCVT.S.D",
  1195  	FCVT_S_H:          "FCVT.S.H",
  1196  	FCVT_S_L:          "FCVT.S.L",
  1197  	FCVT_S_LU:         "FCVT.S.LU",
  1198  	FCVT_S_Q:          "FCVT.S.Q",
  1199  	FCVT_S_W:          "FCVT.S.W",
  1200  	FCVT_S_WU:         "FCVT.S.WU",
  1201  	FCVT_WU_D:         "FCVT.WU.D",
  1202  	FCVT_WU_H:         "FCVT.WU.H",
  1203  	FCVT_WU_Q:         "FCVT.WU.Q",
  1204  	FCVT_WU_S:         "FCVT.WU.S",
  1205  	FCVT_W_D:          "FCVT.W.D",
  1206  	FCVT_W_H:          "FCVT.W.H",
  1207  	FCVT_W_Q:          "FCVT.W.Q",
  1208  	FCVT_W_S:          "FCVT.W.S",
  1209  	FDIV_D:            "FDIV.D",
  1210  	FDIV_H:            "FDIV.H",
  1211  	FDIV_Q:            "FDIV.Q",
  1212  	FDIV_S:            "FDIV.S",
  1213  	FENCE:             "FENCE",
  1214  	FENCE_I:           "FENCE.I",
  1215  	FEQ_D:             "FEQ.D",
  1216  	FEQ_H:             "FEQ.H",
  1217  	FEQ_Q:             "FEQ.Q",
  1218  	FEQ_S:             "FEQ.S",
  1219  	FLD:               "FLD",
  1220  	FLE_D:             "FLE.D",
  1221  	FLE_H:             "FLE.H",
  1222  	FLE_Q:             "FLE.Q",
  1223  	FLE_S:             "FLE.S",
  1224  	FLH:               "FLH",
  1225  	FLQ:               "FLQ",
  1226  	FLT_D:             "FLT.D",
  1227  	FLT_H:             "FLT.H",
  1228  	FLT_Q:             "FLT.Q",
  1229  	FLT_S:             "FLT.S",
  1230  	FLW:               "FLW",
  1231  	FMADD_D:           "FMADD.D",
  1232  	FMADD_H:           "FMADD.H",
  1233  	FMADD_Q:           "FMADD.Q",
  1234  	FMADD_S:           "FMADD.S",
  1235  	FMAX_D:            "FMAX.D",
  1236  	FMAX_H:            "FMAX.H",
  1237  	FMAX_Q:            "FMAX.Q",
  1238  	FMAX_S:            "FMAX.S",
  1239  	FMIN_D:            "FMIN.D",
  1240  	FMIN_H:            "FMIN.H",
  1241  	FMIN_Q:            "FMIN.Q",
  1242  	FMIN_S:            "FMIN.S",
  1243  	FMSUB_D:           "FMSUB.D",
  1244  	FMSUB_H:           "FMSUB.H",
  1245  	FMSUB_Q:           "FMSUB.Q",
  1246  	FMSUB_S:           "FMSUB.S",
  1247  	FMUL_D:            "FMUL.D",
  1248  	FMUL_H:            "FMUL.H",
  1249  	FMUL_Q:            "FMUL.Q",
  1250  	FMUL_S:            "FMUL.S",
  1251  	FMV_D_X:           "FMV.D.X",
  1252  	FMV_H_X:           "FMV.H.X",
  1253  	FMV_W_X:           "FMV.W.X",
  1254  	FMV_X_D:           "FMV.X.D",
  1255  	FMV_X_H:           "FMV.X.H",
  1256  	FMV_X_W:           "FMV.X.W",
  1257  	FNMADD_D:          "FNMADD.D",
  1258  	FNMADD_H:          "FNMADD.H",
  1259  	FNMADD_Q:          "FNMADD.Q",
  1260  	FNMADD_S:          "FNMADD.S",
  1261  	FNMSUB_D:          "FNMSUB.D",
  1262  	FNMSUB_H:          "FNMSUB.H",
  1263  	FNMSUB_Q:          "FNMSUB.Q",
  1264  	FNMSUB_S:          "FNMSUB.S",
  1265  	FSD:               "FSD",
  1266  	FSGNJN_D:          "FSGNJN.D",
  1267  	FSGNJN_H:          "FSGNJN.H",
  1268  	FSGNJN_Q:          "FSGNJN.Q",
  1269  	FSGNJN_S:          "FSGNJN.S",
  1270  	FSGNJX_D:          "FSGNJX.D",
  1271  	FSGNJX_H:          "FSGNJX.H",
  1272  	FSGNJX_Q:          "FSGNJX.Q",
  1273  	FSGNJX_S:          "FSGNJX.S",
  1274  	FSGNJ_D:           "FSGNJ.D",
  1275  	FSGNJ_H:           "FSGNJ.H",
  1276  	FSGNJ_Q:           "FSGNJ.Q",
  1277  	FSGNJ_S:           "FSGNJ.S",
  1278  	FSH:               "FSH",
  1279  	FSQ:               "FSQ",
  1280  	FSQRT_D:           "FSQRT.D",
  1281  	FSQRT_H:           "FSQRT.H",
  1282  	FSQRT_Q:           "FSQRT.Q",
  1283  	FSQRT_S:           "FSQRT.S",
  1284  	FSUB_D:            "FSUB.D",
  1285  	FSUB_H:            "FSUB.H",
  1286  	FSUB_Q:            "FSUB.Q",
  1287  	FSUB_S:            "FSUB.S",
  1288  	FSW:               "FSW",
  1289  	JAL:               "JAL",
  1290  	JALR:              "JALR",
  1291  	LB:                "LB",
  1292  	LBU:               "LBU",
  1293  	LD:                "LD",
  1294  	LH:                "LH",
  1295  	LHU:               "LHU",
  1296  	LR_D:              "LR.D",
  1297  	LR_D_AQ:           "LR.D.AQ",
  1298  	LR_D_AQRL:         "LR.D.AQRL",
  1299  	LR_D_RL:           "LR.D.RL",
  1300  	LR_W:              "LR.W",
  1301  	LR_W_AQ:           "LR.W.AQ",
  1302  	LR_W_AQRL:         "LR.W.AQRL",
  1303  	LR_W_RL:           "LR.W.RL",
  1304  	LUI:               "LUI",
  1305  	LW:                "LW",
  1306  	LWU:               "LWU",
  1307  	MAX:               "MAX",
  1308  	MAXU:              "MAXU",
  1309  	MIN:               "MIN",
  1310  	MINU:              "MINU",
  1311  	MUL:               "MUL",
  1312  	MULH:              "MULH",
  1313  	MULHSU:            "MULHSU",
  1314  	MULHU:             "MULHU",
  1315  	MULW:              "MULW",
  1316  	OR:                "OR",
  1317  	ORC_B:             "ORC.B",
  1318  	ORI:               "ORI",
  1319  	ORN:               "ORN",
  1320  	REM:               "REM",
  1321  	REMU:              "REMU",
  1322  	REMUW:             "REMUW",
  1323  	REMW:              "REMW",
  1324  	REV8:              "REV8",
  1325  	ROL:               "ROL",
  1326  	ROLW:              "ROLW",
  1327  	ROR:               "ROR",
  1328  	RORI:              "RORI",
  1329  	RORIW:             "RORIW",
  1330  	RORW:              "RORW",
  1331  	SB:                "SB",
  1332  	SC_D:              "SC.D",
  1333  	SC_D_AQ:           "SC.D.AQ",
  1334  	SC_D_AQRL:         "SC.D.AQRL",
  1335  	SC_D_RL:           "SC.D.RL",
  1336  	SC_W:              "SC.W",
  1337  	SC_W_AQ:           "SC.W.AQ",
  1338  	SC_W_AQRL:         "SC.W.AQRL",
  1339  	SC_W_RL:           "SC.W.RL",
  1340  	SD:                "SD",
  1341  	SEXT_B:            "SEXT.B",
  1342  	SEXT_H:            "SEXT.H",
  1343  	SH:                "SH",
  1344  	SH1ADD:            "SH1ADD",
  1345  	SH1ADD_UW:         "SH1ADD.UW",
  1346  	SH2ADD:            "SH2ADD",
  1347  	SH2ADD_UW:         "SH2ADD.UW",
  1348  	SH3ADD:            "SH3ADD",
  1349  	SH3ADD_UW:         "SH3ADD.UW",
  1350  	SLL:               "SLL",
  1351  	SLLI:              "SLLI",
  1352  	SLLIW:             "SLLIW",
  1353  	SLLI_UW:           "SLLI.UW",
  1354  	SLLW:              "SLLW",
  1355  	SLT:               "SLT",
  1356  	SLTI:              "SLTI",
  1357  	SLTIU:             "SLTIU",
  1358  	SLTU:              "SLTU",
  1359  	SRA:               "SRA",
  1360  	SRAI:              "SRAI",
  1361  	SRAIW:             "SRAIW",
  1362  	SRAW:              "SRAW",
  1363  	SRL:               "SRL",
  1364  	SRLI:              "SRLI",
  1365  	SRLIW:             "SRLIW",
  1366  	SRLW:              "SRLW",
  1367  	SUB:               "SUB",
  1368  	SUBW:              "SUBW",
  1369  	SW:                "SW",
  1370  	VAADDU_VV:         "VAADDU.VV",
  1371  	VAADDU_VX:         "VAADDU.VX",
  1372  	VAADD_VV:          "VAADD.VV",
  1373  	VAADD_VX:          "VAADD.VX",
  1374  	VADC_VIM:          "VADC.VIM",
  1375  	VADC_VVM:          "VADC.VVM",
  1376  	VADC_VXM:          "VADC.VXM",
  1377  	VADD_VI:           "VADD.VI",
  1378  	VADD_VV:           "VADD.VV",
  1379  	VADD_VX:           "VADD.VX",
  1380  	VAND_VI:           "VAND.VI",
  1381  	VAND_VV:           "VAND.VV",
  1382  	VAND_VX:           "VAND.VX",
  1383  	VASUBU_VV:         "VASUBU.VV",
  1384  	VASUBU_VX:         "VASUBU.VX",
  1385  	VASUB_VV:          "VASUB.VV",
  1386  	VASUB_VX:          "VASUB.VX",
  1387  	VCOMPRESS_VM:      "VCOMPRESS.VM",
  1388  	VCPOP_M:           "VCPOP.M",
  1389  	VDIVU_VV:          "VDIVU.VV",
  1390  	VDIVU_VX:          "VDIVU.VX",
  1391  	VDIV_VV:           "VDIV.VV",
  1392  	VDIV_VX:           "VDIV.VX",
  1393  	VFADD_VF:          "VFADD.VF",
  1394  	VFADD_VV:          "VFADD.VV",
  1395  	VFCLASS_V:         "VFCLASS.V",
  1396  	VFCVT_F_XU_V:      "VFCVT.F.XU.V",
  1397  	VFCVT_F_X_V:       "VFCVT.F.X.V",
  1398  	VFCVT_RTZ_XU_F_V:  "VFCVT.RTZ.XU.F.V",
  1399  	VFCVT_RTZ_X_F_V:   "VFCVT.RTZ.X.F.V",
  1400  	VFCVT_XU_F_V:      "VFCVT.XU.F.V",
  1401  	VFCVT_X_F_V:       "VFCVT.X.F.V",
  1402  	VFDIV_VF:          "VFDIV.VF",
  1403  	VFDIV_VV:          "VFDIV.VV",
  1404  	VFIRST_M:          "VFIRST.M",
  1405  	VFMACC_VF:         "VFMACC.VF",
  1406  	VFMACC_VV:         "VFMACC.VV",
  1407  	VFMADD_VF:         "VFMADD.VF",
  1408  	VFMADD_VV:         "VFMADD.VV",
  1409  	VFMAX_VF:          "VFMAX.VF",
  1410  	VFMAX_VV:          "VFMAX.VV",
  1411  	VFMERGE_VFM:       "VFMERGE.VFM",
  1412  	VFMIN_VF:          "VFMIN.VF",
  1413  	VFMIN_VV:          "VFMIN.VV",
  1414  	VFMSAC_VF:         "VFMSAC.VF",
  1415  	VFMSAC_VV:         "VFMSAC.VV",
  1416  	VFMSUB_VF:         "VFMSUB.VF",
  1417  	VFMSUB_VV:         "VFMSUB.VV",
  1418  	VFMUL_VF:          "VFMUL.VF",
  1419  	VFMUL_VV:          "VFMUL.VV",
  1420  	VFMV_F_S:          "VFMV.F.S",
  1421  	VFMV_S_F:          "VFMV.S.F",
  1422  	VFMV_V_F:          "VFMV.V.F",
  1423  	VFNCVT_F_F_W:      "VFNCVT.F.F.W",
  1424  	VFNCVT_F_XU_W:     "VFNCVT.F.XU.W",
  1425  	VFNCVT_F_X_W:      "VFNCVT.F.X.W",
  1426  	VFNCVT_ROD_F_F_W:  "VFNCVT.ROD.F.F.W",
  1427  	VFNCVT_RTZ_XU_F_W: "VFNCVT.RTZ.XU.F.W",
  1428  	VFNCVT_RTZ_X_F_W:  "VFNCVT.RTZ.X.F.W",
  1429  	VFNCVT_XU_F_W:     "VFNCVT.XU.F.W",
  1430  	VFNCVT_X_F_W:      "VFNCVT.X.F.W",
  1431  	VFNMACC_VF:        "VFNMACC.VF",
  1432  	VFNMACC_VV:        "VFNMACC.VV",
  1433  	VFNMADD_VF:        "VFNMADD.VF",
  1434  	VFNMADD_VV:        "VFNMADD.VV",
  1435  	VFNMSAC_VF:        "VFNMSAC.VF",
  1436  	VFNMSAC_VV:        "VFNMSAC.VV",
  1437  	VFNMSUB_VF:        "VFNMSUB.VF",
  1438  	VFNMSUB_VV:        "VFNMSUB.VV",
  1439  	VFRDIV_VF:         "VFRDIV.VF",
  1440  	VFREC7_V:          "VFREC7.V",
  1441  	VFREDMAX_VS:       "VFREDMAX.VS",
  1442  	VFREDMIN_VS:       "VFREDMIN.VS",
  1443  	VFREDOSUM_VS:      "VFREDOSUM.VS",
  1444  	VFREDUSUM_VS:      "VFREDUSUM.VS",
  1445  	VFRSQRT7_V:        "VFRSQRT7.V",
  1446  	VFRSUB_VF:         "VFRSUB.VF",
  1447  	VFSGNJN_VF:        "VFSGNJN.VF",
  1448  	VFSGNJN_VV:        "VFSGNJN.VV",
  1449  	VFSGNJX_VF:        "VFSGNJX.VF",
  1450  	VFSGNJX_VV:        "VFSGNJX.VV",
  1451  	VFSGNJ_VF:         "VFSGNJ.VF",
  1452  	VFSGNJ_VV:         "VFSGNJ.VV",
  1453  	VFSLIDE1DOWN_VF:   "VFSLIDE1DOWN.VF",
  1454  	VFSLIDE1UP_VF:     "VFSLIDE1UP.VF",
  1455  	VFSQRT_V:          "VFSQRT.V",
  1456  	VFSUB_VF:          "VFSUB.VF",
  1457  	VFSUB_VV:          "VFSUB.VV",
  1458  	VFWADD_VF:         "VFWADD.VF",
  1459  	VFWADD_VV:         "VFWADD.VV",
  1460  	VFWADD_WF:         "VFWADD.WF",
  1461  	VFWADD_WV:         "VFWADD.WV",
  1462  	VFWCVT_F_F_V:      "VFWCVT.F.F.V",
  1463  	VFWCVT_F_XU_V:     "VFWCVT.F.XU.V",
  1464  	VFWCVT_F_X_V:      "VFWCVT.F.X.V",
  1465  	VFWCVT_RTZ_XU_F_V: "VFWCVT.RTZ.XU.F.V",
  1466  	VFWCVT_RTZ_X_F_V:  "VFWCVT.RTZ.X.F.V",
  1467  	VFWCVT_XU_F_V:     "VFWCVT.XU.F.V",
  1468  	VFWCVT_X_F_V:      "VFWCVT.X.F.V",
  1469  	VFWMACC_VF:        "VFWMACC.VF",
  1470  	VFWMACC_VV:        "VFWMACC.VV",
  1471  	VFWMSAC_VF:        "VFWMSAC.VF",
  1472  	VFWMSAC_VV:        "VFWMSAC.VV",
  1473  	VFWMUL_VF:         "VFWMUL.VF",
  1474  	VFWMUL_VV:         "VFWMUL.VV",
  1475  	VFWNMACC_VF:       "VFWNMACC.VF",
  1476  	VFWNMACC_VV:       "VFWNMACC.VV",
  1477  	VFWNMSAC_VF:       "VFWNMSAC.VF",
  1478  	VFWNMSAC_VV:       "VFWNMSAC.VV",
  1479  	VFWREDOSUM_VS:     "VFWREDOSUM.VS",
  1480  	VFWREDUSUM_VS:     "VFWREDUSUM.VS",
  1481  	VFWSUB_VF:         "VFWSUB.VF",
  1482  	VFWSUB_VV:         "VFWSUB.VV",
  1483  	VFWSUB_WF:         "VFWSUB.WF",
  1484  	VFWSUB_WV:         "VFWSUB.WV",
  1485  	VID_V:             "VID.V",
  1486  	VIOTA_M:           "VIOTA.M",
  1487  	VL1RE16_V:         "VL1RE16.V",
  1488  	VL1RE32_V:         "VL1RE32.V",
  1489  	VL1RE64_V:         "VL1RE64.V",
  1490  	VL1RE8_V:          "VL1RE8.V",
  1491  	VL2RE16_V:         "VL2RE16.V",
  1492  	VL2RE32_V:         "VL2RE32.V",
  1493  	VL2RE64_V:         "VL2RE64.V",
  1494  	VL2RE8_V:          "VL2RE8.V",
  1495  	VL4RE16_V:         "VL4RE16.V",
  1496  	VL4RE32_V:         "VL4RE32.V",
  1497  	VL4RE64_V:         "VL4RE64.V",
  1498  	VL4RE8_V:          "VL4RE8.V",
  1499  	VL8RE16_V:         "VL8RE16.V",
  1500  	VL8RE32_V:         "VL8RE32.V",
  1501  	VL8RE64_V:         "VL8RE64.V",
  1502  	VL8RE8_V:          "VL8RE8.V",
  1503  	VLE16FF_V:         "VLE16FF.V",
  1504  	VLE16_V:           "VLE16.V",
  1505  	VLE32FF_V:         "VLE32FF.V",
  1506  	VLE32_V:           "VLE32.V",
  1507  	VLE64FF_V:         "VLE64FF.V",
  1508  	VLE64_V:           "VLE64.V",
  1509  	VLE8FF_V:          "VLE8FF.V",
  1510  	VLE8_V:            "VLE8.V",
  1511  	VLM_V:             "VLM.V",
  1512  	VLOXEI16_V:        "VLOXEI16.V",
  1513  	VLOXEI32_V:        "VLOXEI32.V",
  1514  	VLOXEI64_V:        "VLOXEI64.V",
  1515  	VLOXEI8_V:         "VLOXEI8.V",
  1516  	VLOXSEG2EI16_V:    "VLOXSEG2EI16.V",
  1517  	VLOXSEG2EI32_V:    "VLOXSEG2EI32.V",
  1518  	VLOXSEG2EI64_V:    "VLOXSEG2EI64.V",
  1519  	VLOXSEG2EI8_V:     "VLOXSEG2EI8.V",
  1520  	VLOXSEG3EI16_V:    "VLOXSEG3EI16.V",
  1521  	VLOXSEG3EI32_V:    "VLOXSEG3EI32.V",
  1522  	VLOXSEG3EI64_V:    "VLOXSEG3EI64.V",
  1523  	VLOXSEG3EI8_V:     "VLOXSEG3EI8.V",
  1524  	VLOXSEG4EI16_V:    "VLOXSEG4EI16.V",
  1525  	VLOXSEG4EI32_V:    "VLOXSEG4EI32.V",
  1526  	VLOXSEG4EI64_V:    "VLOXSEG4EI64.V",
  1527  	VLOXSEG4EI8_V:     "VLOXSEG4EI8.V",
  1528  	VLOXSEG5EI16_V:    "VLOXSEG5EI16.V",
  1529  	VLOXSEG5EI32_V:    "VLOXSEG5EI32.V",
  1530  	VLOXSEG5EI64_V:    "VLOXSEG5EI64.V",
  1531  	VLOXSEG5EI8_V:     "VLOXSEG5EI8.V",
  1532  	VLOXSEG6EI16_V:    "VLOXSEG6EI16.V",
  1533  	VLOXSEG6EI32_V:    "VLOXSEG6EI32.V",
  1534  	VLOXSEG6EI64_V:    "VLOXSEG6EI64.V",
  1535  	VLOXSEG6EI8_V:     "VLOXSEG6EI8.V",
  1536  	VLOXSEG7EI16_V:    "VLOXSEG7EI16.V",
  1537  	VLOXSEG7EI32_V:    "VLOXSEG7EI32.V",
  1538  	VLOXSEG7EI64_V:    "VLOXSEG7EI64.V",
  1539  	VLOXSEG7EI8_V:     "VLOXSEG7EI8.V",
  1540  	VLOXSEG8EI16_V:    "VLOXSEG8EI16.V",
  1541  	VLOXSEG8EI32_V:    "VLOXSEG8EI32.V",
  1542  	VLOXSEG8EI64_V:    "VLOXSEG8EI64.V",
  1543  	VLOXSEG8EI8_V:     "VLOXSEG8EI8.V",
  1544  	VLSE16_V:          "VLSE16.V",
  1545  	VLSE32_V:          "VLSE32.V",
  1546  	VLSE64_V:          "VLSE64.V",
  1547  	VLSE8_V:           "VLSE8.V",
  1548  	VLSEG2E16FF_V:     "VLSEG2E16FF.V",
  1549  	VLSEG2E16_V:       "VLSEG2E16.V",
  1550  	VLSEG2E32FF_V:     "VLSEG2E32FF.V",
  1551  	VLSEG2E32_V:       "VLSEG2E32.V",
  1552  	VLSEG2E64FF_V:     "VLSEG2E64FF.V",
  1553  	VLSEG2E64_V:       "VLSEG2E64.V",
  1554  	VLSEG2E8FF_V:      "VLSEG2E8FF.V",
  1555  	VLSEG2E8_V:        "VLSEG2E8.V",
  1556  	VLSEG3E16FF_V:     "VLSEG3E16FF.V",
  1557  	VLSEG3E16_V:       "VLSEG3E16.V",
  1558  	VLSEG3E32FF_V:     "VLSEG3E32FF.V",
  1559  	VLSEG3E32_V:       "VLSEG3E32.V",
  1560  	VLSEG3E64FF_V:     "VLSEG3E64FF.V",
  1561  	VLSEG3E64_V:       "VLSEG3E64.V",
  1562  	VLSEG3E8FF_V:      "VLSEG3E8FF.V",
  1563  	VLSEG3E8_V:        "VLSEG3E8.V",
  1564  	VLSEG4E16FF_V:     "VLSEG4E16FF.V",
  1565  	VLSEG4E16_V:       "VLSEG4E16.V",
  1566  	VLSEG4E32FF_V:     "VLSEG4E32FF.V",
  1567  	VLSEG4E32_V:       "VLSEG4E32.V",
  1568  	VLSEG4E64FF_V:     "VLSEG4E64FF.V",
  1569  	VLSEG4E64_V:       "VLSEG4E64.V",
  1570  	VLSEG4E8FF_V:      "VLSEG4E8FF.V",
  1571  	VLSEG4E8_V:        "VLSEG4E8.V",
  1572  	VLSEG5E16FF_V:     "VLSEG5E16FF.V",
  1573  	VLSEG5E16_V:       "VLSEG5E16.V",
  1574  	VLSEG5E32FF_V:     "VLSEG5E32FF.V",
  1575  	VLSEG5E32_V:       "VLSEG5E32.V",
  1576  	VLSEG5E64FF_V:     "VLSEG5E64FF.V",
  1577  	VLSEG5E64_V:       "VLSEG5E64.V",
  1578  	VLSEG5E8FF_V:      "VLSEG5E8FF.V",
  1579  	VLSEG5E8_V:        "VLSEG5E8.V",
  1580  	VLSEG6E16FF_V:     "VLSEG6E16FF.V",
  1581  	VLSEG6E16_V:       "VLSEG6E16.V",
  1582  	VLSEG6E32FF_V:     "VLSEG6E32FF.V",
  1583  	VLSEG6E32_V:       "VLSEG6E32.V",
  1584  	VLSEG6E64FF_V:     "VLSEG6E64FF.V",
  1585  	VLSEG6E64_V:       "VLSEG6E64.V",
  1586  	VLSEG6E8FF_V:      "VLSEG6E8FF.V",
  1587  	VLSEG6E8_V:        "VLSEG6E8.V",
  1588  	VLSEG7E16FF_V:     "VLSEG7E16FF.V",
  1589  	VLSEG7E16_V:       "VLSEG7E16.V",
  1590  	VLSEG7E32FF_V:     "VLSEG7E32FF.V",
  1591  	VLSEG7E32_V:       "VLSEG7E32.V",
  1592  	VLSEG7E64FF_V:     "VLSEG7E64FF.V",
  1593  	VLSEG7E64_V:       "VLSEG7E64.V",
  1594  	VLSEG7E8FF_V:      "VLSEG7E8FF.V",
  1595  	VLSEG7E8_V:        "VLSEG7E8.V",
  1596  	VLSEG8E16FF_V:     "VLSEG8E16FF.V",
  1597  	VLSEG8E16_V:       "VLSEG8E16.V",
  1598  	VLSEG8E32FF_V:     "VLSEG8E32FF.V",
  1599  	VLSEG8E32_V:       "VLSEG8E32.V",
  1600  	VLSEG8E64FF_V:     "VLSEG8E64FF.V",
  1601  	VLSEG8E64_V:       "VLSEG8E64.V",
  1602  	VLSEG8E8FF_V:      "VLSEG8E8FF.V",
  1603  	VLSEG8E8_V:        "VLSEG8E8.V",
  1604  	VLSSEG2E16_V:      "VLSSEG2E16.V",
  1605  	VLSSEG2E32_V:      "VLSSEG2E32.V",
  1606  	VLSSEG2E64_V:      "VLSSEG2E64.V",
  1607  	VLSSEG2E8_V:       "VLSSEG2E8.V",
  1608  	VLSSEG3E16_V:      "VLSSEG3E16.V",
  1609  	VLSSEG3E32_V:      "VLSSEG3E32.V",
  1610  	VLSSEG3E64_V:      "VLSSEG3E64.V",
  1611  	VLSSEG3E8_V:       "VLSSEG3E8.V",
  1612  	VLSSEG4E16_V:      "VLSSEG4E16.V",
  1613  	VLSSEG4E32_V:      "VLSSEG4E32.V",
  1614  	VLSSEG4E64_V:      "VLSSEG4E64.V",
  1615  	VLSSEG4E8_V:       "VLSSEG4E8.V",
  1616  	VLSSEG5E16_V:      "VLSSEG5E16.V",
  1617  	VLSSEG5E32_V:      "VLSSEG5E32.V",
  1618  	VLSSEG5E64_V:      "VLSSEG5E64.V",
  1619  	VLSSEG5E8_V:       "VLSSEG5E8.V",
  1620  	VLSSEG6E16_V:      "VLSSEG6E16.V",
  1621  	VLSSEG6E32_V:      "VLSSEG6E32.V",
  1622  	VLSSEG6E64_V:      "VLSSEG6E64.V",
  1623  	VLSSEG6E8_V:       "VLSSEG6E8.V",
  1624  	VLSSEG7E16_V:      "VLSSEG7E16.V",
  1625  	VLSSEG7E32_V:      "VLSSEG7E32.V",
  1626  	VLSSEG7E64_V:      "VLSSEG7E64.V",
  1627  	VLSSEG7E8_V:       "VLSSEG7E8.V",
  1628  	VLSSEG8E16_V:      "VLSSEG8E16.V",
  1629  	VLSSEG8E32_V:      "VLSSEG8E32.V",
  1630  	VLSSEG8E64_V:      "VLSSEG8E64.V",
  1631  	VLSSEG8E8_V:       "VLSSEG8E8.V",
  1632  	VLUXEI16_V:        "VLUXEI16.V",
  1633  	VLUXEI32_V:        "VLUXEI32.V",
  1634  	VLUXEI64_V:        "VLUXEI64.V",
  1635  	VLUXEI8_V:         "VLUXEI8.V",
  1636  	VLUXSEG2EI16_V:    "VLUXSEG2EI16.V",
  1637  	VLUXSEG2EI32_V:    "VLUXSEG2EI32.V",
  1638  	VLUXSEG2EI64_V:    "VLUXSEG2EI64.V",
  1639  	VLUXSEG2EI8_V:     "VLUXSEG2EI8.V",
  1640  	VLUXSEG3EI16_V:    "VLUXSEG3EI16.V",
  1641  	VLUXSEG3EI32_V:    "VLUXSEG3EI32.V",
  1642  	VLUXSEG3EI64_V:    "VLUXSEG3EI64.V",
  1643  	VLUXSEG3EI8_V:     "VLUXSEG3EI8.V",
  1644  	VLUXSEG4EI16_V:    "VLUXSEG4EI16.V",
  1645  	VLUXSEG4EI32_V:    "VLUXSEG4EI32.V",
  1646  	VLUXSEG4EI64_V:    "VLUXSEG4EI64.V",
  1647  	VLUXSEG4EI8_V:     "VLUXSEG4EI8.V",
  1648  	VLUXSEG5EI16_V:    "VLUXSEG5EI16.V",
  1649  	VLUXSEG5EI32_V:    "VLUXSEG5EI32.V",
  1650  	VLUXSEG5EI64_V:    "VLUXSEG5EI64.V",
  1651  	VLUXSEG5EI8_V:     "VLUXSEG5EI8.V",
  1652  	VLUXSEG6EI16_V:    "VLUXSEG6EI16.V",
  1653  	VLUXSEG6EI32_V:    "VLUXSEG6EI32.V",
  1654  	VLUXSEG6EI64_V:    "VLUXSEG6EI64.V",
  1655  	VLUXSEG6EI8_V:     "VLUXSEG6EI8.V",
  1656  	VLUXSEG7EI16_V:    "VLUXSEG7EI16.V",
  1657  	VLUXSEG7EI32_V:    "VLUXSEG7EI32.V",
  1658  	VLUXSEG7EI64_V:    "VLUXSEG7EI64.V",
  1659  	VLUXSEG7EI8_V:     "VLUXSEG7EI8.V",
  1660  	VLUXSEG8EI16_V:    "VLUXSEG8EI16.V",
  1661  	VLUXSEG8EI32_V:    "VLUXSEG8EI32.V",
  1662  	VLUXSEG8EI64_V:    "VLUXSEG8EI64.V",
  1663  	VLUXSEG8EI8_V:     "VLUXSEG8EI8.V",
  1664  	VMACC_VV:          "VMACC.VV",
  1665  	VMACC_VX:          "VMACC.VX",
  1666  	VMADC_VI:          "VMADC.VI",
  1667  	VMADC_VIM:         "VMADC.VIM",
  1668  	VMADC_VV:          "VMADC.VV",
  1669  	VMADC_VVM:         "VMADC.VVM",
  1670  	VMADC_VX:          "VMADC.VX",
  1671  	VMADC_VXM:         "VMADC.VXM",
  1672  	VMADD_VV:          "VMADD.VV",
  1673  	VMADD_VX:          "VMADD.VX",
  1674  	VMANDN_MM:         "VMANDN.MM",
  1675  	VMAND_MM:          "VMAND.MM",
  1676  	VMAXU_VV:          "VMAXU.VV",
  1677  	VMAXU_VX:          "VMAXU.VX",
  1678  	VMAX_VV:           "VMAX.VV",
  1679  	VMAX_VX:           "VMAX.VX",
  1680  	VMERGE_VIM:        "VMERGE.VIM",
  1681  	VMERGE_VVM:        "VMERGE.VVM",
  1682  	VMERGE_VXM:        "VMERGE.VXM",
  1683  	VMFEQ_VF:          "VMFEQ.VF",
  1684  	VMFEQ_VV:          "VMFEQ.VV",
  1685  	VMFGE_VF:          "VMFGE.VF",
  1686  	VMFGT_VF:          "VMFGT.VF",
  1687  	VMFLE_VF:          "VMFLE.VF",
  1688  	VMFLE_VV:          "VMFLE.VV",
  1689  	VMFLT_VF:          "VMFLT.VF",
  1690  	VMFLT_VV:          "VMFLT.VV",
  1691  	VMFNE_VF:          "VMFNE.VF",
  1692  	VMFNE_VV:          "VMFNE.VV",
  1693  	VMINU_VV:          "VMINU.VV",
  1694  	VMINU_VX:          "VMINU.VX",
  1695  	VMIN_VV:           "VMIN.VV",
  1696  	VMIN_VX:           "VMIN.VX",
  1697  	VMNAND_MM:         "VMNAND.MM",
  1698  	VMNOR_MM:          "VMNOR.MM",
  1699  	VMORN_MM:          "VMORN.MM",
  1700  	VMOR_MM:           "VMOR.MM",
  1701  	VMSBC_VV:          "VMSBC.VV",
  1702  	VMSBC_VVM:         "VMSBC.VVM",
  1703  	VMSBC_VX:          "VMSBC.VX",
  1704  	VMSBC_VXM:         "VMSBC.VXM",
  1705  	VMSBF_M:           "VMSBF.M",
  1706  	VMSEQ_VI:          "VMSEQ.VI",
  1707  	VMSEQ_VV:          "VMSEQ.VV",
  1708  	VMSEQ_VX:          "VMSEQ.VX",
  1709  	VMSGTU_VI:         "VMSGTU.VI",
  1710  	VMSGTU_VX:         "VMSGTU.VX",
  1711  	VMSGT_VI:          "VMSGT.VI",
  1712  	VMSGT_VX:          "VMSGT.VX",
  1713  	VMSIF_M:           "VMSIF.M",
  1714  	VMSLEU_VI:         "VMSLEU.VI",
  1715  	VMSLEU_VV:         "VMSLEU.VV",
  1716  	VMSLEU_VX:         "VMSLEU.VX",
  1717  	VMSLE_VI:          "VMSLE.VI",
  1718  	VMSLE_VV:          "VMSLE.VV",
  1719  	VMSLE_VX:          "VMSLE.VX",
  1720  	VMSLTU_VV:         "VMSLTU.VV",
  1721  	VMSLTU_VX:         "VMSLTU.VX",
  1722  	VMSLT_VV:          "VMSLT.VV",
  1723  	VMSLT_VX:          "VMSLT.VX",
  1724  	VMSNE_VI:          "VMSNE.VI",
  1725  	VMSNE_VV:          "VMSNE.VV",
  1726  	VMSNE_VX:          "VMSNE.VX",
  1727  	VMSOF_M:           "VMSOF.M",
  1728  	VMULHSU_VV:        "VMULHSU.VV",
  1729  	VMULHSU_VX:        "VMULHSU.VX",
  1730  	VMULHU_VV:         "VMULHU.VV",
  1731  	VMULHU_VX:         "VMULHU.VX",
  1732  	VMULH_VV:          "VMULH.VV",
  1733  	VMULH_VX:          "VMULH.VX",
  1734  	VMUL_VV:           "VMUL.VV",
  1735  	VMUL_VX:           "VMUL.VX",
  1736  	VMV1R_V:           "VMV1R.V",
  1737  	VMV2R_V:           "VMV2R.V",
  1738  	VMV4R_V:           "VMV4R.V",
  1739  	VMV8R_V:           "VMV8R.V",
  1740  	VMV_S_X:           "VMV.S.X",
  1741  	VMV_V_I:           "VMV.V.I",
  1742  	VMV_V_V:           "VMV.V.V",
  1743  	VMV_V_X:           "VMV.V.X",
  1744  	VMV_X_S:           "VMV.X.S",
  1745  	VMXNOR_MM:         "VMXNOR.MM",
  1746  	VMXOR_MM:          "VMXOR.MM",
  1747  	VNCLIPU_WI:        "VNCLIPU.WI",
  1748  	VNCLIPU_WV:        "VNCLIPU.WV",
  1749  	VNCLIPU_WX:        "VNCLIPU.WX",
  1750  	VNCLIP_WI:         "VNCLIP.WI",
  1751  	VNCLIP_WV:         "VNCLIP.WV",
  1752  	VNCLIP_WX:         "VNCLIP.WX",
  1753  	VNMSAC_VV:         "VNMSAC.VV",
  1754  	VNMSAC_VX:         "VNMSAC.VX",
  1755  	VNMSUB_VV:         "VNMSUB.VV",
  1756  	VNMSUB_VX:         "VNMSUB.VX",
  1757  	VNSRA_WI:          "VNSRA.WI",
  1758  	VNSRA_WV:          "VNSRA.WV",
  1759  	VNSRA_WX:          "VNSRA.WX",
  1760  	VNSRL_WI:          "VNSRL.WI",
  1761  	VNSRL_WV:          "VNSRL.WV",
  1762  	VNSRL_WX:          "VNSRL.WX",
  1763  	VOR_VI:            "VOR.VI",
  1764  	VOR_VV:            "VOR.VV",
  1765  	VOR_VX:            "VOR.VX",
  1766  	VREDAND_VS:        "VREDAND.VS",
  1767  	VREDMAXU_VS:       "VREDMAXU.VS",
  1768  	VREDMAX_VS:        "VREDMAX.VS",
  1769  	VREDMINU_VS:       "VREDMINU.VS",
  1770  	VREDMIN_VS:        "VREDMIN.VS",
  1771  	VREDOR_VS:         "VREDOR.VS",
  1772  	VREDSUM_VS:        "VREDSUM.VS",
  1773  	VREDXOR_VS:        "VREDXOR.VS",
  1774  	VREMU_VV:          "VREMU.VV",
  1775  	VREMU_VX:          "VREMU.VX",
  1776  	VREM_VV:           "VREM.VV",
  1777  	VREM_VX:           "VREM.VX",
  1778  	VRGATHEREI16_VV:   "VRGATHEREI16.VV",
  1779  	VRGATHER_VI:       "VRGATHER.VI",
  1780  	VRGATHER_VV:       "VRGATHER.VV",
  1781  	VRGATHER_VX:       "VRGATHER.VX",
  1782  	VRSUB_VI:          "VRSUB.VI",
  1783  	VRSUB_VX:          "VRSUB.VX",
  1784  	VS1R_V:            "VS1R.V",
  1785  	VS2R_V:            "VS2R.V",
  1786  	VS4R_V:            "VS4R.V",
  1787  	VS8R_V:            "VS8R.V",
  1788  	VSADDU_VI:         "VSADDU.VI",
  1789  	VSADDU_VV:         "VSADDU.VV",
  1790  	VSADDU_VX:         "VSADDU.VX",
  1791  	VSADD_VI:          "VSADD.VI",
  1792  	VSADD_VV:          "VSADD.VV",
  1793  	VSADD_VX:          "VSADD.VX",
  1794  	VSBC_VVM:          "VSBC.VVM",
  1795  	VSBC_VXM:          "VSBC.VXM",
  1796  	VSE16_V:           "VSE16.V",
  1797  	VSE32_V:           "VSE32.V",
  1798  	VSE64_V:           "VSE64.V",
  1799  	VSE8_V:            "VSE8.V",
  1800  	VSETIVLI:          "VSETIVLI",
  1801  	VSETVL:            "VSETVL",
  1802  	VSETVLI:           "VSETVLI",
  1803  	VSEXT_VF2:         "VSEXT.VF2",
  1804  	VSEXT_VF4:         "VSEXT.VF4",
  1805  	VSEXT_VF8:         "VSEXT.VF8",
  1806  	VSLIDE1DOWN_VX:    "VSLIDE1DOWN.VX",
  1807  	VSLIDE1UP_VX:      "VSLIDE1UP.VX",
  1808  	VSLIDEDOWN_VI:     "VSLIDEDOWN.VI",
  1809  	VSLIDEDOWN_VX:     "VSLIDEDOWN.VX",
  1810  	VSLIDEUP_VI:       "VSLIDEUP.VI",
  1811  	VSLIDEUP_VX:       "VSLIDEUP.VX",
  1812  	VSLL_VI:           "VSLL.VI",
  1813  	VSLL_VV:           "VSLL.VV",
  1814  	VSLL_VX:           "VSLL.VX",
  1815  	VSMUL_VV:          "VSMUL.VV",
  1816  	VSMUL_VX:          "VSMUL.VX",
  1817  	VSM_V:             "VSM.V",
  1818  	VSOXEI16_V:        "VSOXEI16.V",
  1819  	VSOXEI32_V:        "VSOXEI32.V",
  1820  	VSOXEI64_V:        "VSOXEI64.V",
  1821  	VSOXEI8_V:         "VSOXEI8.V",
  1822  	VSOXSEG2EI16_V:    "VSOXSEG2EI16.V",
  1823  	VSOXSEG2EI32_V:    "VSOXSEG2EI32.V",
  1824  	VSOXSEG2EI64_V:    "VSOXSEG2EI64.V",
  1825  	VSOXSEG2EI8_V:     "VSOXSEG2EI8.V",
  1826  	VSOXSEG3EI16_V:    "VSOXSEG3EI16.V",
  1827  	VSOXSEG3EI32_V:    "VSOXSEG3EI32.V",
  1828  	VSOXSEG3EI64_V:    "VSOXSEG3EI64.V",
  1829  	VSOXSEG3EI8_V:     "VSOXSEG3EI8.V",
  1830  	VSOXSEG4EI16_V:    "VSOXSEG4EI16.V",
  1831  	VSOXSEG4EI32_V:    "VSOXSEG4EI32.V",
  1832  	VSOXSEG4EI64_V:    "VSOXSEG4EI64.V",
  1833  	VSOXSEG4EI8_V:     "VSOXSEG4EI8.V",
  1834  	VSOXSEG5EI16_V:    "VSOXSEG5EI16.V",
  1835  	VSOXSEG5EI32_V:    "VSOXSEG5EI32.V",
  1836  	VSOXSEG5EI64_V:    "VSOXSEG5EI64.V",
  1837  	VSOXSEG5EI8_V:     "VSOXSEG5EI8.V",
  1838  	VSOXSEG6EI16_V:    "VSOXSEG6EI16.V",
  1839  	VSOXSEG6EI32_V:    "VSOXSEG6EI32.V",
  1840  	VSOXSEG6EI64_V:    "VSOXSEG6EI64.V",
  1841  	VSOXSEG6EI8_V:     "VSOXSEG6EI8.V",
  1842  	VSOXSEG7EI16_V:    "VSOXSEG7EI16.V",
  1843  	VSOXSEG7EI32_V:    "VSOXSEG7EI32.V",
  1844  	VSOXSEG7EI64_V:    "VSOXSEG7EI64.V",
  1845  	VSOXSEG7EI8_V:     "VSOXSEG7EI8.V",
  1846  	VSOXSEG8EI16_V:    "VSOXSEG8EI16.V",
  1847  	VSOXSEG8EI32_V:    "VSOXSEG8EI32.V",
  1848  	VSOXSEG8EI64_V:    "VSOXSEG8EI64.V",
  1849  	VSOXSEG8EI8_V:     "VSOXSEG8EI8.V",
  1850  	VSRA_VI:           "VSRA.VI",
  1851  	VSRA_VV:           "VSRA.VV",
  1852  	VSRA_VX:           "VSRA.VX",
  1853  	VSRL_VI:           "VSRL.VI",
  1854  	VSRL_VV:           "VSRL.VV",
  1855  	VSRL_VX:           "VSRL.VX",
  1856  	VSSE16_V:          "VSSE16.V",
  1857  	VSSE32_V:          "VSSE32.V",
  1858  	VSSE64_V:          "VSSE64.V",
  1859  	VSSE8_V:           "VSSE8.V",
  1860  	VSSEG2E16_V:       "VSSEG2E16.V",
  1861  	VSSEG2E32_V:       "VSSEG2E32.V",
  1862  	VSSEG2E64_V:       "VSSEG2E64.V",
  1863  	VSSEG2E8_V:        "VSSEG2E8.V",
  1864  	VSSEG3E16_V:       "VSSEG3E16.V",
  1865  	VSSEG3E32_V:       "VSSEG3E32.V",
  1866  	VSSEG3E64_V:       "VSSEG3E64.V",
  1867  	VSSEG3E8_V:        "VSSEG3E8.V",
  1868  	VSSEG4E16_V:       "VSSEG4E16.V",
  1869  	VSSEG4E32_V:       "VSSEG4E32.V",
  1870  	VSSEG4E64_V:       "VSSEG4E64.V",
  1871  	VSSEG4E8_V:        "VSSEG4E8.V",
  1872  	VSSEG5E16_V:       "VSSEG5E16.V",
  1873  	VSSEG5E32_V:       "VSSEG5E32.V",
  1874  	VSSEG5E64_V:       "VSSEG5E64.V",
  1875  	VSSEG5E8_V:        "VSSEG5E8.V",
  1876  	VSSEG6E16_V:       "VSSEG6E16.V",
  1877  	VSSEG6E32_V:       "VSSEG6E32.V",
  1878  	VSSEG6E64_V:       "VSSEG6E64.V",
  1879  	VSSEG6E8_V:        "VSSEG6E8.V",
  1880  	VSSEG7E16_V:       "VSSEG7E16.V",
  1881  	VSSEG7E32_V:       "VSSEG7E32.V",
  1882  	VSSEG7E64_V:       "VSSEG7E64.V",
  1883  	VSSEG7E8_V:        "VSSEG7E8.V",
  1884  	VSSEG8E16_V:       "VSSEG8E16.V",
  1885  	VSSEG8E32_V:       "VSSEG8E32.V",
  1886  	VSSEG8E64_V:       "VSSEG8E64.V",
  1887  	VSSEG8E8_V:        "VSSEG8E8.V",
  1888  	VSSRA_VI:          "VSSRA.VI",
  1889  	VSSRA_VV:          "VSSRA.VV",
  1890  	VSSRA_VX:          "VSSRA.VX",
  1891  	VSSRL_VI:          "VSSRL.VI",
  1892  	VSSRL_VV:          "VSSRL.VV",
  1893  	VSSRL_VX:          "VSSRL.VX",
  1894  	VSSSEG2E16_V:      "VSSSEG2E16.V",
  1895  	VSSSEG2E32_V:      "VSSSEG2E32.V",
  1896  	VSSSEG2E64_V:      "VSSSEG2E64.V",
  1897  	VSSSEG2E8_V:       "VSSSEG2E8.V",
  1898  	VSSSEG3E16_V:      "VSSSEG3E16.V",
  1899  	VSSSEG3E32_V:      "VSSSEG3E32.V",
  1900  	VSSSEG3E64_V:      "VSSSEG3E64.V",
  1901  	VSSSEG3E8_V:       "VSSSEG3E8.V",
  1902  	VSSSEG4E16_V:      "VSSSEG4E16.V",
  1903  	VSSSEG4E32_V:      "VSSSEG4E32.V",
  1904  	VSSSEG4E64_V:      "VSSSEG4E64.V",
  1905  	VSSSEG4E8_V:       "VSSSEG4E8.V",
  1906  	VSSSEG5E16_V:      "VSSSEG5E16.V",
  1907  	VSSSEG5E32_V:      "VSSSEG5E32.V",
  1908  	VSSSEG5E64_V:      "VSSSEG5E64.V",
  1909  	VSSSEG5E8_V:       "VSSSEG5E8.V",
  1910  	VSSSEG6E16_V:      "VSSSEG6E16.V",
  1911  	VSSSEG6E32_V:      "VSSSEG6E32.V",
  1912  	VSSSEG6E64_V:      "VSSSEG6E64.V",
  1913  	VSSSEG6E8_V:       "VSSSEG6E8.V",
  1914  	VSSSEG7E16_V:      "VSSSEG7E16.V",
  1915  	VSSSEG7E32_V:      "VSSSEG7E32.V",
  1916  	VSSSEG7E64_V:      "VSSSEG7E64.V",
  1917  	VSSSEG7E8_V:       "VSSSEG7E8.V",
  1918  	VSSSEG8E16_V:      "VSSSEG8E16.V",
  1919  	VSSSEG8E32_V:      "VSSSEG8E32.V",
  1920  	VSSSEG8E64_V:      "VSSSEG8E64.V",
  1921  	VSSSEG8E8_V:       "VSSSEG8E8.V",
  1922  	VSSUBU_VV:         "VSSUBU.VV",
  1923  	VSSUBU_VX:         "VSSUBU.VX",
  1924  	VSSUB_VV:          "VSSUB.VV",
  1925  	VSSUB_VX:          "VSSUB.VX",
  1926  	VSUB_VV:           "VSUB.VV",
  1927  	VSUB_VX:           "VSUB.VX",
  1928  	VSUXEI16_V:        "VSUXEI16.V",
  1929  	VSUXEI32_V:        "VSUXEI32.V",
  1930  	VSUXEI64_V:        "VSUXEI64.V",
  1931  	VSUXEI8_V:         "VSUXEI8.V",
  1932  	VSUXSEG2EI16_V:    "VSUXSEG2EI16.V",
  1933  	VSUXSEG2EI32_V:    "VSUXSEG2EI32.V",
  1934  	VSUXSEG2EI64_V:    "VSUXSEG2EI64.V",
  1935  	VSUXSEG2EI8_V:     "VSUXSEG2EI8.V",
  1936  	VSUXSEG3EI16_V:    "VSUXSEG3EI16.V",
  1937  	VSUXSEG3EI32_V:    "VSUXSEG3EI32.V",
  1938  	VSUXSEG3EI64_V:    "VSUXSEG3EI64.V",
  1939  	VSUXSEG3EI8_V:     "VSUXSEG3EI8.V",
  1940  	VSUXSEG4EI16_V:    "VSUXSEG4EI16.V",
  1941  	VSUXSEG4EI32_V:    "VSUXSEG4EI32.V",
  1942  	VSUXSEG4EI64_V:    "VSUXSEG4EI64.V",
  1943  	VSUXSEG4EI8_V:     "VSUXSEG4EI8.V",
  1944  	VSUXSEG5EI16_V:    "VSUXSEG5EI16.V",
  1945  	VSUXSEG5EI32_V:    "VSUXSEG5EI32.V",
  1946  	VSUXSEG5EI64_V:    "VSUXSEG5EI64.V",
  1947  	VSUXSEG5EI8_V:     "VSUXSEG5EI8.V",
  1948  	VSUXSEG6EI16_V:    "VSUXSEG6EI16.V",
  1949  	VSUXSEG6EI32_V:    "VSUXSEG6EI32.V",
  1950  	VSUXSEG6EI64_V:    "VSUXSEG6EI64.V",
  1951  	VSUXSEG6EI8_V:     "VSUXSEG6EI8.V",
  1952  	VSUXSEG7EI16_V:    "VSUXSEG7EI16.V",
  1953  	VSUXSEG7EI32_V:    "VSUXSEG7EI32.V",
  1954  	VSUXSEG7EI64_V:    "VSUXSEG7EI64.V",
  1955  	VSUXSEG7EI8_V:     "VSUXSEG7EI8.V",
  1956  	VSUXSEG8EI16_V:    "VSUXSEG8EI16.V",
  1957  	VSUXSEG8EI32_V:    "VSUXSEG8EI32.V",
  1958  	VSUXSEG8EI64_V:    "VSUXSEG8EI64.V",
  1959  	VSUXSEG8EI8_V:     "VSUXSEG8EI8.V",
  1960  	VWADDU_VV:         "VWADDU.VV",
  1961  	VWADDU_VX:         "VWADDU.VX",
  1962  	VWADDU_WV:         "VWADDU.WV",
  1963  	VWADDU_WX:         "VWADDU.WX",
  1964  	VWADD_VV:          "VWADD.VV",
  1965  	VWADD_VX:          "VWADD.VX",
  1966  	VWADD_WV:          "VWADD.WV",
  1967  	VWADD_WX:          "VWADD.WX",
  1968  	VWMACCSU_VV:       "VWMACCSU.VV",
  1969  	VWMACCSU_VX:       "VWMACCSU.VX",
  1970  	VWMACCUS_VX:       "VWMACCUS.VX",
  1971  	VWMACCU_VV:        "VWMACCU.VV",
  1972  	VWMACCU_VX:        "VWMACCU.VX",
  1973  	VWMACC_VV:         "VWMACC.VV",
  1974  	VWMACC_VX:         "VWMACC.VX",
  1975  	VWMULSU_VV:        "VWMULSU.VV",
  1976  	VWMULSU_VX:        "VWMULSU.VX",
  1977  	VWMULU_VV:         "VWMULU.VV",
  1978  	VWMULU_VX:         "VWMULU.VX",
  1979  	VWMUL_VV:          "VWMUL.VV",
  1980  	VWMUL_VX:          "VWMUL.VX",
  1981  	VWREDSUMU_VS:      "VWREDSUMU.VS",
  1982  	VWREDSUM_VS:       "VWREDSUM.VS",
  1983  	VWSUBU_VV:         "VWSUBU.VV",
  1984  	VWSUBU_VX:         "VWSUBU.VX",
  1985  	VWSUBU_WV:         "VWSUBU.WV",
  1986  	VWSUBU_WX:         "VWSUBU.WX",
  1987  	VWSUB_VV:          "VWSUB.VV",
  1988  	VWSUB_VX:          "VWSUB.VX",
  1989  	VWSUB_WV:          "VWSUB.WV",
  1990  	VWSUB_WX:          "VWSUB.WX",
  1991  	VXOR_VI:           "VXOR.VI",
  1992  	VXOR_VV:           "VXOR.VV",
  1993  	VXOR_VX:           "VXOR.VX",
  1994  	VZEXT_VF2:         "VZEXT.VF2",
  1995  	VZEXT_VF4:         "VZEXT.VF4",
  1996  	VZEXT_VF8:         "VZEXT.VF8",
  1997  	XNOR:              "XNOR",
  1998  	XOR:               "XOR",
  1999  	XORI:              "XORI",
  2000  	ZEXT_H:            "ZEXT.H",
  2001  }
  2002  
  2003  var instFormats = [...]instFormat{
  2004  	// ADD rd, rs1, rs2
  2005  	{mask: 0xfe00707f, value: 0x00000033, op: ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2006  	// ADDI rd, rs1, imm12
  2007  	{mask: 0x0000707f, value: 0x00000013, op: ADDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2008  	// ADDIW rd, rs1, imm12
  2009  	{mask: 0x0000707f, value: 0x0000001b, op: ADDIW, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2010  	// ADDW rd, rs1, rs2
  2011  	{mask: 0xfe00707f, value: 0x0000003b, op: ADDW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2012  	// ADD.UW rd, rs1, rs2
  2013  	{mask: 0xfe00707f, value: 0x0800003b, op: ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2014  	// AMOADD.D rd, rs2, rs1_ptr
  2015  	{mask: 0xfe00707f, value: 0x0000302f, op: AMOADD_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2016  	// AMOADD.D.AQ rd, rs2, rs1_ptr
  2017  	{mask: 0xfe00707f, value: 0x0400302f, op: AMOADD_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2018  	// AMOADD.D.AQRL rd, rs2, rs1_ptr
  2019  	{mask: 0xfe00707f, value: 0x0600302f, op: AMOADD_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2020  	// AMOADD.D.RL rd, rs2, rs1_ptr
  2021  	{mask: 0xfe00707f, value: 0x0200302f, op: AMOADD_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2022  	// AMOADD.W rd, rs2, rs1_ptr
  2023  	{mask: 0xfe00707f, value: 0x0000202f, op: AMOADD_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2024  	// AMOADD.W.AQ rd, rs2, rs1_ptr
  2025  	{mask: 0xfe00707f, value: 0x0400202f, op: AMOADD_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2026  	// AMOADD.W.AQRL rd, rs2, rs1_ptr
  2027  	{mask: 0xfe00707f, value: 0x0600202f, op: AMOADD_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2028  	// AMOADD.W.RL rd, rs2, rs1_ptr
  2029  	{mask: 0xfe00707f, value: 0x0200202f, op: AMOADD_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2030  	// AMOAND.D rd, rs2, rs1_ptr
  2031  	{mask: 0xfe00707f, value: 0x6000302f, op: AMOAND_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2032  	// AMOAND.D.AQ rd, rs2, rs1_ptr
  2033  	{mask: 0xfe00707f, value: 0x6400302f, op: AMOAND_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2034  	// AMOAND.D.AQRL rd, rs2, rs1_ptr
  2035  	{mask: 0xfe00707f, value: 0x6600302f, op: AMOAND_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2036  	// AMOAND.D.RL rd, rs2, rs1_ptr
  2037  	{mask: 0xfe00707f, value: 0x6200302f, op: AMOAND_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2038  	// AMOAND.W rd, rs2, rs1_ptr
  2039  	{mask: 0xfe00707f, value: 0x6000202f, op: AMOAND_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2040  	// AMOAND.W.AQ rd, rs2, rs1_ptr
  2041  	{mask: 0xfe00707f, value: 0x6400202f, op: AMOAND_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2042  	// AMOAND.W.AQRL rd, rs2, rs1_ptr
  2043  	{mask: 0xfe00707f, value: 0x6600202f, op: AMOAND_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2044  	// AMOAND.W.RL rd, rs2, rs1_ptr
  2045  	{mask: 0xfe00707f, value: 0x6200202f, op: AMOAND_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2046  	// AMOMAXU.D rd, rs2, rs1_ptr
  2047  	{mask: 0xfe00707f, value: 0xe000302f, op: AMOMAXU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2048  	// AMOMAXU.D.AQ rd, rs2, rs1_ptr
  2049  	{mask: 0xfe00707f, value: 0xe400302f, op: AMOMAXU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2050  	// AMOMAXU.D.AQRL rd, rs2, rs1_ptr
  2051  	{mask: 0xfe00707f, value: 0xe600302f, op: AMOMAXU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2052  	// AMOMAXU.D.RL rd, rs2, rs1_ptr
  2053  	{mask: 0xfe00707f, value: 0xe200302f, op: AMOMAXU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2054  	// AMOMAXU.W rd, rs2, rs1_ptr
  2055  	{mask: 0xfe00707f, value: 0xe000202f, op: AMOMAXU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2056  	// AMOMAXU.W.AQ rd, rs2, rs1_ptr
  2057  	{mask: 0xfe00707f, value: 0xe400202f, op: AMOMAXU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2058  	// AMOMAXU.W.AQRL rd, rs2, rs1_ptr
  2059  	{mask: 0xfe00707f, value: 0xe600202f, op: AMOMAXU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2060  	// AMOMAXU.W.RL rd, rs2, rs1_ptr
  2061  	{mask: 0xfe00707f, value: 0xe200202f, op: AMOMAXU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2062  	// AMOMAX.D rd, rs2, rs1_ptr
  2063  	{mask: 0xfe00707f, value: 0xa000302f, op: AMOMAX_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2064  	// AMOMAX.D.AQ rd, rs2, rs1_ptr
  2065  	{mask: 0xfe00707f, value: 0xa400302f, op: AMOMAX_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2066  	// AMOMAX.D.AQRL rd, rs2, rs1_ptr
  2067  	{mask: 0xfe00707f, value: 0xa600302f, op: AMOMAX_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2068  	// AMOMAX.D.RL rd, rs2, rs1_ptr
  2069  	{mask: 0xfe00707f, value: 0xa200302f, op: AMOMAX_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2070  	// AMOMAX.W rd, rs2, rs1_ptr
  2071  	{mask: 0xfe00707f, value: 0xa000202f, op: AMOMAX_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2072  	// AMOMAX.W.AQ rd, rs2, rs1_ptr
  2073  	{mask: 0xfe00707f, value: 0xa400202f, op: AMOMAX_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2074  	// AMOMAX.W.AQRL rd, rs2, rs1_ptr
  2075  	{mask: 0xfe00707f, value: 0xa600202f, op: AMOMAX_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2076  	// AMOMAX.W.RL rd, rs2, rs1_ptr
  2077  	{mask: 0xfe00707f, value: 0xa200202f, op: AMOMAX_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2078  	// AMOMINU.D rd, rs2, rs1_ptr
  2079  	{mask: 0xfe00707f, value: 0xc000302f, op: AMOMINU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2080  	// AMOMINU.D.AQ rd, rs2, rs1_ptr
  2081  	{mask: 0xfe00707f, value: 0xc400302f, op: AMOMINU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2082  	// AMOMINU.D.AQRL rd, rs2, rs1_ptr
  2083  	{mask: 0xfe00707f, value: 0xc600302f, op: AMOMINU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2084  	// AMOMINU.D.RL rd, rs2, rs1_ptr
  2085  	{mask: 0xfe00707f, value: 0xc200302f, op: AMOMINU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2086  	// AMOMINU.W rd, rs2, rs1_ptr
  2087  	{mask: 0xfe00707f, value: 0xc000202f, op: AMOMINU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2088  	// AMOMINU.W.AQ rd, rs2, rs1_ptr
  2089  	{mask: 0xfe00707f, value: 0xc400202f, op: AMOMINU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2090  	// AMOMINU.W.AQRL rd, rs2, rs1_ptr
  2091  	{mask: 0xfe00707f, value: 0xc600202f, op: AMOMINU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2092  	// AMOMINU.W.RL rd, rs2, rs1_ptr
  2093  	{mask: 0xfe00707f, value: 0xc200202f, op: AMOMINU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2094  	// AMOMIN.D rd, rs2, rs1_ptr
  2095  	{mask: 0xfe00707f, value: 0x8000302f, op: AMOMIN_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2096  	// AMOMIN.D.AQ rd, rs2, rs1_ptr
  2097  	{mask: 0xfe00707f, value: 0x8400302f, op: AMOMIN_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2098  	// AMOMIN.D.AQRL rd, rs2, rs1_ptr
  2099  	{mask: 0xfe00707f, value: 0x8600302f, op: AMOMIN_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2100  	// AMOMIN.D.RL rd, rs2, rs1_ptr
  2101  	{mask: 0xfe00707f, value: 0x8200302f, op: AMOMIN_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2102  	// AMOMIN.W rd, rs2, rs1_ptr
  2103  	{mask: 0xfe00707f, value: 0x8000202f, op: AMOMIN_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2104  	// AMOMIN.W.AQ rd, rs2, rs1_ptr
  2105  	{mask: 0xfe00707f, value: 0x8400202f, op: AMOMIN_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2106  	// AMOMIN.W.AQRL rd, rs2, rs1_ptr
  2107  	{mask: 0xfe00707f, value: 0x8600202f, op: AMOMIN_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2108  	// AMOMIN.W.RL rd, rs2, rs1_ptr
  2109  	{mask: 0xfe00707f, value: 0x8200202f, op: AMOMIN_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2110  	// AMOOR.D rd, rs2, rs1_ptr
  2111  	{mask: 0xfe00707f, value: 0x4000302f, op: AMOOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2112  	// AMOOR.D.AQ rd, rs2, rs1_ptr
  2113  	{mask: 0xfe00707f, value: 0x4400302f, op: AMOOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2114  	// AMOOR.D.AQRL rd, rs2, rs1_ptr
  2115  	{mask: 0xfe00707f, value: 0x4600302f, op: AMOOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2116  	// AMOOR.D.RL rd, rs2, rs1_ptr
  2117  	{mask: 0xfe00707f, value: 0x4200302f, op: AMOOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2118  	// AMOOR.W rd, rs2, rs1_ptr
  2119  	{mask: 0xfe00707f, value: 0x4000202f, op: AMOOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2120  	// AMOOR.W.AQ rd, rs2, rs1_ptr
  2121  	{mask: 0xfe00707f, value: 0x4400202f, op: AMOOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2122  	// AMOOR.W.AQRL rd, rs2, rs1_ptr
  2123  	{mask: 0xfe00707f, value: 0x4600202f, op: AMOOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2124  	// AMOOR.W.RL rd, rs2, rs1_ptr
  2125  	{mask: 0xfe00707f, value: 0x4200202f, op: AMOOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2126  	// AMOSWAP.D rd, rs2, rs1_ptr
  2127  	{mask: 0xfe00707f, value: 0x0800302f, op: AMOSWAP_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2128  	// AMOSWAP.D.AQ rd, rs2, rs1_ptr
  2129  	{mask: 0xfe00707f, value: 0x0c00302f, op: AMOSWAP_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2130  	// AMOSWAP.D.AQRL rd, rs2, rs1_ptr
  2131  	{mask: 0xfe00707f, value: 0x0e00302f, op: AMOSWAP_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2132  	// AMOSWAP.D.RL rd, rs2, rs1_ptr
  2133  	{mask: 0xfe00707f, value: 0x0a00302f, op: AMOSWAP_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2134  	// AMOSWAP.W rd, rs2, rs1_ptr
  2135  	{mask: 0xfe00707f, value: 0x0800202f, op: AMOSWAP_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2136  	// AMOSWAP.W.AQ rd, rs2, rs1_ptr
  2137  	{mask: 0xfe00707f, value: 0x0c00202f, op: AMOSWAP_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2138  	// AMOSWAP.W.AQRL rd, rs2, rs1_ptr
  2139  	{mask: 0xfe00707f, value: 0x0e00202f, op: AMOSWAP_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2140  	// AMOSWAP.W.RL rd, rs2, rs1_ptr
  2141  	{mask: 0xfe00707f, value: 0x0a00202f, op: AMOSWAP_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2142  	// AMOXOR.D rd, rs2, rs1_ptr
  2143  	{mask: 0xfe00707f, value: 0x2000302f, op: AMOXOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2144  	// AMOXOR.D.AQ rd, rs2, rs1_ptr
  2145  	{mask: 0xfe00707f, value: 0x2400302f, op: AMOXOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2146  	// AMOXOR.D.AQRL rd, rs2, rs1_ptr
  2147  	{mask: 0xfe00707f, value: 0x2600302f, op: AMOXOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2148  	// AMOXOR.D.RL rd, rs2, rs1_ptr
  2149  	{mask: 0xfe00707f, value: 0x2200302f, op: AMOXOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2150  	// AMOXOR.W rd, rs2, rs1_ptr
  2151  	{mask: 0xfe00707f, value: 0x2000202f, op: AMOXOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2152  	// AMOXOR.W.AQ rd, rs2, rs1_ptr
  2153  	{mask: 0xfe00707f, value: 0x2400202f, op: AMOXOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2154  	// AMOXOR.W.AQRL rd, rs2, rs1_ptr
  2155  	{mask: 0xfe00707f, value: 0x2600202f, op: AMOXOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2156  	// AMOXOR.W.RL rd, rs2, rs1_ptr
  2157  	{mask: 0xfe00707f, value: 0x2200202f, op: AMOXOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2158  	// AND rd, rs1, rs2
  2159  	{mask: 0xfe00707f, value: 0x00007033, op: AND, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2160  	// ANDI rd, rs1, imm12
  2161  	{mask: 0x0000707f, value: 0x00007013, op: ANDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2162  	// ANDN rd, rs1, rs2
  2163  	{mask: 0xfe00707f, value: 0x40007033, op: ANDN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2164  	// AUIPC rd, imm20
  2165  	{mask: 0x0000007f, value: 0x00000017, op: AUIPC, args: argTypeList{arg_rd, arg_imm20}},
  2166  	// BCLR rd, rs1, rs2
  2167  	{mask: 0xfe00707f, value: 0x48001033, op: BCLR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2168  	// BCLRI rd, rs1, shamt6
  2169  	{mask: 0xfc00707f, value: 0x48001013, op: BCLRI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2170  	// BEQ rs1, rs2, bimm12
  2171  	{mask: 0x0000707f, value: 0x00000063, op: BEQ, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2172  	// BEXT rd, rs1, rs2
  2173  	{mask: 0xfe00707f, value: 0x48005033, op: BEXT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2174  	// BEXTI rd, rs1, shamt6
  2175  	{mask: 0xfc00707f, value: 0x48005013, op: BEXTI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2176  	// BGE rs1, rs2, bimm12
  2177  	{mask: 0x0000707f, value: 0x00005063, op: BGE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2178  	// BGEU rs1, rs2, bimm12
  2179  	{mask: 0x0000707f, value: 0x00007063, op: BGEU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2180  	// BINV rd, rs1, rs2
  2181  	{mask: 0xfe00707f, value: 0x68001033, op: BINV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2182  	// BINVI rd, rs1, shamt6
  2183  	{mask: 0xfc00707f, value: 0x68001013, op: BINVI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2184  	// BLT rs1, rs2, bimm12
  2185  	{mask: 0x0000707f, value: 0x00004063, op: BLT, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2186  	// BLTU rs1, rs2, bimm12
  2187  	{mask: 0x0000707f, value: 0x00006063, op: BLTU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2188  	// BNE rs1, rs2, bimm12
  2189  	{mask: 0x0000707f, value: 0x00001063, op: BNE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}},
  2190  	// BSET rd, rs1, rs2
  2191  	{mask: 0xfe00707f, value: 0x28001033, op: BSET, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2192  	// BSETI rd, rs1, shamt6
  2193  	{mask: 0xfc00707f, value: 0x28001013, op: BSETI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2194  	// CLZ rd, rs1
  2195  	{mask: 0xfff0707f, value: 0x60001013, op: CLZ, args: argTypeList{arg_rd, arg_rs1}},
  2196  	// CLZW rd, rs1
  2197  	{mask: 0xfff0707f, value: 0x6000101b, op: CLZW, args: argTypeList{arg_rd, arg_rs1}},
  2198  	// CPOP rd, rs1
  2199  	{mask: 0xfff0707f, value: 0x60201013, op: CPOP, args: argTypeList{arg_rd, arg_rs1}},
  2200  	// CPOPW rd, rs1
  2201  	{mask: 0xfff0707f, value: 0x6020101b, op: CPOPW, args: argTypeList{arg_rd, arg_rs1}},
  2202  	// CSRRC rd, csr, rs1
  2203  	{mask: 0x0000707f, value: 0x00003073, op: CSRRC, args: argTypeList{arg_rd, arg_csr, arg_rs1}},
  2204  	// CSRRCI rd, csr, zimm
  2205  	{mask: 0x0000707f, value: 0x00007073, op: CSRRCI, args: argTypeList{arg_rd, arg_csr, arg_zimm}},
  2206  	// CSRRS rd, csr, rs1
  2207  	{mask: 0x0000707f, value: 0x00002073, op: CSRRS, args: argTypeList{arg_rd, arg_csr, arg_rs1}},
  2208  	// CSRRSI rd, csr, zimm
  2209  	{mask: 0x0000707f, value: 0x00006073, op: CSRRSI, args: argTypeList{arg_rd, arg_csr, arg_zimm}},
  2210  	// CSRRW rd, csr, rs1
  2211  	{mask: 0x0000707f, value: 0x00001073, op: CSRRW, args: argTypeList{arg_rd, arg_csr, arg_rs1}},
  2212  	// CSRRWI rd, csr, zimm
  2213  	{mask: 0x0000707f, value: 0x00005073, op: CSRRWI, args: argTypeList{arg_rd, arg_csr, arg_zimm}},
  2214  	// CTZ rd, rs1
  2215  	{mask: 0xfff0707f, value: 0x60101013, op: CTZ, args: argTypeList{arg_rd, arg_rs1}},
  2216  	// CTZW rd, rs1
  2217  	{mask: 0xfff0707f, value: 0x6010101b, op: CTZW, args: argTypeList{arg_rd, arg_rs1}},
  2218  	// CZERO.EQZ rd, rs1, rs2
  2219  	{mask: 0xfe00707f, value: 0x0e005033, op: CZERO_EQZ, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2220  	// CZERO.NEZ rd, rs1, rs2
  2221  	{mask: 0xfe00707f, value: 0x0e007033, op: CZERO_NEZ, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2222  	// C.ADD rd_rs1_n0, c_rs2_n0
  2223  	{mask: 0x0000f003, value: 0x00009002, op: C_ADD, args: argTypeList{arg_rd_rs1_n0, arg_c_rs2_n0}},
  2224  	// C.ADDI rd_rs1_n0, c_nzimm6
  2225  	{mask: 0x0000e003, value: 0x00000001, op: C_ADDI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzimm6}},
  2226  	// C.ADDI16SP c_nzimm10
  2227  	{mask: 0x0000ef83, value: 0x00006101, op: C_ADDI16SP, args: argTypeList{arg_c_nzimm10}},
  2228  	// C.ADDI4SPN rd_p, c_nzuimm10
  2229  	{mask: 0x0000e003, value: 0x00000000, op: C_ADDI4SPN, args: argTypeList{arg_rd_p, arg_c_nzuimm10}},
  2230  	// C.ADDIW rd_rs1_n0, c_imm6
  2231  	{mask: 0x0000e003, value: 0x00002001, op: C_ADDIW, args: argTypeList{arg_rd_rs1_n0, arg_c_imm6}},
  2232  	// C.ADDW rd_rs1_p, rs2_p
  2233  	{mask: 0x0000fc63, value: 0x00009c21, op: C_ADDW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2234  	// C.AND rd_rs1_p, rs2_p
  2235  	{mask: 0x0000fc63, value: 0x00008c61, op: C_AND, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2236  	// C.ANDI rd_rs1_p, c_imm6
  2237  	{mask: 0x0000ec03, value: 0x00008801, op: C_ANDI, args: argTypeList{arg_rd_rs1_p, arg_c_imm6}},
  2238  	// C.BEQZ rs1_p, c_bimm9
  2239  	{mask: 0x0000e003, value: 0x0000c001, op: C_BEQZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}},
  2240  	// C.BNEZ rs1_p, c_bimm9
  2241  	{mask: 0x0000e003, value: 0x0000e001, op: C_BNEZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}},
  2242  	// C.EBREAK
  2243  	{mask: 0x0000ffff, value: 0x00009002, op: C_EBREAK, args: argTypeList{}},
  2244  	// C.FLD fd_p, rs1_p, c_uimm8
  2245  	{mask: 0x0000e003, value: 0x00002000, op: C_FLD, args: argTypeList{arg_fd_p, arg_rs1_p, arg_c_uimm8}},
  2246  	// C.FLDSP fd, c_uimm9sp
  2247  	{mask: 0x0000e003, value: 0x00002002, op: C_FLDSP, args: argTypeList{arg_fd, arg_c_uimm9sp}},
  2248  	// C.FSD rs1_p, fs2_p, c_uimm8
  2249  	{mask: 0x0000e003, value: 0x0000a000, op: C_FSD, args: argTypeList{arg_rs1_p, arg_fs2_p, arg_c_uimm8}},
  2250  	// C.FSDSP c_fs2, c_uimm9sp_s
  2251  	{mask: 0x0000e003, value: 0x0000a002, op: C_FSDSP, args: argTypeList{arg_c_fs2, arg_c_uimm9sp_s}},
  2252  	// C.J c_imm12
  2253  	{mask: 0x0000e003, value: 0x0000a001, op: C_J, args: argTypeList{arg_c_imm12}},
  2254  	// C.JALR c_rs1_n0
  2255  	{mask: 0x0000f07f, value: 0x00009002, op: C_JALR, args: argTypeList{arg_c_rs1_n0}},
  2256  	// C.JR rs1_n0
  2257  	{mask: 0x0000f07f, value: 0x00008002, op: C_JR, args: argTypeList{arg_rs1_n0}},
  2258  	// C.LD rd_p, rs1_p, c_uimm8
  2259  	{mask: 0x0000e003, value: 0x00006000, op: C_LD, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm8}},
  2260  	// C.LDSP rd_n0, c_uimm9sp
  2261  	{mask: 0x0000e003, value: 0x00006002, op: C_LDSP, args: argTypeList{arg_rd_n0, arg_c_uimm9sp}},
  2262  	// C.LI rd_n0, c_imm6
  2263  	{mask: 0x0000e003, value: 0x00004001, op: C_LI, args: argTypeList{arg_rd_n0, arg_c_imm6}},
  2264  	// C.LUI rd_n2, c_nzimm18
  2265  	{mask: 0x0000e003, value: 0x00006001, op: C_LUI, args: argTypeList{arg_rd_n2, arg_c_nzimm18}},
  2266  	// C.LW rd_p, rs1_p, c_uimm7
  2267  	{mask: 0x0000e003, value: 0x00004000, op: C_LW, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm7}},
  2268  	// C.LWSP rd_n0, c_uimm8sp
  2269  	{mask: 0x0000e003, value: 0x00004002, op: C_LWSP, args: argTypeList{arg_rd_n0, arg_c_uimm8sp}},
  2270  	// C.MV rd_n0, c_rs2_n0
  2271  	{mask: 0x0000f003, value: 0x00008002, op: C_MV, args: argTypeList{arg_rd_n0, arg_c_rs2_n0}},
  2272  	// C.NOP c_nzimm6
  2273  	{mask: 0x0000ef83, value: 0x00000001, op: C_NOP, args: argTypeList{arg_c_nzimm6}},
  2274  	// C.OR rd_rs1_p, rs2_p
  2275  	{mask: 0x0000fc63, value: 0x00008c41, op: C_OR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2276  	// C.SD rs1_p, rs2_p, c_uimm8
  2277  	{mask: 0x0000e003, value: 0x0000e000, op: C_SD, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm8}},
  2278  	// C.SDSP c_rs2, c_uimm9sp_s
  2279  	{mask: 0x0000e003, value: 0x0000e002, op: C_SDSP, args: argTypeList{arg_c_rs2, arg_c_uimm9sp_s}},
  2280  	// C.SLLI rd_rs1_n0, c_nzuimm6
  2281  	{mask: 0x0000e003, value: 0x00000002, op: C_SLLI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzuimm6}},
  2282  	// C.SRAI rd_rs1_p, c_nzuimm6
  2283  	{mask: 0x0000ec03, value: 0x00008401, op: C_SRAI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}},
  2284  	// C.SRLI rd_rs1_p, c_nzuimm6
  2285  	{mask: 0x0000ec03, value: 0x00008001, op: C_SRLI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}},
  2286  	// C.SUB rd_rs1_p, rs2_p
  2287  	{mask: 0x0000fc63, value: 0x00008c01, op: C_SUB, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2288  	// C.SUBW rd_rs1_p, rs2_p
  2289  	{mask: 0x0000fc63, value: 0x00009c01, op: C_SUBW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2290  	// C.SW rs1_p, rs2_p, c_uimm7
  2291  	{mask: 0x0000e003, value: 0x0000c000, op: C_SW, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm7}},
  2292  	// C.SWSP c_rs2, c_uimm8sp_s
  2293  	{mask: 0x0000e003, value: 0x0000c002, op: C_SWSP, args: argTypeList{arg_c_rs2, arg_c_uimm8sp_s}},
  2294  	// C.UNIMP
  2295  	{mask: 0x0000ffff, value: 0x00000000, op: C_UNIMP, args: argTypeList{}},
  2296  	// C.XOR rd_rs1_p, rs2_p
  2297  	{mask: 0x0000fc63, value: 0x00008c21, op: C_XOR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}},
  2298  	// DIV rd, rs1, rs2
  2299  	{mask: 0xfe00707f, value: 0x02004033, op: DIV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2300  	// DIVU rd, rs1, rs2
  2301  	{mask: 0xfe00707f, value: 0x02005033, op: DIVU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2302  	// DIVUW rd, rs1, rs2
  2303  	{mask: 0xfe00707f, value: 0x0200503b, op: DIVUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2304  	// DIVW rd, rs1, rs2
  2305  	{mask: 0xfe00707f, value: 0x0200403b, op: DIVW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2306  	// EBREAK
  2307  	{mask: 0xffffffff, value: 0x00100073, op: EBREAK, args: argTypeList{}},
  2308  	// ECALL
  2309  	{mask: 0xffffffff, value: 0x00000073, op: ECALL, args: argTypeList{}},
  2310  	// FADD.D fd, fs1, fs2
  2311  	{mask: 0xfe00007f, value: 0x02000053, op: FADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2312  	// FADD.H fd, fs1, fs2
  2313  	{mask: 0xfe00007f, value: 0x04000053, op: FADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2314  	// FADD.Q fd, fs1, fs2
  2315  	{mask: 0xfe00007f, value: 0x06000053, op: FADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2316  	// FADD.S fd, fs1, fs2
  2317  	{mask: 0xfe00007f, value: 0x00000053, op: FADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2318  	// FCLASS.D rd, fs1
  2319  	{mask: 0xfff0707f, value: 0xe2001053, op: FCLASS_D, args: argTypeList{arg_rd, arg_fs1}},
  2320  	// FCLASS.H rd, fs1
  2321  	{mask: 0xfff0707f, value: 0xe4001053, op: FCLASS_H, args: argTypeList{arg_rd, arg_fs1}},
  2322  	// FCLASS.Q rd, fs1
  2323  	{mask: 0xfff0707f, value: 0xe6001053, op: FCLASS_Q, args: argTypeList{arg_rd, arg_fs1}},
  2324  	// FCLASS.S rd, fs1
  2325  	{mask: 0xfff0707f, value: 0xe0001053, op: FCLASS_S, args: argTypeList{arg_rd, arg_fs1}},
  2326  	// FCVT.D.L fd, rs1
  2327  	{mask: 0xfff0007f, value: 0xd2200053, op: FCVT_D_L, args: argTypeList{arg_fd, arg_rs1}},
  2328  	// FCVT.D.LU fd, rs1
  2329  	{mask: 0xfff0007f, value: 0xd2300053, op: FCVT_D_LU, args: argTypeList{arg_fd, arg_rs1}},
  2330  	// FCVT.D.Q fd, fs1
  2331  	{mask: 0xfff0007f, value: 0x42300053, op: FCVT_D_Q, args: argTypeList{arg_fd, arg_fs1}},
  2332  	// FCVT.D.S fd, fs1
  2333  	{mask: 0xfff0007f, value: 0x42000053, op: FCVT_D_S, args: argTypeList{arg_fd, arg_fs1}},
  2334  	// FCVT.D.W fd, rs1
  2335  	{mask: 0xfff0007f, value: 0xd2000053, op: FCVT_D_W, args: argTypeList{arg_fd, arg_rs1}},
  2336  	// FCVT.D.WU fd, rs1
  2337  	{mask: 0xfff0007f, value: 0xd2100053, op: FCVT_D_WU, args: argTypeList{arg_fd, arg_rs1}},
  2338  	// FCVT.H.L fd, rs1
  2339  	{mask: 0xfff0007f, value: 0xd4200053, op: FCVT_H_L, args: argTypeList{arg_fd, arg_rs1}},
  2340  	// FCVT.H.LU fd, rs1
  2341  	{mask: 0xfff0007f, value: 0xd4300053, op: FCVT_H_LU, args: argTypeList{arg_fd, arg_rs1}},
  2342  	// FCVT.H.S fd, fs1
  2343  	{mask: 0xfff0007f, value: 0x44000053, op: FCVT_H_S, args: argTypeList{arg_fd, arg_fs1}},
  2344  	// FCVT.H.W fd, rs1
  2345  	{mask: 0xfff0007f, value: 0xd4000053, op: FCVT_H_W, args: argTypeList{arg_fd, arg_rs1}},
  2346  	// FCVT.H.WU fd, rs1
  2347  	{mask: 0xfff0007f, value: 0xd4100053, op: FCVT_H_WU, args: argTypeList{arg_fd, arg_rs1}},
  2348  	// FCVT.LU.D rd, fs1
  2349  	{mask: 0xfff0007f, value: 0xc2300053, op: FCVT_LU_D, args: argTypeList{arg_rd, arg_fs1}},
  2350  	// FCVT.LU.H rd, fs1
  2351  	{mask: 0xfff0007f, value: 0xc4300053, op: FCVT_LU_H, args: argTypeList{arg_rd, arg_fs1}},
  2352  	// FCVT.LU.Q rd, fs1
  2353  	{mask: 0xfff0007f, value: 0xc6300053, op: FCVT_LU_Q, args: argTypeList{arg_rd, arg_fs1}},
  2354  	// FCVT.LU.S rd, fs1
  2355  	{mask: 0xfff0007f, value: 0xc0300053, op: FCVT_LU_S, args: argTypeList{arg_rd, arg_fs1}},
  2356  	// FCVT.L.D rd, fs1
  2357  	{mask: 0xfff0007f, value: 0xc2200053, op: FCVT_L_D, args: argTypeList{arg_rd, arg_fs1}},
  2358  	// FCVT.L.H rd, fs1
  2359  	{mask: 0xfff0007f, value: 0xc4200053, op: FCVT_L_H, args: argTypeList{arg_rd, arg_fs1}},
  2360  	// FCVT.L.Q rd, fs1
  2361  	{mask: 0xfff0007f, value: 0xc6200053, op: FCVT_L_Q, args: argTypeList{arg_rd, arg_fs1}},
  2362  	// FCVT.L.S rd, fs1
  2363  	{mask: 0xfff0007f, value: 0xc0200053, op: FCVT_L_S, args: argTypeList{arg_rd, arg_fs1}},
  2364  	// FCVT.Q.D fd, fs1
  2365  	{mask: 0xfff0007f, value: 0x46100053, op: FCVT_Q_D, args: argTypeList{arg_fd, arg_fs1}},
  2366  	// FCVT.Q.L fd, rs1
  2367  	{mask: 0xfff0007f, value: 0xd6200053, op: FCVT_Q_L, args: argTypeList{arg_fd, arg_rs1}},
  2368  	// FCVT.Q.LU fd, rs1
  2369  	{mask: 0xfff0007f, value: 0xd6300053, op: FCVT_Q_LU, args: argTypeList{arg_fd, arg_rs1}},
  2370  	// FCVT.Q.S fd, fs1
  2371  	{mask: 0xfff0007f, value: 0x46000053, op: FCVT_Q_S, args: argTypeList{arg_fd, arg_fs1}},
  2372  	// FCVT.Q.W fd, rs1
  2373  	{mask: 0xfff0007f, value: 0xd6000053, op: FCVT_Q_W, args: argTypeList{arg_fd, arg_rs1}},
  2374  	// FCVT.Q.WU fd, rs1
  2375  	{mask: 0xfff0007f, value: 0xd6100053, op: FCVT_Q_WU, args: argTypeList{arg_fd, arg_rs1}},
  2376  	// FCVT.S.D fd, fs1
  2377  	{mask: 0xfff0007f, value: 0x40100053, op: FCVT_S_D, args: argTypeList{arg_fd, arg_fs1}},
  2378  	// FCVT.S.H fd, fs1
  2379  	{mask: 0xfff0007f, value: 0x40200053, op: FCVT_S_H, args: argTypeList{arg_fd, arg_fs1}},
  2380  	// FCVT.S.L fd, rs1
  2381  	{mask: 0xfff0007f, value: 0xd0200053, op: FCVT_S_L, args: argTypeList{arg_fd, arg_rs1}},
  2382  	// FCVT.S.LU fd, rs1
  2383  	{mask: 0xfff0007f, value: 0xd0300053, op: FCVT_S_LU, args: argTypeList{arg_fd, arg_rs1}},
  2384  	// FCVT.S.Q fd, fs1
  2385  	{mask: 0xfff0007f, value: 0x40300053, op: FCVT_S_Q, args: argTypeList{arg_fd, arg_fs1}},
  2386  	// FCVT.S.W fd, rs1
  2387  	{mask: 0xfff0007f, value: 0xd0000053, op: FCVT_S_W, args: argTypeList{arg_fd, arg_rs1}},
  2388  	// FCVT.S.WU fd, rs1
  2389  	{mask: 0xfff0007f, value: 0xd0100053, op: FCVT_S_WU, args: argTypeList{arg_fd, arg_rs1}},
  2390  	// FCVT.WU.D rd, fs1
  2391  	{mask: 0xfff0007f, value: 0xc2100053, op: FCVT_WU_D, args: argTypeList{arg_rd, arg_fs1}},
  2392  	// FCVT.WU.H rd, fs1
  2393  	{mask: 0xfff0007f, value: 0xc4100053, op: FCVT_WU_H, args: argTypeList{arg_rd, arg_fs1}},
  2394  	// FCVT.WU.Q rd, fs1
  2395  	{mask: 0xfff0007f, value: 0xc6100053, op: FCVT_WU_Q, args: argTypeList{arg_rd, arg_fs1}},
  2396  	// FCVT.WU.S rd, fs1
  2397  	{mask: 0xfff0007f, value: 0xc0100053, op: FCVT_WU_S, args: argTypeList{arg_rd, arg_fs1}},
  2398  	// FCVT.W.D rd, fs1
  2399  	{mask: 0xfff0007f, value: 0xc2000053, op: FCVT_W_D, args: argTypeList{arg_rd, arg_fs1}},
  2400  	// FCVT.W.H rd, fs1
  2401  	{mask: 0xfff0007f, value: 0xc4000053, op: FCVT_W_H, args: argTypeList{arg_rd, arg_fs1}},
  2402  	// FCVT.W.Q rd, fs1
  2403  	{mask: 0xfff0007f, value: 0xc6000053, op: FCVT_W_Q, args: argTypeList{arg_rd, arg_fs1}},
  2404  	// FCVT.W.S rd, fs1
  2405  	{mask: 0xfff0007f, value: 0xc0000053, op: FCVT_W_S, args: argTypeList{arg_rd, arg_fs1}},
  2406  	// FDIV.D fd, fs1, fs2
  2407  	{mask: 0xfe00007f, value: 0x1a000053, op: FDIV_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2408  	// FDIV.H fd, fs1, fs2
  2409  	{mask: 0xfe00007f, value: 0x1c000053, op: FDIV_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2410  	// FDIV.Q fd, fs1, fs2
  2411  	{mask: 0xfe00007f, value: 0x1e000053, op: FDIV_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2412  	// FDIV.S fd, fs1, fs2
  2413  	{mask: 0xfe00007f, value: 0x18000053, op: FDIV_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2414  	// FENCE pred, succ
  2415  	{mask: 0x0000707f, value: 0x0000000f, op: FENCE, args: argTypeList{arg_pred, arg_succ}},
  2416  	// FENCE.I
  2417  	{mask: 0x0000707f, value: 0x0000100f, op: FENCE_I, args: argTypeList{}},
  2418  	// FEQ.D rd, fs1, fs2
  2419  	{mask: 0xfe00707f, value: 0xa2002053, op: FEQ_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2420  	// FEQ.H rd, fs1, fs2
  2421  	{mask: 0xfe00707f, value: 0xa4002053, op: FEQ_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2422  	// FEQ.Q rd, fs1, fs2
  2423  	{mask: 0xfe00707f, value: 0xa6002053, op: FEQ_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2424  	// FEQ.S rd, fs1, fs2
  2425  	{mask: 0xfe00707f, value: 0xa0002053, op: FEQ_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2426  	// FLD fd, rs1_mem
  2427  	{mask: 0x0000707f, value: 0x00003007, op: FLD, args: argTypeList{arg_fd, arg_rs1_mem}},
  2428  	// FLE.D rd, fs1, fs2
  2429  	{mask: 0xfe00707f, value: 0xa2000053, op: FLE_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2430  	// FLE.H rd, fs1, fs2
  2431  	{mask: 0xfe00707f, value: 0xa4000053, op: FLE_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2432  	// FLE.Q rd, fs1, fs2
  2433  	{mask: 0xfe00707f, value: 0xa6000053, op: FLE_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2434  	// FLE.S rd, fs1, fs2
  2435  	{mask: 0xfe00707f, value: 0xa0000053, op: FLE_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2436  	// FLH fd, rs1_mem
  2437  	{mask: 0x0000707f, value: 0x00001007, op: FLH, args: argTypeList{arg_fd, arg_rs1_mem}},
  2438  	// FLQ fd, rs1_mem
  2439  	{mask: 0x0000707f, value: 0x00004007, op: FLQ, args: argTypeList{arg_fd, arg_rs1_mem}},
  2440  	// FLT.D rd, fs1, fs2
  2441  	{mask: 0xfe00707f, value: 0xa2001053, op: FLT_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2442  	// FLT.H rd, fs1, fs2
  2443  	{mask: 0xfe00707f, value: 0xa4001053, op: FLT_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2444  	// FLT.Q rd, fs1, fs2
  2445  	{mask: 0xfe00707f, value: 0xa6001053, op: FLT_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2446  	// FLT.S rd, fs1, fs2
  2447  	{mask: 0xfe00707f, value: 0xa0001053, op: FLT_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}},
  2448  	// FLW fd, rs1_mem
  2449  	{mask: 0x0000707f, value: 0x00002007, op: FLW, args: argTypeList{arg_fd, arg_rs1_mem}},
  2450  	// FMADD.D fd, fs1, fs2, fs3
  2451  	{mask: 0x0600007f, value: 0x02000043, op: FMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2452  	// FMADD.H fd, fs1, fs2, fs3
  2453  	{mask: 0x0600007f, value: 0x04000043, op: FMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2454  	// FMADD.Q fd, fs1, fs2, fs3
  2455  	{mask: 0x0600007f, value: 0x06000043, op: FMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2456  	// FMADD.S fd, fs1, fs2, fs3
  2457  	{mask: 0x0600007f, value: 0x00000043, op: FMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2458  	// FMAX.D fd, fs1, fs2
  2459  	{mask: 0xfe00707f, value: 0x2a001053, op: FMAX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2460  	// FMAX.H fd, fs1, fs2
  2461  	{mask: 0xfe00707f, value: 0x2c001053, op: FMAX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2462  	// FMAX.Q fd, fs1, fs2
  2463  	{mask: 0xfe00707f, value: 0x2e001053, op: FMAX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2464  	// FMAX.S fd, fs1, fs2
  2465  	{mask: 0xfe00707f, value: 0x28001053, op: FMAX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2466  	// FMIN.D fd, fs1, fs2
  2467  	{mask: 0xfe00707f, value: 0x2a000053, op: FMIN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2468  	// FMIN.H fd, fs1, fs2
  2469  	{mask: 0xfe00707f, value: 0x2c000053, op: FMIN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2470  	// FMIN.Q fd, fs1, fs2
  2471  	{mask: 0xfe00707f, value: 0x2e000053, op: FMIN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2472  	// FMIN.S fd, fs1, fs2
  2473  	{mask: 0xfe00707f, value: 0x28000053, op: FMIN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2474  	// FMSUB.D fd, fs1, fs2, fs3
  2475  	{mask: 0x0600007f, value: 0x02000047, op: FMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2476  	// FMSUB.H fd, fs1, fs2, fs3
  2477  	{mask: 0x0600007f, value: 0x04000047, op: FMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2478  	// FMSUB.Q fd, fs1, fs2, fs3
  2479  	{mask: 0x0600007f, value: 0x06000047, op: FMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2480  	// FMSUB.S fd, fs1, fs2, fs3
  2481  	{mask: 0x0600007f, value: 0x00000047, op: FMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2482  	// FMUL.D fd, fs1, fs2
  2483  	{mask: 0xfe00007f, value: 0x12000053, op: FMUL_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2484  	// FMUL.H fd, fs1, fs2
  2485  	{mask: 0xfe00007f, value: 0x14000053, op: FMUL_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2486  	// FMUL.Q fd, fs1, fs2
  2487  	{mask: 0xfe00007f, value: 0x16000053, op: FMUL_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2488  	// FMUL.S fd, fs1, fs2
  2489  	{mask: 0xfe00007f, value: 0x10000053, op: FMUL_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2490  	// FMV.D.X fd, rs1
  2491  	{mask: 0xfff0707f, value: 0xf2000053, op: FMV_D_X, args: argTypeList{arg_fd, arg_rs1}},
  2492  	// FMV.H.X fd, rs1
  2493  	{mask: 0xfff0707f, value: 0xf4000053, op: FMV_H_X, args: argTypeList{arg_fd, arg_rs1}},
  2494  	// FMV.W.X fd, rs1
  2495  	{mask: 0xfff0707f, value: 0xf0000053, op: FMV_W_X, args: argTypeList{arg_fd, arg_rs1}},
  2496  	// FMV.X.D rd, fs1
  2497  	{mask: 0xfff0707f, value: 0xe2000053, op: FMV_X_D, args: argTypeList{arg_rd, arg_fs1}},
  2498  	// FMV.X.H rd, fs1
  2499  	{mask: 0xfff0707f, value: 0xe4000053, op: FMV_X_H, args: argTypeList{arg_rd, arg_fs1}},
  2500  	// FMV.X.W rd, fs1
  2501  	{mask: 0xfff0707f, value: 0xe0000053, op: FMV_X_W, args: argTypeList{arg_rd, arg_fs1}},
  2502  	// FNMADD.D fd, fs1, fs2, fs3
  2503  	{mask: 0x0600007f, value: 0x0200004f, op: FNMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2504  	// FNMADD.H fd, fs1, fs2, fs3
  2505  	{mask: 0x0600007f, value: 0x0400004f, op: FNMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2506  	// FNMADD.Q fd, fs1, fs2, fs3
  2507  	{mask: 0x0600007f, value: 0x0600004f, op: FNMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2508  	// FNMADD.S fd, fs1, fs2, fs3
  2509  	{mask: 0x0600007f, value: 0x0000004f, op: FNMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2510  	// FNMSUB.D fd, fs1, fs2, fs3
  2511  	{mask: 0x0600007f, value: 0x0200004b, op: FNMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2512  	// FNMSUB.H fd, fs1, fs2, fs3
  2513  	{mask: 0x0600007f, value: 0x0400004b, op: FNMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2514  	// FNMSUB.Q fd, fs1, fs2, fs3
  2515  	{mask: 0x0600007f, value: 0x0600004b, op: FNMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2516  	// FNMSUB.S fd, fs1, fs2, fs3
  2517  	{mask: 0x0600007f, value: 0x0000004b, op: FNMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}},
  2518  	// FSD fs2, rs1_store
  2519  	{mask: 0x0000707f, value: 0x00003027, op: FSD, args: argTypeList{arg_fs2, arg_rs1_store}},
  2520  	// FSGNJN.D fd, fs1, fs2
  2521  	{mask: 0xfe00707f, value: 0x22001053, op: FSGNJN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2522  	// FSGNJN.H fd, fs1, fs2
  2523  	{mask: 0xfe00707f, value: 0x24001053, op: FSGNJN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2524  	// FSGNJN.Q fd, fs1, fs2
  2525  	{mask: 0xfe00707f, value: 0x26001053, op: FSGNJN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2526  	// FSGNJN.S fd, fs1, fs2
  2527  	{mask: 0xfe00707f, value: 0x20001053, op: FSGNJN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2528  	// FSGNJX.D fd, fs1, fs2
  2529  	{mask: 0xfe00707f, value: 0x22002053, op: FSGNJX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2530  	// FSGNJX.H fd, fs1, fs2
  2531  	{mask: 0xfe00707f, value: 0x24002053, op: FSGNJX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2532  	// FSGNJX.Q fd, fs1, fs2
  2533  	{mask: 0xfe00707f, value: 0x26002053, op: FSGNJX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2534  	// FSGNJX.S fd, fs1, fs2
  2535  	{mask: 0xfe00707f, value: 0x20002053, op: FSGNJX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2536  	// FSGNJ.D fd, fs1, fs2
  2537  	{mask: 0xfe00707f, value: 0x22000053, op: FSGNJ_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2538  	// FSGNJ.H fd, fs1, fs2
  2539  	{mask: 0xfe00707f, value: 0x24000053, op: FSGNJ_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2540  	// FSGNJ.Q fd, fs1, fs2
  2541  	{mask: 0xfe00707f, value: 0x26000053, op: FSGNJ_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2542  	// FSGNJ.S fd, fs1, fs2
  2543  	{mask: 0xfe00707f, value: 0x20000053, op: FSGNJ_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2544  	// FSH fs2, rs1_store
  2545  	{mask: 0x0000707f, value: 0x00001027, op: FSH, args: argTypeList{arg_fs2, arg_rs1_store}},
  2546  	// FSQ fs2, rs1_store
  2547  	{mask: 0x0000707f, value: 0x00004027, op: FSQ, args: argTypeList{arg_fs2, arg_rs1_store}},
  2548  	// FSQRT.D fd, fs1
  2549  	{mask: 0xfff0007f, value: 0x5a000053, op: FSQRT_D, args: argTypeList{arg_fd, arg_fs1}},
  2550  	// FSQRT.H fd, fs1
  2551  	{mask: 0xfff0007f, value: 0x5c000053, op: FSQRT_H, args: argTypeList{arg_fd, arg_fs1}},
  2552  	// FSQRT.Q fd, fs1
  2553  	{mask: 0xfff0007f, value: 0x5e000053, op: FSQRT_Q, args: argTypeList{arg_fd, arg_fs1}},
  2554  	// FSQRT.S fd, fs1
  2555  	{mask: 0xfff0007f, value: 0x58000053, op: FSQRT_S, args: argTypeList{arg_fd, arg_fs1}},
  2556  	// FSUB.D fd, fs1, fs2
  2557  	{mask: 0xfe00007f, value: 0x0a000053, op: FSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2558  	// FSUB.H fd, fs1, fs2
  2559  	{mask: 0xfe00007f, value: 0x0c000053, op: FSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2560  	// FSUB.Q fd, fs1, fs2
  2561  	{mask: 0xfe00007f, value: 0x0e000053, op: FSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2562  	// FSUB.S fd, fs1, fs2
  2563  	{mask: 0xfe00007f, value: 0x08000053, op: FSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}},
  2564  	// FSW fs2, rs1_store
  2565  	{mask: 0x0000707f, value: 0x00002027, op: FSW, args: argTypeList{arg_fs2, arg_rs1_store}},
  2566  	// JAL rd, jimm20
  2567  	{mask: 0x0000007f, value: 0x0000006f, op: JAL, args: argTypeList{arg_rd, arg_jimm20}},
  2568  	// JALR rd, rs1_mem
  2569  	{mask: 0x0000707f, value: 0x00000067, op: JALR, args: argTypeList{arg_rd, arg_rs1_mem}},
  2570  	// LB rd, rs1_mem
  2571  	{mask: 0x0000707f, value: 0x00000003, op: LB, args: argTypeList{arg_rd, arg_rs1_mem}},
  2572  	// LBU rd, rs1_mem
  2573  	{mask: 0x0000707f, value: 0x00004003, op: LBU, args: argTypeList{arg_rd, arg_rs1_mem}},
  2574  	// LD rd, rs1_mem
  2575  	{mask: 0x0000707f, value: 0x00003003, op: LD, args: argTypeList{arg_rd, arg_rs1_mem}},
  2576  	// LH rd, rs1_mem
  2577  	{mask: 0x0000707f, value: 0x00001003, op: LH, args: argTypeList{arg_rd, arg_rs1_mem}},
  2578  	// LHU rd, rs1_mem
  2579  	{mask: 0x0000707f, value: 0x00005003, op: LHU, args: argTypeList{arg_rd, arg_rs1_mem}},
  2580  	// LR.D rd, rs1_ptr
  2581  	{mask: 0xfff0707f, value: 0x1000302f, op: LR_D, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2582  	// LR.D.AQ rd, rs1_ptr
  2583  	{mask: 0xfff0707f, value: 0x1400302f, op: LR_D_AQ, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2584  	// LR.D.AQRL rd, rs1_ptr
  2585  	{mask: 0xfff0707f, value: 0x1600302f, op: LR_D_AQRL, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2586  	// LR.D.RL rd, rs1_ptr
  2587  	{mask: 0xfff0707f, value: 0x1200302f, op: LR_D_RL, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2588  	// LR.W rd, rs1_ptr
  2589  	{mask: 0xfff0707f, value: 0x1000202f, op: LR_W, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2590  	// LR.W.AQ rd, rs1_ptr
  2591  	{mask: 0xfff0707f, value: 0x1400202f, op: LR_W_AQ, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2592  	// LR.W.AQRL rd, rs1_ptr
  2593  	{mask: 0xfff0707f, value: 0x1600202f, op: LR_W_AQRL, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2594  	// LR.W.RL rd, rs1_ptr
  2595  	{mask: 0xfff0707f, value: 0x1200202f, op: LR_W_RL, args: argTypeList{arg_rd, arg_rs1_ptr}},
  2596  	// LUI rd, imm20
  2597  	{mask: 0x0000007f, value: 0x00000037, op: LUI, args: argTypeList{arg_rd, arg_imm20}},
  2598  	// LW rd, rs1_mem
  2599  	{mask: 0x0000707f, value: 0x00002003, op: LW, args: argTypeList{arg_rd, arg_rs1_mem}},
  2600  	// LWU rd, rs1_mem
  2601  	{mask: 0x0000707f, value: 0x00006003, op: LWU, args: argTypeList{arg_rd, arg_rs1_mem}},
  2602  	// MAX rd, rs1, rs2
  2603  	{mask: 0xfe00707f, value: 0x0a006033, op: MAX, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2604  	// MAXU rd, rs1, rs2
  2605  	{mask: 0xfe00707f, value: 0x0a007033, op: MAXU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2606  	// MIN rd, rs1, rs2
  2607  	{mask: 0xfe00707f, value: 0x0a004033, op: MIN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2608  	// MINU rd, rs1, rs2
  2609  	{mask: 0xfe00707f, value: 0x0a005033, op: MINU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2610  	// MUL rd, rs1, rs2
  2611  	{mask: 0xfe00707f, value: 0x02000033, op: MUL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2612  	// MULH rd, rs1, rs2
  2613  	{mask: 0xfe00707f, value: 0x02001033, op: MULH, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2614  	// MULHSU rd, rs1, rs2
  2615  	{mask: 0xfe00707f, value: 0x02002033, op: MULHSU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2616  	// MULHU rd, rs1, rs2
  2617  	{mask: 0xfe00707f, value: 0x02003033, op: MULHU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2618  	// MULW rd, rs1, rs2
  2619  	{mask: 0xfe00707f, value: 0x0200003b, op: MULW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2620  	// OR rd, rs1, rs2
  2621  	{mask: 0xfe00707f, value: 0x00006033, op: OR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2622  	// ORC.B rd, rs1
  2623  	{mask: 0xfff0707f, value: 0x28705013, op: ORC_B, args: argTypeList{arg_rd, arg_rs1}},
  2624  	// ORI rd, rs1, imm12
  2625  	{mask: 0x0000707f, value: 0x00006013, op: ORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2626  	// ORN rd, rs1, rs2
  2627  	{mask: 0xfe00707f, value: 0x40006033, op: ORN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2628  	// REM rd, rs1, rs2
  2629  	{mask: 0xfe00707f, value: 0x02006033, op: REM, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2630  	// REMU rd, rs1, rs2
  2631  	{mask: 0xfe00707f, value: 0x02007033, op: REMU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2632  	// REMUW rd, rs1, rs2
  2633  	{mask: 0xfe00707f, value: 0x0200703b, op: REMUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2634  	// REMW rd, rs1, rs2
  2635  	{mask: 0xfe00707f, value: 0x0200603b, op: REMW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2636  	// REV8 rd, rs1
  2637  	{mask: 0xfff0707f, value: 0x6b805013, op: REV8, args: argTypeList{arg_rd, arg_rs1}},
  2638  	// ROL rd, rs1, rs2
  2639  	{mask: 0xfe00707f, value: 0x60001033, op: ROL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2640  	// ROLW rd, rs1, rs2
  2641  	{mask: 0xfe00707f, value: 0x6000103b, op: ROLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2642  	// ROR rd, rs1, rs2
  2643  	{mask: 0xfe00707f, value: 0x60005033, op: ROR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2644  	// RORI rd, rs1, shamt6
  2645  	{mask: 0xfc00707f, value: 0x60005013, op: RORI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2646  	// RORIW rd, rs1, shamt5
  2647  	{mask: 0xfe00707f, value: 0x6000501b, op: RORIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}},
  2648  	// RORW rd, rs1, rs2
  2649  	{mask: 0xfe00707f, value: 0x6000503b, op: RORW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2650  	// SB rs2, rs1_store
  2651  	{mask: 0x0000707f, value: 0x00000023, op: SB, args: argTypeList{arg_rs2, arg_rs1_store}},
  2652  	// SC.D rd, rs2, rs1_ptr
  2653  	{mask: 0xfe00707f, value: 0x1800302f, op: SC_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2654  	// SC.D.AQ rd, rs2, rs1_ptr
  2655  	{mask: 0xfe00707f, value: 0x1c00302f, op: SC_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2656  	// SC.D.AQRL rd, rs2, rs1_ptr
  2657  	{mask: 0xfe00707f, value: 0x1e00302f, op: SC_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2658  	// SC.D.RL rd, rs2, rs1_ptr
  2659  	{mask: 0xfe00707f, value: 0x1a00302f, op: SC_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2660  	// SC.W rd, rs2, rs1_ptr
  2661  	{mask: 0xfe00707f, value: 0x1800202f, op: SC_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2662  	// SC.W.AQ rd, rs2, rs1_ptr
  2663  	{mask: 0xfe00707f, value: 0x1c00202f, op: SC_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2664  	// SC.W.AQRL rd, rs2, rs1_ptr
  2665  	{mask: 0xfe00707f, value: 0x1e00202f, op: SC_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2666  	// SC.W.RL rd, rs2, rs1_ptr
  2667  	{mask: 0xfe00707f, value: 0x1a00202f, op: SC_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_ptr}},
  2668  	// SD rs2, rs1_store
  2669  	{mask: 0x0000707f, value: 0x00003023, op: SD, args: argTypeList{arg_rs2, arg_rs1_store}},
  2670  	// SEXT.B rd, rs1
  2671  	{mask: 0xfff0707f, value: 0x60401013, op: SEXT_B, args: argTypeList{arg_rd, arg_rs1}},
  2672  	// SEXT.H rd, rs1
  2673  	{mask: 0xfff0707f, value: 0x60501013, op: SEXT_H, args: argTypeList{arg_rd, arg_rs1}},
  2674  	// SH rs2, rs1_store
  2675  	{mask: 0x0000707f, value: 0x00001023, op: SH, args: argTypeList{arg_rs2, arg_rs1_store}},
  2676  	// SH1ADD rd, rs1, rs2
  2677  	{mask: 0xfe00707f, value: 0x20002033, op: SH1ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2678  	// SH1ADD.UW rd, rs1, rs2
  2679  	{mask: 0xfe00707f, value: 0x2000203b, op: SH1ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2680  	// SH2ADD rd, rs1, rs2
  2681  	{mask: 0xfe00707f, value: 0x20004033, op: SH2ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2682  	// SH2ADD.UW rd, rs1, rs2
  2683  	{mask: 0xfe00707f, value: 0x2000403b, op: SH2ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2684  	// SH3ADD rd, rs1, rs2
  2685  	{mask: 0xfe00707f, value: 0x20006033, op: SH3ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2686  	// SH3ADD.UW rd, rs1, rs2
  2687  	{mask: 0xfe00707f, value: 0x2000603b, op: SH3ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2688  	// SLL rd, rs1, rs2
  2689  	{mask: 0xfe00707f, value: 0x00001033, op: SLL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2690  	// SLLI rd, rs1, shamt6
  2691  	{mask: 0xfc00707f, value: 0x00001013, op: SLLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2692  	// SLLIW rd, rs1, shamt5
  2693  	{mask: 0xfe00707f, value: 0x0000101b, op: SLLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}},
  2694  	// SLLI.UW rd, rs1, shamt6
  2695  	{mask: 0xfc00707f, value: 0x0800101b, op: SLLI_UW, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2696  	// SLLW rd, rs1, rs2
  2697  	{mask: 0xfe00707f, value: 0x0000103b, op: SLLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2698  	// SLT rd, rs1, rs2
  2699  	{mask: 0xfe00707f, value: 0x00002033, op: SLT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2700  	// SLTI rd, rs1, imm12
  2701  	{mask: 0x0000707f, value: 0x00002013, op: SLTI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2702  	// SLTIU rd, rs1, imm12
  2703  	{mask: 0x0000707f, value: 0x00003013, op: SLTIU, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  2704  	// SLTU rd, rs1, rs2
  2705  	{mask: 0xfe00707f, value: 0x00003033, op: SLTU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2706  	// SRA rd, rs1, rs2
  2707  	{mask: 0xfe00707f, value: 0x40005033, op: SRA, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2708  	// SRAI rd, rs1, shamt6
  2709  	{mask: 0xfc00707f, value: 0x40005013, op: SRAI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2710  	// SRAIW rd, rs1, shamt5
  2711  	{mask: 0xfe00707f, value: 0x4000501b, op: SRAIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}},
  2712  	// SRAW rd, rs1, rs2
  2713  	{mask: 0xfe00707f, value: 0x4000503b, op: SRAW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2714  	// SRL rd, rs1, rs2
  2715  	{mask: 0xfe00707f, value: 0x00005033, op: SRL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2716  	// SRLI rd, rs1, shamt6
  2717  	{mask: 0xfc00707f, value: 0x00005013, op: SRLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
  2718  	// SRLIW rd, rs1, shamt5
  2719  	{mask: 0xfe00707f, value: 0x0000501b, op: SRLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}},
  2720  	// SRLW rd, rs1, rs2
  2721  	{mask: 0xfe00707f, value: 0x0000503b, op: SRLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2722  	// SUB rd, rs1, rs2
  2723  	{mask: 0xfe00707f, value: 0x40000033, op: SUB, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2724  	// SUBW rd, rs1, rs2
  2725  	{mask: 0xfe00707f, value: 0x4000003b, op: SUBW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  2726  	// SW rs2, rs1_store
  2727  	{mask: 0x0000707f, value: 0x00002023, op: SW, args: argTypeList{arg_rs2, arg_rs1_store}},
  2728  	// VAADDU.VV vm, vs2, vs1, vd
  2729  	{mask: 0xfc00707f, value: 0x20002057, op: VAADDU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2730  	// VAADDU.VX vm, vs2, rs1, vd
  2731  	{mask: 0xfc00707f, value: 0x20006057, op: VAADDU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2732  	// VAADD.VV vm, vs2, vs1, vd
  2733  	{mask: 0xfc00707f, value: 0x24002057, op: VAADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2734  	// VAADD.VX vm, vs2, rs1, vd
  2735  	{mask: 0xfc00707f, value: 0x24006057, op: VAADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2736  	// VADC.VIM vs2, simm5, vd
  2737  	{mask: 0xfe00707f, value: 0x40003057, op: VADC_VIM, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
  2738  	// VADC.VVM vs2, vs1, vd
  2739  	{mask: 0xfe00707f, value: 0x40000057, op: VADC_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2740  	// VADC.VXM vs2, rs1, vd
  2741  	{mask: 0xfe00707f, value: 0x40004057, op: VADC_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  2742  	// VADD.VI vm, vs2, simm5, vd
  2743  	{mask: 0xfc00707f, value: 0x00003057, op: VADD_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  2744  	// VADD.VV vm, vs2, vs1, vd
  2745  	{mask: 0xfc00707f, value: 0x00000057, op: VADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2746  	// VADD.VX vm, vs2, rs1, vd
  2747  	{mask: 0xfc00707f, value: 0x00004057, op: VADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2748  	// VAND.VI vm, vs2, simm5, vd
  2749  	{mask: 0xfc00707f, value: 0x24003057, op: VAND_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  2750  	// VAND.VV vm, vs2, vs1, vd
  2751  	{mask: 0xfc00707f, value: 0x24000057, op: VAND_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2752  	// VAND.VX vm, vs2, rs1, vd
  2753  	{mask: 0xfc00707f, value: 0x24004057, op: VAND_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2754  	// VASUBU.VV vm, vs2, vs1, vd
  2755  	{mask: 0xfc00707f, value: 0x28002057, op: VASUBU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2756  	// VASUBU.VX vm, vs2, rs1, vd
  2757  	{mask: 0xfc00707f, value: 0x28006057, op: VASUBU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2758  	// VASUB.VV vm, vs2, vs1, vd
  2759  	{mask: 0xfc00707f, value: 0x2c002057, op: VASUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2760  	// VASUB.VX vm, vs2, rs1, vd
  2761  	{mask: 0xfc00707f, value: 0x2c006057, op: VASUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2762  	// VCOMPRESS.VM vs2, vs1, vd
  2763  	{mask: 0xfe00707f, value: 0x5e002057, op: VCOMPRESS_VM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  2764  	// VCPOP.M vm, vs2, rd
  2765  	{mask: 0xfc0ff07f, value: 0x40082057, op: VCPOP_M, args: argTypeList{arg_vm, arg_vs2, arg_rd}},
  2766  	// VDIVU.VV vm, vs2, vs1, vd
  2767  	{mask: 0xfc00707f, value: 0x80002057, op: VDIVU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2768  	// VDIVU.VX vm, vs2, rs1, vd
  2769  	{mask: 0xfc00707f, value: 0x80006057, op: VDIVU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2770  	// VDIV.VV vm, vs2, vs1, vd
  2771  	{mask: 0xfc00707f, value: 0x84002057, op: VDIV_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2772  	// VDIV.VX vm, vs2, rs1, vd
  2773  	{mask: 0xfc00707f, value: 0x84006057, op: VDIV_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  2774  	// VFADD.VF vm, vs2, fs1, vd
  2775  	{mask: 0xfc00707f, value: 0x00005057, op: VFADD_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2776  	// VFADD.VV vm, vs2, vs1, vd
  2777  	{mask: 0xfc00707f, value: 0x00001057, op: VFADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2778  	// VFCLASS.V vm, vs2, vd
  2779  	{mask: 0xfc0ff07f, value: 0x4c081057, op: VFCLASS_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2780  	// VFCVT.F.XU.V vm, vs2, vd
  2781  	{mask: 0xfc0ff07f, value: 0x48011057, op: VFCVT_F_XU_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2782  	// VFCVT.F.X.V vm, vs2, vd
  2783  	{mask: 0xfc0ff07f, value: 0x48019057, op: VFCVT_F_X_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2784  	// VFCVT.RTZ.XU.F.V vm, vs2, vd
  2785  	{mask: 0xfc0ff07f, value: 0x48031057, op: VFCVT_RTZ_XU_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2786  	// VFCVT.RTZ.X.F.V vm, vs2, vd
  2787  	{mask: 0xfc0ff07f, value: 0x48039057, op: VFCVT_RTZ_X_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2788  	// VFCVT.XU.F.V vm, vs2, vd
  2789  	{mask: 0xfc0ff07f, value: 0x48001057, op: VFCVT_XU_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2790  	// VFCVT.X.F.V vm, vs2, vd
  2791  	{mask: 0xfc0ff07f, value: 0x48009057, op: VFCVT_X_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2792  	// VFDIV.VF vm, vs2, fs1, vd
  2793  	{mask: 0xfc00707f, value: 0x80005057, op: VFDIV_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2794  	// VFDIV.VV vm, vs2, vs1, vd
  2795  	{mask: 0xfc00707f, value: 0x80001057, op: VFDIV_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2796  	// VFIRST.M vm, vs2, rd
  2797  	{mask: 0xfc0ff07f, value: 0x4008a057, op: VFIRST_M, args: argTypeList{arg_vm, arg_vs2, arg_rd}},
  2798  	// VFMACC.VF vm, vs2, fs1, vd
  2799  	{mask: 0xfc00707f, value: 0xb0005057, op: VFMACC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2800  	// VFMACC.VV vm, vs2, vs1, vd
  2801  	{mask: 0xfc00707f, value: 0xb0001057, op: VFMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2802  	// VFMADD.VF vm, vs2, fs1, vd
  2803  	{mask: 0xfc00707f, value: 0xa0005057, op: VFMADD_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2804  	// VFMADD.VV vm, vs2, vs1, vd
  2805  	{mask: 0xfc00707f, value: 0xa0001057, op: VFMADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2806  	// VFMAX.VF vm, vs2, fs1, vd
  2807  	{mask: 0xfc00707f, value: 0x18005057, op: VFMAX_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2808  	// VFMAX.VV vm, vs2, vs1, vd
  2809  	{mask: 0xfc00707f, value: 0x18001057, op: VFMAX_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2810  	// VFMERGE.VFM vs2, fs1, vd
  2811  	{mask: 0xfe00707f, value: 0x5c005057, op: VFMERGE_VFM, args: argTypeList{arg_vs2, arg_fs1, arg_vd}},
  2812  	// VFMIN.VF vm, vs2, fs1, vd
  2813  	{mask: 0xfc00707f, value: 0x10005057, op: VFMIN_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2814  	// VFMIN.VV vm, vs2, vs1, vd
  2815  	{mask: 0xfc00707f, value: 0x10001057, op: VFMIN_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2816  	// VFMSAC.VF vm, vs2, fs1, vd
  2817  	{mask: 0xfc00707f, value: 0xb8005057, op: VFMSAC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2818  	// VFMSAC.VV vm, vs2, vs1, vd
  2819  	{mask: 0xfc00707f, value: 0xb8001057, op: VFMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2820  	// VFMSUB.VF vm, vs2, fs1, vd
  2821  	{mask: 0xfc00707f, value: 0xa8005057, op: VFMSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2822  	// VFMSUB.VV vm, vs2, vs1, vd
  2823  	{mask: 0xfc00707f, value: 0xa8001057, op: VFMSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2824  	// VFMUL.VF vm, vs2, fs1, vd
  2825  	{mask: 0xfc00707f, value: 0x90005057, op: VFMUL_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2826  	// VFMUL.VV vm, vs2, vs1, vd
  2827  	{mask: 0xfc00707f, value: 0x90001057, op: VFMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2828  	// VFMV.F.S vs2, fd
  2829  	{mask: 0xfe0ff07f, value: 0x42001057, op: VFMV_F_S, args: argTypeList{arg_vs2, arg_fd}},
  2830  	// VFMV.S.F fs1, vd
  2831  	{mask: 0xfff0707f, value: 0x42005057, op: VFMV_S_F, args: argTypeList{arg_fs1, arg_vd}},
  2832  	// VFMV.V.F fs1, vd
  2833  	{mask: 0xfff0707f, value: 0x5e005057, op: VFMV_V_F, args: argTypeList{arg_fs1, arg_vd}},
  2834  	// VFNCVT.F.F.W vm, vs2, vd
  2835  	{mask: 0xfc0ff07f, value: 0x480a1057, op: VFNCVT_F_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2836  	// VFNCVT.F.XU.W vm, vs2, vd
  2837  	{mask: 0xfc0ff07f, value: 0x48091057, op: VFNCVT_F_XU_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2838  	// VFNCVT.F.X.W vm, vs2, vd
  2839  	{mask: 0xfc0ff07f, value: 0x48099057, op: VFNCVT_F_X_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2840  	// VFNCVT.ROD.F.F.W vm, vs2, vd
  2841  	{mask: 0xfc0ff07f, value: 0x480a9057, op: VFNCVT_ROD_F_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2842  	// VFNCVT.RTZ.XU.F.W vm, vs2, vd
  2843  	{mask: 0xfc0ff07f, value: 0x480b1057, op: VFNCVT_RTZ_XU_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2844  	// VFNCVT.RTZ.X.F.W vm, vs2, vd
  2845  	{mask: 0xfc0ff07f, value: 0x480b9057, op: VFNCVT_RTZ_X_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2846  	// VFNCVT.XU.F.W vm, vs2, vd
  2847  	{mask: 0xfc0ff07f, value: 0x48081057, op: VFNCVT_XU_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2848  	// VFNCVT.X.F.W vm, vs2, vd
  2849  	{mask: 0xfc0ff07f, value: 0x48089057, op: VFNCVT_X_F_W, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2850  	// VFNMACC.VF vm, vs2, fs1, vd
  2851  	{mask: 0xfc00707f, value: 0xb4005057, op: VFNMACC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2852  	// VFNMACC.VV vm, vs2, vs1, vd
  2853  	{mask: 0xfc00707f, value: 0xb4001057, op: VFNMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2854  	// VFNMADD.VF vm, vs2, fs1, vd
  2855  	{mask: 0xfc00707f, value: 0xa4005057, op: VFNMADD_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2856  	// VFNMADD.VV vm, vs2, vs1, vd
  2857  	{mask: 0xfc00707f, value: 0xa4001057, op: VFNMADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2858  	// VFNMSAC.VF vm, vs2, fs1, vd
  2859  	{mask: 0xfc00707f, value: 0xbc005057, op: VFNMSAC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2860  	// VFNMSAC.VV vm, vs2, vs1, vd
  2861  	{mask: 0xfc00707f, value: 0xbc001057, op: VFNMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2862  	// VFNMSUB.VF vm, vs2, fs1, vd
  2863  	{mask: 0xfc00707f, value: 0xac005057, op: VFNMSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2864  	// VFNMSUB.VV vm, vs2, vs1, vd
  2865  	{mask: 0xfc00707f, value: 0xac001057, op: VFNMSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2866  	// VFRDIV.VF vm, vs2, fs1, vd
  2867  	{mask: 0xfc00707f, value: 0x84005057, op: VFRDIV_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2868  	// VFREC7.V vm, vs2, vd
  2869  	{mask: 0xfc0ff07f, value: 0x4c029057, op: VFREC7_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2870  	// VFREDMAX.VS vm, vs2, vs1, vd
  2871  	{mask: 0xfc00707f, value: 0x1c001057, op: VFREDMAX_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2872  	// VFREDMIN.VS vm, vs2, vs1, vd
  2873  	{mask: 0xfc00707f, value: 0x14001057, op: VFREDMIN_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2874  	// VFREDOSUM.VS vm, vs2, vs1, vd
  2875  	{mask: 0xfc00707f, value: 0x0c001057, op: VFREDOSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2876  	// VFREDUSUM.VS vm, vs2, vs1, vd
  2877  	{mask: 0xfc00707f, value: 0x04001057, op: VFREDUSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2878  	// VFRSQRT7.V vm, vs2, vd
  2879  	{mask: 0xfc0ff07f, value: 0x4c021057, op: VFRSQRT7_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2880  	// VFRSUB.VF vm, vs2, fs1, vd
  2881  	{mask: 0xfc00707f, value: 0x9c005057, op: VFRSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2882  	// VFSGNJN.VF vm, vs2, fs1, vd
  2883  	{mask: 0xfc00707f, value: 0x24005057, op: VFSGNJN_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2884  	// VFSGNJN.VV vm, vs2, vs1, vd
  2885  	{mask: 0xfc00707f, value: 0x24001057, op: VFSGNJN_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2886  	// VFSGNJX.VF vm, vs2, fs1, vd
  2887  	{mask: 0xfc00707f, value: 0x28005057, op: VFSGNJX_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2888  	// VFSGNJX.VV vm, vs2, vs1, vd
  2889  	{mask: 0xfc00707f, value: 0x28001057, op: VFSGNJX_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2890  	// VFSGNJ.VF vm, vs2, fs1, vd
  2891  	{mask: 0xfc00707f, value: 0x20005057, op: VFSGNJ_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2892  	// VFSGNJ.VV vm, vs2, vs1, vd
  2893  	{mask: 0xfc00707f, value: 0x20001057, op: VFSGNJ_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2894  	// VFSLIDE1DOWN.VF vm, vs2, fs1, vd
  2895  	{mask: 0xfc00707f, value: 0x3c005057, op: VFSLIDE1DOWN_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2896  	// VFSLIDE1UP.VF vm, vs2, fs1, vd
  2897  	{mask: 0xfc00707f, value: 0x38005057, op: VFSLIDE1UP_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2898  	// VFSQRT.V vm, vs2, vd
  2899  	{mask: 0xfc0ff07f, value: 0x4c001057, op: VFSQRT_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2900  	// VFSUB.VF vm, vs2, fs1, vd
  2901  	{mask: 0xfc00707f, value: 0x08005057, op: VFSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2902  	// VFSUB.VV vm, vs2, vs1, vd
  2903  	{mask: 0xfc00707f, value: 0x08001057, op: VFSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2904  	// VFWADD.VF vm, vs2, fs1, vd
  2905  	{mask: 0xfc00707f, value: 0xc0005057, op: VFWADD_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2906  	// VFWADD.VV vm, vs2, vs1, vd
  2907  	{mask: 0xfc00707f, value: 0xc0001057, op: VFWADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2908  	// VFWADD.WF vm, vs2, fs1, vd
  2909  	{mask: 0xfc00707f, value: 0xd0005057, op: VFWADD_WF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2910  	// VFWADD.WV vm, vs2, vs1, vd
  2911  	{mask: 0xfc00707f, value: 0xd0001057, op: VFWADD_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2912  	// VFWCVT.F.F.V vm, vs2, vd
  2913  	{mask: 0xfc0ff07f, value: 0x48061057, op: VFWCVT_F_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2914  	// VFWCVT.F.XU.V vm, vs2, vd
  2915  	{mask: 0xfc0ff07f, value: 0x48051057, op: VFWCVT_F_XU_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2916  	// VFWCVT.F.X.V vm, vs2, vd
  2917  	{mask: 0xfc0ff07f, value: 0x48059057, op: VFWCVT_F_X_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2918  	// VFWCVT.RTZ.XU.F.V vm, vs2, vd
  2919  	{mask: 0xfc0ff07f, value: 0x48071057, op: VFWCVT_RTZ_XU_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2920  	// VFWCVT.RTZ.X.F.V vm, vs2, vd
  2921  	{mask: 0xfc0ff07f, value: 0x48079057, op: VFWCVT_RTZ_X_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2922  	// VFWCVT.XU.F.V vm, vs2, vd
  2923  	{mask: 0xfc0ff07f, value: 0x48041057, op: VFWCVT_XU_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2924  	// VFWCVT.X.F.V vm, vs2, vd
  2925  	{mask: 0xfc0ff07f, value: 0x48049057, op: VFWCVT_X_F_V, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2926  	// VFWMACC.VF vm, vs2, fs1, vd
  2927  	{mask: 0xfc00707f, value: 0xf0005057, op: VFWMACC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2928  	// VFWMACC.VV vm, vs2, vs1, vd
  2929  	{mask: 0xfc00707f, value: 0xf0001057, op: VFWMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2930  	// VFWMSAC.VF vm, vs2, fs1, vd
  2931  	{mask: 0xfc00707f, value: 0xf8005057, op: VFWMSAC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2932  	// VFWMSAC.VV vm, vs2, vs1, vd
  2933  	{mask: 0xfc00707f, value: 0xf8001057, op: VFWMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2934  	// VFWMUL.VF vm, vs2, fs1, vd
  2935  	{mask: 0xfc00707f, value: 0xe0005057, op: VFWMUL_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2936  	// VFWMUL.VV vm, vs2, vs1, vd
  2937  	{mask: 0xfc00707f, value: 0xe0001057, op: VFWMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2938  	// VFWNMACC.VF vm, vs2, fs1, vd
  2939  	{mask: 0xfc00707f, value: 0xf4005057, op: VFWNMACC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2940  	// VFWNMACC.VV vm, vs2, vs1, vd
  2941  	{mask: 0xfc00707f, value: 0xf4001057, op: VFWNMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2942  	// VFWNMSAC.VF vm, vs2, fs1, vd
  2943  	{mask: 0xfc00707f, value: 0xfc005057, op: VFWNMSAC_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2944  	// VFWNMSAC.VV vm, vs2, vs1, vd
  2945  	{mask: 0xfc00707f, value: 0xfc001057, op: VFWNMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2946  	// VFWREDOSUM.VS vm, vs2, vs1, vd
  2947  	{mask: 0xfc00707f, value: 0xcc001057, op: VFWREDOSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2948  	// VFWREDUSUM.VS vm, vs2, vs1, vd
  2949  	{mask: 0xfc00707f, value: 0xc4001057, op: VFWREDUSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2950  	// VFWSUB.VF vm, vs2, fs1, vd
  2951  	{mask: 0xfc00707f, value: 0xc8005057, op: VFWSUB_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2952  	// VFWSUB.VV vm, vs2, vs1, vd
  2953  	{mask: 0xfc00707f, value: 0xc8001057, op: VFWSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2954  	// VFWSUB.WF vm, vs2, fs1, vd
  2955  	{mask: 0xfc00707f, value: 0xd8005057, op: VFWSUB_WF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  2956  	// VFWSUB.WV vm, vs2, vs1, vd
  2957  	{mask: 0xfc00707f, value: 0xd8001057, op: VFWSUB_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  2958  	// VID.V vm, vd
  2959  	{mask: 0xfdfff07f, value: 0x5008a057, op: VID_V, args: argTypeList{arg_vm, arg_vd}},
  2960  	// VIOTA.M vm, vs2, vd
  2961  	{mask: 0xfc0ff07f, value: 0x50082057, op: VIOTA_M, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  2962  	// VL1RE16.V rs1_ptr, vd
  2963  	{mask: 0xfff0707f, value: 0x02805007, op: VL1RE16_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2964  	// VL1RE32.V rs1_ptr, vd
  2965  	{mask: 0xfff0707f, value: 0x02806007, op: VL1RE32_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2966  	// VL1RE64.V rs1_ptr, vd
  2967  	{mask: 0xfff0707f, value: 0x02807007, op: VL1RE64_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2968  	// VL1RE8.V rs1_ptr, vd
  2969  	{mask: 0xfff0707f, value: 0x02800007, op: VL1RE8_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2970  	// VL2RE16.V rs1_ptr, vd
  2971  	{mask: 0xfff0707f, value: 0x22805007, op: VL2RE16_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2972  	// VL2RE32.V rs1_ptr, vd
  2973  	{mask: 0xfff0707f, value: 0x22806007, op: VL2RE32_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2974  	// VL2RE64.V rs1_ptr, vd
  2975  	{mask: 0xfff0707f, value: 0x22807007, op: VL2RE64_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2976  	// VL2RE8.V rs1_ptr, vd
  2977  	{mask: 0xfff0707f, value: 0x22800007, op: VL2RE8_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2978  	// VL4RE16.V rs1_ptr, vd
  2979  	{mask: 0xfff0707f, value: 0x62805007, op: VL4RE16_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2980  	// VL4RE32.V rs1_ptr, vd
  2981  	{mask: 0xfff0707f, value: 0x62806007, op: VL4RE32_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2982  	// VL4RE64.V rs1_ptr, vd
  2983  	{mask: 0xfff0707f, value: 0x62807007, op: VL4RE64_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2984  	// VL4RE8.V rs1_ptr, vd
  2985  	{mask: 0xfff0707f, value: 0x62800007, op: VL4RE8_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2986  	// VL8RE16.V rs1_ptr, vd
  2987  	{mask: 0xfff0707f, value: 0xe2805007, op: VL8RE16_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2988  	// VL8RE32.V rs1_ptr, vd
  2989  	{mask: 0xfff0707f, value: 0xe2806007, op: VL8RE32_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2990  	// VL8RE64.V rs1_ptr, vd
  2991  	{mask: 0xfff0707f, value: 0xe2807007, op: VL8RE64_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2992  	// VL8RE8.V rs1_ptr, vd
  2993  	{mask: 0xfff0707f, value: 0xe2800007, op: VL8RE8_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  2994  	// VLE16FF.V vm, rs1_ptr, vd
  2995  	{mask: 0xfdf0707f, value: 0x01005007, op: VLE16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  2996  	// VLE16.V vm, rs1_ptr, vd
  2997  	{mask: 0xfdf0707f, value: 0x00005007, op: VLE16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  2998  	// VLE32FF.V vm, rs1_ptr, vd
  2999  	{mask: 0xfdf0707f, value: 0x01006007, op: VLE32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3000  	// VLE32.V vm, rs1_ptr, vd
  3001  	{mask: 0xfdf0707f, value: 0x00006007, op: VLE32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3002  	// VLE64FF.V vm, rs1_ptr, vd
  3003  	{mask: 0xfdf0707f, value: 0x01007007, op: VLE64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3004  	// VLE64.V vm, rs1_ptr, vd
  3005  	{mask: 0xfdf0707f, value: 0x00007007, op: VLE64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3006  	// VLE8FF.V vm, rs1_ptr, vd
  3007  	{mask: 0xfdf0707f, value: 0x01000007, op: VLE8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3008  	// VLE8.V vm, rs1_ptr, vd
  3009  	{mask: 0xfdf0707f, value: 0x00000007, op: VLE8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3010  	// VLM.V rs1_ptr, vd
  3011  	{mask: 0xfff0707f, value: 0x02b00007, op: VLM_V, args: argTypeList{arg_rs1_ptr, arg_vd}},
  3012  	// VLOXEI16.V vm, vs2, rs1_ptr, vd
  3013  	{mask: 0xfc00707f, value: 0x0c005007, op: VLOXEI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3014  	// VLOXEI32.V vm, vs2, rs1_ptr, vd
  3015  	{mask: 0xfc00707f, value: 0x0c006007, op: VLOXEI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3016  	// VLOXEI64.V vm, vs2, rs1_ptr, vd
  3017  	{mask: 0xfc00707f, value: 0x0c007007, op: VLOXEI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3018  	// VLOXEI8.V vm, vs2, rs1_ptr, vd
  3019  	{mask: 0xfc00707f, value: 0x0c000007, op: VLOXEI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3020  	// VLOXSEG2EI16.V vm, vs2, rs1_ptr, vd
  3021  	{mask: 0xfc00707f, value: 0x2c005007, op: VLOXSEG2EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3022  	// VLOXSEG2EI32.V vm, vs2, rs1_ptr, vd
  3023  	{mask: 0xfc00707f, value: 0x2c006007, op: VLOXSEG2EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3024  	// VLOXSEG2EI64.V vm, vs2, rs1_ptr, vd
  3025  	{mask: 0xfc00707f, value: 0x2c007007, op: VLOXSEG2EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3026  	// VLOXSEG2EI8.V vm, vs2, rs1_ptr, vd
  3027  	{mask: 0xfc00707f, value: 0x2c000007, op: VLOXSEG2EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3028  	// VLOXSEG3EI16.V vm, vs2, rs1_ptr, vd
  3029  	{mask: 0xfc00707f, value: 0x4c005007, op: VLOXSEG3EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3030  	// VLOXSEG3EI32.V vm, vs2, rs1_ptr, vd
  3031  	{mask: 0xfc00707f, value: 0x4c006007, op: VLOXSEG3EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3032  	// VLOXSEG3EI64.V vm, vs2, rs1_ptr, vd
  3033  	{mask: 0xfc00707f, value: 0x4c007007, op: VLOXSEG3EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3034  	// VLOXSEG3EI8.V vm, vs2, rs1_ptr, vd
  3035  	{mask: 0xfc00707f, value: 0x4c000007, op: VLOXSEG3EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3036  	// VLOXSEG4EI16.V vm, vs2, rs1_ptr, vd
  3037  	{mask: 0xfc00707f, value: 0x6c005007, op: VLOXSEG4EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3038  	// VLOXSEG4EI32.V vm, vs2, rs1_ptr, vd
  3039  	{mask: 0xfc00707f, value: 0x6c006007, op: VLOXSEG4EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3040  	// VLOXSEG4EI64.V vm, vs2, rs1_ptr, vd
  3041  	{mask: 0xfc00707f, value: 0x6c007007, op: VLOXSEG4EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3042  	// VLOXSEG4EI8.V vm, vs2, rs1_ptr, vd
  3043  	{mask: 0xfc00707f, value: 0x6c000007, op: VLOXSEG4EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3044  	// VLOXSEG5EI16.V vm, vs2, rs1_ptr, vd
  3045  	{mask: 0xfc00707f, value: 0x8c005007, op: VLOXSEG5EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3046  	// VLOXSEG5EI32.V vm, vs2, rs1_ptr, vd
  3047  	{mask: 0xfc00707f, value: 0x8c006007, op: VLOXSEG5EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3048  	// VLOXSEG5EI64.V vm, vs2, rs1_ptr, vd
  3049  	{mask: 0xfc00707f, value: 0x8c007007, op: VLOXSEG5EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3050  	// VLOXSEG5EI8.V vm, vs2, rs1_ptr, vd
  3051  	{mask: 0xfc00707f, value: 0x8c000007, op: VLOXSEG5EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3052  	// VLOXSEG6EI16.V vm, vs2, rs1_ptr, vd
  3053  	{mask: 0xfc00707f, value: 0xac005007, op: VLOXSEG6EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3054  	// VLOXSEG6EI32.V vm, vs2, rs1_ptr, vd
  3055  	{mask: 0xfc00707f, value: 0xac006007, op: VLOXSEG6EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3056  	// VLOXSEG6EI64.V vm, vs2, rs1_ptr, vd
  3057  	{mask: 0xfc00707f, value: 0xac007007, op: VLOXSEG6EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3058  	// VLOXSEG6EI8.V vm, vs2, rs1_ptr, vd
  3059  	{mask: 0xfc00707f, value: 0xac000007, op: VLOXSEG6EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3060  	// VLOXSEG7EI16.V vm, vs2, rs1_ptr, vd
  3061  	{mask: 0xfc00707f, value: 0xcc005007, op: VLOXSEG7EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3062  	// VLOXSEG7EI32.V vm, vs2, rs1_ptr, vd
  3063  	{mask: 0xfc00707f, value: 0xcc006007, op: VLOXSEG7EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3064  	// VLOXSEG7EI64.V vm, vs2, rs1_ptr, vd
  3065  	{mask: 0xfc00707f, value: 0xcc007007, op: VLOXSEG7EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3066  	// VLOXSEG7EI8.V vm, vs2, rs1_ptr, vd
  3067  	{mask: 0xfc00707f, value: 0xcc000007, op: VLOXSEG7EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3068  	// VLOXSEG8EI16.V vm, vs2, rs1_ptr, vd
  3069  	{mask: 0xfc00707f, value: 0xec005007, op: VLOXSEG8EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3070  	// VLOXSEG8EI32.V vm, vs2, rs1_ptr, vd
  3071  	{mask: 0xfc00707f, value: 0xec006007, op: VLOXSEG8EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3072  	// VLOXSEG8EI64.V vm, vs2, rs1_ptr, vd
  3073  	{mask: 0xfc00707f, value: 0xec007007, op: VLOXSEG8EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3074  	// VLOXSEG8EI8.V vm, vs2, rs1_ptr, vd
  3075  	{mask: 0xfc00707f, value: 0xec000007, op: VLOXSEG8EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3076  	// VLSE16.V vm, rs2, rs1_ptr, vd
  3077  	{mask: 0xfc00707f, value: 0x08005007, op: VLSE16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3078  	// VLSE32.V vm, rs2, rs1_ptr, vd
  3079  	{mask: 0xfc00707f, value: 0x08006007, op: VLSE32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3080  	// VLSE64.V vm, rs2, rs1_ptr, vd
  3081  	{mask: 0xfc00707f, value: 0x08007007, op: VLSE64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3082  	// VLSE8.V vm, rs2, rs1_ptr, vd
  3083  	{mask: 0xfc00707f, value: 0x08000007, op: VLSE8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3084  	// VLSEG2E16FF.V vm, rs1_ptr, vd
  3085  	{mask: 0xfdf0707f, value: 0x21005007, op: VLSEG2E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3086  	// VLSEG2E16.V vm, rs1_ptr, vd
  3087  	{mask: 0xfdf0707f, value: 0x20005007, op: VLSEG2E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3088  	// VLSEG2E32FF.V vm, rs1_ptr, vd
  3089  	{mask: 0xfdf0707f, value: 0x21006007, op: VLSEG2E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3090  	// VLSEG2E32.V vm, rs1_ptr, vd
  3091  	{mask: 0xfdf0707f, value: 0x20006007, op: VLSEG2E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3092  	// VLSEG2E64FF.V vm, rs1_ptr, vd
  3093  	{mask: 0xfdf0707f, value: 0x21007007, op: VLSEG2E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3094  	// VLSEG2E64.V vm, rs1_ptr, vd
  3095  	{mask: 0xfdf0707f, value: 0x20007007, op: VLSEG2E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3096  	// VLSEG2E8FF.V vm, rs1_ptr, vd
  3097  	{mask: 0xfdf0707f, value: 0x21000007, op: VLSEG2E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3098  	// VLSEG2E8.V vm, rs1_ptr, vd
  3099  	{mask: 0xfdf0707f, value: 0x20000007, op: VLSEG2E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3100  	// VLSEG3E16FF.V vm, rs1_ptr, vd
  3101  	{mask: 0xfdf0707f, value: 0x41005007, op: VLSEG3E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3102  	// VLSEG3E16.V vm, rs1_ptr, vd
  3103  	{mask: 0xfdf0707f, value: 0x40005007, op: VLSEG3E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3104  	// VLSEG3E32FF.V vm, rs1_ptr, vd
  3105  	{mask: 0xfdf0707f, value: 0x41006007, op: VLSEG3E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3106  	// VLSEG3E32.V vm, rs1_ptr, vd
  3107  	{mask: 0xfdf0707f, value: 0x40006007, op: VLSEG3E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3108  	// VLSEG3E64FF.V vm, rs1_ptr, vd
  3109  	{mask: 0xfdf0707f, value: 0x41007007, op: VLSEG3E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3110  	// VLSEG3E64.V vm, rs1_ptr, vd
  3111  	{mask: 0xfdf0707f, value: 0x40007007, op: VLSEG3E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3112  	// VLSEG3E8FF.V vm, rs1_ptr, vd
  3113  	{mask: 0xfdf0707f, value: 0x41000007, op: VLSEG3E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3114  	// VLSEG3E8.V vm, rs1_ptr, vd
  3115  	{mask: 0xfdf0707f, value: 0x40000007, op: VLSEG3E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3116  	// VLSEG4E16FF.V vm, rs1_ptr, vd
  3117  	{mask: 0xfdf0707f, value: 0x61005007, op: VLSEG4E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3118  	// VLSEG4E16.V vm, rs1_ptr, vd
  3119  	{mask: 0xfdf0707f, value: 0x60005007, op: VLSEG4E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3120  	// VLSEG4E32FF.V vm, rs1_ptr, vd
  3121  	{mask: 0xfdf0707f, value: 0x61006007, op: VLSEG4E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3122  	// VLSEG4E32.V vm, rs1_ptr, vd
  3123  	{mask: 0xfdf0707f, value: 0x60006007, op: VLSEG4E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3124  	// VLSEG4E64FF.V vm, rs1_ptr, vd
  3125  	{mask: 0xfdf0707f, value: 0x61007007, op: VLSEG4E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3126  	// VLSEG4E64.V vm, rs1_ptr, vd
  3127  	{mask: 0xfdf0707f, value: 0x60007007, op: VLSEG4E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3128  	// VLSEG4E8FF.V vm, rs1_ptr, vd
  3129  	{mask: 0xfdf0707f, value: 0x61000007, op: VLSEG4E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3130  	// VLSEG4E8.V vm, rs1_ptr, vd
  3131  	{mask: 0xfdf0707f, value: 0x60000007, op: VLSEG4E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3132  	// VLSEG5E16FF.V vm, rs1_ptr, vd
  3133  	{mask: 0xfdf0707f, value: 0x81005007, op: VLSEG5E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3134  	// VLSEG5E16.V vm, rs1_ptr, vd
  3135  	{mask: 0xfdf0707f, value: 0x80005007, op: VLSEG5E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3136  	// VLSEG5E32FF.V vm, rs1_ptr, vd
  3137  	{mask: 0xfdf0707f, value: 0x81006007, op: VLSEG5E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3138  	// VLSEG5E32.V vm, rs1_ptr, vd
  3139  	{mask: 0xfdf0707f, value: 0x80006007, op: VLSEG5E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3140  	// VLSEG5E64FF.V vm, rs1_ptr, vd
  3141  	{mask: 0xfdf0707f, value: 0x81007007, op: VLSEG5E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3142  	// VLSEG5E64.V vm, rs1_ptr, vd
  3143  	{mask: 0xfdf0707f, value: 0x80007007, op: VLSEG5E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3144  	// VLSEG5E8FF.V vm, rs1_ptr, vd
  3145  	{mask: 0xfdf0707f, value: 0x81000007, op: VLSEG5E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3146  	// VLSEG5E8.V vm, rs1_ptr, vd
  3147  	{mask: 0xfdf0707f, value: 0x80000007, op: VLSEG5E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3148  	// VLSEG6E16FF.V vm, rs1_ptr, vd
  3149  	{mask: 0xfdf0707f, value: 0xa1005007, op: VLSEG6E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3150  	// VLSEG6E16.V vm, rs1_ptr, vd
  3151  	{mask: 0xfdf0707f, value: 0xa0005007, op: VLSEG6E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3152  	// VLSEG6E32FF.V vm, rs1_ptr, vd
  3153  	{mask: 0xfdf0707f, value: 0xa1006007, op: VLSEG6E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3154  	// VLSEG6E32.V vm, rs1_ptr, vd
  3155  	{mask: 0xfdf0707f, value: 0xa0006007, op: VLSEG6E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3156  	// VLSEG6E64FF.V vm, rs1_ptr, vd
  3157  	{mask: 0xfdf0707f, value: 0xa1007007, op: VLSEG6E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3158  	// VLSEG6E64.V vm, rs1_ptr, vd
  3159  	{mask: 0xfdf0707f, value: 0xa0007007, op: VLSEG6E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3160  	// VLSEG6E8FF.V vm, rs1_ptr, vd
  3161  	{mask: 0xfdf0707f, value: 0xa1000007, op: VLSEG6E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3162  	// VLSEG6E8.V vm, rs1_ptr, vd
  3163  	{mask: 0xfdf0707f, value: 0xa0000007, op: VLSEG6E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3164  	// VLSEG7E16FF.V vm, rs1_ptr, vd
  3165  	{mask: 0xfdf0707f, value: 0xc1005007, op: VLSEG7E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3166  	// VLSEG7E16.V vm, rs1_ptr, vd
  3167  	{mask: 0xfdf0707f, value: 0xc0005007, op: VLSEG7E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3168  	// VLSEG7E32FF.V vm, rs1_ptr, vd
  3169  	{mask: 0xfdf0707f, value: 0xc1006007, op: VLSEG7E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3170  	// VLSEG7E32.V vm, rs1_ptr, vd
  3171  	{mask: 0xfdf0707f, value: 0xc0006007, op: VLSEG7E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3172  	// VLSEG7E64FF.V vm, rs1_ptr, vd
  3173  	{mask: 0xfdf0707f, value: 0xc1007007, op: VLSEG7E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3174  	// VLSEG7E64.V vm, rs1_ptr, vd
  3175  	{mask: 0xfdf0707f, value: 0xc0007007, op: VLSEG7E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3176  	// VLSEG7E8FF.V vm, rs1_ptr, vd
  3177  	{mask: 0xfdf0707f, value: 0xc1000007, op: VLSEG7E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3178  	// VLSEG7E8.V vm, rs1_ptr, vd
  3179  	{mask: 0xfdf0707f, value: 0xc0000007, op: VLSEG7E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3180  	// VLSEG8E16FF.V vm, rs1_ptr, vd
  3181  	{mask: 0xfdf0707f, value: 0xe1005007, op: VLSEG8E16FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3182  	// VLSEG8E16.V vm, rs1_ptr, vd
  3183  	{mask: 0xfdf0707f, value: 0xe0005007, op: VLSEG8E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3184  	// VLSEG8E32FF.V vm, rs1_ptr, vd
  3185  	{mask: 0xfdf0707f, value: 0xe1006007, op: VLSEG8E32FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3186  	// VLSEG8E32.V vm, rs1_ptr, vd
  3187  	{mask: 0xfdf0707f, value: 0xe0006007, op: VLSEG8E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3188  	// VLSEG8E64FF.V vm, rs1_ptr, vd
  3189  	{mask: 0xfdf0707f, value: 0xe1007007, op: VLSEG8E64FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3190  	// VLSEG8E64.V vm, rs1_ptr, vd
  3191  	{mask: 0xfdf0707f, value: 0xe0007007, op: VLSEG8E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3192  	// VLSEG8E8FF.V vm, rs1_ptr, vd
  3193  	{mask: 0xfdf0707f, value: 0xe1000007, op: VLSEG8E8FF_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3194  	// VLSEG8E8.V vm, rs1_ptr, vd
  3195  	{mask: 0xfdf0707f, value: 0xe0000007, op: VLSEG8E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vd}},
  3196  	// VLSSEG2E16.V vm, rs2, rs1_ptr, vd
  3197  	{mask: 0xfc00707f, value: 0x28005007, op: VLSSEG2E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3198  	// VLSSEG2E32.V vm, rs2, rs1_ptr, vd
  3199  	{mask: 0xfc00707f, value: 0x28006007, op: VLSSEG2E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3200  	// VLSSEG2E64.V vm, rs2, rs1_ptr, vd
  3201  	{mask: 0xfc00707f, value: 0x28007007, op: VLSSEG2E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3202  	// VLSSEG2E8.V vm, rs2, rs1_ptr, vd
  3203  	{mask: 0xfc00707f, value: 0x28000007, op: VLSSEG2E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3204  	// VLSSEG3E16.V vm, rs2, rs1_ptr, vd
  3205  	{mask: 0xfc00707f, value: 0x48005007, op: VLSSEG3E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3206  	// VLSSEG3E32.V vm, rs2, rs1_ptr, vd
  3207  	{mask: 0xfc00707f, value: 0x48006007, op: VLSSEG3E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3208  	// VLSSEG3E64.V vm, rs2, rs1_ptr, vd
  3209  	{mask: 0xfc00707f, value: 0x48007007, op: VLSSEG3E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3210  	// VLSSEG3E8.V vm, rs2, rs1_ptr, vd
  3211  	{mask: 0xfc00707f, value: 0x48000007, op: VLSSEG3E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3212  	// VLSSEG4E16.V vm, rs2, rs1_ptr, vd
  3213  	{mask: 0xfc00707f, value: 0x68005007, op: VLSSEG4E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3214  	// VLSSEG4E32.V vm, rs2, rs1_ptr, vd
  3215  	{mask: 0xfc00707f, value: 0x68006007, op: VLSSEG4E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3216  	// VLSSEG4E64.V vm, rs2, rs1_ptr, vd
  3217  	{mask: 0xfc00707f, value: 0x68007007, op: VLSSEG4E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3218  	// VLSSEG4E8.V vm, rs2, rs1_ptr, vd
  3219  	{mask: 0xfc00707f, value: 0x68000007, op: VLSSEG4E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3220  	// VLSSEG5E16.V vm, rs2, rs1_ptr, vd
  3221  	{mask: 0xfc00707f, value: 0x88005007, op: VLSSEG5E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3222  	// VLSSEG5E32.V vm, rs2, rs1_ptr, vd
  3223  	{mask: 0xfc00707f, value: 0x88006007, op: VLSSEG5E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3224  	// VLSSEG5E64.V vm, rs2, rs1_ptr, vd
  3225  	{mask: 0xfc00707f, value: 0x88007007, op: VLSSEG5E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3226  	// VLSSEG5E8.V vm, rs2, rs1_ptr, vd
  3227  	{mask: 0xfc00707f, value: 0x88000007, op: VLSSEG5E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3228  	// VLSSEG6E16.V vm, rs2, rs1_ptr, vd
  3229  	{mask: 0xfc00707f, value: 0xa8005007, op: VLSSEG6E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3230  	// VLSSEG6E32.V vm, rs2, rs1_ptr, vd
  3231  	{mask: 0xfc00707f, value: 0xa8006007, op: VLSSEG6E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3232  	// VLSSEG6E64.V vm, rs2, rs1_ptr, vd
  3233  	{mask: 0xfc00707f, value: 0xa8007007, op: VLSSEG6E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3234  	// VLSSEG6E8.V vm, rs2, rs1_ptr, vd
  3235  	{mask: 0xfc00707f, value: 0xa8000007, op: VLSSEG6E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3236  	// VLSSEG7E16.V vm, rs2, rs1_ptr, vd
  3237  	{mask: 0xfc00707f, value: 0xc8005007, op: VLSSEG7E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3238  	// VLSSEG7E32.V vm, rs2, rs1_ptr, vd
  3239  	{mask: 0xfc00707f, value: 0xc8006007, op: VLSSEG7E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3240  	// VLSSEG7E64.V vm, rs2, rs1_ptr, vd
  3241  	{mask: 0xfc00707f, value: 0xc8007007, op: VLSSEG7E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3242  	// VLSSEG7E8.V vm, rs2, rs1_ptr, vd
  3243  	{mask: 0xfc00707f, value: 0xc8000007, op: VLSSEG7E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3244  	// VLSSEG8E16.V vm, rs2, rs1_ptr, vd
  3245  	{mask: 0xfc00707f, value: 0xe8005007, op: VLSSEG8E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3246  	// VLSSEG8E32.V vm, rs2, rs1_ptr, vd
  3247  	{mask: 0xfc00707f, value: 0xe8006007, op: VLSSEG8E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3248  	// VLSSEG8E64.V vm, rs2, rs1_ptr, vd
  3249  	{mask: 0xfc00707f, value: 0xe8007007, op: VLSSEG8E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3250  	// VLSSEG8E8.V vm, rs2, rs1_ptr, vd
  3251  	{mask: 0xfc00707f, value: 0xe8000007, op: VLSSEG8E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vd}},
  3252  	// VLUXEI16.V vm, vs2, rs1_ptr, vd
  3253  	{mask: 0xfc00707f, value: 0x04005007, op: VLUXEI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3254  	// VLUXEI32.V vm, vs2, rs1_ptr, vd
  3255  	{mask: 0xfc00707f, value: 0x04006007, op: VLUXEI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3256  	// VLUXEI64.V vm, vs2, rs1_ptr, vd
  3257  	{mask: 0xfc00707f, value: 0x04007007, op: VLUXEI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3258  	// VLUXEI8.V vm, vs2, rs1_ptr, vd
  3259  	{mask: 0xfc00707f, value: 0x04000007, op: VLUXEI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3260  	// VLUXSEG2EI16.V vm, vs2, rs1_ptr, vd
  3261  	{mask: 0xfc00707f, value: 0x24005007, op: VLUXSEG2EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3262  	// VLUXSEG2EI32.V vm, vs2, rs1_ptr, vd
  3263  	{mask: 0xfc00707f, value: 0x24006007, op: VLUXSEG2EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3264  	// VLUXSEG2EI64.V vm, vs2, rs1_ptr, vd
  3265  	{mask: 0xfc00707f, value: 0x24007007, op: VLUXSEG2EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3266  	// VLUXSEG2EI8.V vm, vs2, rs1_ptr, vd
  3267  	{mask: 0xfc00707f, value: 0x24000007, op: VLUXSEG2EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3268  	// VLUXSEG3EI16.V vm, vs2, rs1_ptr, vd
  3269  	{mask: 0xfc00707f, value: 0x44005007, op: VLUXSEG3EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3270  	// VLUXSEG3EI32.V vm, vs2, rs1_ptr, vd
  3271  	{mask: 0xfc00707f, value: 0x44006007, op: VLUXSEG3EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3272  	// VLUXSEG3EI64.V vm, vs2, rs1_ptr, vd
  3273  	{mask: 0xfc00707f, value: 0x44007007, op: VLUXSEG3EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3274  	// VLUXSEG3EI8.V vm, vs2, rs1_ptr, vd
  3275  	{mask: 0xfc00707f, value: 0x44000007, op: VLUXSEG3EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3276  	// VLUXSEG4EI16.V vm, vs2, rs1_ptr, vd
  3277  	{mask: 0xfc00707f, value: 0x64005007, op: VLUXSEG4EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3278  	// VLUXSEG4EI32.V vm, vs2, rs1_ptr, vd
  3279  	{mask: 0xfc00707f, value: 0x64006007, op: VLUXSEG4EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3280  	// VLUXSEG4EI64.V vm, vs2, rs1_ptr, vd
  3281  	{mask: 0xfc00707f, value: 0x64007007, op: VLUXSEG4EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3282  	// VLUXSEG4EI8.V vm, vs2, rs1_ptr, vd
  3283  	{mask: 0xfc00707f, value: 0x64000007, op: VLUXSEG4EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3284  	// VLUXSEG5EI16.V vm, vs2, rs1_ptr, vd
  3285  	{mask: 0xfc00707f, value: 0x84005007, op: VLUXSEG5EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3286  	// VLUXSEG5EI32.V vm, vs2, rs1_ptr, vd
  3287  	{mask: 0xfc00707f, value: 0x84006007, op: VLUXSEG5EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3288  	// VLUXSEG5EI64.V vm, vs2, rs1_ptr, vd
  3289  	{mask: 0xfc00707f, value: 0x84007007, op: VLUXSEG5EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3290  	// VLUXSEG5EI8.V vm, vs2, rs1_ptr, vd
  3291  	{mask: 0xfc00707f, value: 0x84000007, op: VLUXSEG5EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3292  	// VLUXSEG6EI16.V vm, vs2, rs1_ptr, vd
  3293  	{mask: 0xfc00707f, value: 0xa4005007, op: VLUXSEG6EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3294  	// VLUXSEG6EI32.V vm, vs2, rs1_ptr, vd
  3295  	{mask: 0xfc00707f, value: 0xa4006007, op: VLUXSEG6EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3296  	// VLUXSEG6EI64.V vm, vs2, rs1_ptr, vd
  3297  	{mask: 0xfc00707f, value: 0xa4007007, op: VLUXSEG6EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3298  	// VLUXSEG6EI8.V vm, vs2, rs1_ptr, vd
  3299  	{mask: 0xfc00707f, value: 0xa4000007, op: VLUXSEG6EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3300  	// VLUXSEG7EI16.V vm, vs2, rs1_ptr, vd
  3301  	{mask: 0xfc00707f, value: 0xc4005007, op: VLUXSEG7EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3302  	// VLUXSEG7EI32.V vm, vs2, rs1_ptr, vd
  3303  	{mask: 0xfc00707f, value: 0xc4006007, op: VLUXSEG7EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3304  	// VLUXSEG7EI64.V vm, vs2, rs1_ptr, vd
  3305  	{mask: 0xfc00707f, value: 0xc4007007, op: VLUXSEG7EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3306  	// VLUXSEG7EI8.V vm, vs2, rs1_ptr, vd
  3307  	{mask: 0xfc00707f, value: 0xc4000007, op: VLUXSEG7EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3308  	// VLUXSEG8EI16.V vm, vs2, rs1_ptr, vd
  3309  	{mask: 0xfc00707f, value: 0xe4005007, op: VLUXSEG8EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3310  	// VLUXSEG8EI32.V vm, vs2, rs1_ptr, vd
  3311  	{mask: 0xfc00707f, value: 0xe4006007, op: VLUXSEG8EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3312  	// VLUXSEG8EI64.V vm, vs2, rs1_ptr, vd
  3313  	{mask: 0xfc00707f, value: 0xe4007007, op: VLUXSEG8EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3314  	// VLUXSEG8EI8.V vm, vs2, rs1_ptr, vd
  3315  	{mask: 0xfc00707f, value: 0xe4000007, op: VLUXSEG8EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vd}},
  3316  	// VMACC.VV vm, vs2, vs1, vd
  3317  	{mask: 0xfc00707f, value: 0xb4002057, op: VMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3318  	// VMACC.VX vm, vs2, rs1, vd
  3319  	{mask: 0xfc00707f, value: 0xb4006057, op: VMACC_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3320  	// VMADC.VI vs2, simm5, vd
  3321  	{mask: 0xfe00707f, value: 0x46003057, op: VMADC_VI, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
  3322  	// VMADC.VIM vs2, simm5, vd
  3323  	{mask: 0xfe00707f, value: 0x44003057, op: VMADC_VIM, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
  3324  	// VMADC.VV vs2, vs1, vd
  3325  	{mask: 0xfe00707f, value: 0x46000057, op: VMADC_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3326  	// VMADC.VVM vs2, vs1, vd
  3327  	{mask: 0xfe00707f, value: 0x44000057, op: VMADC_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3328  	// VMADC.VX vs2, rs1, vd
  3329  	{mask: 0xfe00707f, value: 0x46004057, op: VMADC_VX, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3330  	// VMADC.VXM vs2, rs1, vd
  3331  	{mask: 0xfe00707f, value: 0x44004057, op: VMADC_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3332  	// VMADD.VV vm, vs2, vs1, vd
  3333  	{mask: 0xfc00707f, value: 0xa4002057, op: VMADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3334  	// VMADD.VX vm, vs2, rs1, vd
  3335  	{mask: 0xfc00707f, value: 0xa4006057, op: VMADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3336  	// VMANDN.MM vs2, vs1, vd
  3337  	{mask: 0xfe00707f, value: 0x62002057, op: VMANDN_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3338  	// VMAND.MM vs2, vs1, vd
  3339  	{mask: 0xfe00707f, value: 0x66002057, op: VMAND_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3340  	// VMAXU.VV vm, vs2, vs1, vd
  3341  	{mask: 0xfc00707f, value: 0x18000057, op: VMAXU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3342  	// VMAXU.VX vm, vs2, rs1, vd
  3343  	{mask: 0xfc00707f, value: 0x18004057, op: VMAXU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3344  	// VMAX.VV vm, vs2, vs1, vd
  3345  	{mask: 0xfc00707f, value: 0x1c000057, op: VMAX_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3346  	// VMAX.VX vm, vs2, rs1, vd
  3347  	{mask: 0xfc00707f, value: 0x1c004057, op: VMAX_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3348  	// VMERGE.VIM vs2, simm5, vd
  3349  	{mask: 0xfe00707f, value: 0x5c003057, op: VMERGE_VIM, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
  3350  	// VMERGE.VVM vs2, vs1, vd
  3351  	{mask: 0xfe00707f, value: 0x5c000057, op: VMERGE_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3352  	// VMERGE.VXM vs2, rs1, vd
  3353  	{mask: 0xfe00707f, value: 0x5c004057, op: VMERGE_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3354  	// VMFEQ.VF vm, vs2, fs1, vd
  3355  	{mask: 0xfc00707f, value: 0x60005057, op: VMFEQ_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3356  	// VMFEQ.VV vm, vs2, vs1, vd
  3357  	{mask: 0xfc00707f, value: 0x60001057, op: VMFEQ_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3358  	// VMFGE.VF vm, vs2, fs1, vd
  3359  	{mask: 0xfc00707f, value: 0x7c005057, op: VMFGE_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3360  	// VMFGT.VF vm, vs2, fs1, vd
  3361  	{mask: 0xfc00707f, value: 0x74005057, op: VMFGT_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3362  	// VMFLE.VF vm, vs2, fs1, vd
  3363  	{mask: 0xfc00707f, value: 0x64005057, op: VMFLE_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3364  	// VMFLE.VV vm, vs2, vs1, vd
  3365  	{mask: 0xfc00707f, value: 0x64001057, op: VMFLE_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3366  	// VMFLT.VF vm, vs2, fs1, vd
  3367  	{mask: 0xfc00707f, value: 0x6c005057, op: VMFLT_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3368  	// VMFLT.VV vm, vs2, vs1, vd
  3369  	{mask: 0xfc00707f, value: 0x6c001057, op: VMFLT_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3370  	// VMFNE.VF vm, vs2, fs1, vd
  3371  	{mask: 0xfc00707f, value: 0x70005057, op: VMFNE_VF, args: argTypeList{arg_vm, arg_vs2, arg_fs1, arg_vd}},
  3372  	// VMFNE.VV vm, vs2, vs1, vd
  3373  	{mask: 0xfc00707f, value: 0x70001057, op: VMFNE_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3374  	// VMINU.VV vm, vs2, vs1, vd
  3375  	{mask: 0xfc00707f, value: 0x10000057, op: VMINU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3376  	// VMINU.VX vm, vs2, rs1, vd
  3377  	{mask: 0xfc00707f, value: 0x10004057, op: VMINU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3378  	// VMIN.VV vm, vs2, vs1, vd
  3379  	{mask: 0xfc00707f, value: 0x14000057, op: VMIN_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3380  	// VMIN.VX vm, vs2, rs1, vd
  3381  	{mask: 0xfc00707f, value: 0x14004057, op: VMIN_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3382  	// VMNAND.MM vs2, vs1, vd
  3383  	{mask: 0xfe00707f, value: 0x76002057, op: VMNAND_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3384  	// VMNOR.MM vs2, vs1, vd
  3385  	{mask: 0xfe00707f, value: 0x7a002057, op: VMNOR_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3386  	// VMORN.MM vs2, vs1, vd
  3387  	{mask: 0xfe00707f, value: 0x72002057, op: VMORN_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3388  	// VMOR.MM vs2, vs1, vd
  3389  	{mask: 0xfe00707f, value: 0x6a002057, op: VMOR_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3390  	// VMSBC.VV vs2, vs1, vd
  3391  	{mask: 0xfe00707f, value: 0x4e000057, op: VMSBC_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3392  	// VMSBC.VVM vs2, vs1, vd
  3393  	{mask: 0xfe00707f, value: 0x4c000057, op: VMSBC_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3394  	// VMSBC.VX vs2, rs1, vd
  3395  	{mask: 0xfe00707f, value: 0x4e004057, op: VMSBC_VX, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3396  	// VMSBC.VXM vs2, rs1, vd
  3397  	{mask: 0xfe00707f, value: 0x4c004057, op: VMSBC_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3398  	// VMSBF.M vm, vs2, vd
  3399  	{mask: 0xfc0ff07f, value: 0x5000a057, op: VMSBF_M, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3400  	// VMSEQ.VI vm, vs2, simm5, vd
  3401  	{mask: 0xfc00707f, value: 0x60003057, op: VMSEQ_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3402  	// VMSEQ.VV vm, vs2, vs1, vd
  3403  	{mask: 0xfc00707f, value: 0x60000057, op: VMSEQ_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3404  	// VMSEQ.VX vm, vs2, rs1, vd
  3405  	{mask: 0xfc00707f, value: 0x60004057, op: VMSEQ_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3406  	// VMSGTU.VI vm, vs2, simm5, vd
  3407  	{mask: 0xfc00707f, value: 0x78003057, op: VMSGTU_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3408  	// VMSGTU.VX vm, vs2, rs1, vd
  3409  	{mask: 0xfc00707f, value: 0x78004057, op: VMSGTU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3410  	// VMSGT.VI vm, vs2, simm5, vd
  3411  	{mask: 0xfc00707f, value: 0x7c003057, op: VMSGT_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3412  	// VMSGT.VX vm, vs2, rs1, vd
  3413  	{mask: 0xfc00707f, value: 0x7c004057, op: VMSGT_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3414  	// VMSIF.M vm, vs2, vd
  3415  	{mask: 0xfc0ff07f, value: 0x5001a057, op: VMSIF_M, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3416  	// VMSLEU.VI vm, vs2, simm5, vd
  3417  	{mask: 0xfc00707f, value: 0x70003057, op: VMSLEU_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3418  	// VMSLEU.VV vm, vs2, vs1, vd
  3419  	{mask: 0xfc00707f, value: 0x70000057, op: VMSLEU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3420  	// VMSLEU.VX vm, vs2, rs1, vd
  3421  	{mask: 0xfc00707f, value: 0x70004057, op: VMSLEU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3422  	// VMSLE.VI vm, vs2, simm5, vd
  3423  	{mask: 0xfc00707f, value: 0x74003057, op: VMSLE_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3424  	// VMSLE.VV vm, vs2, vs1, vd
  3425  	{mask: 0xfc00707f, value: 0x74000057, op: VMSLE_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3426  	// VMSLE.VX vm, vs2, rs1, vd
  3427  	{mask: 0xfc00707f, value: 0x74004057, op: VMSLE_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3428  	// VMSLTU.VV vm, vs2, vs1, vd
  3429  	{mask: 0xfc00707f, value: 0x68000057, op: VMSLTU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3430  	// VMSLTU.VX vm, vs2, rs1, vd
  3431  	{mask: 0xfc00707f, value: 0x68004057, op: VMSLTU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3432  	// VMSLT.VV vm, vs2, vs1, vd
  3433  	{mask: 0xfc00707f, value: 0x6c000057, op: VMSLT_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3434  	// VMSLT.VX vm, vs2, rs1, vd
  3435  	{mask: 0xfc00707f, value: 0x6c004057, op: VMSLT_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3436  	// VMSNE.VI vm, vs2, simm5, vd
  3437  	{mask: 0xfc00707f, value: 0x64003057, op: VMSNE_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3438  	// VMSNE.VV vm, vs2, vs1, vd
  3439  	{mask: 0xfc00707f, value: 0x64000057, op: VMSNE_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3440  	// VMSNE.VX vm, vs2, rs1, vd
  3441  	{mask: 0xfc00707f, value: 0x64004057, op: VMSNE_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3442  	// VMSOF.M vm, vs2, vd
  3443  	{mask: 0xfc0ff07f, value: 0x50012057, op: VMSOF_M, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3444  	// VMULHSU.VV vm, vs2, vs1, vd
  3445  	{mask: 0xfc00707f, value: 0x98002057, op: VMULHSU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3446  	// VMULHSU.VX vm, vs2, rs1, vd
  3447  	{mask: 0xfc00707f, value: 0x98006057, op: VMULHSU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3448  	// VMULHU.VV vm, vs2, vs1, vd
  3449  	{mask: 0xfc00707f, value: 0x90002057, op: VMULHU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3450  	// VMULHU.VX vm, vs2, rs1, vd
  3451  	{mask: 0xfc00707f, value: 0x90006057, op: VMULHU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3452  	// VMULH.VV vm, vs2, vs1, vd
  3453  	{mask: 0xfc00707f, value: 0x9c002057, op: VMULH_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3454  	// VMULH.VX vm, vs2, rs1, vd
  3455  	{mask: 0xfc00707f, value: 0x9c006057, op: VMULH_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3456  	// VMUL.VV vm, vs2, vs1, vd
  3457  	{mask: 0xfc00707f, value: 0x94002057, op: VMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3458  	// VMUL.VX vm, vs2, rs1, vd
  3459  	{mask: 0xfc00707f, value: 0x94006057, op: VMUL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3460  	// VMV1R.V vs2, vd
  3461  	{mask: 0xfe0ff07f, value: 0x9e003057, op: VMV1R_V, args: argTypeList{arg_vs2, arg_vd}},
  3462  	// VMV2R.V vs2, vd
  3463  	{mask: 0xfe0ff07f, value: 0x9e00b057, op: VMV2R_V, args: argTypeList{arg_vs2, arg_vd}},
  3464  	// VMV4R.V vs2, vd
  3465  	{mask: 0xfe0ff07f, value: 0x9e01b057, op: VMV4R_V, args: argTypeList{arg_vs2, arg_vd}},
  3466  	// VMV8R.V vs2, vd
  3467  	{mask: 0xfe0ff07f, value: 0x9e03b057, op: VMV8R_V, args: argTypeList{arg_vs2, arg_vd}},
  3468  	// VMV.S.X rs1, vd
  3469  	{mask: 0xfff0707f, value: 0x42006057, op: VMV_S_X, args: argTypeList{arg_rs1, arg_vd}},
  3470  	// VMV.V.I simm5, vd
  3471  	{mask: 0xfff0707f, value: 0x5e003057, op: VMV_V_I, args: argTypeList{arg_simm5, arg_vd}},
  3472  	// VMV.V.V vs1, vd
  3473  	{mask: 0xfff0707f, value: 0x5e000057, op: VMV_V_V, args: argTypeList{arg_vs1, arg_vd}},
  3474  	// VMV.V.X rs1, vd
  3475  	{mask: 0xfff0707f, value: 0x5e004057, op: VMV_V_X, args: argTypeList{arg_rs1, arg_vd}},
  3476  	// VMV.X.S vs2, rd
  3477  	{mask: 0xfe0ff07f, value: 0x42002057, op: VMV_X_S, args: argTypeList{arg_vs2, arg_rd}},
  3478  	// VMXNOR.MM vs2, vs1, vd
  3479  	{mask: 0xfe00707f, value: 0x7e002057, op: VMXNOR_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3480  	// VMXOR.MM vs2, vs1, vd
  3481  	{mask: 0xfe00707f, value: 0x6e002057, op: VMXOR_MM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3482  	// VNCLIPU.WI vm, vs2, zimm5, vd
  3483  	{mask: 0xfc00707f, value: 0xb8003057, op: VNCLIPU_WI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3484  	// VNCLIPU.WV vm, vs2, vs1, vd
  3485  	{mask: 0xfc00707f, value: 0xb8000057, op: VNCLIPU_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3486  	// VNCLIPU.WX vm, vs2, rs1, vd
  3487  	{mask: 0xfc00707f, value: 0xb8004057, op: VNCLIPU_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3488  	// VNCLIP.WI vm, vs2, zimm5, vd
  3489  	{mask: 0xfc00707f, value: 0xbc003057, op: VNCLIP_WI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3490  	// VNCLIP.WV vm, vs2, vs1, vd
  3491  	{mask: 0xfc00707f, value: 0xbc000057, op: VNCLIP_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3492  	// VNCLIP.WX vm, vs2, rs1, vd
  3493  	{mask: 0xfc00707f, value: 0xbc004057, op: VNCLIP_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3494  	// VNMSAC.VV vm, vs2, vs1, vd
  3495  	{mask: 0xfc00707f, value: 0xbc002057, op: VNMSAC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3496  	// VNMSAC.VX vm, vs2, rs1, vd
  3497  	{mask: 0xfc00707f, value: 0xbc006057, op: VNMSAC_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3498  	// VNMSUB.VV vm, vs2, vs1, vd
  3499  	{mask: 0xfc00707f, value: 0xac002057, op: VNMSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3500  	// VNMSUB.VX vm, vs2, rs1, vd
  3501  	{mask: 0xfc00707f, value: 0xac006057, op: VNMSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3502  	// VNSRA.WI vm, vs2, zimm5, vd
  3503  	{mask: 0xfc00707f, value: 0xb4003057, op: VNSRA_WI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3504  	// VNSRA.WV vm, vs2, vs1, vd
  3505  	{mask: 0xfc00707f, value: 0xb4000057, op: VNSRA_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3506  	// VNSRA.WX vm, vs2, rs1, vd
  3507  	{mask: 0xfc00707f, value: 0xb4004057, op: VNSRA_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3508  	// VNSRL.WI vm, vs2, zimm5, vd
  3509  	{mask: 0xfc00707f, value: 0xb0003057, op: VNSRL_WI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3510  	// VNSRL.WV vm, vs2, vs1, vd
  3511  	{mask: 0xfc00707f, value: 0xb0000057, op: VNSRL_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3512  	// VNSRL.WX vm, vs2, rs1, vd
  3513  	{mask: 0xfc00707f, value: 0xb0004057, op: VNSRL_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3514  	// VOR.VI vm, vs2, simm5, vd
  3515  	{mask: 0xfc00707f, value: 0x28003057, op: VOR_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3516  	// VOR.VV vm, vs2, vs1, vd
  3517  	{mask: 0xfc00707f, value: 0x28000057, op: VOR_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3518  	// VOR.VX vm, vs2, rs1, vd
  3519  	{mask: 0xfc00707f, value: 0x28004057, op: VOR_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3520  	// VREDAND.VS vm, vs2, vs1, vd
  3521  	{mask: 0xfc00707f, value: 0x04002057, op: VREDAND_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3522  	// VREDMAXU.VS vm, vs2, vs1, vd
  3523  	{mask: 0xfc00707f, value: 0x18002057, op: VREDMAXU_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3524  	// VREDMAX.VS vm, vs2, vs1, vd
  3525  	{mask: 0xfc00707f, value: 0x1c002057, op: VREDMAX_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3526  	// VREDMINU.VS vm, vs2, vs1, vd
  3527  	{mask: 0xfc00707f, value: 0x10002057, op: VREDMINU_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3528  	// VREDMIN.VS vm, vs2, vs1, vd
  3529  	{mask: 0xfc00707f, value: 0x14002057, op: VREDMIN_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3530  	// VREDOR.VS vm, vs2, vs1, vd
  3531  	{mask: 0xfc00707f, value: 0x08002057, op: VREDOR_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3532  	// VREDSUM.VS vm, vs2, vs1, vd
  3533  	{mask: 0xfc00707f, value: 0x00002057, op: VREDSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3534  	// VREDXOR.VS vm, vs2, vs1, vd
  3535  	{mask: 0xfc00707f, value: 0x0c002057, op: VREDXOR_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3536  	// VREMU.VV vm, vs2, vs1, vd
  3537  	{mask: 0xfc00707f, value: 0x88002057, op: VREMU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3538  	// VREMU.VX vm, vs2, rs1, vd
  3539  	{mask: 0xfc00707f, value: 0x88006057, op: VREMU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3540  	// VREM.VV vm, vs2, vs1, vd
  3541  	{mask: 0xfc00707f, value: 0x8c002057, op: VREM_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3542  	// VREM.VX vm, vs2, rs1, vd
  3543  	{mask: 0xfc00707f, value: 0x8c006057, op: VREM_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3544  	// VRGATHEREI16.VV vm, vs2, vs1, vd
  3545  	{mask: 0xfc00707f, value: 0x38000057, op: VRGATHEREI16_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3546  	// VRGATHER.VI vm, vs2, zimm5, vd
  3547  	{mask: 0xfc00707f, value: 0x30003057, op: VRGATHER_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3548  	// VRGATHER.VV vm, vs2, vs1, vd
  3549  	{mask: 0xfc00707f, value: 0x30000057, op: VRGATHER_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3550  	// VRGATHER.VX vm, vs2, rs1, vd
  3551  	{mask: 0xfc00707f, value: 0x30004057, op: VRGATHER_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3552  	// VRSUB.VI vm, vs2, simm5, vd
  3553  	{mask: 0xfc00707f, value: 0x0c003057, op: VRSUB_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3554  	// VRSUB.VX vm, vs2, rs1, vd
  3555  	{mask: 0xfc00707f, value: 0x0c004057, op: VRSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3556  	// VS1R.V rs1_ptr, vs3
  3557  	{mask: 0xfff0707f, value: 0x02800027, op: VS1R_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3558  	// VS2R.V rs1_ptr, vs3
  3559  	{mask: 0xfff0707f, value: 0x22800027, op: VS2R_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3560  	// VS4R.V rs1_ptr, vs3
  3561  	{mask: 0xfff0707f, value: 0x62800027, op: VS4R_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3562  	// VS8R.V rs1_ptr, vs3
  3563  	{mask: 0xfff0707f, value: 0xe2800027, op: VS8R_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3564  	// VSADDU.VI vm, vs2, simm5, vd
  3565  	{mask: 0xfc00707f, value: 0x80003057, op: VSADDU_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3566  	// VSADDU.VV vm, vs2, vs1, vd
  3567  	{mask: 0xfc00707f, value: 0x80000057, op: VSADDU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3568  	// VSADDU.VX vm, vs2, rs1, vd
  3569  	{mask: 0xfc00707f, value: 0x80004057, op: VSADDU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3570  	// VSADD.VI vm, vs2, simm5, vd
  3571  	{mask: 0xfc00707f, value: 0x84003057, op: VSADD_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3572  	// VSADD.VV vm, vs2, vs1, vd
  3573  	{mask: 0xfc00707f, value: 0x84000057, op: VSADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3574  	// VSADD.VX vm, vs2, rs1, vd
  3575  	{mask: 0xfc00707f, value: 0x84004057, op: VSADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3576  	// VSBC.VVM vs2, vs1, vd
  3577  	{mask: 0xfe00707f, value: 0x48000057, op: VSBC_VVM, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
  3578  	// VSBC.VXM vs2, rs1, vd
  3579  	{mask: 0xfe00707f, value: 0x48004057, op: VSBC_VXM, args: argTypeList{arg_vs2, arg_rs1, arg_vd}},
  3580  	// VSE16.V vm, rs1_ptr, vs3
  3581  	{mask: 0xfdf0707f, value: 0x00005027, op: VSE16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3582  	// VSE32.V vm, rs1_ptr, vs3
  3583  	{mask: 0xfdf0707f, value: 0x00006027, op: VSE32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3584  	// VSE64.V vm, rs1_ptr, vs3
  3585  	{mask: 0xfdf0707f, value: 0x00007027, op: VSE64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3586  	// VSE8.V vm, rs1_ptr, vs3
  3587  	{mask: 0xfdf0707f, value: 0x00000027, op: VSE8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3588  	// VSETIVLI vtype_zimm10, zimm, rd
  3589  	{mask: 0xc000707f, value: 0xc0007057, op: VSETIVLI, args: argTypeList{arg_vtype_zimm10, arg_zimm, arg_rd}},
  3590  	// VSETVL rs2, rs1, rd
  3591  	{mask: 0xfe00707f, value: 0x80007057, op: VSETVL, args: argTypeList{arg_rs2, arg_rs1, arg_rd}},
  3592  	// VSETVLI vtype_zimm11, rs1, rd
  3593  	{mask: 0x8000707f, value: 0x00007057, op: VSETVLI, args: argTypeList{arg_vtype_zimm11, arg_rs1, arg_rd}},
  3594  	// VSEXT.VF2 vm, vs2, vd
  3595  	{mask: 0xfc0ff07f, value: 0x4803a057, op: VSEXT_VF2, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3596  	// VSEXT.VF4 vm, vs2, vd
  3597  	{mask: 0xfc0ff07f, value: 0x4802a057, op: VSEXT_VF4, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3598  	// VSEXT.VF8 vm, vs2, vd
  3599  	{mask: 0xfc0ff07f, value: 0x4801a057, op: VSEXT_VF8, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3600  	// VSLIDE1DOWN.VX vm, vs2, rs1, vd
  3601  	{mask: 0xfc00707f, value: 0x3c006057, op: VSLIDE1DOWN_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3602  	// VSLIDE1UP.VX vm, vs2, rs1, vd
  3603  	{mask: 0xfc00707f, value: 0x38006057, op: VSLIDE1UP_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3604  	// VSLIDEDOWN.VI vm, vs2, zimm5, vd
  3605  	{mask: 0xfc00707f, value: 0x3c003057, op: VSLIDEDOWN_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3606  	// VSLIDEDOWN.VX vm, vs2, rs1, vd
  3607  	{mask: 0xfc00707f, value: 0x3c004057, op: VSLIDEDOWN_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3608  	// VSLIDEUP.VI vm, vs2, zimm5, vd
  3609  	{mask: 0xfc00707f, value: 0x38003057, op: VSLIDEUP_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3610  	// VSLIDEUP.VX vm, vs2, rs1, vd
  3611  	{mask: 0xfc00707f, value: 0x38004057, op: VSLIDEUP_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3612  	// VSLL.VI vm, vs2, zimm5, vd
  3613  	{mask: 0xfc00707f, value: 0x94003057, op: VSLL_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3614  	// VSLL.VV vm, vs2, vs1, vd
  3615  	{mask: 0xfc00707f, value: 0x94000057, op: VSLL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3616  	// VSLL.VX vm, vs2, rs1, vd
  3617  	{mask: 0xfc00707f, value: 0x94004057, op: VSLL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3618  	// VSMUL.VV vm, vs2, vs1, vd
  3619  	{mask: 0xfc00707f, value: 0x9c000057, op: VSMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3620  	// VSMUL.VX vm, vs2, rs1, vd
  3621  	{mask: 0xfc00707f, value: 0x9c004057, op: VSMUL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3622  	// VSM.V rs1_ptr, vs3
  3623  	{mask: 0xfff0707f, value: 0x02b00027, op: VSM_V, args: argTypeList{arg_rs1_ptr, arg_vs3}},
  3624  	// VSOXEI16.V vm, vs2, rs1_ptr, vs3
  3625  	{mask: 0xfc00707f, value: 0x0c005027, op: VSOXEI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3626  	// VSOXEI32.V vm, vs2, rs1_ptr, vs3
  3627  	{mask: 0xfc00707f, value: 0x0c006027, op: VSOXEI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3628  	// VSOXEI64.V vm, vs2, rs1_ptr, vs3
  3629  	{mask: 0xfc00707f, value: 0x0c007027, op: VSOXEI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3630  	// VSOXEI8.V vm, vs2, rs1_ptr, vs3
  3631  	{mask: 0xfc00707f, value: 0x0c000027, op: VSOXEI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3632  	// VSOXSEG2EI16.V vm, vs2, rs1_ptr, vs3
  3633  	{mask: 0xfc00707f, value: 0x2c005027, op: VSOXSEG2EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3634  	// VSOXSEG2EI32.V vm, vs2, rs1_ptr, vs3
  3635  	{mask: 0xfc00707f, value: 0x2c006027, op: VSOXSEG2EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3636  	// VSOXSEG2EI64.V vm, vs2, rs1_ptr, vs3
  3637  	{mask: 0xfc00707f, value: 0x2c007027, op: VSOXSEG2EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3638  	// VSOXSEG2EI8.V vm, vs2, rs1_ptr, vs3
  3639  	{mask: 0xfc00707f, value: 0x2c000027, op: VSOXSEG2EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3640  	// VSOXSEG3EI16.V vm, vs2, rs1_ptr, vs3
  3641  	{mask: 0xfc00707f, value: 0x4c005027, op: VSOXSEG3EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3642  	// VSOXSEG3EI32.V vm, vs2, rs1_ptr, vs3
  3643  	{mask: 0xfc00707f, value: 0x4c006027, op: VSOXSEG3EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3644  	// VSOXSEG3EI64.V vm, vs2, rs1_ptr, vs3
  3645  	{mask: 0xfc00707f, value: 0x4c007027, op: VSOXSEG3EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3646  	// VSOXSEG3EI8.V vm, vs2, rs1_ptr, vs3
  3647  	{mask: 0xfc00707f, value: 0x4c000027, op: VSOXSEG3EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3648  	// VSOXSEG4EI16.V vm, vs2, rs1_ptr, vs3
  3649  	{mask: 0xfc00707f, value: 0x6c005027, op: VSOXSEG4EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3650  	// VSOXSEG4EI32.V vm, vs2, rs1_ptr, vs3
  3651  	{mask: 0xfc00707f, value: 0x6c006027, op: VSOXSEG4EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3652  	// VSOXSEG4EI64.V vm, vs2, rs1_ptr, vs3
  3653  	{mask: 0xfc00707f, value: 0x6c007027, op: VSOXSEG4EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3654  	// VSOXSEG4EI8.V vm, vs2, rs1_ptr, vs3
  3655  	{mask: 0xfc00707f, value: 0x6c000027, op: VSOXSEG4EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3656  	// VSOXSEG5EI16.V vm, vs2, rs1_ptr, vs3
  3657  	{mask: 0xfc00707f, value: 0x8c005027, op: VSOXSEG5EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3658  	// VSOXSEG5EI32.V vm, vs2, rs1_ptr, vs3
  3659  	{mask: 0xfc00707f, value: 0x8c006027, op: VSOXSEG5EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3660  	// VSOXSEG5EI64.V vm, vs2, rs1_ptr, vs3
  3661  	{mask: 0xfc00707f, value: 0x8c007027, op: VSOXSEG5EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3662  	// VSOXSEG5EI8.V vm, vs2, rs1_ptr, vs3
  3663  	{mask: 0xfc00707f, value: 0x8c000027, op: VSOXSEG5EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3664  	// VSOXSEG6EI16.V vm, vs2, rs1_ptr, vs3
  3665  	{mask: 0xfc00707f, value: 0xac005027, op: VSOXSEG6EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3666  	// VSOXSEG6EI32.V vm, vs2, rs1_ptr, vs3
  3667  	{mask: 0xfc00707f, value: 0xac006027, op: VSOXSEG6EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3668  	// VSOXSEG6EI64.V vm, vs2, rs1_ptr, vs3
  3669  	{mask: 0xfc00707f, value: 0xac007027, op: VSOXSEG6EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3670  	// VSOXSEG6EI8.V vm, vs2, rs1_ptr, vs3
  3671  	{mask: 0xfc00707f, value: 0xac000027, op: VSOXSEG6EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3672  	// VSOXSEG7EI16.V vm, vs2, rs1_ptr, vs3
  3673  	{mask: 0xfc00707f, value: 0xcc005027, op: VSOXSEG7EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3674  	// VSOXSEG7EI32.V vm, vs2, rs1_ptr, vs3
  3675  	{mask: 0xfc00707f, value: 0xcc006027, op: VSOXSEG7EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3676  	// VSOXSEG7EI64.V vm, vs2, rs1_ptr, vs3
  3677  	{mask: 0xfc00707f, value: 0xcc007027, op: VSOXSEG7EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3678  	// VSOXSEG7EI8.V vm, vs2, rs1_ptr, vs3
  3679  	{mask: 0xfc00707f, value: 0xcc000027, op: VSOXSEG7EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3680  	// VSOXSEG8EI16.V vm, vs2, rs1_ptr, vs3
  3681  	{mask: 0xfc00707f, value: 0xec005027, op: VSOXSEG8EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3682  	// VSOXSEG8EI32.V vm, vs2, rs1_ptr, vs3
  3683  	{mask: 0xfc00707f, value: 0xec006027, op: VSOXSEG8EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3684  	// VSOXSEG8EI64.V vm, vs2, rs1_ptr, vs3
  3685  	{mask: 0xfc00707f, value: 0xec007027, op: VSOXSEG8EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3686  	// VSOXSEG8EI8.V vm, vs2, rs1_ptr, vs3
  3687  	{mask: 0xfc00707f, value: 0xec000027, op: VSOXSEG8EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3688  	// VSRA.VI vm, vs2, zimm5, vd
  3689  	{mask: 0xfc00707f, value: 0xa4003057, op: VSRA_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3690  	// VSRA.VV vm, vs2, vs1, vd
  3691  	{mask: 0xfc00707f, value: 0xa4000057, op: VSRA_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3692  	// VSRA.VX vm, vs2, rs1, vd
  3693  	{mask: 0xfc00707f, value: 0xa4004057, op: VSRA_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3694  	// VSRL.VI vm, vs2, zimm5, vd
  3695  	{mask: 0xfc00707f, value: 0xa0003057, op: VSRL_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3696  	// VSRL.VV vm, vs2, vs1, vd
  3697  	{mask: 0xfc00707f, value: 0xa0000057, op: VSRL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3698  	// VSRL.VX vm, vs2, rs1, vd
  3699  	{mask: 0xfc00707f, value: 0xa0004057, op: VSRL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3700  	// VSSE16.V vm, rs2, rs1_ptr, vs3
  3701  	{mask: 0xfc00707f, value: 0x08005027, op: VSSE16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3702  	// VSSE32.V vm, rs2, rs1_ptr, vs3
  3703  	{mask: 0xfc00707f, value: 0x08006027, op: VSSE32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3704  	// VSSE64.V vm, rs2, rs1_ptr, vs3
  3705  	{mask: 0xfc00707f, value: 0x08007027, op: VSSE64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3706  	// VSSE8.V vm, rs2, rs1_ptr, vs3
  3707  	{mask: 0xfc00707f, value: 0x08000027, op: VSSE8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3708  	// VSSEG2E16.V vm, rs1_ptr, vs3
  3709  	{mask: 0xfdf0707f, value: 0x20005027, op: VSSEG2E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3710  	// VSSEG2E32.V vm, rs1_ptr, vs3
  3711  	{mask: 0xfdf0707f, value: 0x20006027, op: VSSEG2E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3712  	// VSSEG2E64.V vm, rs1_ptr, vs3
  3713  	{mask: 0xfdf0707f, value: 0x20007027, op: VSSEG2E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3714  	// VSSEG2E8.V vm, rs1_ptr, vs3
  3715  	{mask: 0xfdf0707f, value: 0x20000027, op: VSSEG2E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3716  	// VSSEG3E16.V vm, rs1_ptr, vs3
  3717  	{mask: 0xfdf0707f, value: 0x40005027, op: VSSEG3E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3718  	// VSSEG3E32.V vm, rs1_ptr, vs3
  3719  	{mask: 0xfdf0707f, value: 0x40006027, op: VSSEG3E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3720  	// VSSEG3E64.V vm, rs1_ptr, vs3
  3721  	{mask: 0xfdf0707f, value: 0x40007027, op: VSSEG3E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3722  	// VSSEG3E8.V vm, rs1_ptr, vs3
  3723  	{mask: 0xfdf0707f, value: 0x40000027, op: VSSEG3E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3724  	// VSSEG4E16.V vm, rs1_ptr, vs3
  3725  	{mask: 0xfdf0707f, value: 0x60005027, op: VSSEG4E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3726  	// VSSEG4E32.V vm, rs1_ptr, vs3
  3727  	{mask: 0xfdf0707f, value: 0x60006027, op: VSSEG4E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3728  	// VSSEG4E64.V vm, rs1_ptr, vs3
  3729  	{mask: 0xfdf0707f, value: 0x60007027, op: VSSEG4E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3730  	// VSSEG4E8.V vm, rs1_ptr, vs3
  3731  	{mask: 0xfdf0707f, value: 0x60000027, op: VSSEG4E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3732  	// VSSEG5E16.V vm, rs1_ptr, vs3
  3733  	{mask: 0xfdf0707f, value: 0x80005027, op: VSSEG5E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3734  	// VSSEG5E32.V vm, rs1_ptr, vs3
  3735  	{mask: 0xfdf0707f, value: 0x80006027, op: VSSEG5E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3736  	// VSSEG5E64.V vm, rs1_ptr, vs3
  3737  	{mask: 0xfdf0707f, value: 0x80007027, op: VSSEG5E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3738  	// VSSEG5E8.V vm, rs1_ptr, vs3
  3739  	{mask: 0xfdf0707f, value: 0x80000027, op: VSSEG5E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3740  	// VSSEG6E16.V vm, rs1_ptr, vs3
  3741  	{mask: 0xfdf0707f, value: 0xa0005027, op: VSSEG6E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3742  	// VSSEG6E32.V vm, rs1_ptr, vs3
  3743  	{mask: 0xfdf0707f, value: 0xa0006027, op: VSSEG6E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3744  	// VSSEG6E64.V vm, rs1_ptr, vs3
  3745  	{mask: 0xfdf0707f, value: 0xa0007027, op: VSSEG6E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3746  	// VSSEG6E8.V vm, rs1_ptr, vs3
  3747  	{mask: 0xfdf0707f, value: 0xa0000027, op: VSSEG6E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3748  	// VSSEG7E16.V vm, rs1_ptr, vs3
  3749  	{mask: 0xfdf0707f, value: 0xc0005027, op: VSSEG7E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3750  	// VSSEG7E32.V vm, rs1_ptr, vs3
  3751  	{mask: 0xfdf0707f, value: 0xc0006027, op: VSSEG7E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3752  	// VSSEG7E64.V vm, rs1_ptr, vs3
  3753  	{mask: 0xfdf0707f, value: 0xc0007027, op: VSSEG7E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3754  	// VSSEG7E8.V vm, rs1_ptr, vs3
  3755  	{mask: 0xfdf0707f, value: 0xc0000027, op: VSSEG7E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3756  	// VSSEG8E16.V vm, rs1_ptr, vs3
  3757  	{mask: 0xfdf0707f, value: 0xe0005027, op: VSSEG8E16_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3758  	// VSSEG8E32.V vm, rs1_ptr, vs3
  3759  	{mask: 0xfdf0707f, value: 0xe0006027, op: VSSEG8E32_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3760  	// VSSEG8E64.V vm, rs1_ptr, vs3
  3761  	{mask: 0xfdf0707f, value: 0xe0007027, op: VSSEG8E64_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3762  	// VSSEG8E8.V vm, rs1_ptr, vs3
  3763  	{mask: 0xfdf0707f, value: 0xe0000027, op: VSSEG8E8_V, args: argTypeList{arg_vm, arg_rs1_ptr, arg_vs3}},
  3764  	// VSSRA.VI vm, vs2, zimm5, vd
  3765  	{mask: 0xfc00707f, value: 0xac003057, op: VSSRA_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3766  	// VSSRA.VV vm, vs2, vs1, vd
  3767  	{mask: 0xfc00707f, value: 0xac000057, op: VSSRA_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3768  	// VSSRA.VX vm, vs2, rs1, vd
  3769  	{mask: 0xfc00707f, value: 0xac004057, op: VSSRA_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3770  	// VSSRL.VI vm, vs2, zimm5, vd
  3771  	{mask: 0xfc00707f, value: 0xa8003057, op: VSSRL_VI, args: argTypeList{arg_vm, arg_vs2, arg_zimm5, arg_vd}},
  3772  	// VSSRL.VV vm, vs2, vs1, vd
  3773  	{mask: 0xfc00707f, value: 0xa8000057, op: VSSRL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3774  	// VSSRL.VX vm, vs2, rs1, vd
  3775  	{mask: 0xfc00707f, value: 0xa8004057, op: VSSRL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3776  	// VSSSEG2E16.V vm, rs2, rs1_ptr, vs3
  3777  	{mask: 0xfc00707f, value: 0x28005027, op: VSSSEG2E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3778  	// VSSSEG2E32.V vm, rs2, rs1_ptr, vs3
  3779  	{mask: 0xfc00707f, value: 0x28006027, op: VSSSEG2E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3780  	// VSSSEG2E64.V vm, rs2, rs1_ptr, vs3
  3781  	{mask: 0xfc00707f, value: 0x28007027, op: VSSSEG2E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3782  	// VSSSEG2E8.V vm, rs2, rs1_ptr, vs3
  3783  	{mask: 0xfc00707f, value: 0x28000027, op: VSSSEG2E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3784  	// VSSSEG3E16.V vm, rs2, rs1_ptr, vs3
  3785  	{mask: 0xfc00707f, value: 0x48005027, op: VSSSEG3E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3786  	// VSSSEG3E32.V vm, rs2, rs1_ptr, vs3
  3787  	{mask: 0xfc00707f, value: 0x48006027, op: VSSSEG3E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3788  	// VSSSEG3E64.V vm, rs2, rs1_ptr, vs3
  3789  	{mask: 0xfc00707f, value: 0x48007027, op: VSSSEG3E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3790  	// VSSSEG3E8.V vm, rs2, rs1_ptr, vs3
  3791  	{mask: 0xfc00707f, value: 0x48000027, op: VSSSEG3E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3792  	// VSSSEG4E16.V vm, rs2, rs1_ptr, vs3
  3793  	{mask: 0xfc00707f, value: 0x68005027, op: VSSSEG4E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3794  	// VSSSEG4E32.V vm, rs2, rs1_ptr, vs3
  3795  	{mask: 0xfc00707f, value: 0x68006027, op: VSSSEG4E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3796  	// VSSSEG4E64.V vm, rs2, rs1_ptr, vs3
  3797  	{mask: 0xfc00707f, value: 0x68007027, op: VSSSEG4E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3798  	// VSSSEG4E8.V vm, rs2, rs1_ptr, vs3
  3799  	{mask: 0xfc00707f, value: 0x68000027, op: VSSSEG4E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3800  	// VSSSEG5E16.V vm, rs2, rs1_ptr, vs3
  3801  	{mask: 0xfc00707f, value: 0x88005027, op: VSSSEG5E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3802  	// VSSSEG5E32.V vm, rs2, rs1_ptr, vs3
  3803  	{mask: 0xfc00707f, value: 0x88006027, op: VSSSEG5E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3804  	// VSSSEG5E64.V vm, rs2, rs1_ptr, vs3
  3805  	{mask: 0xfc00707f, value: 0x88007027, op: VSSSEG5E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3806  	// VSSSEG5E8.V vm, rs2, rs1_ptr, vs3
  3807  	{mask: 0xfc00707f, value: 0x88000027, op: VSSSEG5E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3808  	// VSSSEG6E16.V vm, rs2, rs1_ptr, vs3
  3809  	{mask: 0xfc00707f, value: 0xa8005027, op: VSSSEG6E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3810  	// VSSSEG6E32.V vm, rs2, rs1_ptr, vs3
  3811  	{mask: 0xfc00707f, value: 0xa8006027, op: VSSSEG6E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3812  	// VSSSEG6E64.V vm, rs2, rs1_ptr, vs3
  3813  	{mask: 0xfc00707f, value: 0xa8007027, op: VSSSEG6E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3814  	// VSSSEG6E8.V vm, rs2, rs1_ptr, vs3
  3815  	{mask: 0xfc00707f, value: 0xa8000027, op: VSSSEG6E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3816  	// VSSSEG7E16.V vm, rs2, rs1_ptr, vs3
  3817  	{mask: 0xfc00707f, value: 0xc8005027, op: VSSSEG7E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3818  	// VSSSEG7E32.V vm, rs2, rs1_ptr, vs3
  3819  	{mask: 0xfc00707f, value: 0xc8006027, op: VSSSEG7E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3820  	// VSSSEG7E64.V vm, rs2, rs1_ptr, vs3
  3821  	{mask: 0xfc00707f, value: 0xc8007027, op: VSSSEG7E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3822  	// VSSSEG7E8.V vm, rs2, rs1_ptr, vs3
  3823  	{mask: 0xfc00707f, value: 0xc8000027, op: VSSSEG7E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3824  	// VSSSEG8E16.V vm, rs2, rs1_ptr, vs3
  3825  	{mask: 0xfc00707f, value: 0xe8005027, op: VSSSEG8E16_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3826  	// VSSSEG8E32.V vm, rs2, rs1_ptr, vs3
  3827  	{mask: 0xfc00707f, value: 0xe8006027, op: VSSSEG8E32_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3828  	// VSSSEG8E64.V vm, rs2, rs1_ptr, vs3
  3829  	{mask: 0xfc00707f, value: 0xe8007027, op: VSSSEG8E64_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3830  	// VSSSEG8E8.V vm, rs2, rs1_ptr, vs3
  3831  	{mask: 0xfc00707f, value: 0xe8000027, op: VSSSEG8E8_V, args: argTypeList{arg_vm, arg_rs2, arg_rs1_ptr, arg_vs3}},
  3832  	// VSSUBU.VV vm, vs2, vs1, vd
  3833  	{mask: 0xfc00707f, value: 0x88000057, op: VSSUBU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3834  	// VSSUBU.VX vm, vs2, rs1, vd
  3835  	{mask: 0xfc00707f, value: 0x88004057, op: VSSUBU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3836  	// VSSUB.VV vm, vs2, vs1, vd
  3837  	{mask: 0xfc00707f, value: 0x8c000057, op: VSSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3838  	// VSSUB.VX vm, vs2, rs1, vd
  3839  	{mask: 0xfc00707f, value: 0x8c004057, op: VSSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3840  	// VSUB.VV vm, vs2, vs1, vd
  3841  	{mask: 0xfc00707f, value: 0x08000057, op: VSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3842  	// VSUB.VX vm, vs2, rs1, vd
  3843  	{mask: 0xfc00707f, value: 0x08004057, op: VSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3844  	// VSUXEI16.V vm, vs2, rs1_ptr, vs3
  3845  	{mask: 0xfc00707f, value: 0x04005027, op: VSUXEI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3846  	// VSUXEI32.V vm, vs2, rs1_ptr, vs3
  3847  	{mask: 0xfc00707f, value: 0x04006027, op: VSUXEI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3848  	// VSUXEI64.V vm, vs2, rs1_ptr, vs3
  3849  	{mask: 0xfc00707f, value: 0x04007027, op: VSUXEI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3850  	// VSUXEI8.V vm, vs2, rs1_ptr, vs3
  3851  	{mask: 0xfc00707f, value: 0x04000027, op: VSUXEI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3852  	// VSUXSEG2EI16.V vm, vs2, rs1_ptr, vs3
  3853  	{mask: 0xfc00707f, value: 0x24005027, op: VSUXSEG2EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3854  	// VSUXSEG2EI32.V vm, vs2, rs1_ptr, vs3
  3855  	{mask: 0xfc00707f, value: 0x24006027, op: VSUXSEG2EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3856  	// VSUXSEG2EI64.V vm, vs2, rs1_ptr, vs3
  3857  	{mask: 0xfc00707f, value: 0x24007027, op: VSUXSEG2EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3858  	// VSUXSEG2EI8.V vm, vs2, rs1_ptr, vs3
  3859  	{mask: 0xfc00707f, value: 0x24000027, op: VSUXSEG2EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3860  	// VSUXSEG3EI16.V vm, vs2, rs1_ptr, vs3
  3861  	{mask: 0xfc00707f, value: 0x44005027, op: VSUXSEG3EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3862  	// VSUXSEG3EI32.V vm, vs2, rs1_ptr, vs3
  3863  	{mask: 0xfc00707f, value: 0x44006027, op: VSUXSEG3EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3864  	// VSUXSEG3EI64.V vm, vs2, rs1_ptr, vs3
  3865  	{mask: 0xfc00707f, value: 0x44007027, op: VSUXSEG3EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3866  	// VSUXSEG3EI8.V vm, vs2, rs1_ptr, vs3
  3867  	{mask: 0xfc00707f, value: 0x44000027, op: VSUXSEG3EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3868  	// VSUXSEG4EI16.V vm, vs2, rs1_ptr, vs3
  3869  	{mask: 0xfc00707f, value: 0x64005027, op: VSUXSEG4EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3870  	// VSUXSEG4EI32.V vm, vs2, rs1_ptr, vs3
  3871  	{mask: 0xfc00707f, value: 0x64006027, op: VSUXSEG4EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3872  	// VSUXSEG4EI64.V vm, vs2, rs1_ptr, vs3
  3873  	{mask: 0xfc00707f, value: 0x64007027, op: VSUXSEG4EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3874  	// VSUXSEG4EI8.V vm, vs2, rs1_ptr, vs3
  3875  	{mask: 0xfc00707f, value: 0x64000027, op: VSUXSEG4EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3876  	// VSUXSEG5EI16.V vm, vs2, rs1_ptr, vs3
  3877  	{mask: 0xfc00707f, value: 0x84005027, op: VSUXSEG5EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3878  	// VSUXSEG5EI32.V vm, vs2, rs1_ptr, vs3
  3879  	{mask: 0xfc00707f, value: 0x84006027, op: VSUXSEG5EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3880  	// VSUXSEG5EI64.V vm, vs2, rs1_ptr, vs3
  3881  	{mask: 0xfc00707f, value: 0x84007027, op: VSUXSEG5EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3882  	// VSUXSEG5EI8.V vm, vs2, rs1_ptr, vs3
  3883  	{mask: 0xfc00707f, value: 0x84000027, op: VSUXSEG5EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3884  	// VSUXSEG6EI16.V vm, vs2, rs1_ptr, vs3
  3885  	{mask: 0xfc00707f, value: 0xa4005027, op: VSUXSEG6EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3886  	// VSUXSEG6EI32.V vm, vs2, rs1_ptr, vs3
  3887  	{mask: 0xfc00707f, value: 0xa4006027, op: VSUXSEG6EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3888  	// VSUXSEG6EI64.V vm, vs2, rs1_ptr, vs3
  3889  	{mask: 0xfc00707f, value: 0xa4007027, op: VSUXSEG6EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3890  	// VSUXSEG6EI8.V vm, vs2, rs1_ptr, vs3
  3891  	{mask: 0xfc00707f, value: 0xa4000027, op: VSUXSEG6EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3892  	// VSUXSEG7EI16.V vm, vs2, rs1_ptr, vs3
  3893  	{mask: 0xfc00707f, value: 0xc4005027, op: VSUXSEG7EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3894  	// VSUXSEG7EI32.V vm, vs2, rs1_ptr, vs3
  3895  	{mask: 0xfc00707f, value: 0xc4006027, op: VSUXSEG7EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3896  	// VSUXSEG7EI64.V vm, vs2, rs1_ptr, vs3
  3897  	{mask: 0xfc00707f, value: 0xc4007027, op: VSUXSEG7EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3898  	// VSUXSEG7EI8.V vm, vs2, rs1_ptr, vs3
  3899  	{mask: 0xfc00707f, value: 0xc4000027, op: VSUXSEG7EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3900  	// VSUXSEG8EI16.V vm, vs2, rs1_ptr, vs3
  3901  	{mask: 0xfc00707f, value: 0xe4005027, op: VSUXSEG8EI16_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3902  	// VSUXSEG8EI32.V vm, vs2, rs1_ptr, vs3
  3903  	{mask: 0xfc00707f, value: 0xe4006027, op: VSUXSEG8EI32_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3904  	// VSUXSEG8EI64.V vm, vs2, rs1_ptr, vs3
  3905  	{mask: 0xfc00707f, value: 0xe4007027, op: VSUXSEG8EI64_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3906  	// VSUXSEG8EI8.V vm, vs2, rs1_ptr, vs3
  3907  	{mask: 0xfc00707f, value: 0xe4000027, op: VSUXSEG8EI8_V, args: argTypeList{arg_vm, arg_vs2, arg_rs1_ptr, arg_vs3}},
  3908  	// VWADDU.VV vm, vs2, vs1, vd
  3909  	{mask: 0xfc00707f, value: 0xc0002057, op: VWADDU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3910  	// VWADDU.VX vm, vs2, rs1, vd
  3911  	{mask: 0xfc00707f, value: 0xc0006057, op: VWADDU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3912  	// VWADDU.WV vm, vs2, vs1, vd
  3913  	{mask: 0xfc00707f, value: 0xd0002057, op: VWADDU_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3914  	// VWADDU.WX vm, vs2, rs1, vd
  3915  	{mask: 0xfc00707f, value: 0xd0006057, op: VWADDU_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3916  	// VWADD.VV vm, vs2, vs1, vd
  3917  	{mask: 0xfc00707f, value: 0xc4002057, op: VWADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3918  	// VWADD.VX vm, vs2, rs1, vd
  3919  	{mask: 0xfc00707f, value: 0xc4006057, op: VWADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3920  	// VWADD.WV vm, vs2, vs1, vd
  3921  	{mask: 0xfc00707f, value: 0xd4002057, op: VWADD_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3922  	// VWADD.WX vm, vs2, rs1, vd
  3923  	{mask: 0xfc00707f, value: 0xd4006057, op: VWADD_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3924  	// VWMACCSU.VV vm, vs2, vs1, vd
  3925  	{mask: 0xfc00707f, value: 0xfc002057, op: VWMACCSU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3926  	// VWMACCSU.VX vm, vs2, rs1, vd
  3927  	{mask: 0xfc00707f, value: 0xfc006057, op: VWMACCSU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3928  	// VWMACCUS.VX vm, vs2, rs1, vd
  3929  	{mask: 0xfc00707f, value: 0xf8006057, op: VWMACCUS_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3930  	// VWMACCU.VV vm, vs2, vs1, vd
  3931  	{mask: 0xfc00707f, value: 0xf0002057, op: VWMACCU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3932  	// VWMACCU.VX vm, vs2, rs1, vd
  3933  	{mask: 0xfc00707f, value: 0xf0006057, op: VWMACCU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3934  	// VWMACC.VV vm, vs2, vs1, vd
  3935  	{mask: 0xfc00707f, value: 0xf4002057, op: VWMACC_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3936  	// VWMACC.VX vm, vs2, rs1, vd
  3937  	{mask: 0xfc00707f, value: 0xf4006057, op: VWMACC_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3938  	// VWMULSU.VV vm, vs2, vs1, vd
  3939  	{mask: 0xfc00707f, value: 0xe8002057, op: VWMULSU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3940  	// VWMULSU.VX vm, vs2, rs1, vd
  3941  	{mask: 0xfc00707f, value: 0xe8006057, op: VWMULSU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3942  	// VWMULU.VV vm, vs2, vs1, vd
  3943  	{mask: 0xfc00707f, value: 0xe0002057, op: VWMULU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3944  	// VWMULU.VX vm, vs2, rs1, vd
  3945  	{mask: 0xfc00707f, value: 0xe0006057, op: VWMULU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3946  	// VWMUL.VV vm, vs2, vs1, vd
  3947  	{mask: 0xfc00707f, value: 0xec002057, op: VWMUL_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3948  	// VWMUL.VX vm, vs2, rs1, vd
  3949  	{mask: 0xfc00707f, value: 0xec006057, op: VWMUL_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3950  	// VWREDSUMU.VS vm, vs2, vs1, vd
  3951  	{mask: 0xfc00707f, value: 0xc0000057, op: VWREDSUMU_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3952  	// VWREDSUM.VS vm, vs2, vs1, vd
  3953  	{mask: 0xfc00707f, value: 0xc4000057, op: VWREDSUM_VS, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3954  	// VWSUBU.VV vm, vs2, vs1, vd
  3955  	{mask: 0xfc00707f, value: 0xc8002057, op: VWSUBU_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3956  	// VWSUBU.VX vm, vs2, rs1, vd
  3957  	{mask: 0xfc00707f, value: 0xc8006057, op: VWSUBU_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3958  	// VWSUBU.WV vm, vs2, vs1, vd
  3959  	{mask: 0xfc00707f, value: 0xd8002057, op: VWSUBU_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3960  	// VWSUBU.WX vm, vs2, rs1, vd
  3961  	{mask: 0xfc00707f, value: 0xd8006057, op: VWSUBU_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3962  	// VWSUB.VV vm, vs2, vs1, vd
  3963  	{mask: 0xfc00707f, value: 0xcc002057, op: VWSUB_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3964  	// VWSUB.VX vm, vs2, rs1, vd
  3965  	{mask: 0xfc00707f, value: 0xcc006057, op: VWSUB_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3966  	// VWSUB.WV vm, vs2, vs1, vd
  3967  	{mask: 0xfc00707f, value: 0xdc002057, op: VWSUB_WV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3968  	// VWSUB.WX vm, vs2, rs1, vd
  3969  	{mask: 0xfc00707f, value: 0xdc006057, op: VWSUB_WX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3970  	// VXOR.VI vm, vs2, simm5, vd
  3971  	{mask: 0xfc00707f, value: 0x2c003057, op: VXOR_VI, args: argTypeList{arg_vm, arg_vs2, arg_simm5, arg_vd}},
  3972  	// VXOR.VV vm, vs2, vs1, vd
  3973  	{mask: 0xfc00707f, value: 0x2c000057, op: VXOR_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
  3974  	// VXOR.VX vm, vs2, rs1, vd
  3975  	{mask: 0xfc00707f, value: 0x2c004057, op: VXOR_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
  3976  	// VZEXT.VF2 vm, vs2, vd
  3977  	{mask: 0xfc0ff07f, value: 0x48032057, op: VZEXT_VF2, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3978  	// VZEXT.VF4 vm, vs2, vd
  3979  	{mask: 0xfc0ff07f, value: 0x48022057, op: VZEXT_VF4, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3980  	// VZEXT.VF8 vm, vs2, vd
  3981  	{mask: 0xfc0ff07f, value: 0x48012057, op: VZEXT_VF8, args: argTypeList{arg_vm, arg_vs2, arg_vd}},
  3982  	// XNOR rd, rs1, rs2
  3983  	{mask: 0xfe00707f, value: 0x40004033, op: XNOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  3984  	// XOR rd, rs1, rs2
  3985  	{mask: 0xfe00707f, value: 0x00004033, op: XOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
  3986  	// XORI rd, rs1, imm12
  3987  	{mask: 0x0000707f, value: 0x00004013, op: XORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}},
  3988  	// ZEXT.H rd, rs1
  3989  	{mask: 0xfff0707f, value: 0x0800403b, op: ZEXT_H, args: argTypeList{arg_rd, arg_rs1}},
  3990  }
  3991  

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