cpu_loong64.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  //go:build loong64
     6  
     7  package cpu
     8  
     9  // CacheLinePadSize is used to prevent false sharing of cache lines.
    10  // We choose 64 because Loongson 3A5000 the L1 Dcache is 4-way 256-line 64-byte-per-line.
    11  const CacheLinePadSize = 64
    12  
    13  // Bit fields for CPUCFG registers, Related reference documents:
    14  // https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_cpucfg
    15  const (
    16  	// CPUCFG1 bits
    17  	cpucfg1_CRC32 = 1 << 25
    18  
    19  	// CPUCFG2 bits
    20  	cpucfg2_LAM_BH = 1 << 27
    21  	cpucfg2_LAMCAS = 1 << 28
    22  )
    23  
    24  // get_cpucfg is implemented in cpu_loong64.s.
    25  func get_cpucfg(reg uint32) uint32
    26  
    27  func doinit() {
    28  	options = []option{
    29  		{Name: "lsx", Feature: &Loong64.HasLSX},
    30  		{Name: "crc32", Feature: &Loong64.HasCRC32},
    31  		{Name: "lamcas", Feature: &Loong64.HasLAMCAS},
    32  		{Name: "lam_bh", Feature: &Loong64.HasLAM_BH},
    33  	}
    34  
    35  	// The CPUCFG data on Loong64 only reflects the hardware capabilities,
    36  	// not the kernel support status, so features such as LSX and LASX that
    37  	// require kernel support cannot be obtained from the CPUCFG data.
    38  	//
    39  	// These features only require hardware capability support and do not
    40  	// require kernel specific support, so they can be obtained directly
    41  	// through CPUCFG
    42  	cfg1 := get_cpucfg(1)
    43  	cfg2 := get_cpucfg(2)
    44  
    45  	Loong64.HasCRC32 = cfgIsSet(cfg1, cpucfg1_CRC32)
    46  	Loong64.HasLAMCAS = cfgIsSet(cfg2, cpucfg2_LAM_BH)
    47  	Loong64.HasLAM_BH = cfgIsSet(cfg2, cpucfg2_LAMCAS)
    48  
    49  	osInit()
    50  }
    51  
    52  func cfgIsSet(cfg uint32, val uint32) bool {
    53  	return cfg&val != 0
    54  }
    55
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