Source file src/runtime/mkpreempt.go

     1  // Copyright 2019 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  //go:build ignore
     6  
     7  // mkpreempt generates the asyncPreempt functions for each
     8  // architecture.
     9  package main
    10  
    11  import (
    12  	"flag"
    13  	"fmt"
    14  	"io"
    15  	"log"
    16  	"os"
    17  	"strings"
    18  )
    19  
    20  // Copied from cmd/compile/internal/ssa/gen/*Ops.go
    21  
    22  var regNames386 = []string{
    23  	"AX",
    24  	"CX",
    25  	"DX",
    26  	"BX",
    27  	"SP",
    28  	"BP",
    29  	"SI",
    30  	"DI",
    31  	"X0",
    32  	"X1",
    33  	"X2",
    34  	"X3",
    35  	"X4",
    36  	"X5",
    37  	"X6",
    38  	"X7",
    39  }
    40  
    41  var regNamesAMD64 = []string{
    42  	"AX",
    43  	"CX",
    44  	"DX",
    45  	"BX",
    46  	"SP",
    47  	"BP",
    48  	"SI",
    49  	"DI",
    50  	"R8",
    51  	"R9",
    52  	"R10",
    53  	"R11",
    54  	"R12",
    55  	"R13",
    56  	"R14",
    57  	"R15",
    58  	"X0",
    59  	"X1",
    60  	"X2",
    61  	"X3",
    62  	"X4",
    63  	"X5",
    64  	"X6",
    65  	"X7",
    66  	"X8",
    67  	"X9",
    68  	"X10",
    69  	"X11",
    70  	"X12",
    71  	"X13",
    72  	"X14",
    73  	"X15",
    74  }
    75  
    76  var out io.Writer
    77  
    78  var arches = map[string]func(){
    79  	"386":     gen386,
    80  	"amd64":   genAMD64,
    81  	"arm":     genARM,
    82  	"arm64":   genARM64,
    83  	"loong64": genLoong64,
    84  	"mips64x": func() { genMIPS(true) },
    85  	"mipsx":   func() { genMIPS(false) },
    86  	"ppc64x":  genPPC64,
    87  	"riscv64": genRISCV64,
    88  	"s390x":   genS390X,
    89  	"wasm":    genWasm,
    90  }
    91  var beLe = map[string]bool{"mips64x": true, "mipsx": true, "ppc64x": true}
    92  
    93  func main() {
    94  	flag.Parse()
    95  	if flag.NArg() > 0 {
    96  		out = os.Stdout
    97  		for _, arch := range flag.Args() {
    98  			gen, ok := arches[arch]
    99  			if !ok {
   100  				log.Fatalf("unknown arch %s", arch)
   101  			}
   102  			header(arch)
   103  			gen()
   104  		}
   105  		return
   106  	}
   107  
   108  	for arch, gen := range arches {
   109  		f, err := os.Create(fmt.Sprintf("preempt_%s.s", arch))
   110  		if err != nil {
   111  			log.Fatal(err)
   112  		}
   113  		out = f
   114  		header(arch)
   115  		gen()
   116  		if err := f.Close(); err != nil {
   117  			log.Fatal(err)
   118  		}
   119  	}
   120  }
   121  
   122  func header(arch string) {
   123  	fmt.Fprintf(out, "// Code generated by mkpreempt.go; DO NOT EDIT.\n\n")
   124  	if beLe[arch] {
   125  		base := arch[:len(arch)-1]
   126  		fmt.Fprintf(out, "//go:build %s || %sle\n\n", base, base)
   127  	}
   128  	fmt.Fprintf(out, "#include \"go_asm.h\"\n")
   129  	if arch == "amd64" {
   130  		fmt.Fprintf(out, "#include \"asm_amd64.h\"\n")
   131  	}
   132  	fmt.Fprintf(out, "#include \"textflag.h\"\n\n")
   133  	fmt.Fprintf(out, "TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0\n")
   134  }
   135  
   136  func p(f string, args ...any) {
   137  	fmted := fmt.Sprintf(f, args...)
   138  	fmt.Fprintf(out, "\t%s\n", strings.ReplaceAll(fmted, "\n", "\n\t"))
   139  }
   140  
   141  func label(l string) {
   142  	fmt.Fprintf(out, "%s\n", l)
   143  }
   144  
   145  type layout struct {
   146  	stack int
   147  	regs  []regPos
   148  	sp    string // stack pointer register
   149  }
   150  
   151  type regPos struct {
   152  	pos int
   153  
   154  	saveOp    string
   155  	restoreOp string
   156  	reg       string
   157  
   158  	// If this register requires special save and restore, these
   159  	// give those operations with a %d placeholder for the stack
   160  	// offset.
   161  	save, restore string
   162  }
   163  
   164  func (l *layout) add(op, reg string, size int) {
   165  	l.regs = append(l.regs, regPos{saveOp: op, restoreOp: op, reg: reg, pos: l.stack})
   166  	l.stack += size
   167  }
   168  
   169  func (l *layout) add2(sop, rop, reg string, size int) {
   170  	l.regs = append(l.regs, regPos{saveOp: sop, restoreOp: rop, reg: reg, pos: l.stack})
   171  	l.stack += size
   172  }
   173  
   174  func (l *layout) addSpecial(save, restore string, size int) {
   175  	l.regs = append(l.regs, regPos{save: save, restore: restore, pos: l.stack})
   176  	l.stack += size
   177  }
   178  
   179  func (l *layout) save() {
   180  	for _, reg := range l.regs {
   181  		if reg.save != "" {
   182  			p(reg.save, reg.pos)
   183  		} else {
   184  			p("%s %s, %d(%s)", reg.saveOp, reg.reg, reg.pos, l.sp)
   185  		}
   186  	}
   187  }
   188  
   189  func (l *layout) restore() {
   190  	for i := len(l.regs) - 1; i >= 0; i-- {
   191  		reg := l.regs[i]
   192  		if reg.restore != "" {
   193  			p(reg.restore, reg.pos)
   194  		} else {
   195  			p("%s %d(%s), %s", reg.restoreOp, reg.pos, l.sp, reg.reg)
   196  		}
   197  	}
   198  }
   199  
   200  func gen386() {
   201  	p("PUSHFL")
   202  	// Save general purpose registers.
   203  	var l = layout{sp: "SP"}
   204  	for _, reg := range regNames386 {
   205  		if reg == "SP" || strings.HasPrefix(reg, "X") {
   206  			continue
   207  		}
   208  		l.add("MOVL", reg, 4)
   209  	}
   210  
   211  	softfloat := "GO386_softfloat"
   212  
   213  	// Save SSE state only if supported.
   214  	lSSE := layout{stack: l.stack, sp: "SP"}
   215  	for i := 0; i < 8; i++ {
   216  		lSSE.add("MOVUPS", fmt.Sprintf("X%d", i), 16)
   217  	}
   218  
   219  	p("ADJSP $%d", lSSE.stack)
   220  	p("NOP SP")
   221  	l.save()
   222  	p("#ifndef %s", softfloat)
   223  	lSSE.save()
   224  	p("#endif")
   225  	p("CALL ·asyncPreempt2(SB)")
   226  	p("#ifndef %s", softfloat)
   227  	lSSE.restore()
   228  	p("#endif")
   229  	l.restore()
   230  	p("ADJSP $%d", -lSSE.stack)
   231  
   232  	p("POPFL")
   233  	p("RET")
   234  }
   235  
   236  func genAMD64() {
   237  	// Assign stack offsets.
   238  	var l = layout{sp: "SP"}
   239  	for _, reg := range regNamesAMD64 {
   240  		if reg == "SP" || reg == "BP" {
   241  			continue
   242  		}
   243  		if !strings.HasPrefix(reg, "X") {
   244  			l.add("MOVQ", reg, 8)
   245  		}
   246  	}
   247  	lSSE := layout{stack: l.stack, sp: "SP"}
   248  	for _, reg := range regNamesAMD64 {
   249  		if strings.HasPrefix(reg, "X") {
   250  			lSSE.add("MOVUPS", reg, 16)
   251  		}
   252  	}
   253  
   254  	// TODO: MXCSR register?
   255  
   256  	p("PUSHQ BP")
   257  	p("MOVQ SP, BP")
   258  	p("// Save flags before clobbering them")
   259  	p("PUSHFQ")
   260  	p("// obj doesn't understand ADD/SUB on SP, but does understand ADJSP")
   261  	p("ADJSP $%d", lSSE.stack)
   262  	p("// But vet doesn't know ADJSP, so suppress vet stack checking")
   263  	p("NOP SP")
   264  
   265  	l.save()
   266  
   267  	lSSE.save()
   268  	p("CALL ·asyncPreempt2(SB)")
   269  	lSSE.restore()
   270  	l.restore()
   271  	p("ADJSP $%d", -lSSE.stack)
   272  	p("POPFQ")
   273  	p("POPQ BP")
   274  	p("RET")
   275  }
   276  
   277  func genARM() {
   278  	// Add integer registers R0-R12.
   279  	// R13 (SP), R14 (LR), R15 (PC) are special and not saved here.
   280  	var l = layout{sp: "R13", stack: 4} // add LR slot
   281  	for i := 0; i <= 12; i++ {
   282  		reg := fmt.Sprintf("R%d", i)
   283  		if i == 10 {
   284  			continue // R10 is g register, no need to save/restore
   285  		}
   286  		l.add("MOVW", reg, 4)
   287  	}
   288  	// Add flag register.
   289  	l.addSpecial(
   290  		"MOVW CPSR, R0\nMOVW R0, %d(R13)",
   291  		"MOVW %d(R13), R0\nMOVW R0, CPSR",
   292  		4)
   293  
   294  	// Add floating point registers F0-F15 and flag register.
   295  	var lfp = layout{stack: l.stack, sp: "R13"}
   296  	lfp.addSpecial(
   297  		"MOVW FPCR, R0\nMOVW R0, %d(R13)",
   298  		"MOVW %d(R13), R0\nMOVW R0, FPCR",
   299  		4)
   300  	for i := 0; i <= 15; i++ {
   301  		reg := fmt.Sprintf("F%d", i)
   302  		lfp.add("MOVD", reg, 8)
   303  	}
   304  
   305  	p("MOVW.W R14, -%d(R13)", lfp.stack) // allocate frame, save LR
   306  	l.save()
   307  	p("MOVB ·goarmsoftfp(SB), R0\nCMP $0, R0\nBNE nofp") // test goarmsoftfp, and skip FP registers if goarmsoftfp!=0.
   308  	lfp.save()
   309  	label("nofp:")
   310  	p("CALL ·asyncPreempt2(SB)")
   311  	p("MOVB ·goarmsoftfp(SB), R0\nCMP $0, R0\nBNE nofp2") // test goarmsoftfp, and skip FP registers if goarmsoftfp!=0.
   312  	lfp.restore()
   313  	label("nofp2:")
   314  	l.restore()
   315  
   316  	p("MOVW %d(R13), R14", lfp.stack)     // sigctxt.pushCall pushes LR on stack, restore it
   317  	p("MOVW.P %d(R13), R15", lfp.stack+4) // load PC, pop frame (including the space pushed by sigctxt.pushCall)
   318  	p("UNDEF")                            // shouldn't get here
   319  }
   320  
   321  func genARM64() {
   322  	// Add integer registers R0-R26
   323  	// R27 (REGTMP), R28 (g), R29 (FP), R30 (LR), R31 (SP) are special
   324  	// and not saved here.
   325  	var l = layout{sp: "RSP", stack: 8} // add slot to save PC of interrupted instruction
   326  	for i := 0; i < 26; i += 2 {
   327  		if i == 18 {
   328  			i--
   329  			continue // R18 is not used, skip
   330  		}
   331  		reg := fmt.Sprintf("(R%d, R%d)", i, i+1)
   332  		l.add2("STP", "LDP", reg, 16)
   333  	}
   334  	// Add flag registers.
   335  	l.addSpecial(
   336  		"MOVD NZCV, R0\nMOVD R0, %d(RSP)",
   337  		"MOVD %d(RSP), R0\nMOVD R0, NZCV",
   338  		8)
   339  	l.addSpecial(
   340  		"MOVD FPSR, R0\nMOVD R0, %d(RSP)",
   341  		"MOVD %d(RSP), R0\nMOVD R0, FPSR",
   342  		8)
   343  	// TODO: FPCR? I don't think we'll change it, so no need to save.
   344  	// Add floating point registers F0-F31.
   345  	for i := 0; i < 31; i += 2 {
   346  		reg := fmt.Sprintf("(F%d, F%d)", i, i+1)
   347  		l.add2("FSTPD", "FLDPD", reg, 16)
   348  	}
   349  	if l.stack%16 != 0 {
   350  		l.stack += 8 // SP needs 16-byte alignment
   351  	}
   352  
   353  	// allocate frame, save PC of interrupted instruction (in LR)
   354  	p("MOVD R30, %d(RSP)", -l.stack)
   355  	p("SUB $%d, RSP", l.stack)
   356  	p("MOVD R29, -8(RSP)") // save frame pointer (only used on Linux)
   357  	p("SUB $8, RSP, R29")  // set up new frame pointer
   358  	// On iOS, save the LR again after decrementing SP. We run the
   359  	// signal handler on the G stack (as it doesn't support sigaltstack),
   360  	// so any writes below SP may be clobbered.
   361  	p("#ifdef GOOS_ios")
   362  	p("MOVD R30, (RSP)")
   363  	p("#endif")
   364  
   365  	l.save()
   366  	p("CALL ·asyncPreempt2(SB)")
   367  	l.restore()
   368  
   369  	p("MOVD %d(RSP), R30", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
   370  	p("MOVD -8(RSP), R29")          // restore frame pointer
   371  	p("MOVD (RSP), R27")            // load PC to REGTMP
   372  	p("ADD $%d, RSP", l.stack+16)   // pop frame (including the space pushed by sigctxt.pushCall)
   373  	p("JMP (R27)")
   374  }
   375  
   376  func genMIPS(_64bit bool) {
   377  	mov := "MOVW"
   378  	movf := "MOVF"
   379  	add := "ADD"
   380  	sub := "SUB"
   381  	r28 := "R28"
   382  	regsize := 4
   383  	softfloat := "GOMIPS_softfloat"
   384  	if _64bit {
   385  		mov = "MOVV"
   386  		movf = "MOVD"
   387  		add = "ADDV"
   388  		sub = "SUBV"
   389  		r28 = "RSB"
   390  		regsize = 8
   391  		softfloat = "GOMIPS64_softfloat"
   392  	}
   393  
   394  	// Add integer registers R1-R22, R24-R25, R28
   395  	// R0 (zero), R23 (REGTMP), R29 (SP), R30 (g), R31 (LR) are special,
   396  	// and not saved here. R26 and R27 are reserved by kernel and not used.
   397  	var l = layout{sp: "R29", stack: regsize} // add slot to save PC of interrupted instruction (in LR)
   398  	for i := 1; i <= 25; i++ {
   399  		if i == 23 {
   400  			continue // R23 is REGTMP
   401  		}
   402  		reg := fmt.Sprintf("R%d", i)
   403  		l.add(mov, reg, regsize)
   404  	}
   405  	l.add(mov, r28, regsize)
   406  	l.addSpecial(
   407  		mov+" HI, R1\n"+mov+" R1, %d(R29)",
   408  		mov+" %d(R29), R1\n"+mov+" R1, HI",
   409  		regsize)
   410  	l.addSpecial(
   411  		mov+" LO, R1\n"+mov+" R1, %d(R29)",
   412  		mov+" %d(R29), R1\n"+mov+" R1, LO",
   413  		regsize)
   414  
   415  	// Add floating point control/status register FCR31 (FCR0-FCR30 are irrelevant)
   416  	var lfp = layout{sp: "R29", stack: l.stack}
   417  	lfp.addSpecial(
   418  		mov+" FCR31, R1\n"+mov+" R1, %d(R29)",
   419  		mov+" %d(R29), R1\n"+mov+" R1, FCR31",
   420  		regsize)
   421  	// Add floating point registers F0-F31.
   422  	for i := 0; i <= 31; i++ {
   423  		reg := fmt.Sprintf("F%d", i)
   424  		lfp.add(movf, reg, regsize)
   425  	}
   426  
   427  	// allocate frame, save PC of interrupted instruction (in LR)
   428  	p(mov+" R31, -%d(R29)", lfp.stack)
   429  	p(sub+" $%d, R29", lfp.stack)
   430  
   431  	l.save()
   432  	p("#ifndef %s", softfloat)
   433  	lfp.save()
   434  	p("#endif")
   435  	p("CALL ·asyncPreempt2(SB)")
   436  	p("#ifndef %s", softfloat)
   437  	lfp.restore()
   438  	p("#endif")
   439  	l.restore()
   440  
   441  	p(mov+" %d(R29), R31", lfp.stack)     // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
   442  	p(mov + " (R29), R23")                // load PC to REGTMP
   443  	p(add+" $%d, R29", lfp.stack+regsize) // pop frame (including the space pushed by sigctxt.pushCall)
   444  	p("JMP (R23)")
   445  }
   446  
   447  func genLoong64() {
   448  	mov := "MOVV"
   449  	movf := "MOVD"
   450  	add := "ADDV"
   451  	sub := "SUBV"
   452  	regsize := 8
   453  
   454  	// Add integer registers r4-r21 r23-r29 r31
   455  	// R0 (zero), R30 (REGTMP), R2 (tp), R3 (SP), R22 (g), R1 (LR) are special,
   456  	var l = layout{sp: "R3", stack: regsize} // add slot to save PC of interrupted instruction (in LR)
   457  	for i := 4; i <= 31; i++ {
   458  		if i == 22 || i == 30 {
   459  			continue
   460  		}
   461  		reg := fmt.Sprintf("R%d", i)
   462  		l.add(mov, reg, regsize)
   463  	}
   464  
   465  	// Add floating point registers F0-F31.
   466  	for i := 0; i <= 31; i++ {
   467  		reg := fmt.Sprintf("F%d", i)
   468  		l.add(movf, reg, regsize)
   469  	}
   470  
   471  	// save/restore FCC0
   472  	l.addSpecial(
   473  		mov+" FCC0, R4\n"+mov+" R4, %d(R3)",
   474  		mov+" %d(R3), R4\n"+mov+" R4, FCC0",
   475  		regsize)
   476  
   477  	// allocate frame, save PC of interrupted instruction (in LR)
   478  	p(mov+" R1, -%d(R3)", l.stack)
   479  	p(sub+" $%d, R3", l.stack)
   480  
   481  	l.save()
   482  	p("CALL ·asyncPreempt2(SB)")
   483  	l.restore()
   484  
   485  	p(mov+" %d(R3), R1", l.stack)      // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
   486  	p(mov + " (R3), R30")              // load PC to REGTMP
   487  	p(add+" $%d, R3", l.stack+regsize) // pop frame (including the space pushed by sigctxt.pushCall)
   488  	p("JMP (R30)")
   489  }
   490  
   491  func genPPC64() {
   492  	// Add integer registers R3-R29
   493  	// R0 (zero), R1 (SP), R30 (g) are special and not saved here.
   494  	// R2 (TOC pointer in PIC mode), R12 (function entry address in PIC mode) have been saved in sigctxt.pushCall.
   495  	// R31 (REGTMP) will be saved manually.
   496  	var l = layout{sp: "R1", stack: 32 + 8} // MinFrameSize on PPC64, plus one word for saving R31
   497  	for i := 3; i <= 29; i++ {
   498  		if i == 12 || i == 13 {
   499  			// R12 has been saved in sigctxt.pushCall.
   500  			// R13 is TLS pointer, not used by Go code. we must NOT
   501  			// restore it, otherwise if we parked and resumed on a
   502  			// different thread we'll mess up TLS addresses.
   503  			continue
   504  		}
   505  		reg := fmt.Sprintf("R%d", i)
   506  		l.add("MOVD", reg, 8)
   507  	}
   508  	l.addSpecial(
   509  		"MOVW CR, R31\nMOVW R31, %d(R1)",
   510  		"MOVW %d(R1), R31\nMOVFL R31, $0xff", // this is MOVW R31, CR
   511  		8)                                    // CR is 4-byte wide, but just keep the alignment
   512  	l.addSpecial(
   513  		"MOVD XER, R31\nMOVD R31, %d(R1)",
   514  		"MOVD %d(R1), R31\nMOVD R31, XER",
   515  		8)
   516  	// Add floating point registers F0-F31.
   517  	for i := 0; i <= 31; i++ {
   518  		reg := fmt.Sprintf("F%d", i)
   519  		l.add("FMOVD", reg, 8)
   520  	}
   521  	// Add floating point control/status register FPSCR.
   522  	l.addSpecial(
   523  		"MOVFL FPSCR, F0\nFMOVD F0, %d(R1)",
   524  		"FMOVD %d(R1), F0\nMOVFL F0, FPSCR",
   525  		8)
   526  
   527  	p("MOVD R31, -%d(R1)", l.stack-32) // save R31 first, we'll use R31 for saving LR
   528  	p("MOVD LR, R31")
   529  	p("MOVDU R31, -%d(R1)", l.stack) // allocate frame, save PC of interrupted instruction (in LR)
   530  
   531  	l.save()
   532  	p("CALL ·asyncPreempt2(SB)")
   533  	l.restore()
   534  
   535  	p("MOVD %d(R1), R31", l.stack) // sigctxt.pushCall has pushed LR, R2, R12 (at interrupt) on stack, restore them
   536  	p("MOVD R31, LR")
   537  	p("MOVD %d(R1), R2", l.stack+8)
   538  	p("MOVD %d(R1), R12", l.stack+16)
   539  	p("MOVD (R1), R31") // load PC to CTR
   540  	p("MOVD R31, CTR")
   541  	p("MOVD 32(R1), R31")        // restore R31
   542  	p("ADD $%d, R1", l.stack+32) // pop frame (including the space pushed by sigctxt.pushCall)
   543  	p("JMP (CTR)")
   544  }
   545  
   546  func genRISCV64() {
   547  	// X0 (zero), X1 (LR), X2 (SP), X3 (GP), X4 (TP), X27 (g), X31 (TMP) are special.
   548  	var l = layout{sp: "X2", stack: 8}
   549  
   550  	// Add integer registers (X5-X26, X28-30).
   551  	for i := 5; i < 31; i++ {
   552  		if i == 27 {
   553  			continue
   554  		}
   555  		reg := fmt.Sprintf("X%d", i)
   556  		l.add("MOV", reg, 8)
   557  	}
   558  
   559  	// Add floating point registers (F0-F31).
   560  	for i := 0; i <= 31; i++ {
   561  		reg := fmt.Sprintf("F%d", i)
   562  		l.add("MOVD", reg, 8)
   563  	}
   564  
   565  	p("MOV X1, -%d(X2)", l.stack)
   566  	p("SUB $%d, X2", l.stack)
   567  	l.save()
   568  	p("CALL ·asyncPreempt2(SB)")
   569  	l.restore()
   570  	p("MOV %d(X2), X1", l.stack)
   571  	p("MOV (X2), X31")
   572  	p("ADD $%d, X2", l.stack+8)
   573  	p("JMP (X31)")
   574  }
   575  
   576  func genS390X() {
   577  	// Add integer registers R0-R12
   578  	// R13 (g), R14 (LR), R15 (SP) are special, and not saved here.
   579  	// Saving R10 (REGTMP) is not necessary, but it is saved anyway.
   580  	var l = layout{sp: "R15", stack: 16} // add slot to save PC of interrupted instruction and flags
   581  	l.addSpecial(
   582  		"STMG R0, R12, %d(R15)",
   583  		"LMG %d(R15), R0, R12",
   584  		13*8)
   585  	// Add floating point registers F0-F31.
   586  	for i := 0; i <= 15; i++ {
   587  		reg := fmt.Sprintf("F%d", i)
   588  		l.add("FMOVD", reg, 8)
   589  	}
   590  
   591  	// allocate frame, save PC of interrupted instruction (in LR) and flags (condition code)
   592  	p("IPM R10") // save flags upfront, as ADD will clobber flags
   593  	p("MOVD R14, -%d(R15)", l.stack)
   594  	p("ADD $-%d, R15", l.stack)
   595  	p("MOVW R10, 8(R15)") // save flags
   596  
   597  	l.save()
   598  	p("CALL ·asyncPreempt2(SB)")
   599  	l.restore()
   600  
   601  	p("MOVD %d(R15), R14", l.stack)    // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
   602  	p("ADD $%d, R15", l.stack+8)       // pop frame (including the space pushed by sigctxt.pushCall)
   603  	p("MOVWZ -%d(R15), R10", l.stack)  // load flags to REGTMP
   604  	p("TMLH R10, $(3<<12)")            // restore flags
   605  	p("MOVD -%d(R15), R10", l.stack+8) // load PC to REGTMP
   606  	p("JMP (R10)")
   607  }
   608  
   609  func genWasm() {
   610  	p("// No async preemption on wasm")
   611  	p("UNDEF")
   612  }
   613  
   614  func notImplemented() {
   615  	p("// Not implemented yet")
   616  	p("JMP ·abort(SB)")
   617  }
   618  

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