Text file
src/runtime/preempt_arm64.s
1 // Code generated by mkpreempt.go; DO NOT EDIT.
2
3 #include "go_asm.h"
4 #include "textflag.h"
5
6 TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
7 MOVD R30, -240(RSP)
8 SUB $240, RSP
9 MOVD R29, -8(RSP)
10 SUB $8, RSP, R29
11 #ifdef GOOS_ios
12 MOVD R30, (RSP)
13 #endif
14 // Save GPs
15 STP (R0, R1), 8(RSP)
16 STP (R2, R3), 24(RSP)
17 STP (R4, R5), 40(RSP)
18 STP (R6, R7), 56(RSP)
19 STP (R8, R9), 72(RSP)
20 STP (R10, R11), 88(RSP)
21 STP (R12, R13), 104(RSP)
22 STP (R14, R15), 120(RSP)
23 STP (R16, R17), 136(RSP)
24 STP (R19, R20), 152(RSP)
25 STP (R21, R22), 168(RSP)
26 STP (R23, R24), 184(RSP)
27 STP (R25, R26), 200(RSP)
28 MOVD NZCV, R0
29 MOVD R0, 216(RSP)
30 MOVD FPSR, R0
31 MOVD R0, 224(RSP)
32 // Save extended register state to p.xRegs.scratch
33 MOVD g_m(g), R0
34 MOVD m_p(R0), R0
35 ADD $(p_xRegs+xRegPerP_scratch), R0, R0
36 #ifdef GOEXPERIMENT_simd
37 MOVBU internal∕cpu·ARM64+const_offsetARM64HasSVE(SB), R27
38 CMP $1, R27
39 BNE saveNEON
40 RDVL $1, R27
41 CMP $32, R27
42 BGT saveNEON
43 ZSTR Z0, (VL*0)(R0)
44 ZSTR Z1, (VL*1)(R0)
45 ZSTR Z2, (VL*2)(R0)
46 ZSTR Z3, (VL*3)(R0)
47 ZSTR Z4, (VL*4)(R0)
48 ZSTR Z5, (VL*5)(R0)
49 ZSTR Z6, (VL*6)(R0)
50 ZSTR Z7, (VL*7)(R0)
51 ZSTR Z8, (VL*8)(R0)
52 ZSTR Z9, (VL*9)(R0)
53 ZSTR Z10, (VL*10)(R0)
54 ZSTR Z11, (VL*11)(R0)
55 ZSTR Z12, (VL*12)(R0)
56 ZSTR Z13, (VL*13)(R0)
57 ZSTR Z14, (VL*14)(R0)
58 ZSTR Z15, (VL*15)(R0)
59 ZSTR Z16, (VL*16)(R0)
60 ZSTR Z17, (VL*17)(R0)
61 ZSTR Z18, (VL*18)(R0)
62 ZSTR Z19, (VL*19)(R0)
63 ZSTR Z20, (VL*20)(R0)
64 ZSTR Z21, (VL*21)(R0)
65 ZSTR Z22, (VL*22)(R0)
66 ZSTR Z23, (VL*23)(R0)
67 ZSTR Z24, (VL*24)(R0)
68 ZSTR Z25, (VL*25)(R0)
69 ZSTR Z26, (VL*26)(R0)
70 ZSTR Z27, (VL*27)(R0)
71 ZSTR Z28, (VL*28)(R0)
72 ZSTR Z29, (VL*29)(R0)
73 ZSTR Z30, (VL*30)(R0)
74 ZSTR Z31, (VL*31)(R0)
75 RDVL $1, R27
76 LSL $5, R27
77 ADD R0, R27
78 PSTR P0, (VL*0)(R27)
79 PSTR P1, (VL*1)(R27)
80 PSTR P2, (VL*2)(R27)
81 PSTR P3, (VL*3)(R27)
82 PSTR P4, (VL*4)(R27)
83 PSTR P5, (VL*5)(R27)
84 PSTR P6, (VL*6)(R27)
85 PSTR P7, (VL*7)(R27)
86 PSTR P8, (VL*8)(R27)
87 PSTR P9, (VL*9)(R27)
88 PSTR P10, (VL*10)(R27)
89 PSTR P11, (VL*11)(R27)
90 PSTR P12, (VL*12)(R27)
91 PSTR P13, (VL*13)(R27)
92 PSTR P14, (VL*14)(R27)
93 PSTR P15, (VL*15)(R27)
94 JMP preempt
95 #endif
96 saveNEON:
97 VST1.P [V0.B16, V1.B16, V2.B16, V3.B16], 64(R0)
98 VST1.P [V4.B16, V5.B16, V6.B16, V7.B16], 64(R0)
99 VST1.P [V8.B16, V9.B16, V10.B16, V11.B16], 64(R0)
100 VST1.P [V12.B16, V13.B16, V14.B16, V15.B16], 64(R0)
101 VST1.P [V16.B16, V17.B16, V18.B16, V19.B16], 64(R0)
102 VST1.P [V20.B16, V21.B16, V22.B16, V23.B16], 64(R0)
103 VST1.P [V24.B16, V25.B16, V26.B16, V27.B16], 64(R0)
104 VST1.P [V28.B16, V29.B16, V30.B16, V31.B16], 64(R0)
105 preempt:
106 CALL ·asyncPreempt2(SB)
107 // Restore non-GPs from *p.xRegs.cache
108 MOVD g_m(g), R0
109 MOVD m_p(R0), R0
110 MOVD (p_xRegs+xRegPerP_cache)(R0), R0
111 #ifdef GOEXPERIMENT_simd
112 MOVBU internal∕cpu·ARM64+const_offsetARM64HasSVE(SB), R27
113 CMP $1, R27
114 BNE restoreNEON
115 RDVL $1, R27
116 CMP $32, R27
117 BGT restoreNEON
118 ZLDR (VL*0)(R0), Z0
119 ZLDR (VL*1)(R0), Z1
120 ZLDR (VL*2)(R0), Z2
121 ZLDR (VL*3)(R0), Z3
122 ZLDR (VL*4)(R0), Z4
123 ZLDR (VL*5)(R0), Z5
124 ZLDR (VL*6)(R0), Z6
125 ZLDR (VL*7)(R0), Z7
126 ZLDR (VL*8)(R0), Z8
127 ZLDR (VL*9)(R0), Z9
128 ZLDR (VL*10)(R0), Z10
129 ZLDR (VL*11)(R0), Z11
130 ZLDR (VL*12)(R0), Z12
131 ZLDR (VL*13)(R0), Z13
132 ZLDR (VL*14)(R0), Z14
133 ZLDR (VL*15)(R0), Z15
134 ZLDR (VL*16)(R0), Z16
135 ZLDR (VL*17)(R0), Z17
136 ZLDR (VL*18)(R0), Z18
137 ZLDR (VL*19)(R0), Z19
138 ZLDR (VL*20)(R0), Z20
139 ZLDR (VL*21)(R0), Z21
140 ZLDR (VL*22)(R0), Z22
141 ZLDR (VL*23)(R0), Z23
142 ZLDR (VL*24)(R0), Z24
143 ZLDR (VL*25)(R0), Z25
144 ZLDR (VL*26)(R0), Z26
145 ZLDR (VL*27)(R0), Z27
146 ZLDR (VL*28)(R0), Z28
147 ZLDR (VL*29)(R0), Z29
148 ZLDR (VL*30)(R0), Z30
149 ZLDR (VL*31)(R0), Z31
150 RDVL $1, R27
151 LSL $5, R27
152 ADD R0, R27
153 PLDR (VL*0)(R27), P0
154 PLDR (VL*1)(R27), P1
155 PLDR (VL*2)(R27), P2
156 PLDR (VL*3)(R27), P3
157 PLDR (VL*4)(R27), P4
158 PLDR (VL*5)(R27), P5
159 PLDR (VL*6)(R27), P6
160 PLDR (VL*7)(R27), P7
161 PLDR (VL*8)(R27), P8
162 PLDR (VL*9)(R27), P9
163 PLDR (VL*10)(R27), P10
164 PLDR (VL*11)(R27), P11
165 PLDR (VL*12)(R27), P12
166 PLDR (VL*13)(R27), P13
167 PLDR (VL*14)(R27), P14
168 PLDR (VL*15)(R27), P15
169 JMP restoreGPs
170 #endif
171 restoreNEON:
172 VLD1.P 64(R0), [V0.B16, V1.B16, V2.B16, V3.B16]
173 VLD1.P 64(R0), [V4.B16, V5.B16, V6.B16, V7.B16]
174 VLD1.P 64(R0), [V8.B16, V9.B16, V10.B16, V11.B16]
175 VLD1.P 64(R0), [V12.B16, V13.B16, V14.B16, V15.B16]
176 VLD1.P 64(R0), [V16.B16, V17.B16, V18.B16, V19.B16]
177 VLD1.P 64(R0), [V20.B16, V21.B16, V22.B16, V23.B16]
178 VLD1.P 64(R0), [V24.B16, V25.B16, V26.B16, V27.B16]
179 VLD1.P 64(R0), [V28.B16, V29.B16, V30.B16, V31.B16]
180 restoreGPs:
181 // Restore GPs
182 MOVD 224(RSP), R0
183 MOVD R0, FPSR
184 MOVD 216(RSP), R0
185 MOVD R0, NZCV
186 LDP 200(RSP), (R25, R26)
187 LDP 184(RSP), (R23, R24)
188 LDP 168(RSP), (R21, R22)
189 LDP 152(RSP), (R19, R20)
190 LDP 136(RSP), (R16, R17)
191 LDP 120(RSP), (R14, R15)
192 LDP 104(RSP), (R12, R13)
193 LDP 88(RSP), (R10, R11)
194 LDP 72(RSP), (R8, R9)
195 LDP 56(RSP), (R6, R7)
196 LDP 40(RSP), (R4, R5)
197 LDP 24(RSP), (R2, R3)
198 LDP 8(RSP), (R0, R1)
199 MOVD 240(RSP), R30
200 MOVD -8(RSP), R29
201 MOVD (RSP), R27
202 ADD $256, RSP
203 RET (R27)
204
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