Source file src/vendor/golang.org/x/sys/cpu/cpu.go
1 // Copyright 2018 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Package cpu implements processor feature detection for 6 // various CPU architectures. 7 package cpu 8 9 import ( 10 "os" 11 "strings" 12 ) 13 14 // Initialized reports whether the CPU features were initialized. 15 // 16 // For some GOOS/GOARCH combinations initialization of the CPU features depends 17 // on reading an operating specific file, e.g. /proc/self/auxv on linux/arm 18 // Initialized will report false if reading the file fails. 19 var Initialized bool 20 21 // CacheLinePad is used to pad structs to avoid false sharing. 22 type CacheLinePad struct{ _ [cacheLineSize]byte } 23 24 // X86 contains the supported CPU features of the 25 // current X86/AMD64 platform. If the current platform 26 // is not X86/AMD64 then all feature flags are false. 27 // 28 // X86 is padded to avoid false sharing. Further the HasAVX 29 // and HasAVX2 are only set if the OS supports XMM and YMM 30 // registers in addition to the CPUID feature bit being set. 31 var X86 struct { 32 _ CacheLinePad 33 HasAES bool // AES hardware implementation (AES NI) 34 HasADX bool // Multi-precision add-carry instruction extensions 35 HasAVX bool // Advanced vector extension 36 HasAVX2 bool // Advanced vector extension 2 37 HasAVX512 bool // Advanced vector extension 512 38 HasAVX512F bool // Advanced vector extension 512 Foundation Instructions 39 HasAVX512CD bool // Advanced vector extension 512 Conflict Detection Instructions 40 HasAVX512ER bool // Advanced vector extension 512 Exponential and Reciprocal Instructions 41 HasAVX512PF bool // Advanced vector extension 512 Prefetch Instructions 42 HasAVX512VL bool // Advanced vector extension 512 Vector Length Extensions 43 HasAVX512BW bool // Advanced vector extension 512 Byte and Word Instructions 44 HasAVX512DQ bool // Advanced vector extension 512 Doubleword and Quadword Instructions 45 HasAVX512IFMA bool // Advanced vector extension 512 Integer Fused Multiply Add 46 HasAVX512VBMI bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 47 HasAVX5124VNNIW bool // Advanced vector extension 512 Vector Neural Network Instructions Word variable precision 48 HasAVX5124FMAPS bool // Advanced vector extension 512 Fused Multiply Accumulation Packed Single precision 49 HasAVX512VPOPCNTDQ bool // Advanced vector extension 512 Double and quad word population count instructions 50 HasAVX512VPCLMULQDQ bool // Advanced vector extension 512 Vector carry-less multiply operations 51 HasAVX512VNNI bool // Advanced vector extension 512 Vector Neural Network Instructions 52 HasAVX512GFNI bool // Advanced vector extension 512 Galois field New Instructions 53 HasAVX512VAES bool // Advanced vector extension 512 Vector AES instructions 54 HasAVX512VBMI2 bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 2 55 HasAVX512BITALG bool // Advanced vector extension 512 Bit Algorithms 56 HasAVX512BF16 bool // Advanced vector extension 512 BFloat16 Instructions 57 HasAMXTile bool // Advanced Matrix Extension Tile instructions 58 HasAMXInt8 bool // Advanced Matrix Extension Int8 instructions 59 HasAMXBF16 bool // Advanced Matrix Extension BFloat16 instructions 60 HasBMI1 bool // Bit manipulation instruction set 1 61 HasBMI2 bool // Bit manipulation instruction set 2 62 HasCX16 bool // Compare and exchange 16 Bytes 63 HasERMS bool // Enhanced REP for MOVSB and STOSB 64 HasFMA bool // Fused-multiply-add instructions 65 HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers. 66 HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM 67 HasPOPCNT bool // Hamming weight instruction POPCNT. 68 HasRDRAND bool // RDRAND instruction (on-chip random number generator) 69 HasRDSEED bool // RDSEED instruction (on-chip random number generator) 70 HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64) 71 HasSSE3 bool // Streaming SIMD extension 3 72 HasSSSE3 bool // Supplemental streaming SIMD extension 3 73 HasSSE41 bool // Streaming SIMD extension 4 and 4.1 74 HasSSE42 bool // Streaming SIMD extension 4 and 4.2 75 _ CacheLinePad 76 } 77 78 // ARM64 contains the supported CPU features of the 79 // current ARMv8(aarch64) platform. If the current platform 80 // is not arm64 then all feature flags are false. 81 var ARM64 struct { 82 _ CacheLinePad 83 HasFP bool // Floating-point instruction set (always available) 84 HasASIMD bool // Advanced SIMD (always available) 85 HasEVTSTRM bool // Event stream support 86 HasAES bool // AES hardware implementation 87 HasPMULL bool // Polynomial multiplication instruction set 88 HasSHA1 bool // SHA1 hardware implementation 89 HasSHA2 bool // SHA2 hardware implementation 90 HasCRC32 bool // CRC32 hardware implementation 91 HasATOMICS bool // Atomic memory operation instruction set 92 HasFPHP bool // Half precision floating-point instruction set 93 HasASIMDHP bool // Advanced SIMD half precision instruction set 94 HasCPUID bool // CPUID identification scheme registers 95 HasASIMDRDM bool // Rounding double multiply add/subtract instruction set 96 HasJSCVT bool // Javascript conversion from floating-point to integer 97 HasFCMA bool // Floating-point multiplication and addition of complex numbers 98 HasLRCPC bool // Release Consistent processor consistent support 99 HasDCPOP bool // Persistent memory support 100 HasSHA3 bool // SHA3 hardware implementation 101 HasSM3 bool // SM3 hardware implementation 102 HasSM4 bool // SM4 hardware implementation 103 HasASIMDDP bool // Advanced SIMD double precision instruction set 104 HasSHA512 bool // SHA512 hardware implementation 105 HasSVE bool // Scalable Vector Extensions 106 HasSVE2 bool // Scalable Vector Extensions 2 107 HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32 108 HasDIT bool // Data Independent Timing support 109 HasI8MM bool // Advanced SIMD Int8 matrix multiplication instructions 110 _ CacheLinePad 111 } 112 113 // ARM contains the supported CPU features of the current ARM (32-bit) platform. 114 // All feature flags are false if: 115 // 1. the current platform is not arm, or 116 // 2. the current operating system is not Linux. 117 var ARM struct { 118 _ CacheLinePad 119 HasSWP bool // SWP instruction support 120 HasHALF bool // Half-word load and store support 121 HasTHUMB bool // ARM Thumb instruction set 122 Has26BIT bool // Address space limited to 26-bits 123 HasFASTMUL bool // 32-bit operand, 64-bit result multiplication support 124 HasFPA bool // Floating point arithmetic support 125 HasVFP bool // Vector floating point support 126 HasEDSP bool // DSP Extensions support 127 HasJAVA bool // Java instruction set 128 HasIWMMXT bool // Intel Wireless MMX technology support 129 HasCRUNCH bool // MaverickCrunch context switching and handling 130 HasTHUMBEE bool // Thumb EE instruction set 131 HasNEON bool // NEON instruction set 132 HasVFPv3 bool // Vector floating point version 3 support 133 HasVFPv3D16 bool // Vector floating point version 3 D8-D15 134 HasTLS bool // Thread local storage support 135 HasVFPv4 bool // Vector floating point version 4 support 136 HasIDIVA bool // Integer divide instruction support in ARM mode 137 HasIDIVT bool // Integer divide instruction support in Thumb mode 138 HasVFPD32 bool // Vector floating point version 3 D15-D31 139 HasLPAE bool // Large Physical Address Extensions 140 HasEVTSTRM bool // Event stream support 141 HasAES bool // AES hardware implementation 142 HasPMULL bool // Polynomial multiplication instruction set 143 HasSHA1 bool // SHA1 hardware implementation 144 HasSHA2 bool // SHA2 hardware implementation 145 HasCRC32 bool // CRC32 hardware implementation 146 _ CacheLinePad 147 } 148 149 // MIPS64X contains the supported CPU features of the current mips64/mips64le 150 // platforms. If the current platform is not mips64/mips64le or the current 151 // operating system is not Linux then all feature flags are false. 152 var MIPS64X struct { 153 _ CacheLinePad 154 HasMSA bool // MIPS SIMD architecture 155 _ CacheLinePad 156 } 157 158 // PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms. 159 // If the current platform is not ppc64/ppc64le then all feature flags are false. 160 // 161 // For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00, 162 // since there are no optional categories. There are some exceptions that also 163 // require kernel support to work (DARN, SCV), so there are feature bits for 164 // those as well. The struct is padded to avoid false sharing. 165 var PPC64 struct { 166 _ CacheLinePad 167 HasDARN bool // Hardware random number generator (requires kernel enablement) 168 HasSCV bool // Syscall vectored (requires kernel enablement) 169 IsPOWER8 bool // ISA v2.07 (POWER8) 170 IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8 171 _ CacheLinePad 172 } 173 174 // S390X contains the supported CPU features of the current IBM Z 175 // (s390x) platform. If the current platform is not IBM Z then all 176 // feature flags are false. 177 // 178 // S390X is padded to avoid false sharing. Further HasVX is only set 179 // if the OS supports vector registers in addition to the STFLE 180 // feature bit being set. 181 var S390X struct { 182 _ CacheLinePad 183 HasZARCH bool // z/Architecture mode is active [mandatory] 184 HasSTFLE bool // store facility list extended 185 HasLDISP bool // long (20-bit) displacements 186 HasEIMM bool // 32-bit immediates 187 HasDFP bool // decimal floating point 188 HasETF3EH bool // ETF-3 enhanced 189 HasMSA bool // message security assist (CPACF) 190 HasAES bool // KM-AES{128,192,256} functions 191 HasAESCBC bool // KMC-AES{128,192,256} functions 192 HasAESCTR bool // KMCTR-AES{128,192,256} functions 193 HasAESGCM bool // KMA-GCM-AES{128,192,256} functions 194 HasGHASH bool // KIMD-GHASH function 195 HasSHA1 bool // K{I,L}MD-SHA-1 functions 196 HasSHA256 bool // K{I,L}MD-SHA-256 functions 197 HasSHA512 bool // K{I,L}MD-SHA-512 functions 198 HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions 199 HasVX bool // vector facility 200 HasVXE bool // vector-enhancements facility 1 201 _ CacheLinePad 202 } 203 204 // RISCV64 contains the supported CPU features and performance characteristics for riscv64 205 // platforms. The booleans in RISCV64, with the exception of HasFastMisaligned, indicate 206 // the presence of RISC-V extensions. 207 // 208 // It is safe to assume that all the RV64G extensions are supported and so they are omitted from 209 // this structure. As riscv64 Go programs require at least RV64G, the code that populates 210 // this structure cannot run successfully if some of the RV64G extensions are missing. 211 // The struct is padded to avoid false sharing. 212 var RISCV64 struct { 213 _ CacheLinePad 214 HasFastMisaligned bool // Fast misaligned accesses 215 HasC bool // Compressed instruction-set extension 216 HasV bool // Vector extension compatible with RVV 1.0 217 HasZba bool // Address generation instructions extension 218 HasZbb bool // Basic bit-manipulation extension 219 HasZbs bool // Single-bit instructions extension 220 _ CacheLinePad 221 } 222 223 func init() { 224 archInit() 225 initOptions() 226 processOptions() 227 } 228 229 // options contains the cpu debug options that can be used in GODEBUG. 230 // Options are arch dependent and are added by the arch specific initOptions functions. 231 // Features that are mandatory for the specific GOARCH should have the Required field set 232 // (e.g. SSE2 on amd64). 233 var options []option 234 235 // Option names should be lower case. e.g. avx instead of AVX. 236 type option struct { 237 Name string 238 Feature *bool 239 Specified bool // whether feature value was specified in GODEBUG 240 Enable bool // whether feature should be enabled 241 Required bool // whether feature is mandatory and can not be disabled 242 } 243 244 func processOptions() { 245 env := os.Getenv("GODEBUG") 246 field: 247 for env != "" { 248 field := "" 249 i := strings.IndexByte(env, ',') 250 if i < 0 { 251 field, env = env, "" 252 } else { 253 field, env = env[:i], env[i+1:] 254 } 255 if len(field) < 4 || field[:4] != "cpu." { 256 continue 257 } 258 i = strings.IndexByte(field, '=') 259 if i < 0 { 260 print("GODEBUG sys/cpu: no value specified for \"", field, "\"\n") 261 continue 262 } 263 key, value := field[4:i], field[i+1:] // e.g. "SSE2", "on" 264 265 var enable bool 266 switch value { 267 case "on": 268 enable = true 269 case "off": 270 enable = false 271 default: 272 print("GODEBUG sys/cpu: value \"", value, "\" not supported for cpu option \"", key, "\"\n") 273 continue field 274 } 275 276 if key == "all" { 277 for i := range options { 278 options[i].Specified = true 279 options[i].Enable = enable || options[i].Required 280 } 281 continue field 282 } 283 284 for i := range options { 285 if options[i].Name == key { 286 options[i].Specified = true 287 options[i].Enable = enable 288 continue field 289 } 290 } 291 292 print("GODEBUG sys/cpu: unknown cpu feature \"", key, "\"\n") 293 } 294 295 for _, o := range options { 296 if !o.Specified { 297 continue 298 } 299 300 if o.Enable && !*o.Feature { 301 print("GODEBUG sys/cpu: can not enable \"", o.Name, "\", missing CPU support\n") 302 continue 303 } 304 305 if !o.Enable && o.Required { 306 print("GODEBUG sys/cpu: can not disable \"", o.Name, "\", required CPU feature\n") 307 continue 308 } 309 310 *o.Feature = o.Enable 311 } 312 } 313