cpu_linux_riscv64.go

     1  // Copyright 2024 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package cpu
     6  
     7  import (
     8  	"syscall"
     9  	"unsafe"
    10  )
    11  
    12  // RISC-V extension discovery code for Linux. The approach here is to first try the riscv_hwprobe
    13  // syscall falling back to HWCAP to check for the C extension if riscv_hwprobe is not available.
    14  //
    15  // A note on detection of the Vector extension using HWCAP.
    16  //
    17  // Support for the Vector extension version 1.0 was added to the Linux kernel in release 6.5.
    18  // Support for the riscv_hwprobe syscall was added in 6.4. It follows that if the riscv_hwprobe
    19  // syscall is not available then neither is the Vector extension (which needs kernel support).
    20  // The riscv_hwprobe syscall should then be all we need to detect the Vector extension.
    21  // However, some RISC-V board manufacturers ship boards with an older kernel on top of which
    22  // they have back-ported various versions of the Vector extension patches but not the riscv_hwprobe
    23  // patches. These kernels advertise support for the Vector extension using HWCAP. Falling
    24  // back to HWCAP to detect the Vector extension, if riscv_hwprobe is not available, or simply not
    25  // bothering with riscv_hwprobe at all and just using HWCAP may then seem like an attractive option.
    26  //
    27  // Unfortunately, simply checking the 'V' bit in AT_HWCAP will not work as this bit is used by
    28  // RISC-V board and cloud instance providers to mean different things. The Lichee Pi 4A board
    29  // and the Scaleway RV1 cloud instances use the 'V' bit to advertise their support for the unratified
    30  // 0.7.1 version of the Vector Specification. The Banana Pi BPI-F3 and the CanMV-K230 board use
    31  // it to advertise support for 1.0 of the Vector extension. Versions 0.7.1 and 1.0 of the Vector
    32  // extension are binary incompatible. HWCAP can then not be used in isolation to populate the
    33  // HasV field as this field indicates that the underlying CPU is compatible with RVV 1.0.
    34  //
    35  // There is a way at runtime to distinguish between versions 0.7.1 and 1.0 of the Vector
    36  // specification by issuing a RVV 1.0 vsetvli instruction and checking the vill bit of the vtype
    37  // register. This check would allow us to safely detect version 1.0 of the Vector extension
    38  // with HWCAP, if riscv_hwprobe were not available. However, the check cannot
    39  // be added until the assembler supports the Vector instructions.
    40  //
    41  // Note the riscv_hwprobe syscall does not suffer from these ambiguities by design as all of the
    42  // extensions it advertises support for are explicitly versioned. It's also worth noting that
    43  // the riscv_hwprobe syscall is the only way to detect multi-letter RISC-V extensions, e.g., Zba.
    44  // These cannot be detected using HWCAP and so riscv_hwprobe must be used to detect the majority
    45  // of RISC-V extensions.
    46  //
    47  // Please see https://docs.kernel.org/arch/riscv/hwprobe.html for more information.
    48  
    49  // golang.org/x/sys/cpu is not allowed to depend on golang.org/x/sys/unix so we must
    50  // reproduce the constants, types and functions needed to make the riscv_hwprobe syscall
    51  // here.
    52  
    53  const (
    54  	// Copied from golang.org/x/sys/unix/ztypes_linux_riscv64.go.
    55  	riscv_HWPROBE_KEY_IMA_EXT_0   = 0x4
    56  	riscv_HWPROBE_IMA_C           = 0x2
    57  	riscv_HWPROBE_IMA_V           = 0x4
    58  	riscv_HWPROBE_EXT_ZBA         = 0x8
    59  	riscv_HWPROBE_EXT_ZBB         = 0x10
    60  	riscv_HWPROBE_EXT_ZBS         = 0x20
    61  	riscv_HWPROBE_KEY_CPUPERF_0   = 0x5
    62  	riscv_HWPROBE_MISALIGNED_FAST = 0x3
    63  	riscv_HWPROBE_MISALIGNED_MASK = 0x7
    64  )
    65  
    66  const (
    67  	// sys_RISCV_HWPROBE is copied from golang.org/x/sys/unix/zsysnum_linux_riscv64.go.
    68  	sys_RISCV_HWPROBE = 258
    69  )
    70  
    71  // riscvHWProbePairs is copied from golang.org/x/sys/unix/ztypes_linux_riscv64.go.
    72  type riscvHWProbePairs struct {
    73  	key   int64
    74  	value uint64
    75  }
    76  
    77  const (
    78  	// CPU features
    79  	hwcap_RISCV_ISA_C = 1 << ('C' - 'A')
    80  )
    81  
    82  func doinit() {
    83  	// A slice of key/value pair structures is passed to the RISCVHWProbe syscall. The key
    84  	// field should be initialised with one of the key constants defined above, e.g.,
    85  	// RISCV_HWPROBE_KEY_IMA_EXT_0. The syscall will set the value field to the appropriate value.
    86  	// If the kernel does not recognise a key it will set the key field to -1 and the value field to 0.
    87  
    88  	pairs := []riscvHWProbePairs{
    89  		{riscv_HWPROBE_KEY_IMA_EXT_0, 0},
    90  		{riscv_HWPROBE_KEY_CPUPERF_0, 0},
    91  	}
    92  
    93  	// This call only indicates that extensions are supported if they are implemented on all cores.
    94  	if riscvHWProbe(pairs, 0) {
    95  		if pairs[0].key != -1 {
    96  			v := uint(pairs[0].value)
    97  			RISCV64.HasC = isSet(v, riscv_HWPROBE_IMA_C)
    98  			RISCV64.HasV = isSet(v, riscv_HWPROBE_IMA_V)
    99  			RISCV64.HasZba = isSet(v, riscv_HWPROBE_EXT_ZBA)
   100  			RISCV64.HasZbb = isSet(v, riscv_HWPROBE_EXT_ZBB)
   101  			RISCV64.HasZbs = isSet(v, riscv_HWPROBE_EXT_ZBS)
   102  		}
   103  		if pairs[1].key != -1 {
   104  			v := pairs[1].value & riscv_HWPROBE_MISALIGNED_MASK
   105  			RISCV64.HasFastMisaligned = v == riscv_HWPROBE_MISALIGNED_FAST
   106  		}
   107  	}
   108  
   109  	// Let's double check with HWCAP if the C extension does not appear to be supported.
   110  	// This may happen if we're running on a kernel older than 6.4.
   111  
   112  	if !RISCV64.HasC {
   113  		RISCV64.HasC = isSet(hwCap, hwcap_RISCV_ISA_C)
   114  	}
   115  }
   116  
   117  func isSet(hwc uint, value uint) bool {
   118  	return hwc&value != 0
   119  }
   120  
   121  // riscvHWProbe is a simplified version of the generated wrapper function found in
   122  // golang.org/x/sys/unix/zsyscall_linux_riscv64.go. We simplify it by removing the
   123  // cpuCount and cpus parameters which we do not need. We always want to pass 0 for
   124  // these parameters here so the kernel only reports the extensions that are present
   125  // on all cores.
   126  func riscvHWProbe(pairs []riscvHWProbePairs, flags uint) bool {
   127  	var _zero uintptr
   128  	var p0 unsafe.Pointer
   129  	if len(pairs) > 0 {
   130  		p0 = unsafe.Pointer(&pairs[0])
   131  	} else {
   132  		p0 = unsafe.Pointer(&_zero)
   133  	}
   134  
   135  	_, _, e1 := syscall.Syscall6(sys_RISCV_HWPROBE, uintptr(p0), uintptr(len(pairs)), uintptr(0), uintptr(0), uintptr(flags), 0)
   136  	return e1 == 0
   137  }
   138
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