1
2
3
4
5 package loong64
6
7 import (
8 "cmd/internal/obj"
9 "cmd/internal/objabi"
10 "fmt"
11 "log"
12 "math/bits"
13 "slices"
14 )
15
16
17
18
19 type ctxt0 struct {
20 ctxt *obj.Link
21 newprog obj.ProgAlloc
22 cursym *obj.LSym
23 autosize int32
24 instoffset int64
25 pc int64
26 }
27
28
29
30 const (
31 FuncAlign = 4
32 loopAlign = 16
33 )
34
35 type Optab struct {
36 as obj.As
37 from1 uint8
38 reg uint8
39 from3 uint8
40 to1 uint8
41 to2 uint8
42 type_ int8
43 size int8
44 param int16
45 flag uint8
46 }
47
48 const (
49 NOTUSETMP = 1 << iota
50
51
52
53 branchLoopHead
54 )
55
56 var optab = []Optab{
57 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, C_NONE, 0, 0, 0, 0},
58
59 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
60 {AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
61 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 1, 4, 0, 0},
62 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 1, 4, 0, 0},
63 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
64 {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
65 {AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
66
67 {ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
68 {ASUBV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
69 {AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
70 {AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
71 {AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
72 {ASUB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
73 {ASUBV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
74 {AADD, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
75 {AADDV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
76 {AAND, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
77 {ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
78 {ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
79 {AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
80 {ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
81 {ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
82 {ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
83 {ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
84 {AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
85 {AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
86 {AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
87 {AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
88 {AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
89 {AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
90 {ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
91
92 {AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
93 {AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
94 {AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0},
95 {AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0},
96 {AVANDV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
97 {AVANDV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
98 {AXVANDV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
99 {AXVANDV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
100 {AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
101 {AVANDB, C_U8CON, C_NONE, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
102 {AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
103 {AXVANDB, C_U8CON, C_NONE, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
104
105 {AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
106 {AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
107 {AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
108 {AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
109
110 {AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
111 {AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
112 {AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
113 {AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
114 {AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
115 {AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
116 {AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
117 {AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
118
119 {AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
120 {AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
121 {AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
122 {AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
123 {AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
124 {AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
125 {AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
126 {AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
127
128 {AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
129 {AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
130 {AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
131 {AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
132 {AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
133 {AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
134 {AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
135 {AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
136
137 {AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
138 {AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
139 {AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
140 {AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
141 {AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
142 {AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
143 {AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
144 {AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
145
146 {ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
147 {AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
148 {AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
149 {AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
150 {AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
151 {AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0},
152 {AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0},
153 {AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
154 {AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
155
156 {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
157 {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
158 {AVSHUFB, C_VREG, C_VREG, C_VREG, C_VREG, C_NONE, 37, 4, 0, 0},
159 {AXVSHUFB, C_XREG, C_XREG, C_XREG, C_XREG, C_NONE, 37, 4, 0, 0},
160
161 {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
162 {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
163
164 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
165 {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
166 {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
167 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
168 {AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
169 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
170 {AMOVWU, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
171 {AMOVV, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
172 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
173 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
174 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
175 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
176 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
177 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
178
179 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
180 {AMOVWU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
181 {AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
182 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
183 {AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
184 {AMOVW, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
185 {AMOVWU, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
186 {AMOVV, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
187 {AMOVB, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
188 {AMOVBU, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
189 {AVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
190 {AXVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
191 {AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
192 {AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
193
194 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
195 {AMOVWU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
196 {AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
197 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
198 {AMOVBU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
199 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
200 {AMOVWU, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
201 {AMOVV, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
202 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
203 {AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
204 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
205 {AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
206 {AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
207 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
208 {AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
209 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
210 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
211 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
212 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
213 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
214 {AMOVWP, C_REG, C_NONE, C_NONE, C_SOREG_16, C_NONE, 73, 4, 0, 0},
215 {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 73, 12, 0, 0},
216 {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG_64, C_NONE, 73, 24, 0, 0},
217
218 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
219 {AMOVWU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
220 {AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
221 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
222 {AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
223 {AMOVW, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
224 {AMOVWU, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
225 {AMOVV, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
226 {AMOVB, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
227 {AMOVBU, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
228 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
229 {AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
230 {AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
231 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
232 {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
233 {AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
234 {AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
235 {AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
236 {AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
237 {AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
238 {AMOVWP, C_SOREG_16, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0},
239 {AMOVWP, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 74, 12, 0, 0},
240 {AMOVWP, C_LOREG_64, C_NONE, C_NONE, C_REG, C_NONE, 74, 24, 0, 0},
241
242 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
243 {AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
244 {AMOVW, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
245 {AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
246
247 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
248 {AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
249 {AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
250 {AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
251
252 {AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
253 {AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
254 {AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
255 {AMOVV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
256 {AMOVV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 67, 4, 0, NOTUSETMP},
257 {AMOVV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 68, 8, 0, NOTUSETMP},
258 {AMOVV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 69, 12, 0, NOTUSETMP},
259 {AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
260
261 {AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
262 {AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
263 {AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
264 {AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
265
266 {AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
267 {AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
268 {AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
269 {AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
270
271 {AADDV16, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
272 {AADDV16, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
273
274 {AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
275 {AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
276 {AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
277 {AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
278
279 {AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
280 {AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
281 {AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
282 {AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
283 {AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
284 {AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
285
286 {AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
287 {AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
288 {AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
289 {AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
290 {AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
291 {AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
292
293 {AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
294 {AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
295 {AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
296 {AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
297 {AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
298 {AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
299 {AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
300 {AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
301 {AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
302 {AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
303 {AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
304 {AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
305 {AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
306 {AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
307 {AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
308 {AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
309
310 {ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
311 {ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
312
313 {ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
314 {ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
315
316 {ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0},
317 {ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
318 {ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
319
320 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
321 {ASYSCALL, C_U15CON, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
322
323 {ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
324 {ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
325 {ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
326 {ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
327 {ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
328
329 {AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
330 {AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
331
332 {AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0},
333 {AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0},
334
335 {AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
336 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
337 {AMOVF, C_SOREG_12, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
338 {AMOVD, C_SOREG_12, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
339
340 {AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
341 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
342 {AMOVF, C_LOREG_32, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
343 {AMOVD, C_LOREG_32, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
344 {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
345 {AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
346
347 {AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
348 {AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
349 {AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 29, 4, REGZERO, 0},
350 {AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 29, 4, REGZERO, 0},
351
352 {AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
353 {AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
354 {AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 29, 12, REGZERO, 0},
355 {AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 29, 12, REGZERO, 0},
356 {AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
357 {AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
358
359 {AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
360 {AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
361 {AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
362 {AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
363 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
364 {AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
365 {AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
366 {AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0},
367 {AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
368 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
369
370 {AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0},
371
372 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
373 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
374 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
375 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
376 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
377
378 {AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
379 {AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
380 {AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
381 {AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
382 {AMOVWU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
383
384 {AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0},
385 {AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0},
386
387 {AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0},
388
389 {ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
390 {ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
391
392 {ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0},
393 {AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0},
394 {ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
395
396
397 {AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
398 {AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
399 {AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
400 {AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
401 {AMOVD, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
402 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
403 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
404
405
406 {AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
407 {AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
408 {AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
409 {AMOVWU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
410 {AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
411 {AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
412 {AMOVD, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
413 {AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0},
414 {AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0},
415
416 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
417 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
418 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
419 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
420
421 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 43, 4, 0, 0},
422 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 44, 4, 0, 0},
423
424 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
425 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
426 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0},
427
428 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
429
430 {AVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
431 {AXVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
432
433 {APRELD, C_SOREG_12, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
434 {APRELDX, C_SOREG_16, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
435
436 {AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
437
438 {obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
439 {obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
440 {obj.APCDATA, C_DCON, C_NONE, C_NONE, C_DCON, C_NONE, 0, 0, 0, 0},
441 {obj.AFUNCDATA, C_U12CON, C_NONE, C_NONE, C_ADDR, C_NONE, 0, 0, 0, 0},
442 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
443 {obj.ANOP, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
444 {obj.ANOP, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
445 {obj.ANOP, C_REG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
446 {obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
447 }
448
449 var atomicInst = map[obj.As]uint32{
450 AAMSWAPB: 0x070B8 << 15,
451 AAMSWAPH: 0x070B9 << 15,
452 AAMSWAPW: 0x070C0 << 15,
453 AAMSWAPV: 0x070C1 << 15,
454 AAMCASB: 0x070B0 << 15,
455 AAMCASH: 0x070B1 << 15,
456 AAMCASW: 0x070B2 << 15,
457 AAMCASV: 0x070B3 << 15,
458 AAMADDW: 0x070C2 << 15,
459 AAMADDV: 0x070C3 << 15,
460 AAMANDW: 0x070C4 << 15,
461 AAMANDV: 0x070C5 << 15,
462 AAMORW: 0x070C6 << 15,
463 AAMORV: 0x070C7 << 15,
464 AAMXORW: 0x070C8 << 15,
465 AAMXORV: 0x070C9 << 15,
466 AAMMAXW: 0x070CA << 15,
467 AAMMAXV: 0x070CB << 15,
468 AAMMINW: 0x070CC << 15,
469 AAMMINV: 0x070CD << 15,
470 AAMMAXWU: 0x070CE << 15,
471 AAMMAXVU: 0x070CF << 15,
472 AAMMINWU: 0x070D0 << 15,
473 AAMMINVU: 0x070D1 << 15,
474 AAMSWAPDBB: 0x070BC << 15,
475 AAMSWAPDBH: 0x070BD << 15,
476 AAMSWAPDBW: 0x070D2 << 15,
477 AAMSWAPDBV: 0x070D3 << 15,
478 AAMCASDBB: 0x070B4 << 15,
479 AAMCASDBH: 0x070B5 << 15,
480 AAMCASDBW: 0x070B6 << 15,
481 AAMCASDBV: 0x070B7 << 15,
482 AAMADDDBW: 0x070D4 << 15,
483 AAMADDDBV: 0x070D5 << 15,
484 AAMANDDBW: 0x070D6 << 15,
485 AAMANDDBV: 0x070D7 << 15,
486 AAMORDBW: 0x070D8 << 15,
487 AAMORDBV: 0x070D9 << 15,
488 AAMXORDBW: 0x070DA << 15,
489 AAMXORDBV: 0x070DB << 15,
490 AAMMAXDBW: 0x070DC << 15,
491 AAMMAXDBV: 0x070DD << 15,
492 AAMMINDBW: 0x070DE << 15,
493 AAMMINDBV: 0x070DF << 15,
494 AAMMAXDBWU: 0x070E0 << 15,
495 AAMMAXDBVU: 0x070E1 << 15,
496 AAMMINDBWU: 0x070E2 << 15,
497 AAMMINDBVU: 0x070E3 << 15,
498 }
499
500 func IsAtomicInst(as obj.As) bool {
501 _, ok := atomicInst[as]
502
503 return ok
504 }
505
506
507
508 func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int {
509 if !((alignedValue&(alignedValue-1) == 0) && 8 <= alignedValue && alignedValue <= 2048) {
510 ctxt.Diag("alignment value of an instruction must be a power of two and in the range [8, 2048], got %d\n", alignedValue)
511 }
512 return int(-pc & (alignedValue - 1))
513 }
514
515 var oprange [ALAST & obj.AMask][]Optab
516
517 var xcmp [C_NCLASS][C_NCLASS]bool
518
519 func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
520 if ctxt.Retpoline {
521 ctxt.Diag("-spectre=ret not supported on loong64")
522 ctxt.Retpoline = false
523 }
524
525 p := cursym.Func().Text
526 if p == nil || p.Link == nil {
527 return
528 }
529
530 c := ctxt0{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset + ctxt.Arch.FixedFrameSize)}
531
532 if oprange[AOR&obj.AMask] == nil {
533 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
534 }
535
536 pc := int64(0)
537 p.Pc = pc
538
539 var m int
540 var o *Optab
541 for p = p.Link; p != nil; p = p.Link {
542 p.Pc = pc
543 o = c.oplook(p)
544 m = int(o.size)
545 if m == 0 {
546 switch p.As {
547 case obj.APCALIGN:
548 alignedValue := p.From.Offset
549 m = pcAlignPadLength(ctxt, pc, alignedValue)
550
551 if int32(alignedValue) > cursym.Func().Align {
552 cursym.Func().Align = int32(alignedValue)
553 }
554 break
555 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
556 continue
557 default:
558 c.ctxt.Diag("zero-width instruction\n%v", p)
559 }
560 }
561
562 pc += int64(m)
563 }
564
565 c.cursym.Size = pc
566
567
568
569 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
570 if q := p.To.Target(); q != nil && q.Pc < p.Pc {
571 q.Mark |= branchLoopHead
572 }
573 }
574
575
576 for {
577 rescan := false
578 pc = 0
579 prev := c.cursym.Func().Text
580 for p = prev.Link; p != nil; prev, p = p, p.Link {
581 p.Pc = pc
582 o = c.oplook(p)
583
584
585
586
587
588
589
590 if p.Mark&branchLoopHead != 0 && pc&(loopAlign-1) != 0 &&
591 !(prev.As == obj.APCALIGN && prev.From.Offset >= loopAlign) {
592 q := c.newprog()
593 prev.Link = q
594 q.Link = p
595 q.Pc = pc
596 q.As = obj.APCALIGN
597 q.From.Type = obj.TYPE_CONST
598 q.From.Offset = loopAlign
599
600
601
602
603
604
605
606 pc += int64(pcAlignPadLength(ctxt, pc, loopAlign))
607 p.Pc = pc
608 rescan = true
609 }
610
611
612
613
614
615 if o.type_ == 6 && p.To.Target() != nil {
616 otxt := p.To.Target().Pc - pc
617
618
619
620
621
622 bound := int64(1 << (18 - 1))
623
624 switch p.As {
625 case ABFPT, ABFPF:
626 bound = int64(1 << (23 - 1))
627 }
628
629 if otxt < -bound || otxt >= bound {
630 q := c.newprog()
631 q.Link = p.Link
632 p.Link = q
633 q.As = AJMP
634 q.Pos = p.Pos
635 q.To.Type = obj.TYPE_BRANCH
636 q.To.SetTarget(p.To.Target())
637 p.To.SetTarget(q)
638 q = c.newprog()
639 q.Link = p.Link
640 p.Link = q
641 q.As = AJMP
642 q.Pos = p.Pos
643 q.To.Type = obj.TYPE_BRANCH
644 q.To.SetTarget(q.Link.Link)
645 rescan = true
646 }
647 }
648
649 m = int(o.size)
650 if m == 0 {
651 switch p.As {
652 case obj.APCALIGN:
653 alignedValue := p.From.Offset
654 m = pcAlignPadLength(ctxt, pc, alignedValue)
655 break
656 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
657 continue
658 default:
659 c.ctxt.Diag("zero-width instruction\n%v", p)
660 }
661 }
662
663 pc += int64(m)
664 }
665
666 c.cursym.Size = pc
667
668 if !rescan {
669 break
670 }
671 }
672
673 pc += -pc & (FuncAlign - 1)
674 c.cursym.Size = pc
675
676
677
678 c.cursym.Grow(c.cursym.Size)
679
680 bp := c.cursym.P
681 var i int32
682 var out [6]uint32
683 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
684 c.pc = p.Pc
685 o = c.oplook(p)
686 if int(o.size) > 4*len(out) {
687 log.Fatalf("out array in span0 is too small, need at least %d for %v", o.size/4, p)
688 }
689 if p.As == obj.APCALIGN {
690 alignedValue := p.From.Offset
691 v := pcAlignPadLength(c.ctxt, p.Pc, alignedValue)
692 for i = 0; i < int32(v/4); i++ {
693
694 c.ctxt.Arch.ByteOrder.PutUint32(bp, OP_12IRR(c.opirr(AAND), 0, 0, 0))
695 bp = bp[4:]
696 }
697 continue
698 }
699 c.asmout(p, o, out[:])
700 for i = 0; i < int32(o.size/4); i++ {
701 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
702 bp = bp[4:]
703 }
704 }
705
706
707
708
709
710 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, c.isRestartable)
711
712
713 for _, jt := range cursym.Func().JumpTables {
714 for i, p := range jt.Targets {
715
716
717 jt.Sym.WriteAddr(ctxt, int64(i)*8, 8, cursym, p.Pc)
718 }
719 }
720 }
721
722
723 func (c *ctxt0) isUnsafePoint(p *obj.Prog) bool {
724
725
726 return p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP
727 }
728
729
730
731 func (c *ctxt0) isRestartable(p *obj.Prog) bool {
732 if c.isUnsafePoint(p) {
733 return false
734 }
735
736
737
738
739
740
741
742 o := c.oplook(p)
743 return o.size > 4 && o.flag&NOTUSETMP == 0
744 }
745
746 func isint32(v int64) bool {
747 return int64(int32(v)) == v
748 }
749
750 func (c *ctxt0) aclass(a *obj.Addr) int {
751 switch a.Type {
752 case obj.TYPE_NONE:
753 return C_NONE
754
755 case obj.TYPE_REG:
756 return c.rclass(a.Reg)
757
758 case obj.TYPE_MEM:
759 switch a.Name {
760 case obj.NAME_EXTERN,
761 obj.NAME_STATIC:
762 if a.Sym == nil {
763 break
764 }
765 c.instoffset = a.Offset
766 if a.Sym.Type == objabi.STLSBSS {
767 if c.ctxt.Flag_shared {
768 return C_TLS_IE
769 } else {
770 return C_TLS_LE
771 }
772 }
773 return C_ADDR
774
775 case obj.NAME_AUTO:
776 if a.Reg == REGSP {
777
778
779 a.Reg = obj.REG_NONE
780 }
781 c.instoffset = int64(c.autosize) + a.Offset
782 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
783 return C_SAUTO
784 }
785 return C_LAUTO
786
787 case obj.NAME_PARAM:
788 if a.Reg == REGSP {
789
790
791 a.Reg = obj.REG_NONE
792 }
793 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
794 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
795 return C_SAUTO
796 }
797 return C_LAUTO
798
799 case obj.NAME_NONE:
800 if a.Index != 0 {
801 if a.Offset != 0 {
802 return C_GOK
803 }
804
805 return C_ROFF
806 }
807
808 c.instoffset = a.Offset
809 if c.instoffset == 0 {
810 return C_ZOREG
811 }
812 if c.instoffset >= -BIG_8 && c.instoffset < BIG_8 {
813 return C_SOREG_8
814 } else if c.instoffset >= -BIG_9 && c.instoffset < BIG_9 {
815 return C_SOREG_9
816 } else if c.instoffset >= -BIG_10 && c.instoffset < BIG_10 {
817 return C_SOREG_10
818 } else if c.instoffset >= -BIG_11 && c.instoffset < BIG_11 {
819 return C_SOREG_11
820 } else if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
821 return C_SOREG_12
822 } else if c.instoffset >= -BIG_16 && c.instoffset < BIG_16 {
823 return C_SOREG_16
824 } else if c.instoffset >= -BIG_32 && c.instoffset < BIG_32 {
825 return C_LOREG_32
826 } else {
827 return C_LOREG_64
828 }
829
830 case obj.NAME_GOTREF:
831 return C_GOTADDR
832 }
833
834 return C_GOK
835
836 case obj.TYPE_TEXTSIZE:
837 return C_TEXTSIZE
838
839 case obj.TYPE_CONST,
840 obj.TYPE_ADDR:
841 switch a.Name {
842 case obj.NAME_NONE:
843 c.instoffset = a.Offset
844 if a.Reg != 0 {
845 if -BIG_12 <= c.instoffset && c.instoffset <= BIG_12 {
846 return C_SACON
847 }
848 if isint32(c.instoffset) {
849 return C_LACON
850 }
851 return C_DACON
852 }
853
854 case obj.NAME_EXTERN,
855 obj.NAME_STATIC:
856 s := a.Sym
857 if s == nil {
858 return C_GOK
859 }
860
861 c.instoffset = a.Offset
862 if s.Type == objabi.STLSBSS {
863 c.ctxt.Diag("taking address of TLS variable is not supported")
864 }
865 return C_EXTADDR
866
867 case obj.NAME_AUTO:
868 if a.Reg == REGSP {
869
870
871 a.Reg = obj.REG_NONE
872 }
873 c.instoffset = int64(c.autosize) + a.Offset
874 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
875 return C_SACON
876 }
877 return C_LACON
878
879 case obj.NAME_PARAM:
880 if a.Reg == REGSP {
881
882
883 a.Reg = obj.REG_NONE
884 }
885 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
886 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
887 return C_SACON
888 }
889 return C_LACON
890
891 default:
892 return C_GOK
893 }
894
895 if c.instoffset != int64(int32(c.instoffset)) {
896 return dconClass(c.instoffset)
897 }
898
899 if c.instoffset >= 0 {
900 sbits := bits.Len64(uint64(c.instoffset))
901 switch {
902 case sbits <= 8:
903 return C_ZCON + sbits
904 case sbits <= 12:
905 if c.instoffset <= 0x7ff {
906 return C_US12CON
907 }
908 return C_U12CON
909 case sbits <= 13:
910 if c.instoffset&0xfff == 0 {
911 return C_U13CON20_0
912 }
913 return C_U13CON
914 case sbits <= 15:
915 if c.instoffset&0xfff == 0 {
916 return C_U15CON20_0
917 }
918 return C_U15CON
919 }
920 } else {
921 sbits := bits.Len64(uint64(^c.instoffset))
922 switch {
923 case sbits < 5:
924 return C_S5CON
925 case sbits < 12:
926 return C_S12CON
927 case sbits < 13:
928 if c.instoffset&0xfff == 0 {
929 return C_S13CON20_0
930 }
931 return C_S13CON
932 }
933 }
934
935 if c.instoffset&0xfff == 0 {
936 return C_32CON20_0
937 }
938 return C_32CON
939
940 case obj.TYPE_BRANCH:
941 return C_BRAN
942 }
943
944 return C_GOK
945 }
946
947
948
949
950
951
952
953 const (
954 ALL1 = iota
955 ALL0
956 ST1
957 ST0
958 )
959
960
961
962 func mask(suf int8, len int8) (uint64, uint64) {
963 if len == 12 {
964 if suf == 0 {
965 return 0xfff, 0x800
966 } else {
967 return 0xfff0000000000000, 0x8000000000000000
968 }
969 } else {
970 if suf == 12 {
971 return 0xfffff000, 0x80000000
972 } else {
973 return 0xfffff00000000, 0x8000000000000
974 }
975 }
976 }
977
978
979
980
981
982 func bitField(val int64, suf int8, len int8) int8 {
983 mask1, mask2 := mask(suf, len)
984 if uint64(val)&mask1 == mask1 {
985 return ALL1
986 } else if uint64(val)&mask1 == 0x0 {
987 return ALL0
988 } else if uint64(val)&mask2 == mask2 {
989 return ST1
990 } else {
991 return ST0
992 }
993 }
994
995
996
997
998
999
1000
1001
1002
1003 func dconClass(offset int64) int {
1004 tzb := bits.TrailingZeros64(uint64(offset))
1005 hi12 := bitField(offset, 52, 12)
1006 hi20 := bitField(offset, 32, 20)
1007 lo20 := bitField(offset, 12, 20)
1008 lo12 := bitField(offset, 0, 12)
1009 if tzb >= 52 {
1010 return C_DCON12_0
1011 }
1012 if tzb >= 32 {
1013 if ((hi20 == ALL1 || hi20 == ST1) && hi12 == ALL1) || ((hi20 == ALL0 || hi20 == ST0) && hi12 == ALL0) {
1014 return C_DCON20S_0
1015 }
1016 return C_DCON32_0
1017 }
1018 if tzb >= 12 {
1019 if lo20 == ST1 || lo20 == ALL1 {
1020 if hi20 == ALL1 {
1021 return C_DCON12_20S
1022 }
1023 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1024 return C_DCON20S_20
1025 }
1026 return C_DCON32_20
1027 }
1028 if hi20 == ALL0 {
1029 return C_DCON12_20S
1030 }
1031 if (hi20 == ST0 && hi12 == ALL0) || ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) {
1032 return C_DCON20S_20
1033 }
1034 return C_DCON32_20
1035 }
1036 if lo12 == ST1 || lo12 == ALL1 {
1037 if lo20 == ALL1 {
1038 if hi20 == ALL1 {
1039 return C_DCON12_12S
1040 }
1041 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1042 return C_DCON20S_12S
1043 }
1044 return C_DCON32_12S
1045 }
1046 if lo20 == ST1 {
1047 if hi20 == ALL1 {
1048
1049 return C_DCON12_32S
1050 }
1051 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1052 return C_DCON20S_32
1053 }
1054 return C_DCON
1055 }
1056 if lo20 == ALL0 {
1057 if hi20 == ALL0 {
1058 return C_DCON12_12U
1059 }
1060 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1061 return C_DCON20S_12U
1062 }
1063 return C_DCON32_12U
1064 }
1065 if hi20 == ALL0 {
1066 return C_DCON12_32S
1067 }
1068 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1069 return C_DCON20S_32
1070 }
1071 return C_DCON
1072 }
1073 if lo20 == ALL0 {
1074 if hi20 == ALL0 {
1075 return C_DCON12_12U
1076 }
1077 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1078 return C_DCON20S_12U
1079 }
1080 return C_DCON32_12U
1081 }
1082 if lo20 == ST1 || lo20 == ALL1 {
1083 if hi20 == ALL1 {
1084 return C_DCON12_32S
1085 }
1086 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1087 return C_DCON20S_32
1088 }
1089 return C_DCON
1090 }
1091 if hi20 == ALL0 {
1092 return C_DCON12_32S
1093 }
1094 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1095 return C_DCON20S_32
1096 }
1097 return C_DCON
1098 }
1099
1100
1101
1102 func (c *ctxt0) rclass(r int16) int {
1103 switch {
1104 case REG_R0 <= r && r <= REG_R31:
1105 return C_REG
1106 case REG_F0 <= r && r <= REG_F31:
1107 return C_FREG
1108 case REG_FCC0 <= r && r <= REG_FCC7:
1109 return C_FCCREG
1110 case REG_FCSR0 <= r && r <= REG_FCSR3:
1111 return C_FCSRREG
1112 case REG_V0 <= r && r <= REG_V31:
1113 return C_VREG
1114 case REG_X0 <= r && r <= REG_X31:
1115 return C_XREG
1116 case r >= REG_ARNG && r < REG_ELEM:
1117 return C_ARNG
1118 case r >= REG_ELEM && r < REG_ELEM_END:
1119 return C_ELEM
1120 }
1121
1122 return C_GOK
1123 }
1124
1125 func oclass(a *obj.Addr) int {
1126 return int(a.Class) - 1
1127 }
1128
1129 func prasm(p *obj.Prog) {
1130 fmt.Printf("%v\n", p)
1131 }
1132
1133 func (c *ctxt0) oplook(p *obj.Prog) *Optab {
1134 if oprange[AOR&obj.AMask] == nil {
1135 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
1136 }
1137
1138 restArgsIndex := 0
1139 restArgsLen := len(p.RestArgs)
1140 if restArgsLen > 2 {
1141 c.ctxt.Diag("too many RestArgs: got %v, maximum is 2\n", restArgsLen)
1142 return nil
1143 }
1144
1145 restArgsv := [2]int{C_NONE + 1, C_NONE + 1}
1146 for i, ap := range p.RestArgs {
1147 restArgsv[i] = int(ap.Addr.Class)
1148 if restArgsv[i] == 0 {
1149 restArgsv[i] = c.aclass(&ap.Addr) + 1
1150 ap.Addr.Class = int8(restArgsv[i])
1151 }
1152 }
1153
1154 a1 := int(p.Optab)
1155 if a1 != 0 {
1156 return &optab[a1-1]
1157 }
1158
1159
1160 a1 = int(p.From.Class)
1161 if a1 == 0 {
1162 a1 = c.aclass(&p.From) + 1
1163 p.From.Class = int8(a1)
1164 }
1165 a1--
1166
1167
1168 a4 := int(p.To.Class)
1169 if a4 == 0 {
1170 a4 = c.aclass(&p.To) + 1
1171 p.To.Class = int8(a4)
1172 }
1173 a4--
1174
1175
1176 a2 := C_NONE
1177 if p.Reg != 0 {
1178 a2 = c.rclass(p.Reg)
1179 } else if restArgsLen > 0 {
1180 a2 = restArgsv[restArgsIndex] - 1
1181 restArgsIndex++
1182 }
1183
1184
1185 a5 := C_NONE
1186 if p.RegTo2 != 0 {
1187 a5 = C_REG
1188 }
1189
1190
1191 a3 := C_NONE
1192 if restArgsLen > 0 && restArgsIndex < restArgsLen {
1193 a3 = restArgsv[restArgsIndex] - 1
1194 restArgsIndex++
1195 }
1196
1197 ops := oprange[p.As&obj.AMask]
1198 c1 := &xcmp[a1]
1199 c2 := &xcmp[a2]
1200 c3 := &xcmp[a3]
1201 c4 := &xcmp[a4]
1202 c5 := &xcmp[a5]
1203 for i := range ops {
1204 op := &ops[i]
1205 if c1[op.from1] && c2[op.reg] && c3[op.from3] && c4[op.to1] && c5[op.to2] {
1206 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1207 return op
1208 }
1209 }
1210
1211 c.ctxt.Diag("illegal combination %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5))
1212 prasm(p)
1213
1214 return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}
1215 }
1216
1217 func cmp(a int, b int) bool {
1218 if a == b {
1219 return true
1220 }
1221 switch a {
1222 case C_DCON:
1223 return cmp(C_32CON, b) || cmp(C_DCON12_20S, b) || cmp(C_DCON32_12S, b) || b == C_DCON12_0
1224 case C_32CON:
1225 return cmp(C_32CON20_0, b) || cmp(C_U15CON, b) || cmp(C_13CON, b) || cmp(C_12CON, b)
1226 case C_32CON20_0:
1227 return b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_S13CON20_0 || b == C_ZCON
1228 case C_U15CON:
1229 return cmp(C_U12CON, b) || b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_U13CON
1230 case C_13CON:
1231 return cmp(C_U13CON, b) || cmp(C_S13CON, b)
1232 case C_U13CON:
1233 return cmp(C_12CON, b) || b == C_U13CON20_0
1234 case C_S13CON:
1235 return cmp(C_12CON, b) || b == C_S13CON20_0
1236 case C_12CON:
1237 return cmp(C_U12CON, b) || cmp(C_S12CON, b)
1238 case C_UU12CON:
1239 return cmp(C_U12CON, b)
1240 case C_U12CON:
1241 return cmp(C_U8CON, b) || b == C_US12CON
1242 case C_U8CON:
1243 return cmp(C_U7CON, b)
1244 case C_U7CON:
1245 return cmp(C_U6CON, b)
1246 case C_U6CON:
1247 return cmp(C_U5CON, b)
1248 case C_U5CON:
1249 return cmp(C_U4CON, b)
1250 case C_U4CON:
1251 return cmp(C_U3CON, b)
1252 case C_U3CON:
1253 return cmp(C_U2CON, b)
1254 case C_U2CON:
1255 return cmp(C_U1CON, b)
1256 case C_U1CON:
1257 return cmp(C_ZCON, b)
1258 case C_US12CON:
1259 return cmp(C_S12CON, b)
1260 case C_S12CON:
1261 return cmp(C_S5CON, b) || cmp(C_U8CON, b) || b == C_US12CON
1262 case C_S5CON:
1263 return cmp(C_ZCON, b) || cmp(C_U4CON, b)
1264
1265 case C_DCON12_20S:
1266 if b == C_DCON20S_20 || b == C_DCON12_12S ||
1267 b == C_DCON20S_12S || b == C_DCON12_12U ||
1268 b == C_DCON20S_12U || b == C_DCON20S_0 {
1269 return true
1270 }
1271
1272 case C_DCON32_12S:
1273 if b == C_DCON32_20 || b == C_DCON12_32S ||
1274 b == C_DCON20S_32 || b == C_DCON32_12U ||
1275 b == C_DCON32_0 {
1276 return true
1277 }
1278
1279 case C_LACON:
1280 return b == C_SACON
1281
1282 case C_LAUTO:
1283 return b == C_SAUTO
1284
1285 case C_REG:
1286 return b == C_ZCON
1287
1288 case C_LOREG_64:
1289 if b == C_ZOREG || b == C_SOREG_8 ||
1290 b == C_SOREG_9 || b == C_SOREG_10 ||
1291 b == C_SOREG_11 || b == C_SOREG_12 ||
1292 b == C_SOREG_16 || b == C_LOREG_32 {
1293 return true
1294 }
1295
1296 case C_LOREG_32:
1297 return cmp(C_SOREG_16, b)
1298
1299 case C_SOREG_16:
1300 return cmp(C_SOREG_12, b)
1301
1302 case C_SOREG_12:
1303 return cmp(C_SOREG_11, b)
1304
1305 case C_SOREG_11:
1306 return cmp(C_SOREG_10, b)
1307
1308 case C_SOREG_10:
1309 return cmp(C_SOREG_9, b)
1310
1311 case C_SOREG_9:
1312 return cmp(C_SOREG_8, b)
1313
1314 case C_SOREG_8:
1315 return b == C_ZOREG
1316 }
1317
1318 return false
1319 }
1320
1321 func ocmp(p1, p2 Optab) int {
1322 if p1.as != p2.as {
1323 return int(p1.as) - int(p2.as)
1324 }
1325 if p1.from1 != p2.from1 {
1326 return int(p1.from1) - int(p2.from1)
1327 }
1328 if p1.reg != p2.reg {
1329 return int(p1.reg) - int(p2.reg)
1330 }
1331 if p1.to1 != p2.to1 {
1332 return int(p1.to1) - int(p2.to1)
1333 }
1334 return 0
1335 }
1336
1337 func opset(a, b0 obj.As) {
1338 oprange[a&obj.AMask] = oprange[b0]
1339 }
1340
1341 func buildop(ctxt *obj.Link) {
1342 if ctxt.DiagFunc == nil {
1343 ctxt.DiagFunc = func(format string, args ...interface{}) {
1344 log.Printf(format, args...)
1345 }
1346 }
1347
1348 if oprange[AOR&obj.AMask] != nil {
1349
1350
1351
1352 return
1353 }
1354
1355 for i := range C_NCLASS {
1356 for j := range C_NCLASS {
1357 if cmp(j, i) {
1358 xcmp[i][j] = true
1359 }
1360 }
1361 }
1362
1363 slices.SortFunc(optab, ocmp)
1364 for i := 0; i < len(optab); i++ {
1365 as, start := optab[i].as, i
1366 for ; i < len(optab)-1; i++ {
1367 if optab[i+1].as != as {
1368 break
1369 }
1370 }
1371 r0 := as & obj.AMask
1372 oprange[r0] = optab[start : i+1]
1373 switch as {
1374 default:
1375 ctxt.Diag("unknown op in build: %v", as)
1376 ctxt.DiagFlush()
1377 log.Fatalf("bad code")
1378
1379 case AABSF:
1380 opset(AMOVFD, r0)
1381 opset(AMOVDF, r0)
1382 opset(AMOVWF, r0)
1383 opset(AMOVFW, r0)
1384 opset(AMOVWD, r0)
1385 opset(AMOVDW, r0)
1386 opset(ANEGF, r0)
1387 opset(ANEGD, r0)
1388 opset(AABSD, r0)
1389 opset(ATRUNCDW, r0)
1390 opset(ATRUNCFW, r0)
1391 opset(ASQRTF, r0)
1392 opset(ASQRTD, r0)
1393 opset(AFCLASSF, r0)
1394 opset(AFCLASSD, r0)
1395 opset(AFLOGBF, r0)
1396 opset(AFLOGBD, r0)
1397
1398 case AMOVVF:
1399 opset(AMOVVD, r0)
1400 opset(AMOVFV, r0)
1401 opset(AMOVDV, r0)
1402 opset(ATRUNCDV, r0)
1403 opset(ATRUNCFV, r0)
1404 opset(AFFINTFW, r0)
1405 opset(AFFINTFV, r0)
1406 opset(AFFINTDW, r0)
1407 opset(AFFINTDV, r0)
1408 opset(AFTINTWF, r0)
1409 opset(AFTINTWD, r0)
1410 opset(AFTINTVF, r0)
1411 opset(AFTINTVD, r0)
1412 opset(AFTINTRPWF, r0)
1413 opset(AFTINTRPWD, r0)
1414 opset(AFTINTRPVF, r0)
1415 opset(AFTINTRPVD, r0)
1416 opset(AFTINTRMWF, r0)
1417 opset(AFTINTRMWD, r0)
1418 opset(AFTINTRMVF, r0)
1419 opset(AFTINTRMVD, r0)
1420 opset(AFTINTRZWF, r0)
1421 opset(AFTINTRZWD, r0)
1422 opset(AFTINTRZVF, r0)
1423 opset(AFTINTRZVD, r0)
1424 opset(AFTINTRNEWF, r0)
1425 opset(AFTINTRNEWD, r0)
1426 opset(AFTINTRNEVF, r0)
1427 opset(AFTINTRNEVD, r0)
1428
1429 case AADD:
1430 opset(ASGT, r0)
1431 opset(ASGTU, r0)
1432 opset(AADDU, r0)
1433
1434 case AADDV:
1435 opset(AADDVU, r0)
1436
1437 case AADDF:
1438 opset(ADIVF, r0)
1439 opset(ADIVD, r0)
1440 opset(AMULF, r0)
1441 opset(AMULD, r0)
1442 opset(ASUBF, r0)
1443 opset(ASUBD, r0)
1444 opset(AADDD, r0)
1445 opset(AFMINF, r0)
1446 opset(AFMIND, r0)
1447 opset(AFMAXF, r0)
1448 opset(AFMAXD, r0)
1449 opset(AFCOPYSGF, r0)
1450 opset(AFCOPYSGD, r0)
1451 opset(AFSCALEBF, r0)
1452 opset(AFSCALEBD, r0)
1453 opset(AFMAXAF, r0)
1454 opset(AFMAXAD, r0)
1455 opset(AFMINAF, r0)
1456 opset(AFMINAD, r0)
1457
1458 case AFMADDF:
1459 opset(AFMADDD, r0)
1460 opset(AFMSUBF, r0)
1461 opset(AFMSUBD, r0)
1462 opset(AFNMADDF, r0)
1463 opset(AFNMADDD, r0)
1464 opset(AFNMSUBF, r0)
1465 opset(AFNMSUBD, r0)
1466
1467 case AAND:
1468 opset(AOR, r0)
1469 opset(AXOR, r0)
1470 opset(AORN, r0)
1471 opset(AANDN, r0)
1472
1473 case ABEQ:
1474 opset(ABNE, r0)
1475 opset(ABLT, r0)
1476 opset(ABGE, r0)
1477 opset(ABGEU, r0)
1478 opset(ABLTU, r0)
1479
1480 case ABLEZ:
1481 opset(ABGEZ, r0)
1482 opset(ABLTZ, r0)
1483 opset(ABGTZ, r0)
1484
1485 case AMOVB:
1486 opset(AMOVH, r0)
1487
1488 case AMOVBU:
1489 opset(AMOVHU, r0)
1490
1491 case AMOVWP:
1492 opset(AMOVVP, r0)
1493 opset(ASC, r0)
1494 opset(ASCV, r0)
1495 opset(ALL, r0)
1496 opset(ALLV, r0)
1497
1498 case AMUL:
1499 opset(AMULU, r0)
1500 opset(AMULH, r0)
1501 opset(AMULHU, r0)
1502 opset(AREM, r0)
1503 opset(AREMU, r0)
1504 opset(ADIV, r0)
1505 opset(ADIVU, r0)
1506
1507 case AMULV:
1508 opset(AMULVU, r0)
1509 opset(AMULHV, r0)
1510 opset(AMULHVU, r0)
1511 opset(AREMV, r0)
1512 opset(AREMVU, r0)
1513 opset(ADIVV, r0)
1514 opset(ADIVVU, r0)
1515
1516 case ASLL:
1517 opset(ASRL, r0)
1518 opset(ASRA, r0)
1519 opset(AROTR, r0)
1520
1521 case ASLLV:
1522 opset(ASRAV, r0)
1523 opset(ASRLV, r0)
1524 opset(AROTRV, r0)
1525
1526 case ABSTRPICKW:
1527 opset(ABSTRPICKV, r0)
1528 opset(ABSTRINSW, r0)
1529 opset(ABSTRINSV, r0)
1530
1531 case ASUB:
1532 opset(ASUBU, r0)
1533 opset(ANOR, r0)
1534
1535 case ASUBV:
1536 opset(ASUBVU, r0)
1537
1538 case ASYSCALL:
1539 opset(ADBAR, r0)
1540 opset(ABREAK, r0)
1541
1542 case ACMPEQF:
1543 opset(ACMPGTF, r0)
1544 opset(ACMPGTD, r0)
1545 opset(ACMPGEF, r0)
1546 opset(ACMPGED, r0)
1547 opset(ACMPEQD, r0)
1548
1549 case ABFPT:
1550 opset(ABFPF, r0)
1551
1552 case AALSLV:
1553 opset(AALSLW, r0)
1554 opset(AALSLWU, r0)
1555
1556 case AMOVW,
1557 AMOVD,
1558 AMOVF,
1559 AMOVV,
1560 ARFE,
1561 AJAL,
1562 AJMP,
1563 AMOVWU,
1564 AVMOVQ,
1565 AXVMOVQ,
1566 AVSHUFB,
1567 AXVSHUFB,
1568 ANEGW,
1569 ANEGV,
1570 AWORD,
1571 APRELD,
1572 APRELDX,
1573 AFSEL,
1574 AADDV16,
1575 obj.ANOP,
1576 obj.ATEXT,
1577 obj.AFUNCDATA,
1578 obj.APCALIGN,
1579 obj.APCDATA:
1580 break
1581
1582 case ARDTIMELW:
1583 opset(ARDTIMEHW, r0)
1584 opset(ARDTIMED, r0)
1585
1586 case ACLOW:
1587 opset(ACLZW, r0)
1588 opset(ACTOW, r0)
1589 opset(ACTZW, r0)
1590 opset(ACLOV, r0)
1591 opset(ACLZV, r0)
1592 opset(ACTOV, r0)
1593 opset(ACTZV, r0)
1594 opset(AREVB2H, r0)
1595 opset(AREVB4H, r0)
1596 opset(AREVB2W, r0)
1597 opset(AREVBV, r0)
1598 opset(AREVH2W, r0)
1599 opset(AREVHV, r0)
1600 opset(ABITREV4B, r0)
1601 opset(ABITREV8B, r0)
1602 opset(ABITREVW, r0)
1603 opset(ABITREVV, r0)
1604 opset(AEXTWB, r0)
1605 opset(AEXTWH, r0)
1606 opset(ACPUCFG, r0)
1607
1608 case ATEQ:
1609 opset(ATNE, r0)
1610
1611 case AMASKEQZ:
1612 opset(AMASKNEZ, r0)
1613 opset(ACRCWBW, r0)
1614 opset(ACRCWHW, r0)
1615 opset(ACRCWWW, r0)
1616 opset(ACRCWVW, r0)
1617 opset(ACRCCWBW, r0)
1618 opset(ACRCCWHW, r0)
1619 opset(ACRCCWWW, r0)
1620 opset(ACRCCWVW, r0)
1621
1622 case ANOOP:
1623 opset(obj.AUNDEF, r0)
1624
1625 case AAMSWAPW:
1626 for i := range atomicInst {
1627 if i == AAMSWAPW {
1628 continue
1629 }
1630 opset(i, r0)
1631 }
1632
1633 case AVSEQB:
1634 opset(AVSEQH, r0)
1635 opset(AVSEQW, r0)
1636 opset(AVSEQV, r0)
1637 opset(AVILVLB, r0)
1638 opset(AVILVLH, r0)
1639 opset(AVILVLW, r0)
1640 opset(AVILVLV, r0)
1641 opset(AVILVHB, r0)
1642 opset(AVILVHH, r0)
1643 opset(AVILVHW, r0)
1644 opset(AVILVHV, r0)
1645 opset(AVMULB, r0)
1646 opset(AVMULH, r0)
1647 opset(AVMULW, r0)
1648 opset(AVMULV, r0)
1649 opset(AVMUHB, r0)
1650 opset(AVMUHH, r0)
1651 opset(AVMUHW, r0)
1652 opset(AVMUHV, r0)
1653 opset(AVMUHBU, r0)
1654 opset(AVMUHHU, r0)
1655 opset(AVMUHWU, r0)
1656 opset(AVMUHVU, r0)
1657 opset(AVDIVB, r0)
1658 opset(AVDIVH, r0)
1659 opset(AVDIVW, r0)
1660 opset(AVDIVV, r0)
1661 opset(AVMODB, r0)
1662 opset(AVMODH, r0)
1663 opset(AVMODW, r0)
1664 opset(AVMODV, r0)
1665 opset(AVDIVBU, r0)
1666 opset(AVDIVHU, r0)
1667 opset(AVDIVWU, r0)
1668 opset(AVDIVVU, r0)
1669 opset(AVMODBU, r0)
1670 opset(AVMODHU, r0)
1671 opset(AVMODWU, r0)
1672 opset(AVMODVU, r0)
1673 opset(AVMULWEVHB, r0)
1674 opset(AVMULWEVWH, r0)
1675 opset(AVMULWEVVW, r0)
1676 opset(AVMULWEVQV, r0)
1677 opset(AVMULWODHB, r0)
1678 opset(AVMULWODWH, r0)
1679 opset(AVMULWODVW, r0)
1680 opset(AVMULWODQV, r0)
1681 opset(AVMULWEVHBU, r0)
1682 opset(AVMULWEVWHU, r0)
1683 opset(AVMULWEVVWU, r0)
1684 opset(AVMULWEVQVU, r0)
1685 opset(AVMULWODHBU, r0)
1686 opset(AVMULWODWHU, r0)
1687 opset(AVMULWODVWU, r0)
1688 opset(AVMULWODQVU, r0)
1689 opset(AVMULWEVHBUB, r0)
1690 opset(AVMULWEVWHUH, r0)
1691 opset(AVMULWEVVWUW, r0)
1692 opset(AVMULWEVQVUV, r0)
1693 opset(AVMULWODHBUB, r0)
1694 opset(AVMULWODWHUH, r0)
1695 opset(AVMULWODVWUW, r0)
1696 opset(AVMULWODQVUV, r0)
1697 opset(AVADDF, r0)
1698 opset(AVADDD, r0)
1699 opset(AVSUBF, r0)
1700 opset(AVSUBD, r0)
1701 opset(AVMULF, r0)
1702 opset(AVMULD, r0)
1703 opset(AVDIVF, r0)
1704 opset(AVDIVD, r0)
1705 opset(AVSHUFH, r0)
1706 opset(AVSHUFW, r0)
1707 opset(AVSHUFV, r0)
1708
1709 case AXVSEQB:
1710 opset(AXVSEQH, r0)
1711 opset(AXVSEQW, r0)
1712 opset(AXVSEQV, r0)
1713 opset(AXVILVLB, r0)
1714 opset(AXVILVLH, r0)
1715 opset(AXVILVLW, r0)
1716 opset(AXVILVLV, r0)
1717 opset(AXVILVHB, r0)
1718 opset(AXVILVHH, r0)
1719 opset(AXVILVHW, r0)
1720 opset(AXVILVHV, r0)
1721 opset(AXVMULB, r0)
1722 opset(AXVMULH, r0)
1723 opset(AXVMULW, r0)
1724 opset(AXVMULV, r0)
1725 opset(AXVMUHB, r0)
1726 opset(AXVMUHH, r0)
1727 opset(AXVMUHW, r0)
1728 opset(AXVMUHV, r0)
1729 opset(AXVMUHBU, r0)
1730 opset(AXVMUHHU, r0)
1731 opset(AXVMUHWU, r0)
1732 opset(AXVMUHVU, r0)
1733 opset(AXVDIVB, r0)
1734 opset(AXVDIVH, r0)
1735 opset(AXVDIVW, r0)
1736 opset(AXVDIVV, r0)
1737 opset(AXVMODB, r0)
1738 opset(AXVMODH, r0)
1739 opset(AXVMODW, r0)
1740 opset(AXVMODV, r0)
1741 opset(AXVDIVBU, r0)
1742 opset(AXVDIVHU, r0)
1743 opset(AXVDIVWU, r0)
1744 opset(AXVDIVVU, r0)
1745 opset(AXVMODBU, r0)
1746 opset(AXVMODHU, r0)
1747 opset(AXVMODWU, r0)
1748 opset(AXVMODVU, r0)
1749 opset(AXVMULWEVHB, r0)
1750 opset(AXVMULWEVWH, r0)
1751 opset(AXVMULWEVVW, r0)
1752 opset(AXVMULWEVQV, r0)
1753 opset(AXVMULWODHB, r0)
1754 opset(AXVMULWODWH, r0)
1755 opset(AXVMULWODVW, r0)
1756 opset(AXVMULWODQV, r0)
1757 opset(AXVMULWEVHBU, r0)
1758 opset(AXVMULWEVWHU, r0)
1759 opset(AXVMULWEVVWU, r0)
1760 opset(AXVMULWEVQVU, r0)
1761 opset(AXVMULWODHBU, r0)
1762 opset(AXVMULWODWHU, r0)
1763 opset(AXVMULWODVWU, r0)
1764 opset(AXVMULWODQVU, r0)
1765 opset(AXVMULWEVHBUB, r0)
1766 opset(AXVMULWEVWHUH, r0)
1767 opset(AXVMULWEVVWUW, r0)
1768 opset(AXVMULWEVQVUV, r0)
1769 opset(AXVMULWODHBUB, r0)
1770 opset(AXVMULWODWHUH, r0)
1771 opset(AXVMULWODVWUW, r0)
1772 opset(AXVMULWODQVUV, r0)
1773 opset(AXVADDF, r0)
1774 opset(AXVADDD, r0)
1775 opset(AXVSUBF, r0)
1776 opset(AXVSUBD, r0)
1777 opset(AXVMULF, r0)
1778 opset(AXVMULD, r0)
1779 opset(AXVDIVF, r0)
1780 opset(AXVDIVD, r0)
1781 opset(AXVSHUFH, r0)
1782 opset(AXVSHUFW, r0)
1783 opset(AXVSHUFV, r0)
1784
1785 case AVANDB:
1786 opset(AVORB, r0)
1787 opset(AVXORB, r0)
1788 opset(AVNORB, r0)
1789 opset(AVSHUF4IB, r0)
1790 opset(AVSHUF4IH, r0)
1791 opset(AVSHUF4IW, r0)
1792 opset(AVSHUF4IV, r0)
1793 opset(AVPERMIW, r0)
1794 opset(AVEXTRINSB, r0)
1795 opset(AVEXTRINSH, r0)
1796 opset(AVEXTRINSW, r0)
1797 opset(AVEXTRINSV, r0)
1798
1799 case AXVANDB:
1800 opset(AXVORB, r0)
1801 opset(AXVXORB, r0)
1802 opset(AXVNORB, r0)
1803 opset(AXVSHUF4IB, r0)
1804 opset(AXVSHUF4IH, r0)
1805 opset(AXVSHUF4IW, r0)
1806 opset(AXVSHUF4IV, r0)
1807 opset(AXVPERMIW, r0)
1808 opset(AXVPERMIV, r0)
1809 opset(AXVPERMIQ, r0)
1810 opset(AXVEXTRINSB, r0)
1811 opset(AXVEXTRINSH, r0)
1812 opset(AXVEXTRINSW, r0)
1813 opset(AXVEXTRINSV, r0)
1814
1815 case AVANDV:
1816 opset(AVORV, r0)
1817 opset(AVXORV, r0)
1818 opset(AVNORV, r0)
1819 opset(AVANDNV, r0)
1820 opset(AVORNV, r0)
1821
1822 case AXVANDV:
1823 opset(AXVORV, r0)
1824 opset(AXVXORV, r0)
1825 opset(AXVNORV, r0)
1826 opset(AXVANDNV, r0)
1827 opset(AXVORNV, r0)
1828
1829 case AVPCNTB:
1830 opset(AVPCNTH, r0)
1831 opset(AVPCNTW, r0)
1832 opset(AVPCNTV, r0)
1833 opset(AVFSQRTF, r0)
1834 opset(AVFSQRTD, r0)
1835 opset(AVFRECIPF, r0)
1836 opset(AVFRECIPD, r0)
1837 opset(AVFRSQRTF, r0)
1838 opset(AVFRSQRTD, r0)
1839 opset(AVNEGB, r0)
1840 opset(AVNEGH, r0)
1841 opset(AVNEGW, r0)
1842 opset(AVNEGV, r0)
1843 opset(AVFRINTRNEF, r0)
1844 opset(AVFRINTRNED, r0)
1845 opset(AVFRINTRZF, r0)
1846 opset(AVFRINTRZD, r0)
1847 opset(AVFRINTRPF, r0)
1848 opset(AVFRINTRPD, r0)
1849 opset(AVFRINTRMF, r0)
1850 opset(AVFRINTRMD, r0)
1851 opset(AVFRINTF, r0)
1852 opset(AVFRINTD, r0)
1853 opset(AVFCLASSF, r0)
1854 opset(AVFCLASSD, r0)
1855
1856 case AXVPCNTB:
1857 opset(AXVPCNTH, r0)
1858 opset(AXVPCNTW, r0)
1859 opset(AXVPCNTV, r0)
1860 opset(AXVFSQRTF, r0)
1861 opset(AXVFSQRTD, r0)
1862 opset(AXVFRECIPF, r0)
1863 opset(AXVFRECIPD, r0)
1864 opset(AXVFRSQRTF, r0)
1865 opset(AXVFRSQRTD, r0)
1866 opset(AXVNEGB, r0)
1867 opset(AXVNEGH, r0)
1868 opset(AXVNEGW, r0)
1869 opset(AXVNEGV, r0)
1870 opset(AXVFRINTRNEF, r0)
1871 opset(AXVFRINTRNED, r0)
1872 opset(AXVFRINTRZF, r0)
1873 opset(AXVFRINTRZD, r0)
1874 opset(AXVFRINTRPF, r0)
1875 opset(AXVFRINTRPD, r0)
1876 opset(AXVFRINTRMF, r0)
1877 opset(AXVFRINTRMD, r0)
1878 opset(AXVFRINTF, r0)
1879 opset(AXVFRINTD, r0)
1880 opset(AXVFCLASSF, r0)
1881 opset(AXVFCLASSD, r0)
1882
1883 case AVADDB:
1884 opset(AVADDH, r0)
1885 opset(AVADDW, r0)
1886 opset(AVADDV, r0)
1887 opset(AVADDQ, r0)
1888 opset(AVSUBB, r0)
1889 opset(AVSUBH, r0)
1890 opset(AVSUBW, r0)
1891 opset(AVSUBV, r0)
1892 opset(AVSUBQ, r0)
1893
1894 case AXVADDB:
1895 opset(AXVADDH, r0)
1896 opset(AXVADDW, r0)
1897 opset(AXVADDV, r0)
1898 opset(AXVADDQ, r0)
1899 opset(AXVSUBB, r0)
1900 opset(AXVSUBH, r0)
1901 opset(AXVSUBW, r0)
1902 opset(AXVSUBV, r0)
1903 opset(AXVSUBQ, r0)
1904
1905 case AVSLLB:
1906 opset(AVSRLB, r0)
1907 opset(AVSRAB, r0)
1908 opset(AVROTRB, r0)
1909 opset(AVBITCLRB, r0)
1910 opset(AVBITSETB, r0)
1911 opset(AVBITREVB, r0)
1912
1913 case AXVSLLB:
1914 opset(AXVSRLB, r0)
1915 opset(AXVSRAB, r0)
1916 opset(AXVROTRB, r0)
1917 opset(AXVBITCLRB, r0)
1918 opset(AXVBITSETB, r0)
1919 opset(AXVBITREVB, r0)
1920
1921 case AVSLLH:
1922 opset(AVSRLH, r0)
1923 opset(AVSRAH, r0)
1924 opset(AVROTRH, r0)
1925 opset(AVBITCLRH, r0)
1926 opset(AVBITSETH, r0)
1927 opset(AVBITREVH, r0)
1928
1929 case AXVSLLH:
1930 opset(AXVSRLH, r0)
1931 opset(AXVSRAH, r0)
1932 opset(AXVROTRH, r0)
1933 opset(AXVBITCLRH, r0)
1934 opset(AXVBITSETH, r0)
1935 opset(AXVBITREVH, r0)
1936
1937 case AVSLLW:
1938 opset(AVSRLW, r0)
1939 opset(AVSRAW, r0)
1940 opset(AVROTRW, r0)
1941 opset(AVADDBU, r0)
1942 opset(AVADDHU, r0)
1943 opset(AVADDWU, r0)
1944 opset(AVADDVU, r0)
1945 opset(AVSUBBU, r0)
1946 opset(AVSUBHU, r0)
1947 opset(AVSUBWU, r0)
1948 opset(AVSUBVU, r0)
1949 opset(AVBITCLRW, r0)
1950 opset(AVBITSETW, r0)
1951 opset(AVBITREVW, r0)
1952
1953 case AXVSLLW:
1954 opset(AXVSRLW, r0)
1955 opset(AXVSRAW, r0)
1956 opset(AXVROTRW, r0)
1957 opset(AXVADDBU, r0)
1958 opset(AXVADDHU, r0)
1959 opset(AXVADDWU, r0)
1960 opset(AXVADDVU, r0)
1961 opset(AXVSUBBU, r0)
1962 opset(AXVSUBHU, r0)
1963 opset(AXVSUBWU, r0)
1964 opset(AXVSUBVU, r0)
1965 opset(AXVBITCLRW, r0)
1966 opset(AXVBITSETW, r0)
1967 opset(AXVBITREVW, r0)
1968
1969 case AVSLLV:
1970 opset(AVSRLV, r0)
1971 opset(AVSRAV, r0)
1972 opset(AVROTRV, r0)
1973 opset(AVBITCLRV, r0)
1974 opset(AVBITSETV, r0)
1975 opset(AVBITREVV, r0)
1976
1977 case AXVSLLV:
1978 opset(AXVSRLV, r0)
1979 opset(AXVSRAV, r0)
1980 opset(AXVROTRV, r0)
1981 opset(AXVBITCLRV, r0)
1982 opset(AXVBITSETV, r0)
1983 opset(AXVBITREVV, r0)
1984
1985 case AVSETEQV:
1986 opset(AVSETNEV, r0)
1987 opset(AVSETANYEQB, r0)
1988 opset(AVSETANYEQH, r0)
1989 opset(AVSETANYEQW, r0)
1990 opset(AVSETANYEQV, r0)
1991 opset(AVSETALLNEB, r0)
1992 opset(AVSETALLNEH, r0)
1993 opset(AVSETALLNEW, r0)
1994 opset(AVSETALLNEV, r0)
1995
1996 case AXVSETEQV:
1997 opset(AXVSETNEV, r0)
1998 opset(AXVSETANYEQB, r0)
1999 opset(AXVSETANYEQH, r0)
2000 opset(AXVSETANYEQW, r0)
2001 opset(AXVSETANYEQV, r0)
2002 opset(AXVSETALLNEB, r0)
2003 opset(AXVSETALLNEH, r0)
2004 opset(AXVSETALLNEW, r0)
2005 opset(AXVSETALLNEV, r0)
2006
2007 }
2008 }
2009 }
2010
2011 func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
2012 return op | (r1&0x1F)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4 & 0x1F)
2013 }
2014
2015
2016
2017
2018 func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32 {
2019 return op | (r1&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2020 }
2021
2022
2023
2024 func OP_RR(op uint32, r2 uint32, r3 uint32) uint32 {
2025 return op | (r2&0x1F)<<5 | (r3&0x1F)<<0
2026 }
2027
2028 func OP_2IRRR(op uint32, i uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
2029 return op | (i&0x3)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4&0x1F)<<0
2030 }
2031
2032 func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32 {
2033 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | ((i >> 16) & 0x1F)
2034 }
2035
2036 func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2037 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2038 }
2039
2040 func OP_14IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2041 return op | (i&0x3FFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2042 }
2043
2044 func OP_12IR_5I(op uint32, i1 uint32, r2 uint32, i2 uint32) uint32 {
2045 return op | (i1&0xFFF)<<10 | (r2&0x1F)<<5 | (i2&0x1F)<<0
2046 }
2047
2048 func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2049 return op | (i&0xFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2050 }
2051
2052 func OP_11IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2053 return op | (i&0x7FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2054 }
2055
2056 func OP_10IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2057 return op | (i&0x3FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2058 }
2059
2060 func OP_9IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2061 return op | (i&0x1FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2062 }
2063
2064 func OP_8IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2065 return op | (i&0xFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2066 }
2067
2068 func OP_6IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2069 return op | (i&0x3F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2070 }
2071
2072 func OP_5IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2073 return op | (i&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2074 }
2075
2076 func OP_4IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2077 return op | (i&0xF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2078 }
2079
2080 func OP_3IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2081 return op | (i&0x7)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2082 }
2083
2084 func OP_IR(op uint32, i uint32, r2 uint32) uint32 {
2085 return op | (i&0xFFFFF)<<5 | (r2&0x1F)<<0
2086 }
2087
2088 func OP_15I(op uint32, i uint32) uint32 {
2089 return op | (i&0x7FFF)<<0
2090 }
2091
2092
2093
2094
2095
2096 func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32 {
2097 return op | (i1 << 16) | (r2&0x1F)<<5 | (i3 << 10) | (r4&0x1F)<<0
2098 }
2099
2100
2101 func OP_B_BL(op uint32, i uint32) uint32 {
2102 return op | ((i & 0xFFFF) << 10) | ((i >> 16) & 0x3FF)
2103 }
2104
2105 func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
2106 o1 := uint32(0)
2107 o2 := uint32(0)
2108 o3 := uint32(0)
2109 o4 := uint32(0)
2110 o5 := uint32(0)
2111 o6 := uint32(0)
2112
2113 add := AADDU
2114 add = AADDVU
2115
2116 switch o.type_ {
2117 default:
2118 c.ctxt.Diag("unknown type %d", o.type_)
2119 prasm(p)
2120
2121 case 0:
2122 break
2123
2124 case 1:
2125 switch p.As {
2126 case AMOVW:
2127 o1 = OP_RRR(c.oprrr(ASLL), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
2128 case AMOVV:
2129 o1 = OP_RRR(c.oprrr(AOR), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
2130 case AVMOVQ:
2131 o1 = OP_6IRR(c.opirr(AVSLLV), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
2132 case AXVMOVQ:
2133 o1 = OP_6IRR(c.opirr(AXVSLLV), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
2134 default:
2135 c.ctxt.Diag("unexpected encoding\n%v", p)
2136 }
2137
2138 case 2:
2139 r := int(p.Reg)
2140 if p.As == ANEGW || p.As == ANEGV {
2141 r = REGZERO
2142 }
2143 if r == 0 {
2144 r = int(p.To.Reg)
2145 }
2146 o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
2147
2148 case 3:
2149 v := c.regoff(&p.From)
2150
2151 r := int(p.From.Reg)
2152 if r == 0 {
2153 r = int(o.param)
2154 }
2155 a := add
2156 if o.from1 == C_12CON && v > 0 {
2157 a = AOR
2158 }
2159
2160 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.To.Reg))
2161
2162 case 4:
2163 v := c.regoff(&p.From)
2164 r := int(p.Reg)
2165 if r == 0 {
2166 r = int(p.To.Reg)
2167 }
2168 if p.As == AADDV16 {
2169 if v&65535 != 0 {
2170 c.ctxt.Diag("%v: the constant must be a multiple of 65536.\n", p)
2171 }
2172 o1 = OP_16IRR(c.opirr(p.As), uint32(v>>16), uint32(r), uint32(p.To.Reg))
2173 } else {
2174 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2175 }
2176
2177 case 5:
2178 v := c.regoff(&p.From)
2179 o1 = OP_15I(c.opi(p.As), uint32(v))
2180
2181 case 6:
2182 v := int32(0)
2183 if p.To.Target() != nil {
2184 v = int32(p.To.Target().Pc-p.Pc) >> 2
2185 }
2186 as, rd, rj, width := p.As, p.Reg, p.From.Reg, 16
2187 switch as {
2188 case ABGTZ, ABLEZ:
2189 rd, rj = rj, rd
2190 case ABFPT, ABFPF:
2191 width = 21
2192
2193
2194 if rj == 0 {
2195 rj = REG_FCC0
2196 }
2197 case ABEQ, ABNE:
2198 if rd == 0 || rd == REGZERO || rj == REGZERO {
2199
2200 width = 21
2201 as = -as
2202 if rj == 0 || rj == REGZERO {
2203 rj = rd
2204 }
2205 }
2206 }
2207 switch width {
2208 case 21:
2209 if (v<<11)>>11 != v {
2210 c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
2211 }
2212 o1 = OP_16IR_5I(c.opirr(as), uint32(v), uint32(rj))
2213 case 16:
2214 if (v<<16)>>16 != v {
2215 c.ctxt.Diag("16 bit-width, short branch too far\n%v", p)
2216 }
2217 o1 = OP_16IRR(c.opirr(as), uint32(v), uint32(rj), uint32(rd))
2218 default:
2219 c.ctxt.Diag("unexpected branch encoding\n%v", p)
2220 }
2221
2222 case 7:
2223 r := int(p.To.Reg)
2224 if r == 0 {
2225 r = int(o.param)
2226 }
2227 v := c.regoff(&p.To)
2228 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2229
2230 case 8:
2231 r := int(p.From.Reg)
2232 if r == 0 {
2233 r = int(o.param)
2234 }
2235 v := c.regoff(&p.From)
2236 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2237
2238 case 9:
2239 o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
2240
2241 case 10:
2242 v := c.regoff(&p.From)
2243 a := AOR
2244 if v < 0 {
2245 a = AADDU
2246 }
2247 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2248 r := int(p.Reg)
2249 if r == 0 {
2250 r = int(p.To.Reg)
2251 }
2252 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2253
2254 case 11:
2255 v := int32(0)
2256 if p.To.Target() != nil {
2257 v = int32(p.To.Target().Pc-p.Pc) >> 2
2258 }
2259 o1 = OP_B_BL(c.opirr(p.As), uint32(v))
2260 if p.To.Sym != nil {
2261 c.cursym.AddRel(c.ctxt, obj.Reloc{
2262 Type: objabi.R_CALLLOONG64,
2263 Off: int32(c.pc),
2264 Siz: 4,
2265 Sym: p.To.Sym,
2266 Add: p.To.Offset,
2267 })
2268 }
2269
2270 case 12:
2271 switch p.As {
2272 case AMOVB:
2273 o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg))
2274 case AMOVH:
2275 o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg))
2276 case AMOVBU:
2277 o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg))
2278 case AMOVHU:
2279 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2280 case AMOVWU:
2281 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2282 default:
2283 c.ctxt.Diag("unexpected encoding\n%v", p)
2284 }
2285
2286 case 13:
2287 v := c.regoff(&p.From)
2288 r := int(p.Reg)
2289 if r == 0 {
2290 r = int(p.To.Reg)
2291 }
2292 o1 = OP_3IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2293
2294 case 14:
2295 v := c.regoff(&p.From)
2296 r := int(p.Reg)
2297 if r == 0 {
2298 r = int(p.To.Reg)
2299 }
2300 o1 = OP_4IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2301
2302 case 15:
2303 v := c.regoff(&p.From)
2304 r := int(p.Reg)
2305 if r == 0 {
2306 r = REGZERO
2307 }
2308
2316 if p.As == ATEQ {
2317 o1 = OP_16IRR(c.opirr(ABNE), uint32(2), uint32(r), uint32(p.To.Reg))
2318 } else {
2319 o1 = OP_16IRR(c.opirr(ABEQ), uint32(2), uint32(r), uint32(p.To.Reg))
2320 }
2321 o2 = OP_15I(c.opi(ABREAK), uint32(v))
2322
2323 case 16:
2324 v := c.regoff(&p.From)
2325 r := int(p.Reg)
2326 if r == 0 {
2327 r = int(p.To.Reg)
2328 }
2329
2330
2331 if v >= 32 && vshift(p.As) {
2332 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x3f, uint32(r), uint32(p.To.Reg))
2333 } else {
2334 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x1f, uint32(r), uint32(p.To.Reg))
2335 }
2336
2337 case 17:
2338 rd, rj := p.To.Reg, p.Reg
2339 if rj == obj.REG_NONE {
2340 rj = rd
2341 }
2342 msb, lsb := p.From.Offset, p.GetFrom3().Offset
2343
2344
2345 var b uint32
2346 if p.As == ABSTRPICKW || p.As == ABSTRINSW {
2347 b = 32
2348 } else {
2349 b = 64
2350 }
2351 if lsb < 0 || uint32(lsb) >= b || msb < 0 || uint32(msb) >= b || uint32(lsb) > uint32(msb) {
2352 c.ctxt.Diag("illegal bit number\n%v", p)
2353 }
2354
2355 o1 = OP_IRIR(c.opirir(p.As), uint32(msb), uint32(rj), uint32(lsb), uint32(rd))
2356
2357 case 18:
2358 r := int(p.Reg)
2359 if r == 0 {
2360 r = int(o.param)
2361 }
2362 o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.To.Reg), uint32(r))
2363 if p.As == obj.ACALL {
2364 c.cursym.AddRel(c.ctxt, obj.Reloc{
2365 Type: objabi.R_CALLIND,
2366 Off: int32(c.pc),
2367 })
2368 }
2369
2370 case 19:
2371
2372
2373 v := c.regoff(&p.From)
2374 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2375 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2376
2377 case 20:
2378 o1 = OP_RRR(c.oprrr(p.As), uint32(p.To.Index), uint32(p.To.Reg), uint32(p.From.Reg))
2379
2380 case 21:
2381 o1 = OP_RRR(c.oprrr(-p.As), uint32(p.From.Index), uint32(p.From.Reg), uint32(p.To.Reg))
2382
2383 case 22:
2384 v := c.regoff(&p.From)
2385 r := int(p.Reg)
2386 if r == 0 {
2387 r = int(p.To.Reg)
2388 }
2389
2390 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2391
2392 case 23:
2393 v := c.regoff(&p.From)
2394 r := int(p.Reg)
2395 if r == 0 {
2396 r = int(p.To.Reg)
2397 }
2398
2399
2400 if p.As == AVSHUF4IV || p.As == AXVSHUF4IV {
2401 operand := uint32(v)
2402 c.checkoperand(p, operand, 15)
2403 }
2404
2405 o1 = OP_8IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2406
2407 case 24:
2408 v := c.regoff(&p.From)
2409 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2410 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2411 r := int(p.Reg)
2412 if r == 0 {
2413 r = int(p.To.Reg)
2414 }
2415 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2416
2417 case 25:
2418 v := c.regoff(&p.From)
2419 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2420
2421 case 26:
2422 v := c.regoff(&p.From)
2423 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2424 r := int(p.Reg)
2425 if r == 0 {
2426 r = int(p.To.Reg)
2427 }
2428 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2429
2430 case 27:
2431 v := c.regoff(&p.From)
2432 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2433 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2434 r := int(p.From.Reg)
2435 if r == 0 {
2436 r = int(o.param)
2437 }
2438 o3 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2439
2440 case 28:
2441 v := c.regoff(&p.From)
2442 r := int(p.From.Reg)
2443 if r == 0 {
2444 r = int(o.param)
2445 }
2446 switch o.size {
2447 case 12:
2448 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2449 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2450 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2451
2452 case 4:
2453 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2454 }
2455
2456 case 29:
2457 v := c.regoff(&p.To)
2458 r := int(p.To.Reg)
2459 if r == 0 {
2460 r = int(o.param)
2461 }
2462 switch o.size {
2463 case 12:
2464 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2465 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2466 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2467
2468 case 4:
2469 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2470 }
2471
2472 case 30:
2473 a := c.specialFpMovInst(p.As, oclass(&p.From), oclass(&p.To))
2474 o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
2475
2476 case 31:
2477 v := c.regoff(&p.From)
2478 r := int(p.Reg)
2479 if r == 0 {
2480 r = int(p.To.Reg)
2481 }
2482 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2483
2484 case 32:
2485 v := c.regoff(&p.From)
2486 r := int(p.Reg)
2487 if r == 0 {
2488 r = int(p.To.Reg)
2489 }
2490 o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2491
2492 case 33:
2493 ca := uint32(p.From.Reg)
2494 fk := uint32(p.Reg)
2495 fd := uint32(p.To.Reg)
2496 fj := fd
2497 if len(p.RestArgs) > 0 {
2498 fj = uint32(p.GetFrom3().Reg)
2499 }
2500 o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F)
2501
2502 case 34:
2503 v := c.regoff(&p.From)
2504 a := AADDU
2505 if v > 0 {
2506 a = AOR
2507 }
2508 a2 := c.specialFpMovInst(p.As, C_REG, oclass(&p.To))
2509 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2510 o2 = OP_RR(a2, uint32(REGTMP), uint32(p.To.Reg))
2511
2512 case 35:
2513 v := c.regoff(&p.To)
2514 r := int(p.To.Reg)
2515 if r == 0 {
2516 r = int(o.param)
2517 }
2518 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2519 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2520 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2521
2522 case 36:
2523 v := c.regoff(&p.From)
2524 r := int(p.From.Reg)
2525 if r == 0 {
2526 r = int(o.param)
2527 }
2528 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2529 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2530 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2531
2532 case 37:
2533 r := int(p.To.Reg)
2534 if len(p.RestArgs) > 0 {
2535 r = int(p.GetFrom3().Reg)
2536 }
2537 o1 = OP_RRRR(c.oprrrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(r), uint32(p.To.Reg))
2538
2539 case 38:
2540 o1 = uint32(c.regoff(&p.From))
2541
2542 case 39:
2543 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2544 if v == 0 {
2545 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2546 }
2547
2548 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2549 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2550 index := uint32(p.To.Index)
2551 c.checkindex(p, index, m)
2552 o1 = v | (index << 10) | (Rj << 5) | Vd
2553
2554 case 40:
2555 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2556 if v == 0 {
2557 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2558 }
2559
2560 Vj := uint32(p.From.Reg & EXT_REG_MASK)
2561 Rd := uint32(p.To.Reg & EXT_REG_MASK)
2562 index := uint32(p.From.Index)
2563 c.checkindex(p, index, m)
2564 o1 = v | (index << 10) | (Vj << 5) | Rd
2565
2566 case 41:
2567 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2568 if v == 0 {
2569 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2570 }
2571
2572 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2573 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2574 o1 = v | (Rj << 5) | Vd
2575
2576 case 42:
2577 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2578 if v == 0 {
2579 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2580 }
2581
2582 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2583 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2584 o1 = v | (Xj << 5) | Xd
2585
2586 case 43:
2587 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2588 if v == 0 {
2589 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2590 }
2591
2592 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2593 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2594 index := uint32(p.To.Index)
2595 c.checkindex(p, index, m)
2596 o1 = v | (index << 10) | (Xj << 5) | Xd
2597
2598 case 44:
2599 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2600 if v == 0 {
2601 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2602 }
2603
2604 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2605 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2606 index := uint32(p.From.Index)
2607 c.checkindex(p, index, m)
2608 o1 = v | (index << 10) | (Xj << 5) | Xd
2609
2610 case 45:
2611 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2612 if v == 0 {
2613 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2614 }
2615
2616 vj := uint32(p.From.Reg & EXT_REG_MASK)
2617 vd := uint32(p.To.Reg & EXT_REG_MASK)
2618 index := uint32(p.From.Index)
2619 c.checkindex(p, index, m)
2620 o1 = v | (index << 10) | (vj << 5) | vd
2621
2622 case 46:
2623 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, true)
2624 if v == 0 {
2625 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2626 }
2627
2628 si := c.regoff(&p.From)
2629 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2630 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2631 switch v & 0xc00000 {
2632 case 0x800000:
2633 o1 = OP_12IRR(v, uint32(si), Rj, Vd)
2634 case 0x400000:
2635 if si&1 != 0 {
2636 c.ctxt.Diag("%v: offset must be a multiple of 2.\n", p)
2637 }
2638 o1 = OP_11IRR(v, uint32(si>>1), Rj, Vd)
2639 case 0x0:
2640 switch v & 0x300000 {
2641 case 0x200000:
2642 if si&3 != 0 {
2643 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
2644 }
2645 o1 = OP_10IRR(v, uint32(si>>2), Rj, Vd)
2646 case 0x100000:
2647 if si&7 != 0 {
2648 c.ctxt.Diag("%v: offset must be a multiple of 8.\n", p)
2649 }
2650 o1 = OP_9IRR(v, uint32(si>>3), Rj, Vd)
2651 }
2652 }
2653
2654 case 47:
2655 offs := c.regoff(&p.From)
2656 hint := p.GetFrom3().Offset
2657 o1 = OP_12IR_5I(c.opiir(p.As), uint32(offs), uint32(p.From.Reg), uint32(hint))
2658
2659 case 48:
2660 offs := c.regoff(&p.From)
2661 hint := p.RestArgs[1].Offset
2662 n := uint64(p.GetFrom3().Offset)
2663
2664 addrSeq := (n >> 0) & 0x1
2665 blkSize := (n >> 1) & 0x7ff
2666 blkNums := (n >> 12) & 0x1ff
2667 stride := (n >> 21) & 0xffff
2668
2669 if blkSize > 1024 {
2670 c.ctxt.Diag("%v: block_size amount out of range[16, 1024]: %v\n", p, blkSize)
2671 }
2672
2673 if blkNums > 256 {
2674 c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkSize)
2675 }
2676
2677 v := (uint64(offs) & 0xffff)
2678 v += addrSeq << 16
2679 v += ((blkSize / 16) - 1) << 20
2680 v += (blkNums - 1) << 32
2681 v += stride << 44
2682
2683 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2684 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2685 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2686 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2687 o5 = OP_5IRR(c.opirr(p.As), uint32(REGTMP), uint32(p.From.Reg), uint32(hint))
2688
2689 case 49:
2690 if p.As == ANOOP {
2691
2692 o1 = OP_12IRR(c.opirr(AAND), 0, 0, 0)
2693 } else {
2694
2695 o1 = OP_15I(c.opi(ABREAK), 0)
2696 }
2697
2698
2699 case 50:
2700 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2701 c.cursym.AddRel(c.ctxt, obj.Reloc{
2702 Type: objabi.R_LOONG64_ADDR_HI,
2703 Off: int32(c.pc),
2704 Siz: 4,
2705 Sym: p.To.Sym,
2706 Add: p.To.Offset,
2707 })
2708 o2 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2709 c.cursym.AddRel(c.ctxt, obj.Reloc{
2710 Type: objabi.R_LOONG64_ADDR_LO,
2711 Off: int32(c.pc + 4),
2712 Siz: 4,
2713 Sym: p.To.Sym,
2714 Add: p.To.Offset,
2715 })
2716
2717 case 51:
2718 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2719 c.cursym.AddRel(c.ctxt, obj.Reloc{
2720 Type: objabi.R_LOONG64_ADDR_HI,
2721 Off: int32(c.pc),
2722 Siz: 4,
2723 Sym: p.From.Sym,
2724 Add: p.From.Offset,
2725 })
2726 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2727 c.cursym.AddRel(c.ctxt, obj.Reloc{
2728 Type: objabi.R_LOONG64_ADDR_LO,
2729 Off: int32(c.pc + 4),
2730 Siz: 4,
2731 Sym: p.From.Sym,
2732 Add: p.From.Offset,
2733 })
2734
2735 case 52:
2736
2737
2738 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2739 c.cursym.AddRel(c.ctxt, obj.Reloc{
2740 Type: objabi.R_LOONG64_ADDR_HI,
2741 Off: int32(c.pc),
2742 Siz: 4,
2743 Sym: p.From.Sym,
2744 Add: p.From.Offset,
2745 })
2746 o2 = OP_12IRR(c.opirr(add), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2747 c.cursym.AddRel(c.ctxt, obj.Reloc{
2748 Type: objabi.R_LOONG64_ADDR_LO,
2749 Off: int32(c.pc + 4),
2750 Siz: 4,
2751 Sym: p.From.Sym,
2752 Add: p.From.Offset,
2753 })
2754
2755 case 53:
2756
2757
2758 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2759 c.cursym.AddRel(c.ctxt, obj.Reloc{
2760 Type: objabi.R_LOONG64_TLS_LE_HI,
2761 Off: int32(c.pc),
2762 Siz: 4,
2763 Sym: p.To.Sym,
2764 Add: p.To.Offset,
2765 })
2766 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2767 c.cursym.AddRel(c.ctxt, obj.Reloc{
2768 Type: objabi.R_LOONG64_TLS_LE_LO,
2769 Off: int32(c.pc + 4),
2770 Siz: 4,
2771 Sym: p.To.Sym,
2772 Add: p.To.Offset,
2773 })
2774 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2775 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2776
2777 case 54:
2778
2779
2780 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2781 c.cursym.AddRel(c.ctxt, obj.Reloc{
2782 Type: objabi.R_LOONG64_TLS_LE_HI,
2783 Off: int32(c.pc),
2784 Siz: 4,
2785 Sym: p.From.Sym,
2786 Add: p.From.Offset,
2787 })
2788 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2789 c.cursym.AddRel(c.ctxt, obj.Reloc{
2790 Type: objabi.R_LOONG64_TLS_LE_LO,
2791 Off: int32(c.pc + 4),
2792 Siz: 4,
2793 Sym: p.From.Sym,
2794 Add: p.From.Offset,
2795 })
2796 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2797 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2798
2799 case 56:
2800 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2801 c.cursym.AddRel(c.ctxt, obj.Reloc{
2802 Type: objabi.R_LOONG64_TLS_IE_HI,
2803 Off: int32(c.pc),
2804 Siz: 4,
2805 Sym: p.To.Sym,
2806 })
2807 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2808 c.cursym.AddRel(c.ctxt, obj.Reloc{
2809 Type: objabi.R_LOONG64_TLS_IE_LO,
2810 Off: int32(c.pc + 4),
2811 Siz: 4,
2812 Sym: p.To.Sym,
2813 })
2814 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
2815 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2816
2817 case 57:
2818 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2819 c.cursym.AddRel(c.ctxt, obj.Reloc{
2820 Type: objabi.R_LOONG64_TLS_IE_HI,
2821 Off: int32(c.pc),
2822 Siz: 4,
2823 Sym: p.From.Sym,
2824 })
2825 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2826 c.cursym.AddRel(c.ctxt, obj.Reloc{
2827 Type: objabi.R_LOONG64_TLS_IE_LO,
2828 Off: int32(c.pc + 4),
2829 Siz: 4,
2830 Sym: p.From.Sym,
2831 })
2832 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
2833 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2834
2835 case 59:
2836
2837
2838 v := c.vregoff(&p.From)
2839 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2840 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2841 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2842 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2843
2844 case 60:
2845 v := c.vregoff(&p.From)
2846 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2847 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2848 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2849 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2850 r := int(p.Reg)
2851 if r == 0 {
2852 r = int(p.To.Reg)
2853 }
2854 o5 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2855
2856 case 61:
2857 o1 = uint32(c.vregoff(&p.From))
2858 o2 = uint32(c.vregoff(&p.From) >> 32)
2859
2860 case 62:
2861 o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
2862
2863 case 64:
2864 sa := p.From.Offset - 1
2865 if sa < 0 || sa > 3 {
2866 c.ctxt.Diag("%v: shift amount out of range[1, 4].\n", p)
2867 }
2868 r := p.GetFrom3().Reg
2869 o1 = OP_2IRRR(c.opirrr(p.As), uint32(sa), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
2870
2871 case 65:
2872 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2873 c.cursym.AddRel(c.ctxt, obj.Reloc{
2874 Type: objabi.R_LOONG64_GOT_HI,
2875 Off: int32(c.pc),
2876 Siz: 4,
2877 Sym: p.From.Sym,
2878 })
2879 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2880 c.cursym.AddRel(c.ctxt, obj.Reloc{
2881 Type: objabi.R_LOONG64_GOT_LO,
2882 Off: int32(c.pc + 4),
2883 Siz: 4,
2884 Sym: p.From.Sym,
2885 })
2886
2887 case 66:
2888 rk := p.From.Reg
2889 rj := p.To.Reg
2890 rd := p.RegTo2
2891
2892
2893
2894 if rd == rj || rd == rk {
2895 c.ctxt.Diag("illegal register combination: %v\n", p)
2896 }
2897 o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
2898
2899 case 67:
2900 v := c.vregoff(&p.From)
2901 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(p.To.Reg))
2902
2903 case 68:
2904 v := c.vregoff(&p.From)
2905 contype := c.aclass(&p.From)
2906 switch contype {
2907 default:
2908 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2909 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2910 case C_DCON20S_20:
2911 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2912 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2913 case C_DCON12_12S:
2914 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(p.To.Reg))
2915 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2916 case C_DCON20S_12S, C_DCON20S_0:
2917 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
2918 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2919 case C_DCON12_12U:
2920 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2921 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2922 case C_DCON20S_12U:
2923 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2924 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2925 }
2926
2927 case 69:
2928 v := c.vregoff(&p.From)
2929 contype := c.aclass(&p.From)
2930 switch contype {
2931 default:
2932 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
2933 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2934 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2935 case C_DCON32_20:
2936 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2937 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2938 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2939 case C_DCON12_32S:
2940 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2941 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2942 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2943 case C_DCON20S_32:
2944 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2945 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2946 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2947 case C_DCON32_12U:
2948 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2949 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2950 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2951 }
2952
2953 case 70:
2954 v := c.vregoff(&p.From)
2955 r := int(p.Reg)
2956 if r == 0 {
2957 r = int(p.To.Reg)
2958 }
2959 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(REGTMP))
2960 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2961
2962 case 71:
2963 v := c.vregoff(&p.From)
2964 r := int(p.Reg)
2965 if r == 0 {
2966 r = int(p.To.Reg)
2967 }
2968 contype := c.aclass(&p.From)
2969 switch contype {
2970 default:
2971 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2972 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2973 case C_DCON20S_20:
2974 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2975 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2976 case C_DCON12_12S:
2977 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(REGTMP))
2978 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2979 case C_DCON20S_12S, C_DCON20S_0:
2980 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
2981 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2982 case C_DCON12_12U:
2983 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
2984 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2985 case C_DCON20S_12U:
2986 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
2987 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2988 }
2989 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2990
2991 case 72:
2992 v := c.vregoff(&p.From)
2993 r := int(p.Reg)
2994 if r == 0 {
2995 r = int(p.To.Reg)
2996 }
2997 contype := c.aclass(&p.From)
2998 switch contype {
2999 default:
3000 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
3001 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3002 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3003 case C_DCON32_20:
3004 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3005 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3006 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3007 case C_DCON12_32S:
3008 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3009 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3010 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3011 case C_DCON20S_32:
3012 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3013 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3014 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3015 case C_DCON32_12U:
3016 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
3017 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3018 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3019 }
3020 o4 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
3021
3022 case 73:
3023 v := c.vregoff(&p.To)
3024 r := p.To.Reg
3025 if v&3 != 0 {
3026 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
3027 }
3028
3029 switch o.size {
3030 case 4:
3031 o1 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(r), uint32(p.From.Reg))
3032 case 12:
3033 o1 = OP_16IRR(c.opirr(AADDV16), uint32(v>>16), uint32(REG_R0), uint32(REGTMP))
3034 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
3035 o3 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(REGTMP), uint32(p.From.Reg))
3036 case 24:
3037 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3038 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3039 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3040 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3041 o5 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(r))
3042 o6 = OP_14IRR(c.opirr(p.As), uint32(0), uint32(r), uint32(p.From.Reg))
3043 }
3044
3045 case 74:
3046 v := c.vregoff(&p.From)
3047 r := p.From.Reg
3048 if v&3 != 0 {
3049 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
3050 }
3051
3052 switch o.size {
3053 case 4:
3054 o1 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(r), uint32(p.To.Reg))
3055 case 12:
3056 o1 = OP_16IRR(c.opirr(AADDV16), uint32(v>>16), uint32(REG_R0), uint32(REGTMP))
3057 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
3058 o3 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(REGTMP), uint32(p.To.Reg))
3059 case 24:
3060 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3061 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3062 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3063 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3064 o5 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(r))
3065 o6 = OP_14IRR(c.opirr(p.As), uint32(0), uint32(r), uint32(p.To.Reg))
3066 }
3067
3068 }
3069
3070 out[0] = o1
3071 out[1] = o2
3072 out[2] = o3
3073 out[3] = o4
3074 out[4] = o5
3075 out[5] = o6
3076 }
3077
3078
3079 func (c *ctxt0) checkoperand(p *obj.Prog, operand uint32, mask uint32) {
3080 if (operand & ^mask) != 0 {
3081 c.ctxt.Diag("operand out of range 0 to %d: %v", mask, p)
3082 }
3083 }
3084
3085
3086 func (c *ctxt0) checkindex(p *obj.Prog, index uint32, mask uint32) {
3087 if (index & ^mask) != 0 {
3088 c.ctxt.Diag("register element index out of range 0 to %d: %v", mask, p)
3089 }
3090 }
3091
3092 func (c *ctxt0) vregoff(a *obj.Addr) int64 {
3093 c.instoffset = 0
3094 c.aclass(a)
3095 return c.instoffset
3096 }
3097
3098 func (c *ctxt0) regoff(a *obj.Addr) int32 {
3099 return int32(c.vregoff(a))
3100 }
3101
3102 func (c *ctxt0) oprrrr(a obj.As) uint32 {
3103 switch a {
3104 case AFMADDF:
3105 return 0x81 << 20
3106 case AFMADDD:
3107 return 0x82 << 20
3108 case AFMSUBF:
3109 return 0x85 << 20
3110 case AFMSUBD:
3111 return 0x86 << 20
3112 case AFNMADDF:
3113 return 0x89 << 20
3114 case AFNMADDD:
3115 return 0x8a << 20
3116 case AFNMSUBF:
3117 return 0x8d << 20
3118 case AFNMSUBD:
3119 return 0x8e << 20
3120 case AVSHUFB:
3121 return 0x0D5 << 20
3122 case AXVSHUFB:
3123 return 0x0D6 << 20
3124 }
3125
3126 c.ctxt.Diag("bad rrrr opcode %v", a)
3127 return 0
3128 }
3129
3130 func (c *ctxt0) oprrr(a obj.As) uint32 {
3131 switch a {
3132 case AADD:
3133 return 0x20 << 15
3134 case AADDU:
3135 return 0x20 << 15
3136 case ASGT:
3137 return 0x24 << 15
3138 case ASGTU:
3139 return 0x25 << 15
3140 case AMASKEQZ:
3141 return 0x26 << 15
3142 case AMASKNEZ:
3143 return 0x27 << 15
3144 case AAND:
3145 return 0x29 << 15
3146 case AOR:
3147 return 0x2a << 15
3148 case AXOR:
3149 return 0x2b << 15
3150 case AORN:
3151 return 0x2c << 15
3152 case AANDN:
3153 return 0x2d << 15
3154 case ASUB:
3155 return 0x22 << 15
3156 case ASUBU, ANEGW:
3157 return 0x22 << 15
3158 case ANOR:
3159 return 0x28 << 15
3160 case ASLL:
3161 return 0x2e << 15
3162 case ASRL:
3163 return 0x2f << 15
3164 case ASRA:
3165 return 0x30 << 15
3166 case AROTR:
3167 return 0x36 << 15
3168 case ASLLV:
3169 return 0x31 << 15
3170 case ASRLV:
3171 return 0x32 << 15
3172 case ASRAV:
3173 return 0x33 << 15
3174 case AROTRV:
3175 return 0x37 << 15
3176 case AADDV:
3177 return 0x21 << 15
3178 case AADDVU:
3179 return 0x21 << 15
3180 case ASUBV:
3181 return 0x23 << 15
3182 case ASUBVU, ANEGV:
3183 return 0x23 << 15
3184
3185 case AMUL:
3186 return 0x38 << 15
3187 case AMULU:
3188 return 0x38 << 15
3189 case AMULH:
3190 return 0x39 << 15
3191 case AMULHU:
3192 return 0x3a << 15
3193 case AMULV:
3194 return 0x3b << 15
3195 case AMULVU:
3196 return 0x3b << 15
3197 case AMULHV:
3198 return 0x3c << 15
3199 case AMULHVU:
3200 return 0x3d << 15
3201 case ADIV:
3202 return 0x40 << 15
3203 case ADIVU:
3204 return 0x42 << 15
3205 case ADIVV:
3206 return 0x44 << 15
3207 case ADIVVU:
3208 return 0x46 << 15
3209 case AREM:
3210 return 0x41 << 15
3211 case AREMU:
3212 return 0x43 << 15
3213 case AREMV:
3214 return 0x45 << 15
3215 case AREMVU:
3216 return 0x47 << 15
3217 case ACRCWBW:
3218 return 0x48 << 15
3219 case ACRCWHW:
3220 return 0x49 << 15
3221 case ACRCWWW:
3222 return 0x4a << 15
3223 case ACRCWVW:
3224 return 0x4b << 15
3225 case ACRCCWBW:
3226 return 0x4c << 15
3227 case ACRCCWHW:
3228 return 0x4d << 15
3229 case ACRCCWWW:
3230 return 0x4e << 15
3231 case ACRCCWVW:
3232 return 0x4f << 15
3233 case AJMP:
3234 return 0x13 << 26
3235 case AJAL:
3236 return (0x13 << 26) | 1
3237
3238 case ADIVF:
3239 return 0x20d << 15
3240 case ADIVD:
3241 return 0x20e << 15
3242 case AMULF:
3243 return 0x209 << 15
3244 case AMULD:
3245 return 0x20a << 15
3246 case ASUBF:
3247 return 0x205 << 15
3248 case ASUBD:
3249 return 0x206 << 15
3250 case AADDF:
3251 return 0x201 << 15
3252 case AADDD:
3253 return 0x202 << 15
3254 case ACMPEQF:
3255 return 0x0c1<<20 | 0x4<<15
3256 case ACMPEQD:
3257 return 0x0c2<<20 | 0x4<<15
3258 case ACMPGED:
3259 return 0x0c2<<20 | 0x7<<15
3260 case ACMPGEF:
3261 return 0x0c1<<20 | 0x7<<15
3262 case ACMPGTD:
3263 return 0x0c2<<20 | 0x3<<15
3264 case ACMPGTF:
3265 return 0x0c1<<20 | 0x3<<15
3266 case AFMINF:
3267 return 0x215 << 15
3268 case AFMIND:
3269 return 0x216 << 15
3270 case AFMAXF:
3271 return 0x211 << 15
3272 case AFMAXD:
3273 return 0x212 << 15
3274 case AFMAXAF:
3275 return 0x219 << 15
3276 case AFMAXAD:
3277 return 0x21a << 15
3278 case AFMINAF:
3279 return 0x21d << 15
3280 case AFMINAD:
3281 return 0x21e << 15
3282 case AFSCALEBF:
3283 return 0x221 << 15
3284 case AFSCALEBD:
3285 return 0x222 << 15
3286 case AFCOPYSGF:
3287 return 0x225 << 15
3288 case AFCOPYSGD:
3289 return 0x226 << 15
3290 case -AMOVB:
3291 return 0x07000 << 15
3292 case -AMOVH:
3293 return 0x07008 << 15
3294 case -AMOVW:
3295 return 0x07010 << 15
3296 case -AMOVV:
3297 return 0x07018 << 15
3298 case -AMOVBU:
3299 return 0x07040 << 15
3300 case -AMOVHU:
3301 return 0x07048 << 15
3302 case -AMOVWU:
3303 return 0x07050 << 15
3304 case AMOVB:
3305 return 0x07020 << 15
3306 case AMOVH:
3307 return 0x07028 << 15
3308 case AMOVW:
3309 return 0x07030 << 15
3310 case AMOVV:
3311 return 0x07038 << 15
3312 case -AMOVF:
3313 return 0x07060 << 15
3314 case -AMOVD:
3315 return 0x07068 << 15
3316 case AMOVF:
3317 return 0x07070 << 15
3318 case AMOVD:
3319 return 0x07078 << 15
3320 case -AVMOVQ:
3321 return 0x07080 << 15
3322 case -AXVMOVQ:
3323 return 0x07090 << 15
3324 case AVMOVQ:
3325 return 0x07088 << 15
3326 case AXVMOVQ:
3327 return 0x07098 << 15
3328 case AVSEQB:
3329 return 0x0e000 << 15
3330 case AXVSEQB:
3331 return 0x0e800 << 15
3332 case AVSEQH:
3333 return 0x0e001 << 15
3334 case AXVSEQH:
3335 return 0x0e801 << 15
3336 case AVSEQW:
3337 return 0x0e002 << 15
3338 case AXVSEQW:
3339 return 0x0e802 << 15
3340 case AVSEQV:
3341 return 0x0e003 << 15
3342 case AXVSEQV:
3343 return 0x0e803 << 15
3344 case AVANDV:
3345 return 0x0E24C << 15
3346 case AVORV:
3347 return 0x0E24D << 15
3348 case AVXORV:
3349 return 0x0E24E << 15
3350 case AVNORV:
3351 return 0x0E24F << 15
3352 case AVANDNV:
3353 return 0x0E250 << 15
3354 case AVORNV:
3355 return 0x0E251 << 15
3356 case AXVANDV:
3357 return 0x0EA4C << 15
3358 case AXVORV:
3359 return 0x0EA4D << 15
3360 case AXVXORV:
3361 return 0x0EA4E << 15
3362 case AXVNORV:
3363 return 0x0EA4F << 15
3364 case AXVANDNV:
3365 return 0x0EA50 << 15
3366 case AXVORNV:
3367 return 0x0EA51 << 15
3368 case AVDIVB:
3369 return 0xe1c0 << 15
3370 case AVDIVH:
3371 return 0xe1c1 << 15
3372 case AVDIVW:
3373 return 0xe1c2 << 15
3374 case AVDIVV:
3375 return 0xe1c3 << 15
3376 case AVMODB:
3377 return 0xe1c4 << 15
3378 case AVMODH:
3379 return 0xe1c5 << 15
3380 case AVMODW:
3381 return 0xe1c6 << 15
3382 case AVMODV:
3383 return 0xe1c7 << 15
3384 case AVDIVBU:
3385 return 0xe1c8 << 15
3386 case AVDIVHU:
3387 return 0xe1c9 << 15
3388 case AVDIVWU:
3389 return 0xe1ca << 15
3390 case AVDIVVU:
3391 return 0xe1cb << 15
3392 case AVMODBU:
3393 return 0xe1cc << 15
3394 case AVMODHU:
3395 return 0xe1cd << 15
3396 case AVMODWU:
3397 return 0xe1ce << 15
3398 case AVMODVU:
3399 return 0xe1cf << 15
3400 case AXVDIVB:
3401 return 0xe9c0 << 15
3402 case AXVDIVH:
3403 return 0xe9c1 << 15
3404 case AXVDIVW:
3405 return 0xe9c2 << 15
3406 case AXVDIVV:
3407 return 0xe9c3 << 15
3408 case AXVMODB:
3409 return 0xe9c4 << 15
3410 case AXVMODH:
3411 return 0xe9c5 << 15
3412 case AXVMODW:
3413 return 0xe9c6 << 15
3414 case AXVMODV:
3415 return 0xe9c7 << 15
3416 case AXVDIVBU:
3417 return 0xe9c8 << 15
3418 case AXVDIVHU:
3419 return 0xe9c9 << 15
3420 case AXVDIVWU:
3421 return 0xe9ca << 15
3422 case AXVDIVVU:
3423 return 0xe9cb << 15
3424 case AXVMODBU:
3425 return 0xe9cc << 15
3426 case AXVMODHU:
3427 return 0xe9cd << 15
3428 case AXVMODWU:
3429 return 0xe9ce << 15
3430 case AXVMODVU:
3431 return 0xe9cf << 15
3432 case AVMULWEVHB:
3433 return 0xe120 << 15
3434 case AVMULWEVWH:
3435 return 0xe121 << 15
3436 case AVMULWEVVW:
3437 return 0xe122 << 15
3438 case AVMULWEVQV:
3439 return 0xe123 << 15
3440 case AVMULWODHB:
3441 return 0xe124 << 15
3442 case AVMULWODWH:
3443 return 0xe125 << 15
3444 case AVMULWODVW:
3445 return 0xe126 << 15
3446 case AVMULWODQV:
3447 return 0xe127 << 15
3448 case AVMULWEVHBU:
3449 return 0xe130 << 15
3450 case AVMULWEVWHU:
3451 return 0xe131 << 15
3452 case AVMULWEVVWU:
3453 return 0xe132 << 15
3454 case AVMULWEVQVU:
3455 return 0xe133 << 15
3456 case AVMULWODHBU:
3457 return 0xe134 << 15
3458 case AVMULWODWHU:
3459 return 0xe135 << 15
3460 case AVMULWODVWU:
3461 return 0xe136 << 15
3462 case AVMULWODQVU:
3463 return 0xe137 << 15
3464 case AVMULWEVHBUB:
3465 return 0xe140 << 15
3466 case AVMULWEVWHUH:
3467 return 0xe141 << 15
3468 case AVMULWEVVWUW:
3469 return 0xe142 << 15
3470 case AVMULWEVQVUV:
3471 return 0xe143 << 15
3472 case AVMULWODHBUB:
3473 return 0xe144 << 15
3474 case AVMULWODWHUH:
3475 return 0xe145 << 15
3476 case AVMULWODVWUW:
3477 return 0xe146 << 15
3478 case AVMULWODQVUV:
3479 return 0xe147 << 15
3480 case AXVMULWEVHB:
3481 return 0xe920 << 15
3482 case AXVMULWEVWH:
3483 return 0xe921 << 15
3484 case AXVMULWEVVW:
3485 return 0xe922 << 15
3486 case AXVMULWEVQV:
3487 return 0xe923 << 15
3488 case AXVMULWODHB:
3489 return 0xe924 << 15
3490 case AXVMULWODWH:
3491 return 0xe925 << 15
3492 case AXVMULWODVW:
3493 return 0xe926 << 15
3494 case AXVMULWODQV:
3495 return 0xe927 << 15
3496 case AXVMULWEVHBU:
3497 return 0xe930 << 15
3498 case AXVMULWEVWHU:
3499 return 0xe931 << 15
3500 case AXVMULWEVVWU:
3501 return 0xe932 << 15
3502 case AXVMULWEVQVU:
3503 return 0xe933 << 15
3504 case AXVMULWODHBU:
3505 return 0xe934 << 15
3506 case AXVMULWODWHU:
3507 return 0xe935 << 15
3508 case AXVMULWODVWU:
3509 return 0xe936 << 15
3510 case AXVMULWODQVU:
3511 return 0xe937 << 15
3512 case AXVMULWEVHBUB:
3513 return 0xe940 << 15
3514 case AXVMULWEVWHUH:
3515 return 0xe941 << 15
3516 case AXVMULWEVVWUW:
3517 return 0xe942 << 15
3518 case AXVMULWEVQVUV:
3519 return 0xe943 << 15
3520 case AXVMULWODHBUB:
3521 return 0xe944 << 15
3522 case AXVMULWODWHUH:
3523 return 0xe945 << 15
3524 case AXVMULWODVWUW:
3525 return 0xe946 << 15
3526 case AXVMULWODQVUV:
3527 return 0xe947 << 15
3528 case AVSLLB:
3529 return 0xe1d0 << 15
3530 case AVSLLH:
3531 return 0xe1d1 << 15
3532 case AVSLLW:
3533 return 0xe1d2 << 15
3534 case AVSLLV:
3535 return 0xe1d3 << 15
3536 case AVSRLB:
3537 return 0xe1d4 << 15
3538 case AVSRLH:
3539 return 0xe1d5 << 15
3540 case AVSRLW:
3541 return 0xe1d6 << 15
3542 case AVSRLV:
3543 return 0xe1d7 << 15
3544 case AVSRAB:
3545 return 0xe1d8 << 15
3546 case AVSRAH:
3547 return 0xe1d9 << 15
3548 case AVSRAW:
3549 return 0xe1da << 15
3550 case AVSRAV:
3551 return 0xe1db << 15
3552 case AVROTRB:
3553 return 0xe1dc << 15
3554 case AVROTRH:
3555 return 0xe1dd << 15
3556 case AVROTRW:
3557 return 0xe1de << 15
3558 case AVROTRV:
3559 return 0xe1df << 15
3560 case AXVSLLB:
3561 return 0xe9d0 << 15
3562 case AXVSLLH:
3563 return 0xe9d1 << 15
3564 case AXVSLLW:
3565 return 0xe9d2 << 15
3566 case AXVSLLV:
3567 return 0xe9d3 << 15
3568 case AXVSRLB:
3569 return 0xe9d4 << 15
3570 case AXVSRLH:
3571 return 0xe9d5 << 15
3572 case AXVSRLW:
3573 return 0xe9d6 << 15
3574 case AXVSRLV:
3575 return 0xe9d7 << 15
3576 case AXVSRAB:
3577 return 0xe9d8 << 15
3578 case AXVSRAH:
3579 return 0xe9d9 << 15
3580 case AXVSRAW:
3581 return 0xe9da << 15
3582 case AXVSRAV:
3583 return 0xe9db << 15
3584 case AXVROTRB:
3585 return 0xe9dc << 15
3586 case AXVROTRH:
3587 return 0xe9dd << 15
3588 case AXVROTRW:
3589 return 0xe9de << 15
3590 case AXVROTRV:
3591 return 0xe9df << 15
3592 case AVADDB:
3593 return 0xe014 << 15
3594 case AVADDH:
3595 return 0xe015 << 15
3596 case AVADDW:
3597 return 0xe016 << 15
3598 case AVADDV:
3599 return 0xe017 << 15
3600 case AVADDQ:
3601 return 0xe25a << 15
3602 case AVSUBB:
3603 return 0xe018 << 15
3604 case AVSUBH:
3605 return 0xe019 << 15
3606 case AVSUBW:
3607 return 0xe01a << 15
3608 case AVSUBV:
3609 return 0xe01b << 15
3610 case AVSUBQ:
3611 return 0xe25b << 15
3612 case AXVADDB:
3613 return 0xe814 << 15
3614 case AXVADDH:
3615 return 0xe815 << 15
3616 case AXVADDW:
3617 return 0xe816 << 15
3618 case AXVADDV:
3619 return 0xe817 << 15
3620 case AXVADDQ:
3621 return 0xea5a << 15
3622 case AXVSUBB:
3623 return 0xe818 << 15
3624 case AXVSUBH:
3625 return 0xe819 << 15
3626 case AXVSUBW:
3627 return 0xe81a << 15
3628 case AXVSUBV:
3629 return 0xe81b << 15
3630 case AXVSUBQ:
3631 return 0xea5b << 15
3632 case AVILVLB:
3633 return 0xe234 << 15
3634 case AVILVLH:
3635 return 0xe235 << 15
3636 case AVILVLW:
3637 return 0xe236 << 15
3638 case AVILVLV:
3639 return 0xe237 << 15
3640 case AVILVHB:
3641 return 0xe238 << 15
3642 case AVILVHH:
3643 return 0xe239 << 15
3644 case AVILVHW:
3645 return 0xe23a << 15
3646 case AVILVHV:
3647 return 0xe23b << 15
3648 case AXVILVLB:
3649 return 0xea34 << 15
3650 case AXVILVLH:
3651 return 0xea35 << 15
3652 case AXVILVLW:
3653 return 0xea36 << 15
3654 case AXVILVLV:
3655 return 0xea37 << 15
3656 case AXVILVHB:
3657 return 0xea38 << 15
3658 case AXVILVHH:
3659 return 0xea39 << 15
3660 case AXVILVHW:
3661 return 0xea3a << 15
3662 case AXVILVHV:
3663 return 0xea3b << 15
3664 case AVMULB:
3665 return 0xe108 << 15
3666 case AVMULH:
3667 return 0xe109 << 15
3668 case AVMULW:
3669 return 0xe10a << 15
3670 case AVMULV:
3671 return 0xe10b << 15
3672 case AVMUHB:
3673 return 0xe10c << 15
3674 case AVMUHH:
3675 return 0xe10d << 15
3676 case AVMUHW:
3677 return 0xe10e << 15
3678 case AVMUHV:
3679 return 0xe10f << 15
3680 case AVMUHBU:
3681 return 0xe110 << 15
3682 case AVMUHHU:
3683 return 0xe111 << 15
3684 case AVMUHWU:
3685 return 0xe112 << 15
3686 case AVMUHVU:
3687 return 0xe113 << 15
3688 case AXVMULB:
3689 return 0xe908 << 15
3690 case AXVMULH:
3691 return 0xe909 << 15
3692 case AXVMULW:
3693 return 0xe90a << 15
3694 case AXVMULV:
3695 return 0xe90b << 15
3696 case AXVMUHB:
3697 return 0xe90c << 15
3698 case AXVMUHH:
3699 return 0xe90d << 15
3700 case AXVMUHW:
3701 return 0xe90e << 15
3702 case AXVMUHV:
3703 return 0xe90f << 15
3704 case AXVMUHBU:
3705 return 0xe910 << 15
3706 case AXVMUHHU:
3707 return 0xe911 << 15
3708 case AXVMUHWU:
3709 return 0xe912 << 15
3710 case AXVMUHVU:
3711 return 0xe913 << 15
3712 case AVADDF:
3713 return 0xe261 << 15
3714 case AVADDD:
3715 return 0xe262 << 15
3716 case AVSUBF:
3717 return 0xe265 << 15
3718 case AVSUBD:
3719 return 0xe266 << 15
3720 case AVMULF:
3721 return 0xe271 << 15
3722 case AVMULD:
3723 return 0xe272 << 15
3724 case AVDIVF:
3725 return 0xe275 << 15
3726 case AVDIVD:
3727 return 0xe276 << 15
3728 case AXVADDF:
3729 return 0xea61 << 15
3730 case AXVADDD:
3731 return 0xea62 << 15
3732 case AXVSUBF:
3733 return 0xea65 << 15
3734 case AXVSUBD:
3735 return 0xea66 << 15
3736 case AXVMULF:
3737 return 0xea71 << 15
3738 case AXVMULD:
3739 return 0xea72 << 15
3740 case AXVDIVF:
3741 return 0xea75 << 15
3742 case AXVDIVD:
3743 return 0xea76 << 15
3744 case AVBITCLRB:
3745 return 0xe218 << 15
3746 case AVBITCLRH:
3747 return 0xe219 << 15
3748 case AVBITCLRW:
3749 return 0xe21a << 15
3750 case AVBITCLRV:
3751 return 0xe21b << 15
3752 case AVBITSETB:
3753 return 0xe21c << 15
3754 case AVBITSETH:
3755 return 0xe21d << 15
3756 case AVBITSETW:
3757 return 0xe21e << 15
3758 case AVBITSETV:
3759 return 0xe21f << 15
3760 case AVBITREVB:
3761 return 0xe220 << 15
3762 case AVBITREVH:
3763 return 0xe221 << 15
3764 case AVBITREVW:
3765 return 0xe222 << 15
3766 case AVBITREVV:
3767 return 0xe223 << 15
3768 case AXVBITCLRB:
3769 return 0xea18 << 15
3770 case AXVBITCLRH:
3771 return 0xea19 << 15
3772 case AXVBITCLRW:
3773 return 0xea1a << 15
3774 case AXVBITCLRV:
3775 return 0xea1b << 15
3776 case AXVBITSETB:
3777 return 0xea1c << 15
3778 case AXVBITSETH:
3779 return 0xea1d << 15
3780 case AXVBITSETW:
3781 return 0xea1e << 15
3782 case AXVBITSETV:
3783 return 0xea1f << 15
3784 case AXVBITREVB:
3785 return 0xea20 << 15
3786 case AXVBITREVH:
3787 return 0xea21 << 15
3788 case AXVBITREVW:
3789 return 0xea22 << 15
3790 case AXVBITREVV:
3791 return 0xea23 << 15
3792 case AVSHUFH:
3793 return 0x0E2F5 << 15
3794 case AVSHUFW:
3795 return 0x0E2F6 << 15
3796 case AVSHUFV:
3797 return 0x0E2F7 << 15
3798 case AXVSHUFH:
3799 return 0x0EAF5 << 15
3800 case AXVSHUFW:
3801 return 0x0EAF6 << 15
3802 case AXVSHUFV:
3803 return 0x0EAF7 << 15
3804 }
3805
3806 if a < 0 {
3807 c.ctxt.Diag("bad rrr opcode -%v", -a)
3808 } else {
3809 c.ctxt.Diag("bad rrr opcode %v", a)
3810 }
3811 return 0
3812 }
3813
3814 func (c *ctxt0) oprr(a obj.As) uint32 {
3815 switch a {
3816 case ACLOW:
3817 return 0x4 << 10
3818 case ACLZW:
3819 return 0x5 << 10
3820 case ACTOW:
3821 return 0x6 << 10
3822 case ACTZW:
3823 return 0x7 << 10
3824 case ACLOV:
3825 return 0x8 << 10
3826 case ACLZV:
3827 return 0x9 << 10
3828 case ACTOV:
3829 return 0xa << 10
3830 case ACTZV:
3831 return 0xb << 10
3832 case AREVB2H:
3833 return 0xc << 10
3834 case AREVB4H:
3835 return 0xd << 10
3836 case AREVB2W:
3837 return 0xe << 10
3838 case AREVBV:
3839 return 0xf << 10
3840 case AREVH2W:
3841 return 0x10 << 10
3842 case AREVHV:
3843 return 0x11 << 10
3844 case ABITREV4B:
3845 return 0x12 << 10
3846 case ABITREV8B:
3847 return 0x13 << 10
3848 case ABITREVW:
3849 return 0x14 << 10
3850 case ABITREVV:
3851 return 0x15 << 10
3852 case AEXTWH:
3853 return 0x16 << 10
3854 case AEXTWB:
3855 return 0x17 << 10
3856 case ACPUCFG:
3857 return 0x1b << 10
3858 case ARDTIMELW:
3859 return 0x18 << 10
3860 case ARDTIMEHW:
3861 return 0x19 << 10
3862 case ARDTIMED:
3863 return 0x1a << 10
3864 case ATRUNCFV:
3865 return 0x46a9 << 10
3866 case ATRUNCDV:
3867 return 0x46aa << 10
3868 case ATRUNCFW:
3869 return 0x46a1 << 10
3870 case ATRUNCDW:
3871 return 0x46a2 << 10
3872 case AMOVFV:
3873 return 0x46c9 << 10
3874 case AMOVDV:
3875 return 0x46ca << 10
3876 case AMOVVF:
3877 return 0x4746 << 10
3878 case AMOVVD:
3879 return 0x474a << 10
3880 case AMOVFW:
3881 return 0x46c1 << 10
3882 case AMOVDW:
3883 return 0x46c2 << 10
3884 case AMOVWF:
3885 return 0x4744 << 10
3886 case AMOVDF:
3887 return 0x4646 << 10
3888 case AMOVWD:
3889 return 0x4748 << 10
3890 case AMOVFD:
3891 return 0x4649 << 10
3892 case AABSF:
3893 return 0x4501 << 10
3894 case AABSD:
3895 return 0x4502 << 10
3896 case AMOVF:
3897 return 0x4525 << 10
3898 case AMOVD:
3899 return 0x4526 << 10
3900 case ANEGF:
3901 return 0x4505 << 10
3902 case ANEGD:
3903 return 0x4506 << 10
3904 case ASQRTF:
3905 return 0x4511 << 10
3906 case ASQRTD:
3907 return 0x4512 << 10
3908 case AFLOGBF:
3909 return 0x4509 << 10
3910 case AFLOGBD:
3911 return 0x450a << 10
3912 case AFCLASSF:
3913 return 0x450d << 10
3914 case AFCLASSD:
3915 return 0x450e << 10
3916 case AFFINTFW:
3917 return 0x4744 << 10
3918 case AFFINTFV:
3919 return 0x4746 << 10
3920 case AFFINTDW:
3921 return 0x4748 << 10
3922 case AFFINTDV:
3923 return 0x474a << 10
3924 case AFTINTWF:
3925 return 0x46c1 << 10
3926 case AFTINTWD:
3927 return 0x46c2 << 10
3928 case AFTINTVF:
3929 return 0x46c9 << 10
3930 case AFTINTVD:
3931 return 0x46ca << 10
3932 case AFTINTRMWF:
3933 return 0x4681 << 10
3934 case AFTINTRMWD:
3935 return 0x4682 << 10
3936 case AFTINTRMVF:
3937 return 0x4689 << 10
3938 case AFTINTRMVD:
3939 return 0x468a << 10
3940 case AFTINTRPWF:
3941 return 0x4691 << 10
3942 case AFTINTRPWD:
3943 return 0x4692 << 10
3944 case AFTINTRPVF:
3945 return 0x4699 << 10
3946 case AFTINTRPVD:
3947 return 0x469a << 10
3948 case AFTINTRZWF:
3949 return 0x46a1 << 10
3950 case AFTINTRZWD:
3951 return 0x46a2 << 10
3952 case AFTINTRZVF:
3953 return 0x46a9 << 10
3954 case AFTINTRZVD:
3955 return 0x46aa << 10
3956 case AFTINTRNEWF:
3957 return 0x46b1 << 10
3958 case AFTINTRNEWD:
3959 return 0x46b2 << 10
3960 case AFTINTRNEVF:
3961 return 0x46b9 << 10
3962 case AFTINTRNEVD:
3963 return 0x46ba << 10
3964 case AVPCNTB:
3965 return 0x1ca708 << 10
3966 case AVPCNTH:
3967 return 0x1ca709 << 10
3968 case AVPCNTW:
3969 return 0x1ca70a << 10
3970 case AVPCNTV:
3971 return 0x1ca70b << 10
3972 case AXVPCNTB:
3973 return 0x1da708 << 10
3974 case AXVPCNTH:
3975 return 0x1da709 << 10
3976 case AXVPCNTW:
3977 return 0x1da70a << 10
3978 case AXVPCNTV:
3979 return 0x1da70b << 10
3980 case AVFSQRTF:
3981 return 0x1ca739 << 10
3982 case AVFSQRTD:
3983 return 0x1ca73a << 10
3984 case AVFRECIPF:
3985 return 0x1ca73d << 10
3986 case AVFRECIPD:
3987 return 0x1ca73e << 10
3988 case AVFRSQRTF:
3989 return 0x1ca741 << 10
3990 case AVFRSQRTD:
3991 return 0x1ca742 << 10
3992 case AXVFSQRTF:
3993 return 0x1da739 << 10
3994 case AXVFSQRTD:
3995 return 0x1da73a << 10
3996 case AXVFRECIPF:
3997 return 0x1da73d << 10
3998 case AXVFRECIPD:
3999 return 0x1da73e << 10
4000 case AXVFRSQRTF:
4001 return 0x1da741 << 10
4002 case AXVFRSQRTD:
4003 return 0x1da742 << 10
4004 case AVNEGB:
4005 return 0x1ca70c << 10
4006 case AVNEGH:
4007 return 0x1ca70d << 10
4008 case AVNEGW:
4009 return 0x1ca70e << 10
4010 case AVNEGV:
4011 return 0x1ca70f << 10
4012 case AXVNEGB:
4013 return 0x1da70c << 10
4014 case AXVNEGH:
4015 return 0x1da70d << 10
4016 case AXVNEGW:
4017 return 0x1da70e << 10
4018 case AXVNEGV:
4019 return 0x1da70f << 10
4020 case AVFRINTRNEF:
4021 return 0x1ca75d << 10
4022 case AVFRINTRNED:
4023 return 0x1ca75e << 10
4024 case AVFRINTRZF:
4025 return 0x1ca759 << 10
4026 case AVFRINTRZD:
4027 return 0x1ca75a << 10
4028 case AVFRINTRPF:
4029 return 0x1ca755 << 10
4030 case AVFRINTRPD:
4031 return 0x1ca756 << 10
4032 case AVFRINTRMF:
4033 return 0x1ca751 << 10
4034 case AVFRINTRMD:
4035 return 0x1ca752 << 10
4036 case AVFRINTF:
4037 return 0x1ca74d << 10
4038 case AVFRINTD:
4039 return 0x1ca74e << 10
4040 case AXVFRINTRNEF:
4041 return 0x1da75d << 10
4042 case AXVFRINTRNED:
4043 return 0x1da75e << 10
4044 case AXVFRINTRZF:
4045 return 0x1da759 << 10
4046 case AXVFRINTRZD:
4047 return 0x1da75a << 10
4048 case AXVFRINTRPF:
4049 return 0x1da755 << 10
4050 case AXVFRINTRPD:
4051 return 0x1da756 << 10
4052 case AXVFRINTRMF:
4053 return 0x1da751 << 10
4054 case AXVFRINTRMD:
4055 return 0x1da752 << 10
4056 case AXVFRINTF:
4057 return 0x1da74d << 10
4058 case AXVFRINTD:
4059 return 0x1da74e << 10
4060 case AVFCLASSF:
4061 return 0x1ca735 << 10
4062 case AVFCLASSD:
4063 return 0x1ca736 << 10
4064 case AXVFCLASSF:
4065 return 0x1da735 << 10
4066 case AXVFCLASSD:
4067 return 0x1da736 << 10
4068 case AVSETEQV:
4069 return 0x1ca726<<10 | 0x0<<3
4070 case AVSETNEV:
4071 return 0x1ca727<<10 | 0x0<<3
4072 case AVSETANYEQB:
4073 return 0x1ca728<<10 | 0x0<<3
4074 case AVSETANYEQH:
4075 return 0x1ca729<<10 | 0x0<<3
4076 case AVSETANYEQW:
4077 return 0x1ca72a<<10 | 0x0<<3
4078 case AVSETANYEQV:
4079 return 0x1ca72b<<10 | 0x0<<3
4080 case AVSETALLNEB:
4081 return 0x1ca72c<<10 | 0x0<<3
4082 case AVSETALLNEH:
4083 return 0x1ca72d<<10 | 0x0<<3
4084 case AVSETALLNEW:
4085 return 0x1ca72e<<10 | 0x0<<3
4086 case AVSETALLNEV:
4087 return 0x1ca72f<<10 | 0x0<<3
4088 case AXVSETEQV:
4089 return 0x1da726<<10 | 0x0<<3
4090 case AXVSETNEV:
4091 return 0x1da727<<10 | 0x0<<3
4092 case AXVSETANYEQB:
4093 return 0x1da728<<10 | 0x0<<3
4094 case AXVSETANYEQH:
4095 return 0x1da729<<10 | 0x0<<3
4096 case AXVSETANYEQW:
4097 return 0x1da72a<<10 | 0x0<<3
4098 case AXVSETANYEQV:
4099 return 0x1da72b<<10 | 0x0<<3
4100 case AXVSETALLNEB:
4101 return 0x1da72c<<10 | 0x0<<3
4102 case AXVSETALLNEH:
4103 return 0x1da72d<<10 | 0x0<<3
4104 case AXVSETALLNEW:
4105 return 0x1da72e<<10 | 0x0<<3
4106 case AXVSETALLNEV:
4107 return 0x1da72f<<10 | 0x0<<3
4108 }
4109
4110 c.ctxt.Diag("bad rr opcode %v", a)
4111 return 0
4112 }
4113
4114 func (c *ctxt0) opi(a obj.As) uint32 {
4115 switch a {
4116 case ASYSCALL:
4117 return 0x56 << 15
4118 case ABREAK:
4119 return 0x54 << 15
4120 case ADBAR:
4121 return 0x70e4 << 15
4122 }
4123
4124 c.ctxt.Diag("bad ic opcode %v", a)
4125
4126 return 0
4127 }
4128
4129 func (c *ctxt0) opir(a obj.As) uint32 {
4130 switch a {
4131 case ALU12IW:
4132 return 0x0a << 25
4133 case ALU32ID:
4134 return 0x0b << 25
4135 case APCALAU12I:
4136 return 0x0d << 25
4137 case APCADDU12I:
4138 return 0x0e << 25
4139 }
4140 return 0
4141 }
4142
4143 func (c *ctxt0) opirr(a obj.As) uint32 {
4144 switch a {
4145 case AADD, AADDU:
4146 return 0x00a << 22
4147 case ASGT:
4148 return 0x008 << 22
4149 case ASGTU:
4150 return 0x009 << 22
4151 case AAND:
4152 return 0x00d << 22
4153 case AOR:
4154 return 0x00e << 22
4155 case ALU52ID:
4156 return 0x00c << 22
4157 case AXOR:
4158 return 0x00f << 22
4159 case ASLL:
4160 return 0x00081 << 15
4161 case ASRL:
4162 return 0x00089 << 15
4163 case ASRA:
4164 return 0x00091 << 15
4165 case AROTR:
4166 return 0x00099 << 15
4167 case AADDV:
4168 return 0x00b << 22
4169 case AADDVU:
4170 return 0x00b << 22
4171 case AADDV16:
4172 return 0x4 << 26
4173
4174 case AJMP:
4175 return 0x14 << 26
4176 case AJAL:
4177 return 0x15 << 26
4178
4179 case AJIRL:
4180 return 0x13 << 26
4181 case ABLTU:
4182 return 0x1a << 26
4183 case ABLT, ABLTZ, ABGTZ:
4184 return 0x18 << 26
4185 case ABGEU:
4186 return 0x1b << 26
4187 case ABGE, ABGEZ, ABLEZ:
4188 return 0x19 << 26
4189 case -ABEQ:
4190 return 0x10 << 26
4191 case -ABNE:
4192 return 0x11 << 26
4193 case ABEQ:
4194 return 0x16 << 26
4195 case ABNE:
4196 return 0x17 << 26
4197 case ABFPT:
4198 return 0x12<<26 | 0x1<<8
4199 case ABFPF:
4200 return 0x12<<26 | 0x0<<8
4201 case APRELDX:
4202 return 0x07058 << 15
4203 case AMOVB,
4204 AMOVBU:
4205 return 0x0a4 << 22
4206 case AMOVH,
4207 AMOVHU:
4208 return 0x0a5 << 22
4209 case AMOVW,
4210 AMOVWU:
4211 return 0x0a6 << 22
4212 case AMOVV:
4213 return 0x0a7 << 22
4214 case AMOVF:
4215 return 0x0ad << 22
4216 case AMOVD:
4217 return 0x0af << 22
4218 case AMOVVP:
4219 return 0x27 << 24
4220 case AMOVWP:
4221 return 0x25 << 24
4222 case -AMOVB:
4223 return 0x0a0 << 22
4224 case -AMOVBU:
4225 return 0x0a8 << 22
4226 case -AMOVH:
4227 return 0x0a1 << 22
4228 case -AMOVHU:
4229 return 0x0a9 << 22
4230 case -AMOVW:
4231 return 0x0a2 << 22
4232 case -AMOVWU:
4233 return 0x0aa << 22
4234 case -AMOVV:
4235 return 0x0a3 << 22
4236 case -AMOVF:
4237 return 0x0ac << 22
4238 case -AMOVD:
4239 return 0x0ae << 22
4240 case -AMOVVP:
4241 return 0x26 << 24
4242 case -AMOVWP:
4243 return 0x24 << 24
4244 case -AVMOVQ:
4245 return 0x0b0 << 22
4246 case -AXVMOVQ:
4247 return 0x0b2 << 22
4248 case AVMOVQ:
4249 return 0x0b1 << 22
4250 case AXVMOVQ:
4251 return 0x0b3 << 22
4252 case ASLLV:
4253 return 0x0041 << 16
4254 case ASRLV:
4255 return 0x0045 << 16
4256 case ASRAV:
4257 return 0x0049 << 16
4258 case AROTRV:
4259 return 0x004d << 16
4260 case -ALL:
4261 return 0x020 << 24
4262 case -ALLV:
4263 return 0x022 << 24
4264 case ASC:
4265 return 0x021 << 24
4266 case ASCV:
4267 return 0x023 << 24
4268 case AVANDB:
4269 return 0x1CF4 << 18
4270 case AVORB:
4271 return 0x1CF5 << 18
4272 case AVXORB:
4273 return 0x1CF6 << 18
4274 case AVNORB:
4275 return 0x1CF7 << 18
4276 case AXVANDB:
4277 return 0x1DF4 << 18
4278 case AXVORB:
4279 return 0x1DF5 << 18
4280 case AXVXORB:
4281 return 0x1DF6 << 18
4282 case AXVNORB:
4283 return 0x1DF7 << 18
4284 case AVSEQB:
4285 return 0x0E500 << 15
4286 case AVSEQH:
4287 return 0x0E501 << 15
4288 case AVSEQW:
4289 return 0x0E502 << 15
4290 case AVSEQV:
4291 return 0x0E503 << 15
4292 case AXVSEQB:
4293 return 0x0ED00 << 15
4294 case AXVSEQH:
4295 return 0x0ED01 << 15
4296 case AXVSEQW:
4297 return 0x0ED02 << 15
4298 case AXVSEQV:
4299 return 0x0ED03 << 15
4300 case AVROTRB:
4301 return 0x1ca8<<18 | 0x1<<13
4302 case AVROTRH:
4303 return 0x1ca8<<18 | 0x1<<14
4304 case AVROTRW:
4305 return 0x1ca8<<18 | 0x1<<15
4306 case AVROTRV:
4307 return 0x1ca8<<18 | 0x1<<16
4308 case AXVROTRB:
4309 return 0x1da8<<18 | 0x1<<13
4310 case AXVROTRH:
4311 return 0x1da8<<18 | 0x1<<14
4312 case AXVROTRW:
4313 return 0x1da8<<18 | 0x1<<15
4314 case AXVROTRV:
4315 return 0x1da8<<18 | 0x1<<16
4316 case AVSLLB:
4317 return 0x1ccb<<18 | 0x1<<13
4318 case AVSLLH:
4319 return 0x1ccb<<18 | 0x1<<14
4320 case AVSLLW:
4321 return 0x1ccb<<18 | 0x1<<15
4322 case AVSLLV:
4323 return 0x1ccb<<18 | 0x1<<16
4324 case AVSRLB:
4325 return 0x1ccc<<18 | 0x1<<13
4326 case AVSRLH:
4327 return 0x1ccc<<18 | 0x1<<14
4328 case AVSRLW:
4329 return 0x1ccc<<18 | 0x1<<15
4330 case AVSRLV:
4331 return 0x1ccc<<18 | 0x1<<16
4332 case AVSRAB:
4333 return 0x1ccd<<18 | 0x1<<13
4334 case AVSRAH:
4335 return 0x1ccd<<18 | 0x1<<14
4336 case AVSRAW:
4337 return 0x1ccd<<18 | 0x1<<15
4338 case AVSRAV:
4339 return 0x1ccd<<18 | 0x1<<16
4340 case AXVSLLB:
4341 return 0x1dcb<<18 | 0x1<<13
4342 case AXVSLLH:
4343 return 0x1dcb<<18 | 0x1<<14
4344 case AXVSLLW:
4345 return 0x1dcb<<18 | 0x1<<15
4346 case AXVSLLV:
4347 return 0x1dcb<<18 | 0x1<<16
4348 case AXVSRLB:
4349 return 0x1dcc<<18 | 0x1<<13
4350 case AXVSRLH:
4351 return 0x1dcc<<18 | 0x1<<14
4352 case AXVSRLW:
4353 return 0x1dcc<<18 | 0x1<<15
4354 case AXVSRLV:
4355 return 0x1dcc<<18 | 0x1<<16
4356 case AXVSRAB:
4357 return 0x1dcd<<18 | 0x1<<13
4358 case AXVSRAH:
4359 return 0x1dcd<<18 | 0x1<<14
4360 case AXVSRAW:
4361 return 0x1dcd<<18 | 0x1<<15
4362 case AXVSRAV:
4363 return 0x1dcd<<18 | 0x1<<16
4364 case AVADDBU:
4365 return 0xe514 << 15
4366 case AVADDHU:
4367 return 0xe515 << 15
4368 case AVADDWU:
4369 return 0xe516 << 15
4370 case AVADDVU:
4371 return 0xe517 << 15
4372 case AVSUBBU:
4373 return 0xe518 << 15
4374 case AVSUBHU:
4375 return 0xe519 << 15
4376 case AVSUBWU:
4377 return 0xe51a << 15
4378 case AVSUBVU:
4379 return 0xe51b << 15
4380 case AXVADDBU:
4381 return 0xed14 << 15
4382 case AXVADDHU:
4383 return 0xed15 << 15
4384 case AXVADDWU:
4385 return 0xed16 << 15
4386 case AXVADDVU:
4387 return 0xed17 << 15
4388 case AXVSUBBU:
4389 return 0xed18 << 15
4390 case AXVSUBHU:
4391 return 0xed19 << 15
4392 case AXVSUBWU:
4393 return 0xed1a << 15
4394 case AXVSUBVU:
4395 return 0xed1b << 15
4396 case AVSHUF4IB:
4397 return 0x1ce4 << 18
4398 case AVSHUF4IH:
4399 return 0x1ce5 << 18
4400 case AVSHUF4IW:
4401 return 0x1ce6 << 18
4402 case AVSHUF4IV:
4403 return 0x1ce7 << 18
4404 case AXVSHUF4IB:
4405 return 0x1de4 << 18
4406 case AXVSHUF4IH:
4407 return 0x1de5 << 18
4408 case AXVSHUF4IW:
4409 return 0x1de6 << 18
4410 case AXVSHUF4IV:
4411 return 0x1de7 << 18
4412 case AVPERMIW:
4413 return 0x1cf9 << 18
4414 case AXVPERMIW:
4415 return 0x1df9 << 18
4416 case AXVPERMIV:
4417 return 0x1dfa << 18
4418 case AXVPERMIQ:
4419 return 0x1dfb << 18
4420 case AVEXTRINSB:
4421 return 0x1ce3 << 18
4422 case AVEXTRINSH:
4423 return 0x1ce2 << 18
4424 case AVEXTRINSW:
4425 return 0x1ce1 << 18
4426 case AVEXTRINSV:
4427 return 0x1ce0 << 18
4428 case AXVEXTRINSB:
4429 return 0x1de3 << 18
4430 case AXVEXTRINSH:
4431 return 0x1de2 << 18
4432 case AXVEXTRINSW:
4433 return 0x1de1 << 18
4434 case AXVEXTRINSV:
4435 return 0x1de0 << 18
4436 case AVBITCLRB:
4437 return 0x1CC4<<18 | 0x1<<13
4438 case AVBITCLRH:
4439 return 0x1CC4<<18 | 0x1<<14
4440 case AVBITCLRW:
4441 return 0x1CC4<<18 | 0x1<<15
4442 case AVBITCLRV:
4443 return 0x1CC4<<18 | 0x1<<16
4444 case AVBITSETB:
4445 return 0x1CC5<<18 | 0x1<<13
4446 case AVBITSETH:
4447 return 0x1CC5<<18 | 0x1<<14
4448 case AVBITSETW:
4449 return 0x1CC5<<18 | 0x1<<15
4450 case AVBITSETV:
4451 return 0x1CC5<<18 | 0x1<<16
4452 case AVBITREVB:
4453 return 0x1CC6<<18 | 0x1<<13
4454 case AVBITREVH:
4455 return 0x1CC6<<18 | 0x1<<14
4456 case AVBITREVW:
4457 return 0x1CC6<<18 | 0x1<<15
4458 case AVBITREVV:
4459 return 0x1CC6<<18 | 0x1<<16
4460 case AXVBITCLRB:
4461 return 0x1DC4<<18 | 0x1<<13
4462 case AXVBITCLRH:
4463 return 0x1DC4<<18 | 0x1<<14
4464 case AXVBITCLRW:
4465 return 0x1DC4<<18 | 0x1<<15
4466 case AXVBITCLRV:
4467 return 0x1DC4<<18 | 0x1<<16
4468 case AXVBITSETB:
4469 return 0x1DC5<<18 | 0x1<<13
4470 case AXVBITSETH:
4471 return 0x1DC5<<18 | 0x1<<14
4472 case AXVBITSETW:
4473 return 0x1DC5<<18 | 0x1<<15
4474 case AXVBITSETV:
4475 return 0x1DC5<<18 | 0x1<<16
4476 case AXVBITREVB:
4477 return 0x1DC6<<18 | 0x1<<13
4478 case AXVBITREVH:
4479 return 0x1DC6<<18 | 0x1<<14
4480 case AXVBITREVW:
4481 return 0x1DC6<<18 | 0x1<<15
4482 case AXVBITREVV:
4483 return 0x1DC6<<18 | 0x1<<16
4484 }
4485
4486 if a < 0 {
4487 c.ctxt.Diag("bad irr opcode -%v", -a)
4488 } else {
4489 c.ctxt.Diag("bad irr opcode %v", a)
4490 }
4491 return 0
4492 }
4493
4494 func (c *ctxt0) opirrr(a obj.As) uint32 {
4495 switch a {
4496 case AALSLW:
4497 return 0x2 << 17
4498 case AALSLWU:
4499 return 0x3 << 17
4500 case AALSLV:
4501 return 0x16 << 17
4502 }
4503
4504 return 0
4505 }
4506
4507 func (c *ctxt0) opirir(a obj.As) uint32 {
4508 switch a {
4509 case ABSTRINSW:
4510 return 0x3<<21 | 0x0<<15
4511 case ABSTRINSV:
4512 return 0x2 << 22
4513 case ABSTRPICKW:
4514 return 0x3<<21 | 0x1<<15
4515 case ABSTRPICKV:
4516 return 0x3 << 22
4517 }
4518
4519 return 0
4520 }
4521
4522 func (c *ctxt0) opiir(a obj.As) uint32 {
4523 switch a {
4524 case APRELD:
4525 return 0x0AB << 22
4526 }
4527
4528 return 0
4529 }
4530
4531 func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 {
4532 switch a {
4533 case AMOVV:
4534 switch fclass {
4535 case C_REG:
4536 switch tclass {
4537 case C_FREG:
4538 return 0x452a << 10
4539 case C_FCCREG:
4540 return 0x4536 << 10
4541 case C_FCSRREG:
4542 return 0x4530 << 10
4543 }
4544 case C_FREG:
4545 switch tclass {
4546 case C_REG:
4547 return 0x452e << 10
4548 case C_FCCREG:
4549 return 0x4534 << 10
4550 }
4551 case C_FCCREG:
4552 switch tclass {
4553 case C_REG:
4554 return 0x4537 << 10
4555 case C_FREG:
4556 return 0x4535 << 10
4557 }
4558 case C_FCSRREG:
4559 switch tclass {
4560 case C_REG:
4561 return 0x4532 << 10
4562 }
4563 }
4564
4565 case AMOVW:
4566 switch fclass {
4567 case C_REG:
4568 switch tclass {
4569 case C_FREG:
4570 return 0x4529 << 10
4571 }
4572 case C_FREG:
4573 switch tclass {
4574 case C_REG:
4575 return 0x452d << 10
4576 }
4577 }
4578 }
4579
4580 c.ctxt.Diag("bad class combination: %s %d,%d\n", a, fclass, tclass)
4581
4582 return 0
4583 }
4584
4585 func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) {
4586 farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
4587 tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
4588 fclass := c.rclass(fReg)
4589 tclass := c.rclass(tReg)
4590
4591 switch fclass | (tclass << 16) {
4592 case C_REG | (C_ELEM << 16):
4593
4594 switch a {
4595 case AVMOVQ:
4596 switch tarng {
4597 case ARNG_B:
4598 return (0x01CBAE << 14), 0xf
4599 case ARNG_H:
4600 return (0x03975E << 13), 0x7
4601 case ARNG_W:
4602 return (0x072EBE << 12), 0x3
4603 case ARNG_V:
4604 return (0x0E5D7E << 11), 0x1
4605 }
4606 case AXVMOVQ:
4607 switch tarng {
4608 case ARNG_W:
4609 return (0x03B75E << 13), 0x7
4610 case ARNG_V:
4611 return (0x076EBE << 12), 0x3
4612 }
4613 }
4614
4615 case C_ELEM | (C_REG << 16):
4616
4617 switch a {
4618 case AVMOVQ:
4619 switch farng {
4620 case ARNG_B:
4621 return (0x01CBBE << 14), 0xf
4622 case ARNG_H:
4623 return (0x03977E << 13), 0x7
4624 case ARNG_W:
4625 return (0x072EFE << 12), 0x3
4626 case ARNG_V:
4627 return (0x0E5DFE << 11), 0x1
4628 case ARNG_BU:
4629 return (0x01CBCE << 14), 0xf
4630 case ARNG_HU:
4631 return (0x03979E << 13), 0x7
4632 case ARNG_WU:
4633 return (0x072F3E << 12), 0x3
4634 case ARNG_VU:
4635 return (0x0E5E7E << 11), 0x1
4636 }
4637 case AXVMOVQ:
4638 switch farng {
4639 case ARNG_W:
4640 return (0x03B77E << 13), 0x7
4641 case ARNG_V:
4642 return (0x076EFE << 12), 0x3
4643 case ARNG_WU:
4644 return (0x03B79E << 13), 0x7
4645 case ARNG_VU:
4646 return (0x076F3E << 12), 0x3
4647 }
4648 }
4649
4650 case C_REG | (C_ARNG << 16):
4651 switch {
4652 case offset_flag:
4653
4654 switch a {
4655 case AVMOVQ:
4656 switch tarng {
4657 case ARNG_16B:
4658 return (0xC2 << 22), 0x0
4659 case ARNG_8H:
4660 return (0x182 << 21), 0x0
4661 case ARNG_4W:
4662 return (0x302 << 20), 0x0
4663 case ARNG_2V:
4664 return (0x602 << 19), 0x0
4665 }
4666 case AXVMOVQ:
4667 switch tarng {
4668 case ARNG_32B:
4669 return (0xCA << 22), 0x0
4670 case ARNG_16H:
4671 return (0x192 << 21), 0x0
4672 case ARNG_8W:
4673 return (0x322 << 20), 0x0
4674 case ARNG_4V:
4675 return (0x642 << 19), 0x0
4676 }
4677 }
4678 default:
4679
4680 switch a {
4681 case AVMOVQ:
4682 switch tarng {
4683 case ARNG_16B:
4684 return (0x1CA7C0 << 10), 0x0
4685 case ARNG_8H:
4686 return (0x1CA7C1 << 10), 0x0
4687 case ARNG_4W:
4688 return (0x1CA7C2 << 10), 0x0
4689 case ARNG_2V:
4690 return (0x1CA7C3 << 10), 0x0
4691 }
4692 case AXVMOVQ:
4693 switch tarng {
4694 case ARNG_32B:
4695 return (0x1DA7C0 << 10), 0x0
4696 case ARNG_16H:
4697 return (0x1DA7C1 << 10), 0x0
4698 case ARNG_8W:
4699 return (0x1DA7C2 << 10), 0x0
4700 case ARNG_4V:
4701 return (0x1DA7C3 << 10), 0x0
4702 }
4703 }
4704 }
4705
4706 case C_XREG | (C_ARNG << 16):
4707
4708 switch a {
4709 case AVMOVQ:
4710 return 0, 0
4711 case AXVMOVQ:
4712 switch tarng {
4713 case ARNG_32B:
4714 return (0x1DC1C0 << 10), 0x0
4715 case ARNG_16H:
4716 return (0x1DC1E0 << 10), 0x0
4717 case ARNG_8W:
4718 return (0x1DC1F0 << 10), 0x0
4719 case ARNG_4V:
4720 return (0x1DC1F8 << 10), 0x0
4721 case ARNG_2Q:
4722 return (0x1DC1FC << 10), 0x0
4723 }
4724 }
4725
4726 case C_XREG | (C_ELEM << 16):
4727
4728 switch a {
4729 case AVMOVQ:
4730 return 0, 0
4731 case AXVMOVQ:
4732 switch tarng {
4733 case ARNG_W:
4734 return (0x03B7FE << 13), 0x7
4735 case ARNG_V:
4736 return (0x076FFE << 12), 0x3
4737 }
4738 }
4739
4740 case C_ELEM | (C_XREG << 16):
4741
4742 switch a {
4743 case AVMOVQ:
4744 return 0, 0
4745 case AXVMOVQ:
4746 switch farng {
4747 case ARNG_W:
4748 return (0x03B81E << 13), 0x7
4749 case ARNG_V:
4750 return (0x07703E << 12), 0x3
4751 }
4752 }
4753
4754 case C_ELEM | (C_ARNG << 16):
4755
4756 switch a {
4757 case AVMOVQ:
4758 switch int32(farng) | (int32(tarng) << 16) {
4759 case int32(ARNG_B) | (int32(ARNG_16B) << 16):
4760 return (0x01CBDE << 14), 0xf
4761 case int32(ARNG_H) | (int32(ARNG_8H) << 16):
4762 return (0x0397BE << 13), 0x7
4763 case int32(ARNG_W) | (int32(ARNG_4W) << 16):
4764 return (0x072F7E << 12), 0x3
4765 case int32(ARNG_V) | (int32(ARNG_2V) << 16):
4766 return (0x0E5EFE << 11), 0x1
4767 }
4768 case AXVMOVQ:
4769 return 0, 0
4770 }
4771 }
4772
4773 return 0, 0
4774 }
4775
4776 func vshift(a obj.As) bool {
4777 switch a {
4778 case ASLLV,
4779 ASRLV,
4780 ASRAV,
4781 AROTRV:
4782 return true
4783 }
4784 return false
4785 }
4786
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