1
2
3
4
5 package loong64
6
7 import (
8 "cmd/internal/obj"
9 "cmd/internal/objabi"
10 "fmt"
11 "log"
12 "math/bits"
13 "slices"
14 )
15
16
17
18
19 type ctxt0 struct {
20 ctxt *obj.Link
21 newprog obj.ProgAlloc
22 cursym *obj.LSym
23 autosize int32
24 instoffset int64
25 pc int64
26 }
27
28
29
30 const (
31 FuncAlign = 4
32 loopAlign = 16
33 )
34
35 type Optab struct {
36 as obj.As
37 from1 uint8
38 reg uint8
39 from3 uint8
40 to1 uint8
41 to2 uint8
42 type_ int8
43 size int8
44 param int16
45 flag uint8
46 }
47
48 const (
49 NOTUSETMP = 1 << iota
50
51
52
53 branchLoopHead
54 )
55
56 var optab = []Optab{
57 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, C_NONE, 0, 0, 0, 0},
58
59 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
60 {AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
61 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 1, 4, 0, 0},
62 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 1, 4, 0, 0},
63 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
64 {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
65 {AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
66
67 {ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
68 {ASUBV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
69 {AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
70 {AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
71 {AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
72 {ASUB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
73 {ASUBV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
74 {AADD, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
75 {AADDV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
76 {AAND, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
77 {ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
78 {ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
79 {AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
80 {ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
81 {ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
82 {ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
83 {ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
84 {AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
85 {AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
86 {AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
87 {AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
88 {AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
89 {AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
90 {ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
91
92 {AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
93 {AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
94 {AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0},
95 {AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0},
96 {AVANDV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
97 {AVANDV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
98 {AXVANDV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
99 {AXVANDV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
100 {AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
101 {AVANDB, C_U8CON, C_NONE, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
102 {AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
103 {AXVANDB, C_U8CON, C_NONE, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
104
105 {AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
106 {AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
107 {AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
108 {AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
109
110 {AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
111 {AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
112 {AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
113 {AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
114 {AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
115 {AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
116 {AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
117 {AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
118
119 {AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
120 {AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
121 {AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
122 {AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
123 {AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
124 {AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
125 {AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
126 {AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
127
128 {AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
129 {AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
130 {AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
131 {AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
132 {AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
133 {AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
134 {AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
135 {AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
136
137 {AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
138 {AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
139 {AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
140 {AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
141 {AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
142 {AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
143 {AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
144 {AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
145
146 {ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
147 {AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
148 {AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
149 {AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
150 {AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
151 {AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0},
152 {AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0},
153 {AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
154 {AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
155
156 {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
157 {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
158 {AVSHUFB, C_VREG, C_VREG, C_VREG, C_VREG, C_NONE, 37, 4, 0, 0},
159 {AXVSHUFB, C_XREG, C_XREG, C_XREG, C_XREG, C_NONE, 37, 4, 0, 0},
160
161 {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
162 {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
163
164 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
165 {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
166 {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
167 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
168 {AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
169 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
170 {AMOVWU, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
171 {AMOVV, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
172 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
173 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
174 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
175 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
176 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
177 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
178
179 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
180 {AMOVWU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
181 {AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
182 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
183 {AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
184 {AMOVW, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
185 {AMOVWU, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
186 {AMOVV, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
187 {AMOVB, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
188 {AMOVBU, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
189 {AVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
190 {AXVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
191 {AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
192 {AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
193
194 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
195 {AMOVWU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
196 {AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
197 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
198 {AMOVBU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
199 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
200 {AMOVWU, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
201 {AMOVV, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
202 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
203 {AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
204 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
205 {AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
206 {AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
207 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
208 {AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
209 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
210 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
211 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
212 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
213 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
214 {AMOVWP, C_REG, C_NONE, C_NONE, C_SOREG_16, C_NONE, 73, 4, 0, 0},
215 {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 73, 12, 0, 0},
216 {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG_64, C_NONE, 73, 24, 0, 0},
217
218 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
219 {AMOVWU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
220 {AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
221 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
222 {AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
223 {AMOVW, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
224 {AMOVWU, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
225 {AMOVV, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
226 {AMOVB, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
227 {AMOVBU, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
228 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
229 {AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
230 {AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
231 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
232 {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
233 {AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
234 {AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
235 {AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
236 {AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
237 {AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
238 {AMOVWP, C_SOREG_16, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0},
239 {AMOVWP, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 74, 12, 0, 0},
240 {AMOVWP, C_LOREG_64, C_NONE, C_NONE, C_REG, C_NONE, 74, 24, 0, 0},
241
242 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
243 {AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
244 {AMOVW, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
245 {AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
246
247 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
248 {AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
249 {AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
250 {AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
251
252 {AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
253 {AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
254 {AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
255 {AMOVV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
256 {AMOVV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 67, 4, 0, NOTUSETMP},
257 {AMOVV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 68, 8, 0, NOTUSETMP},
258 {AMOVV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 69, 12, 0, NOTUSETMP},
259 {AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
260
261 {AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
262 {AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
263 {AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
264 {AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
265
266 {AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
267 {AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
268 {AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
269 {AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
270
271 {AADDV16, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
272 {AADDV16, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
273
274 {AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
275 {AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
276 {AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
277 {AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
278
279 {AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
280 {AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
281 {AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
282 {AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
283 {AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
284 {AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
285
286 {AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
287 {AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
288 {AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
289 {AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
290 {AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
291 {AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
292
293 {AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
294 {AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
295 {AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
296 {AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
297 {AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
298 {AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
299 {AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
300 {AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
301 {AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
302 {AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
303 {AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
304 {AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
305 {AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
306 {AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
307 {AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
308 {AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
309
310 {ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
311 {ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
312
313 {ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
314 {ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
315
316 {ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0},
317 {ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
318 {ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
319
320 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
321 {ASYSCALL, C_U15CON, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
322
323 {ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
324 {ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
325 {ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
326 {ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
327 {ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
328
329 {AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
330 {AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
331
332 {AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0},
333 {AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0},
334
335 {AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
336 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
337 {AMOVF, C_SOREG_12, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
338 {AMOVD, C_SOREG_12, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
339
340 {AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
341 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
342 {AMOVF, C_LOREG_32, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
343 {AMOVD, C_LOREG_32, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
344 {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
345 {AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
346
347 {AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
348 {AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
349 {AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 29, 4, REGZERO, 0},
350 {AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 29, 4, REGZERO, 0},
351
352 {AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
353 {AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
354 {AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 29, 12, REGZERO, 0},
355 {AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 29, 12, REGZERO, 0},
356 {AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
357 {AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
358
359 {AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
360 {AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
361 {AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
362 {AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
363 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
364 {AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
365 {AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
366 {AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0},
367 {AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
368 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
369
370 {AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0},
371
372 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
373 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
374 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
375 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
376 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
377
378 {AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
379 {AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
380 {AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
381 {AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
382 {AMOVWU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
383
384 {AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0},
385 {AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0},
386
387 {AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0},
388
389 {ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
390 {ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
391
392 {ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0},
393 {AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0},
394 {ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
395
396
397 {AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
398 {AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
399 {AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
400 {AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
401 {AMOVD, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
402 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
403 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
404
405
406 {AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
407 {AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
408 {AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
409 {AMOVWU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
410 {AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
411 {AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
412 {AMOVD, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
413 {AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0},
414 {AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0},
415
416 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
417 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
418 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
419 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
420
421 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 43, 4, 0, 0},
422 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 44, 4, 0, 0},
423
424 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
425 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
426 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0},
427
428 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
429
430 {AVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
431 {AXVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
432
433 {APRELD, C_SOREG_12, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
434 {APRELDX, C_SOREG_16, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
435
436 {AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
437
438 {obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
439 {obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
440 {obj.APCDATA, C_DCON, C_NONE, C_NONE, C_DCON, C_NONE, 0, 0, 0, 0},
441 {obj.AFUNCDATA, C_U12CON, C_NONE, C_NONE, C_ADDR, C_NONE, 0, 0, 0, 0},
442 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
443 {obj.ANOP, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
444 {obj.ANOP, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
445 {obj.ANOP, C_REG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
446 {obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
447 }
448
449 var atomicInst = map[obj.As]uint32{
450 AAMSWAPB: 0x070B8 << 15,
451 AAMSWAPH: 0x070B9 << 15,
452 AAMSWAPW: 0x070C0 << 15,
453 AAMSWAPV: 0x070C1 << 15,
454 AAMCASB: 0x070B0 << 15,
455 AAMCASH: 0x070B1 << 15,
456 AAMCASW: 0x070B2 << 15,
457 AAMCASV: 0x070B3 << 15,
458 AAMADDW: 0x070C2 << 15,
459 AAMADDV: 0x070C3 << 15,
460 AAMANDW: 0x070C4 << 15,
461 AAMANDV: 0x070C5 << 15,
462 AAMORW: 0x070C6 << 15,
463 AAMORV: 0x070C7 << 15,
464 AAMXORW: 0x070C8 << 15,
465 AAMXORV: 0x070C9 << 15,
466 AAMMAXW: 0x070CA << 15,
467 AAMMAXV: 0x070CB << 15,
468 AAMMINW: 0x070CC << 15,
469 AAMMINV: 0x070CD << 15,
470 AAMMAXWU: 0x070CE << 15,
471 AAMMAXVU: 0x070CF << 15,
472 AAMMINWU: 0x070D0 << 15,
473 AAMMINVU: 0x070D1 << 15,
474 AAMSWAPDBB: 0x070BC << 15,
475 AAMSWAPDBH: 0x070BD << 15,
476 AAMSWAPDBW: 0x070D2 << 15,
477 AAMSWAPDBV: 0x070D3 << 15,
478 AAMCASDBB: 0x070B4 << 15,
479 AAMCASDBH: 0x070B5 << 15,
480 AAMCASDBW: 0x070B6 << 15,
481 AAMCASDBV: 0x070B7 << 15,
482 AAMADDDBW: 0x070D4 << 15,
483 AAMADDDBV: 0x070D5 << 15,
484 AAMANDDBW: 0x070D6 << 15,
485 AAMANDDBV: 0x070D7 << 15,
486 AAMORDBW: 0x070D8 << 15,
487 AAMORDBV: 0x070D9 << 15,
488 AAMXORDBW: 0x070DA << 15,
489 AAMXORDBV: 0x070DB << 15,
490 AAMMAXDBW: 0x070DC << 15,
491 AAMMAXDBV: 0x070DD << 15,
492 AAMMINDBW: 0x070DE << 15,
493 AAMMINDBV: 0x070DF << 15,
494 AAMMAXDBWU: 0x070E0 << 15,
495 AAMMAXDBVU: 0x070E1 << 15,
496 AAMMINDBWU: 0x070E2 << 15,
497 AAMMINDBVU: 0x070E3 << 15,
498 }
499
500 func IsAtomicInst(as obj.As) bool {
501 _, ok := atomicInst[as]
502
503 return ok
504 }
505
506
507
508 func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int {
509 if !((alignedValue&(alignedValue-1) == 0) && 8 <= alignedValue && alignedValue <= 2048) {
510 ctxt.Diag("alignment value of an instruction must be a power of two and in the range [8, 2048], got %d\n", alignedValue)
511 }
512 return int(-pc & (alignedValue - 1))
513 }
514
515 var oprange [ALAST & obj.AMask][]Optab
516
517 var xcmp [C_NCLASS][C_NCLASS]bool
518
519 func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
520 if ctxt.Retpoline {
521 ctxt.Diag("-spectre=ret not supported on loong64")
522 ctxt.Retpoline = false
523 }
524
525 p := cursym.Func().Text
526 if p == nil || p.Link == nil {
527 return
528 }
529
530 c := ctxt0{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset + ctxt.Arch.FixedFrameSize)}
531
532 if oprange[AOR&obj.AMask] == nil {
533 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
534 }
535
536 pc := int64(0)
537 p.Pc = pc
538
539 var m int
540 var o *Optab
541 for p = p.Link; p != nil; p = p.Link {
542 p.Pc = pc
543 o = c.oplook(p)
544 m = int(o.size)
545 if m == 0 {
546 switch p.As {
547 case obj.APCALIGN:
548 alignedValue := p.From.Offset
549 m = pcAlignPadLength(ctxt, pc, alignedValue)
550
551 if int32(alignedValue) > cursym.Func().Align {
552 cursym.Func().Align = int32(alignedValue)
553 }
554 break
555 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
556 continue
557 default:
558 c.ctxt.Diag("zero-width instruction\n%v", p)
559 }
560 }
561
562 pc += int64(m)
563 }
564
565 c.cursym.Size = pc
566
567
568
569 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
570 if q := p.To.Target(); q != nil && q.Pc < p.Pc {
571 q.Mark |= branchLoopHead
572 }
573 }
574
575
576 for {
577 rescan := false
578 pc = 0
579 prev := c.cursym.Func().Text
580 for p = prev.Link; p != nil; prev, p = p, p.Link {
581 p.Pc = pc
582 o = c.oplook(p)
583
584
585
586
587
588
589
590 if p.Mark&branchLoopHead != 0 && pc&(loopAlign-1) != 0 &&
591 !(prev.As == obj.APCALIGN && prev.From.Offset >= loopAlign) {
592 q := c.newprog()
593 prev.Link = q
594 q.Link = p
595 q.Pc = pc
596 q.As = obj.APCALIGN
597 q.From.Type = obj.TYPE_CONST
598 q.From.Offset = loopAlign
599
600
601
602
603
604
605
606 pc += int64(pcAlignPadLength(ctxt, pc, loopAlign))
607 p.Pc = pc
608 rescan = true
609 }
610
611
612
613
614
615 if o.type_ == 6 && p.To.Target() != nil {
616 otxt := p.To.Target().Pc - pc
617
618
619
620
621
622 bound := int64(1 << (18 - 1))
623
624 switch p.As {
625 case ABFPT, ABFPF:
626 bound = int64(1 << (23 - 1))
627 }
628
629 if otxt < -bound || otxt >= bound {
630 q := c.newprog()
631 q.Link = p.Link
632 p.Link = q
633 q.As = AJMP
634 q.Pos = p.Pos
635 q.To.Type = obj.TYPE_BRANCH
636 q.To.SetTarget(p.To.Target())
637 p.To.SetTarget(q)
638 q = c.newprog()
639 q.Link = p.Link
640 p.Link = q
641 q.As = AJMP
642 q.Pos = p.Pos
643 q.To.Type = obj.TYPE_BRANCH
644 q.To.SetTarget(q.Link.Link)
645 rescan = true
646 }
647 }
648
649 m = int(o.size)
650 if m == 0 {
651 switch p.As {
652 case obj.APCALIGN:
653 alignedValue := p.From.Offset
654 m = pcAlignPadLength(ctxt, pc, alignedValue)
655 break
656 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
657 continue
658 default:
659 c.ctxt.Diag("zero-width instruction\n%v", p)
660 }
661 }
662
663 pc += int64(m)
664 }
665
666 c.cursym.Size = pc
667
668 if !rescan {
669 break
670 }
671 }
672
673 pc += -pc & (FuncAlign - 1)
674 c.cursym.Size = pc
675
676
677
678 c.cursym.Grow(c.cursym.Size)
679
680 bp := c.cursym.P
681 var i int32
682 var out [6]uint32
683 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
684 c.pc = p.Pc
685 o = c.oplook(p)
686 if int(o.size) > 4*len(out) {
687 log.Fatalf("out array in span0 is too small, need at least %d for %v", o.size/4, p)
688 }
689 if p.As == obj.APCALIGN {
690 alignedValue := p.From.Offset
691 v := pcAlignPadLength(c.ctxt, p.Pc, alignedValue)
692 for i = 0; i < int32(v/4); i++ {
693
694 c.ctxt.Arch.ByteOrder.PutUint32(bp, OP_12IRR(c.opirr(AAND), 0, 0, 0))
695 bp = bp[4:]
696 }
697 continue
698 }
699 c.asmout(p, o, out[:])
700 for i = 0; i < int32(o.size/4); i++ {
701 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
702 bp = bp[4:]
703 }
704 }
705
706
707
708
709
710 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, c.isRestartable)
711
712
713 for _, jt := range cursym.Func().JumpTables {
714 for i, p := range jt.Targets {
715
716
717 jt.Sym.WriteAddr(ctxt, int64(i)*8, 8, cursym, p.Pc)
718 }
719 }
720 }
721
722
723 func (c *ctxt0) isUnsafePoint(p *obj.Prog) bool {
724
725
726 return p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP
727 }
728
729
730
731 func (c *ctxt0) isRestartable(p *obj.Prog) bool {
732 if c.isUnsafePoint(p) {
733 return false
734 }
735
736
737
738
739
740
741
742 o := c.oplook(p)
743 return o.size > 4 && o.flag&NOTUSETMP == 0
744 }
745
746 func isint32(v int64) bool {
747 return int64(int32(v)) == v
748 }
749
750 func (c *ctxt0) aclass(a *obj.Addr) int {
751 switch a.Type {
752 case obj.TYPE_NONE:
753 return C_NONE
754
755 case obj.TYPE_REG:
756 return c.rclass(a.Reg)
757
758 case obj.TYPE_MEM:
759 switch a.Name {
760 case obj.NAME_EXTERN,
761 obj.NAME_STATIC:
762 if a.Sym == nil {
763 break
764 }
765 c.instoffset = a.Offset
766 if a.Sym.Type == objabi.STLSBSS {
767 if c.ctxt.Flag_shared {
768 return C_TLS_IE
769 } else {
770 return C_TLS_LE
771 }
772 }
773 return C_ADDR
774
775 case obj.NAME_AUTO:
776 if a.Reg == REGSP {
777
778
779 a.Reg = obj.REG_NONE
780 }
781 c.instoffset = int64(c.autosize) + a.Offset
782 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
783 return C_SAUTO
784 }
785 return C_LAUTO
786
787 case obj.NAME_PARAM:
788 if a.Reg == REGSP {
789
790
791 a.Reg = obj.REG_NONE
792 }
793 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
794 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
795 return C_SAUTO
796 }
797 return C_LAUTO
798
799 case obj.NAME_NONE:
800 if a.Index != 0 {
801 if a.Offset != 0 {
802 return C_GOK
803 }
804
805 return C_ROFF
806 }
807
808 c.instoffset = a.Offset
809 if c.instoffset == 0 {
810 return C_ZOREG
811 }
812 if c.instoffset >= -BIG_8 && c.instoffset < BIG_8 {
813 return C_SOREG_8
814 } else if c.instoffset >= -BIG_9 && c.instoffset < BIG_9 {
815 return C_SOREG_9
816 } else if c.instoffset >= -BIG_10 && c.instoffset < BIG_10 {
817 return C_SOREG_10
818 } else if c.instoffset >= -BIG_11 && c.instoffset < BIG_11 {
819 return C_SOREG_11
820 } else if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
821 return C_SOREG_12
822 } else if c.instoffset >= -BIG_16 && c.instoffset < BIG_16 {
823 return C_SOREG_16
824 } else if c.instoffset >= -BIG_32 && c.instoffset < BIG_32 {
825 return C_LOREG_32
826 } else {
827 return C_LOREG_64
828 }
829
830 case obj.NAME_GOTREF:
831 return C_GOTADDR
832 }
833
834 return C_GOK
835
836 case obj.TYPE_TEXTSIZE:
837 return C_TEXTSIZE
838
839 case obj.TYPE_CONST,
840 obj.TYPE_ADDR:
841 switch a.Name {
842 case obj.NAME_NONE:
843 c.instoffset = a.Offset
844 if a.Reg != 0 {
845 if -BIG_12 <= c.instoffset && c.instoffset <= BIG_12 {
846 return C_SACON
847 }
848 if isint32(c.instoffset) {
849 return C_LACON
850 }
851 return C_DACON
852 }
853
854 case obj.NAME_EXTERN,
855 obj.NAME_STATIC:
856 s := a.Sym
857 if s == nil {
858 return C_GOK
859 }
860
861 c.instoffset = a.Offset
862 if s.Type == objabi.STLSBSS {
863 c.ctxt.Diag("taking address of TLS variable is not supported")
864 }
865 return C_EXTADDR
866
867 case obj.NAME_AUTO:
868 if a.Reg == REGSP {
869
870
871 a.Reg = obj.REG_NONE
872 }
873 c.instoffset = int64(c.autosize) + a.Offset
874 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
875 return C_SACON
876 }
877 return C_LACON
878
879 case obj.NAME_PARAM:
880 if a.Reg == REGSP {
881
882
883 a.Reg = obj.REG_NONE
884 }
885 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
886 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
887 return C_SACON
888 }
889 return C_LACON
890
891 default:
892 return C_GOK
893 }
894
895 if c.instoffset != int64(int32(c.instoffset)) {
896 return dconClass(c.instoffset)
897 }
898
899 if c.instoffset >= 0 {
900 sbits := bits.Len64(uint64(c.instoffset))
901 switch {
902 case sbits <= 8:
903 return C_ZCON + sbits
904 case sbits <= 12:
905 if c.instoffset <= 0x7ff {
906 return C_US12CON
907 }
908 return C_U12CON
909 case sbits <= 13:
910 if c.instoffset&0xfff == 0 {
911 return C_U13CON20_0
912 }
913 return C_U13CON
914 case sbits <= 15:
915 if c.instoffset&0xfff == 0 {
916 return C_U15CON20_0
917 }
918 return C_U15CON
919 }
920 } else {
921 sbits := bits.Len64(uint64(^c.instoffset))
922 switch {
923 case sbits < 5:
924 return C_S5CON
925 case sbits < 12:
926 return C_S12CON
927 case sbits < 13:
928 if c.instoffset&0xfff == 0 {
929 return C_S13CON20_0
930 }
931 return C_S13CON
932 }
933 }
934
935 if c.instoffset&0xfff == 0 {
936 return C_32CON20_0
937 }
938 return C_32CON
939
940 case obj.TYPE_BRANCH:
941 return C_BRAN
942 }
943
944 return C_GOK
945 }
946
947
948
949
950
951
952
953 const (
954 ALL1 = iota
955 ALL0
956 ST1
957 ST0
958 )
959
960
961
962 func mask(suf int8, len int8) (uint64, uint64) {
963 if len == 12 {
964 if suf == 0 {
965 return 0xfff, 0x800
966 } else {
967 return 0xfff0000000000000, 0x8000000000000000
968 }
969 } else {
970 if suf == 12 {
971 return 0xfffff000, 0x80000000
972 } else {
973 return 0xfffff00000000, 0x8000000000000
974 }
975 }
976 }
977
978
979
980
981
982 func bitField(val int64, suf int8, len int8) int8 {
983 mask1, mask2 := mask(suf, len)
984 if uint64(val)&mask1 == mask1 {
985 return ALL1
986 } else if uint64(val)&mask1 == 0x0 {
987 return ALL0
988 } else if uint64(val)&mask2 == mask2 {
989 return ST1
990 } else {
991 return ST0
992 }
993 }
994
995
996
997
998
999
1000
1001
1002
1003 func dconClass(offset int64) int {
1004 tzb := bits.TrailingZeros64(uint64(offset))
1005 hi12 := bitField(offset, 52, 12)
1006 hi20 := bitField(offset, 32, 20)
1007 lo20 := bitField(offset, 12, 20)
1008 lo12 := bitField(offset, 0, 12)
1009 if tzb >= 52 {
1010 return C_DCON12_0
1011 }
1012 if tzb >= 32 {
1013 if ((hi20 == ALL1 || hi20 == ST1) && hi12 == ALL1) || ((hi20 == ALL0 || hi20 == ST0) && hi12 == ALL0) {
1014 return C_DCON20S_0
1015 }
1016 return C_DCON32_0
1017 }
1018 if tzb >= 12 {
1019 if lo20 == ST1 || lo20 == ALL1 {
1020 if hi20 == ALL1 {
1021 return C_DCON12_20S
1022 }
1023 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1024 return C_DCON20S_20
1025 }
1026 return C_DCON32_20
1027 }
1028 if hi20 == ALL0 {
1029 return C_DCON12_20S
1030 }
1031 if (hi20 == ST0 && hi12 == ALL0) || ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) {
1032 return C_DCON20S_20
1033 }
1034 return C_DCON32_20
1035 }
1036 if lo12 == ST1 || lo12 == ALL1 {
1037 if lo20 == ALL1 {
1038 if hi20 == ALL1 {
1039 return C_DCON12_12S
1040 }
1041 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1042 return C_DCON20S_12S
1043 }
1044 return C_DCON32_12S
1045 }
1046 if lo20 == ST1 {
1047 if hi20 == ALL1 {
1048
1049 return C_DCON12_32S
1050 }
1051 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1052 return C_DCON20S_32
1053 }
1054 return C_DCON
1055 }
1056 if lo20 == ALL0 {
1057 if hi20 == ALL0 {
1058 return C_DCON12_12U
1059 }
1060 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1061 return C_DCON20S_12U
1062 }
1063 return C_DCON32_12U
1064 }
1065 if hi20 == ALL0 {
1066 return C_DCON12_32S
1067 }
1068 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1069 return C_DCON20S_32
1070 }
1071 return C_DCON
1072 }
1073 if lo20 == ALL0 {
1074 if hi20 == ALL0 {
1075 return C_DCON12_12U
1076 }
1077 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1078 return C_DCON20S_12U
1079 }
1080 return C_DCON32_12U
1081 }
1082 if lo20 == ST1 || lo20 == ALL1 {
1083 if hi20 == ALL1 {
1084 return C_DCON12_32S
1085 }
1086 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1087 return C_DCON20S_32
1088 }
1089 return C_DCON
1090 }
1091 if hi20 == ALL0 {
1092 return C_DCON12_32S
1093 }
1094 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1095 return C_DCON20S_32
1096 }
1097 return C_DCON
1098 }
1099
1100
1101
1102 func (c *ctxt0) rclass(r int16) int {
1103 switch {
1104 case REG_R0 <= r && r <= REG_R31:
1105 return C_REG
1106 case REG_F0 <= r && r <= REG_F31:
1107 return C_FREG
1108 case REG_FCC0 <= r && r <= REG_FCC7:
1109 return C_FCCREG
1110 case REG_FCSR0 <= r && r <= REG_FCSR3:
1111 return C_FCSRREG
1112 case REG_V0 <= r && r <= REG_V31:
1113 return C_VREG
1114 case REG_X0 <= r && r <= REG_X31:
1115 return C_XREG
1116 case r >= REG_ARNG && r < REG_ELEM:
1117 return C_ARNG
1118 case r >= REG_ELEM && r < REG_ELEM_END:
1119 return C_ELEM
1120 }
1121
1122 return C_GOK
1123 }
1124
1125 func oclass(a *obj.Addr) int {
1126 return int(a.Class) - 1
1127 }
1128
1129 func prasm(p *obj.Prog) {
1130 fmt.Printf("%v\n", p)
1131 }
1132
1133 func (c *ctxt0) oplook(p *obj.Prog) *Optab {
1134 if oprange[AOR&obj.AMask] == nil {
1135 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
1136 }
1137
1138 restArgsIndex := 0
1139 restArgsLen := len(p.RestArgs)
1140 if restArgsLen > 2 {
1141 c.ctxt.Diag("too many RestArgs: got %v, maximum is 2\n", restArgsLen)
1142 return nil
1143 }
1144
1145 restArgsv := [2]int{C_NONE + 1, C_NONE + 1}
1146 for i, ap := range p.RestArgs {
1147 restArgsv[i] = int(ap.Addr.Class)
1148 if restArgsv[i] == 0 {
1149 restArgsv[i] = c.aclass(&ap.Addr) + 1
1150 ap.Addr.Class = int8(restArgsv[i])
1151 }
1152 }
1153
1154 a1 := int(p.Optab)
1155 if a1 != 0 {
1156 return &optab[a1-1]
1157 }
1158
1159
1160 a1 = int(p.From.Class)
1161 if a1 == 0 {
1162 a1 = c.aclass(&p.From) + 1
1163 p.From.Class = int8(a1)
1164 }
1165 a1--
1166
1167
1168 a4 := int(p.To.Class)
1169 if a4 == 0 {
1170 a4 = c.aclass(&p.To) + 1
1171 p.To.Class = int8(a4)
1172 }
1173 a4--
1174
1175
1176 a2 := C_NONE
1177 if p.Reg != 0 {
1178 a2 = c.rclass(p.Reg)
1179 } else if restArgsLen > 0 {
1180 a2 = restArgsv[restArgsIndex] - 1
1181 restArgsIndex++
1182 }
1183
1184
1185 a5 := C_NONE
1186 if p.RegTo2 != 0 {
1187 a5 = C_REG
1188 }
1189
1190
1191 a3 := C_NONE
1192 if restArgsLen > 0 && restArgsIndex < restArgsLen {
1193 a3 = restArgsv[restArgsIndex] - 1
1194 restArgsIndex++
1195 }
1196
1197 ops := oprange[p.As&obj.AMask]
1198 c1 := &xcmp[a1]
1199 c2 := &xcmp[a2]
1200 c3 := &xcmp[a3]
1201 c4 := &xcmp[a4]
1202 c5 := &xcmp[a5]
1203 for i := range ops {
1204 op := &ops[i]
1205 if c1[op.from1] && c2[op.reg] && c3[op.from3] && c4[op.to1] && c5[op.to2] {
1206 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1207 return op
1208 }
1209 }
1210
1211 c.ctxt.Diag("illegal combination %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5))
1212 prasm(p)
1213
1214 return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}
1215 }
1216
1217 func cmp(a int, b int) bool {
1218 if a == b {
1219 return true
1220 }
1221 switch a {
1222 case C_DCON:
1223 return cmp(C_32CON, b) || cmp(C_DCON12_20S, b) || cmp(C_DCON32_12S, b) || b == C_DCON12_0
1224 case C_32CON:
1225 return cmp(C_32CON20_0, b) || cmp(C_U15CON, b) || cmp(C_13CON, b) || cmp(C_12CON, b)
1226 case C_32CON20_0:
1227 return b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_S13CON20_0 || b == C_ZCON
1228 case C_U15CON:
1229 return cmp(C_U12CON, b) || b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_U13CON
1230 case C_13CON:
1231 return cmp(C_U13CON, b) || cmp(C_S13CON, b)
1232 case C_U13CON:
1233 return cmp(C_12CON, b) || b == C_U13CON20_0
1234 case C_S13CON:
1235 return cmp(C_12CON, b) || b == C_S13CON20_0
1236 case C_12CON:
1237 return cmp(C_U12CON, b) || cmp(C_S12CON, b)
1238 case C_UU12CON:
1239 return cmp(C_U12CON, b)
1240 case C_U12CON:
1241 return cmp(C_U8CON, b) || b == C_US12CON
1242 case C_U8CON:
1243 return cmp(C_U7CON, b)
1244 case C_U7CON:
1245 return cmp(C_U6CON, b)
1246 case C_U6CON:
1247 return cmp(C_U5CON, b)
1248 case C_U5CON:
1249 return cmp(C_U4CON, b)
1250 case C_U4CON:
1251 return cmp(C_U3CON, b)
1252 case C_U3CON:
1253 return cmp(C_U2CON, b)
1254 case C_U2CON:
1255 return cmp(C_U1CON, b)
1256 case C_U1CON:
1257 return cmp(C_ZCON, b)
1258 case C_US12CON:
1259 return cmp(C_S12CON, b)
1260 case C_S12CON:
1261 return cmp(C_S5CON, b) || cmp(C_U8CON, b) || b == C_US12CON
1262 case C_S5CON:
1263 return cmp(C_ZCON, b) || cmp(C_U4CON, b)
1264
1265 case C_DCON12_20S:
1266 if b == C_DCON20S_20 || b == C_DCON12_12S ||
1267 b == C_DCON20S_12S || b == C_DCON12_12U ||
1268 b == C_DCON20S_12U || b == C_DCON20S_0 {
1269 return true
1270 }
1271
1272 case C_DCON32_12S:
1273 if b == C_DCON32_20 || b == C_DCON12_32S ||
1274 b == C_DCON20S_32 || b == C_DCON32_12U ||
1275 b == C_DCON32_0 {
1276 return true
1277 }
1278
1279 case C_LACON:
1280 return b == C_SACON
1281
1282 case C_LAUTO:
1283 return b == C_SAUTO
1284
1285 case C_REG:
1286 return b == C_ZCON
1287
1288 case C_LOREG_64:
1289 if b == C_ZOREG || b == C_SOREG_8 ||
1290 b == C_SOREG_9 || b == C_SOREG_10 ||
1291 b == C_SOREG_11 || b == C_SOREG_12 ||
1292 b == C_SOREG_16 || b == C_LOREG_32 {
1293 return true
1294 }
1295
1296 case C_LOREG_32:
1297 return cmp(C_SOREG_16, b)
1298
1299 case C_SOREG_16:
1300 return cmp(C_SOREG_12, b)
1301
1302 case C_SOREG_12:
1303 return cmp(C_SOREG_11, b)
1304
1305 case C_SOREG_11:
1306 return cmp(C_SOREG_10, b)
1307
1308 case C_SOREG_10:
1309 return cmp(C_SOREG_9, b)
1310
1311 case C_SOREG_9:
1312 return cmp(C_SOREG_8, b)
1313
1314 case C_SOREG_8:
1315 return b == C_ZOREG
1316 }
1317
1318 return false
1319 }
1320
1321 func ocmp(p1, p2 Optab) int {
1322 if p1.as != p2.as {
1323 return int(p1.as) - int(p2.as)
1324 }
1325 if p1.from1 != p2.from1 {
1326 return int(p1.from1) - int(p2.from1)
1327 }
1328 if p1.reg != p2.reg {
1329 return int(p1.reg) - int(p2.reg)
1330 }
1331 if p1.to1 != p2.to1 {
1332 return int(p1.to1) - int(p2.to1)
1333 }
1334 return 0
1335 }
1336
1337 func opset(a, b0 obj.As) {
1338 oprange[a&obj.AMask] = oprange[b0]
1339 }
1340
1341 func buildop(ctxt *obj.Link) {
1342 if ctxt.DiagFunc == nil {
1343 ctxt.DiagFunc = func(format string, args ...any) {
1344 log.Printf(format, args...)
1345 }
1346 }
1347
1348 if oprange[AOR&obj.AMask] != nil {
1349
1350
1351
1352 return
1353 }
1354
1355 for i := range C_NCLASS {
1356 for j := range C_NCLASS {
1357 if cmp(j, i) {
1358 xcmp[i][j] = true
1359 }
1360 }
1361 }
1362
1363 slices.SortFunc(optab, ocmp)
1364 for i := 0; i < len(optab); i++ {
1365 as, start := optab[i].as, i
1366 for ; i < len(optab)-1; i++ {
1367 if optab[i+1].as != as {
1368 break
1369 }
1370 }
1371 r0 := as & obj.AMask
1372 oprange[r0] = optab[start : i+1]
1373 switch as {
1374 default:
1375 ctxt.Diag("unknown op in build: %v", as)
1376 ctxt.DiagFlush()
1377 log.Fatalf("bad code")
1378
1379 case AABSF:
1380 opset(AMOVFD, r0)
1381 opset(AMOVDF, r0)
1382 opset(AMOVWF, r0)
1383 opset(AMOVFW, r0)
1384 opset(AMOVWD, r0)
1385 opset(AMOVDW, r0)
1386 opset(ANEGF, r0)
1387 opset(ANEGD, r0)
1388 opset(AABSD, r0)
1389 opset(ATRUNCDW, r0)
1390 opset(ATRUNCFW, r0)
1391 opset(ASQRTF, r0)
1392 opset(ASQRTD, r0)
1393 opset(AFCLASSF, r0)
1394 opset(AFCLASSD, r0)
1395 opset(AFLOGBF, r0)
1396 opset(AFLOGBD, r0)
1397
1398 case AMOVVF:
1399 opset(AMOVVD, r0)
1400 opset(AMOVFV, r0)
1401 opset(AMOVDV, r0)
1402 opset(ATRUNCDV, r0)
1403 opset(ATRUNCFV, r0)
1404 opset(AFFINTFW, r0)
1405 opset(AFFINTFV, r0)
1406 opset(AFFINTDW, r0)
1407 opset(AFFINTDV, r0)
1408 opset(AFTINTWF, r0)
1409 opset(AFTINTWD, r0)
1410 opset(AFTINTVF, r0)
1411 opset(AFTINTVD, r0)
1412 opset(AFTINTRPWF, r0)
1413 opset(AFTINTRPWD, r0)
1414 opset(AFTINTRPVF, r0)
1415 opset(AFTINTRPVD, r0)
1416 opset(AFTINTRMWF, r0)
1417 opset(AFTINTRMWD, r0)
1418 opset(AFTINTRMVF, r0)
1419 opset(AFTINTRMVD, r0)
1420 opset(AFTINTRZWF, r0)
1421 opset(AFTINTRZWD, r0)
1422 opset(AFTINTRZVF, r0)
1423 opset(AFTINTRZVD, r0)
1424 opset(AFTINTRNEWF, r0)
1425 opset(AFTINTRNEWD, r0)
1426 opset(AFTINTRNEVF, r0)
1427 opset(AFTINTRNEVD, r0)
1428
1429 case AADD:
1430 opset(ASGT, r0)
1431 opset(ASGTU, r0)
1432 opset(AADDU, r0)
1433
1434 case AADDV:
1435 opset(AADDVU, r0)
1436
1437 case AADDF:
1438 opset(ADIVF, r0)
1439 opset(ADIVD, r0)
1440 opset(AMULF, r0)
1441 opset(AMULD, r0)
1442 opset(ASUBF, r0)
1443 opset(ASUBD, r0)
1444 opset(AADDD, r0)
1445 opset(AFMINF, r0)
1446 opset(AFMIND, r0)
1447 opset(AFMAXF, r0)
1448 opset(AFMAXD, r0)
1449 opset(AFCOPYSGF, r0)
1450 opset(AFCOPYSGD, r0)
1451 opset(AFSCALEBF, r0)
1452 opset(AFSCALEBD, r0)
1453 opset(AFMAXAF, r0)
1454 opset(AFMAXAD, r0)
1455 opset(AFMINAF, r0)
1456 opset(AFMINAD, r0)
1457
1458 case AFMADDF:
1459 opset(AFMADDD, r0)
1460 opset(AFMSUBF, r0)
1461 opset(AFMSUBD, r0)
1462 opset(AFNMADDF, r0)
1463 opset(AFNMADDD, r0)
1464 opset(AFNMSUBF, r0)
1465 opset(AFNMSUBD, r0)
1466
1467 case AAND:
1468 opset(AOR, r0)
1469 opset(AXOR, r0)
1470 opset(AORN, r0)
1471 opset(AANDN, r0)
1472
1473 case ABEQ:
1474 opset(ABNE, r0)
1475 opset(ABLT, r0)
1476 opset(ABGE, r0)
1477 opset(ABGEU, r0)
1478 opset(ABLTU, r0)
1479
1480 case ABLEZ:
1481 opset(ABGEZ, r0)
1482 opset(ABLTZ, r0)
1483 opset(ABGTZ, r0)
1484
1485 case AMOVB:
1486 opset(AMOVH, r0)
1487
1488 case AMOVBU:
1489 opset(AMOVHU, r0)
1490
1491 case AMOVWP:
1492 opset(AMOVVP, r0)
1493 opset(ASC, r0)
1494 opset(ASCV, r0)
1495 opset(ALL, r0)
1496 opset(ALLV, r0)
1497
1498 case AMUL:
1499 opset(AMULU, r0)
1500 opset(AMULH, r0)
1501 opset(AMULHU, r0)
1502 opset(AREM, r0)
1503 opset(AREMU, r0)
1504 opset(ADIV, r0)
1505 opset(ADIVU, r0)
1506 opset(AMULWVW, r0)
1507 opset(AMULWVWU, r0)
1508
1509 case AMULV:
1510 opset(AMULVU, r0)
1511 opset(AMULHV, r0)
1512 opset(AMULHVU, r0)
1513 opset(AREMV, r0)
1514 opset(AREMVU, r0)
1515 opset(ADIVV, r0)
1516 opset(ADIVVU, r0)
1517
1518 case ASLL:
1519 opset(ASRL, r0)
1520 opset(ASRA, r0)
1521 opset(AROTR, r0)
1522
1523 case ASLLV:
1524 opset(ASRAV, r0)
1525 opset(ASRLV, r0)
1526 opset(AROTRV, r0)
1527
1528 case ABSTRPICKW:
1529 opset(ABSTRPICKV, r0)
1530 opset(ABSTRINSW, r0)
1531 opset(ABSTRINSV, r0)
1532
1533 case ASUB:
1534 opset(ASUBU, r0)
1535 opset(ANOR, r0)
1536
1537 case ASUBV:
1538 opset(ASUBVU, r0)
1539
1540 case ASYSCALL:
1541 opset(ADBAR, r0)
1542 opset(ABREAK, r0)
1543
1544 case ACMPEQF:
1545 opset(ACMPGTF, r0)
1546 opset(ACMPGTD, r0)
1547 opset(ACMPGEF, r0)
1548 opset(ACMPGED, r0)
1549 opset(ACMPEQD, r0)
1550
1551 case ABFPT:
1552 opset(ABFPF, r0)
1553
1554 case AALSLV:
1555 opset(AALSLW, r0)
1556 opset(AALSLWU, r0)
1557
1558 case AMOVW,
1559 AMOVD,
1560 AMOVF,
1561 AMOVV,
1562 ARFE,
1563 AJAL,
1564 AJMP,
1565 AMOVWU,
1566 AVMOVQ,
1567 AXVMOVQ,
1568 AVSHUFB,
1569 AXVSHUFB,
1570 ANEGW,
1571 ANEGV,
1572 AWORD,
1573 APRELD,
1574 APRELDX,
1575 AFSEL,
1576 AADDV16,
1577 obj.ANOP,
1578 obj.ATEXT,
1579 obj.AFUNCDATA,
1580 obj.APCALIGN,
1581 obj.APCDATA:
1582 break
1583
1584 case ARDTIMELW:
1585 opset(ARDTIMEHW, r0)
1586 opset(ARDTIMED, r0)
1587
1588 case ACLOW:
1589 opset(ACLZW, r0)
1590 opset(ACTOW, r0)
1591 opset(ACTZW, r0)
1592 opset(ACLOV, r0)
1593 opset(ACLZV, r0)
1594 opset(ACTOV, r0)
1595 opset(ACTZV, r0)
1596 opset(AREVB2H, r0)
1597 opset(AREVB4H, r0)
1598 opset(AREVB2W, r0)
1599 opset(AREVBV, r0)
1600 opset(AREVH2W, r0)
1601 opset(AREVHV, r0)
1602 opset(ABITREV4B, r0)
1603 opset(ABITREV8B, r0)
1604 opset(ABITREVW, r0)
1605 opset(ABITREVV, r0)
1606 opset(AEXTWB, r0)
1607 opset(AEXTWH, r0)
1608 opset(ACPUCFG, r0)
1609
1610 case ATEQ:
1611 opset(ATNE, r0)
1612
1613 case AMASKEQZ:
1614 opset(AMASKNEZ, r0)
1615 opset(ACRCWBW, r0)
1616 opset(ACRCWHW, r0)
1617 opset(ACRCWWW, r0)
1618 opset(ACRCWVW, r0)
1619 opset(ACRCCWBW, r0)
1620 opset(ACRCCWHW, r0)
1621 opset(ACRCCWWW, r0)
1622 opset(ACRCCWVW, r0)
1623
1624 case ANOOP:
1625 opset(obj.AUNDEF, r0)
1626
1627 case AAMSWAPW:
1628 for i := range atomicInst {
1629 if i == AAMSWAPW {
1630 continue
1631 }
1632 opset(i, r0)
1633 }
1634
1635 case AVSEQB:
1636 opset(AVSEQH, r0)
1637 opset(AVSEQW, r0)
1638 opset(AVSEQV, r0)
1639 opset(AVILVLB, r0)
1640 opset(AVILVLH, r0)
1641 opset(AVILVLW, r0)
1642 opset(AVILVLV, r0)
1643 opset(AVILVHB, r0)
1644 opset(AVILVHH, r0)
1645 opset(AVILVHW, r0)
1646 opset(AVILVHV, r0)
1647 opset(AVMULB, r0)
1648 opset(AVMULH, r0)
1649 opset(AVMULW, r0)
1650 opset(AVMULV, r0)
1651 opset(AVMUHB, r0)
1652 opset(AVMUHH, r0)
1653 opset(AVMUHW, r0)
1654 opset(AVMUHV, r0)
1655 opset(AVMUHBU, r0)
1656 opset(AVMUHHU, r0)
1657 opset(AVMUHWU, r0)
1658 opset(AVMUHVU, r0)
1659 opset(AVDIVB, r0)
1660 opset(AVDIVH, r0)
1661 opset(AVDIVW, r0)
1662 opset(AVDIVV, r0)
1663 opset(AVMODB, r0)
1664 opset(AVMODH, r0)
1665 opset(AVMODW, r0)
1666 opset(AVMODV, r0)
1667 opset(AVDIVBU, r0)
1668 opset(AVDIVHU, r0)
1669 opset(AVDIVWU, r0)
1670 opset(AVDIVVU, r0)
1671 opset(AVMODBU, r0)
1672 opset(AVMODHU, r0)
1673 opset(AVMODWU, r0)
1674 opset(AVMODVU, r0)
1675 opset(AVMULWEVHB, r0)
1676 opset(AVMULWEVWH, r0)
1677 opset(AVMULWEVVW, r0)
1678 opset(AVMULWEVQV, r0)
1679 opset(AVMULWODHB, r0)
1680 opset(AVMULWODWH, r0)
1681 opset(AVMULWODVW, r0)
1682 opset(AVMULWODQV, r0)
1683 opset(AVMULWEVHBU, r0)
1684 opset(AVMULWEVWHU, r0)
1685 opset(AVMULWEVVWU, r0)
1686 opset(AVMULWEVQVU, r0)
1687 opset(AVMULWODHBU, r0)
1688 opset(AVMULWODWHU, r0)
1689 opset(AVMULWODVWU, r0)
1690 opset(AVMULWODQVU, r0)
1691 opset(AVMULWEVHBUB, r0)
1692 opset(AVMULWEVWHUH, r0)
1693 opset(AVMULWEVVWUW, r0)
1694 opset(AVMULWEVQVUV, r0)
1695 opset(AVMULWODHBUB, r0)
1696 opset(AVMULWODWHUH, r0)
1697 opset(AVMULWODVWUW, r0)
1698 opset(AVMULWODQVUV, r0)
1699 opset(AVADDF, r0)
1700 opset(AVADDD, r0)
1701 opset(AVSUBF, r0)
1702 opset(AVSUBD, r0)
1703 opset(AVMULF, r0)
1704 opset(AVMULD, r0)
1705 opset(AVDIVF, r0)
1706 opset(AVDIVD, r0)
1707 opset(AVSHUFH, r0)
1708 opset(AVSHUFW, r0)
1709 opset(AVSHUFV, r0)
1710
1711 case AXVSEQB:
1712 opset(AXVSEQH, r0)
1713 opset(AXVSEQW, r0)
1714 opset(AXVSEQV, r0)
1715 opset(AXVILVLB, r0)
1716 opset(AXVILVLH, r0)
1717 opset(AXVILVLW, r0)
1718 opset(AXVILVLV, r0)
1719 opset(AXVILVHB, r0)
1720 opset(AXVILVHH, r0)
1721 opset(AXVILVHW, r0)
1722 opset(AXVILVHV, r0)
1723 opset(AXVMULB, r0)
1724 opset(AXVMULH, r0)
1725 opset(AXVMULW, r0)
1726 opset(AXVMULV, r0)
1727 opset(AXVMUHB, r0)
1728 opset(AXVMUHH, r0)
1729 opset(AXVMUHW, r0)
1730 opset(AXVMUHV, r0)
1731 opset(AXVMUHBU, r0)
1732 opset(AXVMUHHU, r0)
1733 opset(AXVMUHWU, r0)
1734 opset(AXVMUHVU, r0)
1735 opset(AXVDIVB, r0)
1736 opset(AXVDIVH, r0)
1737 opset(AXVDIVW, r0)
1738 opset(AXVDIVV, r0)
1739 opset(AXVMODB, r0)
1740 opset(AXVMODH, r0)
1741 opset(AXVMODW, r0)
1742 opset(AXVMODV, r0)
1743 opset(AXVDIVBU, r0)
1744 opset(AXVDIVHU, r0)
1745 opset(AXVDIVWU, r0)
1746 opset(AXVDIVVU, r0)
1747 opset(AXVMODBU, r0)
1748 opset(AXVMODHU, r0)
1749 opset(AXVMODWU, r0)
1750 opset(AXVMODVU, r0)
1751 opset(AXVMULWEVHB, r0)
1752 opset(AXVMULWEVWH, r0)
1753 opset(AXVMULWEVVW, r0)
1754 opset(AXVMULWEVQV, r0)
1755 opset(AXVMULWODHB, r0)
1756 opset(AXVMULWODWH, r0)
1757 opset(AXVMULWODVW, r0)
1758 opset(AXVMULWODQV, r0)
1759 opset(AXVMULWEVHBU, r0)
1760 opset(AXVMULWEVWHU, r0)
1761 opset(AXVMULWEVVWU, r0)
1762 opset(AXVMULWEVQVU, r0)
1763 opset(AXVMULWODHBU, r0)
1764 opset(AXVMULWODWHU, r0)
1765 opset(AXVMULWODVWU, r0)
1766 opset(AXVMULWODQVU, r0)
1767 opset(AXVMULWEVHBUB, r0)
1768 opset(AXVMULWEVWHUH, r0)
1769 opset(AXVMULWEVVWUW, r0)
1770 opset(AXVMULWEVQVUV, r0)
1771 opset(AXVMULWODHBUB, r0)
1772 opset(AXVMULWODWHUH, r0)
1773 opset(AXVMULWODVWUW, r0)
1774 opset(AXVMULWODQVUV, r0)
1775 opset(AXVADDF, r0)
1776 opset(AXVADDD, r0)
1777 opset(AXVSUBF, r0)
1778 opset(AXVSUBD, r0)
1779 opset(AXVMULF, r0)
1780 opset(AXVMULD, r0)
1781 opset(AXVDIVF, r0)
1782 opset(AXVDIVD, r0)
1783 opset(AXVSHUFH, r0)
1784 opset(AXVSHUFW, r0)
1785 opset(AXVSHUFV, r0)
1786
1787 case AVANDB:
1788 opset(AVORB, r0)
1789 opset(AVXORB, r0)
1790 opset(AVNORB, r0)
1791 opset(AVSHUF4IB, r0)
1792 opset(AVSHUF4IH, r0)
1793 opset(AVSHUF4IW, r0)
1794 opset(AVSHUF4IV, r0)
1795 opset(AVPERMIW, r0)
1796 opset(AVEXTRINSB, r0)
1797 opset(AVEXTRINSH, r0)
1798 opset(AVEXTRINSW, r0)
1799 opset(AVEXTRINSV, r0)
1800
1801 case AXVANDB:
1802 opset(AXVORB, r0)
1803 opset(AXVXORB, r0)
1804 opset(AXVNORB, r0)
1805 opset(AXVSHUF4IB, r0)
1806 opset(AXVSHUF4IH, r0)
1807 opset(AXVSHUF4IW, r0)
1808 opset(AXVSHUF4IV, r0)
1809 opset(AXVPERMIW, r0)
1810 opset(AXVPERMIV, r0)
1811 opset(AXVPERMIQ, r0)
1812 opset(AXVEXTRINSB, r0)
1813 opset(AXVEXTRINSH, r0)
1814 opset(AXVEXTRINSW, r0)
1815 opset(AXVEXTRINSV, r0)
1816
1817 case AVANDV:
1818 opset(AVORV, r0)
1819 opset(AVXORV, r0)
1820 opset(AVNORV, r0)
1821 opset(AVANDNV, r0)
1822 opset(AVORNV, r0)
1823
1824 case AXVANDV:
1825 opset(AXVORV, r0)
1826 opset(AXVXORV, r0)
1827 opset(AXVNORV, r0)
1828 opset(AXVANDNV, r0)
1829 opset(AXVORNV, r0)
1830
1831 case AVPCNTB:
1832 opset(AVPCNTH, r0)
1833 opset(AVPCNTW, r0)
1834 opset(AVPCNTV, r0)
1835 opset(AVFSQRTF, r0)
1836 opset(AVFSQRTD, r0)
1837 opset(AVFRECIPF, r0)
1838 opset(AVFRECIPD, r0)
1839 opset(AVFRSQRTF, r0)
1840 opset(AVFRSQRTD, r0)
1841 opset(AVNEGB, r0)
1842 opset(AVNEGH, r0)
1843 opset(AVNEGW, r0)
1844 opset(AVNEGV, r0)
1845 opset(AVFRINTRNEF, r0)
1846 opset(AVFRINTRNED, r0)
1847 opset(AVFRINTRZF, r0)
1848 opset(AVFRINTRZD, r0)
1849 opset(AVFRINTRPF, r0)
1850 opset(AVFRINTRPD, r0)
1851 opset(AVFRINTRMF, r0)
1852 opset(AVFRINTRMD, r0)
1853 opset(AVFRINTF, r0)
1854 opset(AVFRINTD, r0)
1855 opset(AVFCLASSF, r0)
1856 opset(AVFCLASSD, r0)
1857
1858 case AXVPCNTB:
1859 opset(AXVPCNTH, r0)
1860 opset(AXVPCNTW, r0)
1861 opset(AXVPCNTV, r0)
1862 opset(AXVFSQRTF, r0)
1863 opset(AXVFSQRTD, r0)
1864 opset(AXVFRECIPF, r0)
1865 opset(AXVFRECIPD, r0)
1866 opset(AXVFRSQRTF, r0)
1867 opset(AXVFRSQRTD, r0)
1868 opset(AXVNEGB, r0)
1869 opset(AXVNEGH, r0)
1870 opset(AXVNEGW, r0)
1871 opset(AXVNEGV, r0)
1872 opset(AXVFRINTRNEF, r0)
1873 opset(AXVFRINTRNED, r0)
1874 opset(AXVFRINTRZF, r0)
1875 opset(AXVFRINTRZD, r0)
1876 opset(AXVFRINTRPF, r0)
1877 opset(AXVFRINTRPD, r0)
1878 opset(AXVFRINTRMF, r0)
1879 opset(AXVFRINTRMD, r0)
1880 opset(AXVFRINTF, r0)
1881 opset(AXVFRINTD, r0)
1882 opset(AXVFCLASSF, r0)
1883 opset(AXVFCLASSD, r0)
1884
1885 case AVADDB:
1886 opset(AVADDH, r0)
1887 opset(AVADDW, r0)
1888 opset(AVADDV, r0)
1889 opset(AVADDQ, r0)
1890 opset(AVSUBB, r0)
1891 opset(AVSUBH, r0)
1892 opset(AVSUBW, r0)
1893 opset(AVSUBV, r0)
1894 opset(AVSUBQ, r0)
1895 opset(AVSADDB, r0)
1896 opset(AVSADDH, r0)
1897 opset(AVSADDW, r0)
1898 opset(AVSADDV, r0)
1899 opset(AVSSUBB, r0)
1900 opset(AVSSUBH, r0)
1901 opset(AVSSUBW, r0)
1902 opset(AVSSUBV, r0)
1903 opset(AVSADDBU, r0)
1904 opset(AVSADDHU, r0)
1905 opset(AVSADDWU, r0)
1906 opset(AVSADDVU, r0)
1907 opset(AVSSUBBU, r0)
1908 opset(AVSSUBHU, r0)
1909 opset(AVSSUBWU, r0)
1910 opset(AVSSUBVU, r0)
1911
1912 case AXVADDB:
1913 opset(AXVADDH, r0)
1914 opset(AXVADDW, r0)
1915 opset(AXVADDV, r0)
1916 opset(AXVADDQ, r0)
1917 opset(AXVSUBB, r0)
1918 opset(AXVSUBH, r0)
1919 opset(AXVSUBW, r0)
1920 opset(AXVSUBV, r0)
1921 opset(AXVSUBQ, r0)
1922 opset(AXVSADDB, r0)
1923 opset(AXVSADDH, r0)
1924 opset(AXVSADDW, r0)
1925 opset(AXVSADDV, r0)
1926 opset(AXVSSUBB, r0)
1927 opset(AXVSSUBH, r0)
1928 opset(AXVSSUBW, r0)
1929 opset(AXVSSUBV, r0)
1930 opset(AXVSADDBU, r0)
1931 opset(AXVSADDHU, r0)
1932 opset(AXVSADDWU, r0)
1933 opset(AXVSADDVU, r0)
1934 opset(AXVSSUBBU, r0)
1935 opset(AXVSSUBHU, r0)
1936 opset(AXVSSUBWU, r0)
1937 opset(AXVSSUBVU, r0)
1938
1939 case AVSLLB:
1940 opset(AVSRLB, r0)
1941 opset(AVSRAB, r0)
1942 opset(AVROTRB, r0)
1943 opset(AVBITCLRB, r0)
1944 opset(AVBITSETB, r0)
1945 opset(AVBITREVB, r0)
1946
1947 case AXVSLLB:
1948 opset(AXVSRLB, r0)
1949 opset(AXVSRAB, r0)
1950 opset(AXVROTRB, r0)
1951 opset(AXVBITCLRB, r0)
1952 opset(AXVBITSETB, r0)
1953 opset(AXVBITREVB, r0)
1954
1955 case AVSLLH:
1956 opset(AVSRLH, r0)
1957 opset(AVSRAH, r0)
1958 opset(AVROTRH, r0)
1959 opset(AVBITCLRH, r0)
1960 opset(AVBITSETH, r0)
1961 opset(AVBITREVH, r0)
1962
1963 case AXVSLLH:
1964 opset(AXVSRLH, r0)
1965 opset(AXVSRAH, r0)
1966 opset(AXVROTRH, r0)
1967 opset(AXVBITCLRH, r0)
1968 opset(AXVBITSETH, r0)
1969 opset(AXVBITREVH, r0)
1970
1971 case AVSLLW:
1972 opset(AVSRLW, r0)
1973 opset(AVSRAW, r0)
1974 opset(AVROTRW, r0)
1975 opset(AVADDBU, r0)
1976 opset(AVADDHU, r0)
1977 opset(AVADDWU, r0)
1978 opset(AVADDVU, r0)
1979 opset(AVSUBBU, r0)
1980 opset(AVSUBHU, r0)
1981 opset(AVSUBWU, r0)
1982 opset(AVSUBVU, r0)
1983 opset(AVBITCLRW, r0)
1984 opset(AVBITSETW, r0)
1985 opset(AVBITREVW, r0)
1986
1987 case AXVSLLW:
1988 opset(AXVSRLW, r0)
1989 opset(AXVSRAW, r0)
1990 opset(AXVROTRW, r0)
1991 opset(AXVADDBU, r0)
1992 opset(AXVADDHU, r0)
1993 opset(AXVADDWU, r0)
1994 opset(AXVADDVU, r0)
1995 opset(AXVSUBBU, r0)
1996 opset(AXVSUBHU, r0)
1997 opset(AXVSUBWU, r0)
1998 opset(AXVSUBVU, r0)
1999 opset(AXVBITCLRW, r0)
2000 opset(AXVBITSETW, r0)
2001 opset(AXVBITREVW, r0)
2002
2003 case AVSLLV:
2004 opset(AVSRLV, r0)
2005 opset(AVSRAV, r0)
2006 opset(AVROTRV, r0)
2007 opset(AVBITCLRV, r0)
2008 opset(AVBITSETV, r0)
2009 opset(AVBITREVV, r0)
2010
2011 case AXVSLLV:
2012 opset(AXVSRLV, r0)
2013 opset(AXVSRAV, r0)
2014 opset(AXVROTRV, r0)
2015 opset(AXVBITCLRV, r0)
2016 opset(AXVBITSETV, r0)
2017 opset(AXVBITREVV, r0)
2018
2019 case AVSETEQV:
2020 opset(AVSETNEV, r0)
2021 opset(AVSETANYEQB, r0)
2022 opset(AVSETANYEQH, r0)
2023 opset(AVSETANYEQW, r0)
2024 opset(AVSETANYEQV, r0)
2025 opset(AVSETALLNEB, r0)
2026 opset(AVSETALLNEH, r0)
2027 opset(AVSETALLNEW, r0)
2028 opset(AVSETALLNEV, r0)
2029
2030 case AXVSETEQV:
2031 opset(AXVSETNEV, r0)
2032 opset(AXVSETANYEQB, r0)
2033 opset(AXVSETANYEQH, r0)
2034 opset(AXVSETANYEQW, r0)
2035 opset(AXVSETANYEQV, r0)
2036 opset(AXVSETALLNEB, r0)
2037 opset(AXVSETALLNEH, r0)
2038 opset(AXVSETALLNEW, r0)
2039 opset(AXVSETALLNEV, r0)
2040
2041 }
2042 }
2043 }
2044
2045 func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
2046 return op | (r1&0x1F)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4 & 0x1F)
2047 }
2048
2049
2050
2051
2052 func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32 {
2053 return op | (r1&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2054 }
2055
2056
2057
2058 func OP_RR(op uint32, r2 uint32, r3 uint32) uint32 {
2059 return op | (r2&0x1F)<<5 | (r3&0x1F)<<0
2060 }
2061
2062 func OP_2IRRR(op uint32, i uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
2063 return op | (i&0x3)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4&0x1F)<<0
2064 }
2065
2066 func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32 {
2067 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | ((i >> 16) & 0x1F)
2068 }
2069
2070 func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2071 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2072 }
2073
2074 func OP_14IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2075 return op | (i&0x3FFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2076 }
2077
2078 func OP_12IR_5I(op uint32, i1 uint32, r2 uint32, i2 uint32) uint32 {
2079 return op | (i1&0xFFF)<<10 | (r2&0x1F)<<5 | (i2&0x1F)<<0
2080 }
2081
2082 func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2083 return op | (i&0xFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2084 }
2085
2086 func OP_11IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2087 return op | (i&0x7FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2088 }
2089
2090 func OP_10IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2091 return op | (i&0x3FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2092 }
2093
2094 func OP_9IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2095 return op | (i&0x1FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2096 }
2097
2098 func OP_8IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2099 return op | (i&0xFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2100 }
2101
2102 func OP_6IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2103 return op | (i&0x3F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2104 }
2105
2106 func OP_5IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2107 return op | (i&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2108 }
2109
2110 func OP_4IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2111 return op | (i&0xF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2112 }
2113
2114 func OP_3IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2115 return op | (i&0x7)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2116 }
2117
2118 func OP_IR(op uint32, i uint32, r2 uint32) uint32 {
2119 return op | (i&0xFFFFF)<<5 | (r2&0x1F)<<0
2120 }
2121
2122 func OP_15I(op uint32, i uint32) uint32 {
2123 return op | (i&0x7FFF)<<0
2124 }
2125
2126
2127
2128
2129
2130 func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32 {
2131 return op | (i1 << 16) | (r2&0x1F)<<5 | (i3 << 10) | (r4&0x1F)<<0
2132 }
2133
2134
2135 func OP_B_BL(op uint32, i uint32) uint32 {
2136 return op | ((i & 0xFFFF) << 10) | ((i >> 16) & 0x3FF)
2137 }
2138
2139 func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
2140 o1 := uint32(0)
2141 o2 := uint32(0)
2142 o3 := uint32(0)
2143 o4 := uint32(0)
2144 o5 := uint32(0)
2145 o6 := uint32(0)
2146
2147 add := AADDU
2148 add = AADDVU
2149
2150 switch o.type_ {
2151 default:
2152 c.ctxt.Diag("unknown type %d", o.type_)
2153 prasm(p)
2154
2155 case 0:
2156 break
2157
2158 case 1:
2159 switch p.As {
2160 case AMOVW:
2161 o1 = OP_RRR(c.oprrr(ASLL), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
2162 case AMOVV:
2163 o1 = OP_RRR(c.oprrr(AOR), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
2164 case AVMOVQ:
2165 o1 = OP_6IRR(c.opirr(AVSLLV), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
2166 case AXVMOVQ:
2167 o1 = OP_6IRR(c.opirr(AXVSLLV), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
2168 default:
2169 c.ctxt.Diag("unexpected encoding\n%v", p)
2170 }
2171
2172 case 2:
2173 r := int(p.Reg)
2174 if p.As == ANEGW || p.As == ANEGV {
2175 r = REGZERO
2176 }
2177 if r == 0 {
2178 r = int(p.To.Reg)
2179 }
2180 o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
2181
2182 case 3:
2183 v := c.regoff(&p.From)
2184
2185 r := int(p.From.Reg)
2186 if r == 0 {
2187 r = int(o.param)
2188 }
2189 a := add
2190 if o.from1 == C_12CON && v > 0 {
2191 a = AOR
2192 }
2193
2194 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.To.Reg))
2195
2196 case 4:
2197 v := c.regoff(&p.From)
2198 r := int(p.Reg)
2199 if r == 0 {
2200 r = int(p.To.Reg)
2201 }
2202 if p.As == AADDV16 {
2203 if v&65535 != 0 {
2204 c.ctxt.Diag("%v: the constant must be a multiple of 65536.\n", p)
2205 }
2206 o1 = OP_16IRR(c.opirr(p.As), uint32(v>>16), uint32(r), uint32(p.To.Reg))
2207 } else {
2208 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2209 }
2210
2211 case 5:
2212 v := c.regoff(&p.From)
2213 o1 = OP_15I(c.opi(p.As), uint32(v))
2214
2215 case 6:
2216 v := int32(0)
2217 if p.To.Target() != nil {
2218 v = int32(p.To.Target().Pc-p.Pc) >> 2
2219 }
2220 as, rd, rj, width := p.As, p.Reg, p.From.Reg, 16
2221 switch as {
2222 case ABGTZ, ABLEZ:
2223 rd, rj = rj, rd
2224 case ABFPT, ABFPF:
2225 width = 21
2226
2227
2228 if rj == 0 {
2229 rj = REG_FCC0
2230 }
2231 case ABEQ, ABNE:
2232 if rd == 0 || rd == REGZERO || rj == REGZERO {
2233
2234 width = 21
2235 as = -as
2236 if rj == 0 || rj == REGZERO {
2237 rj = rd
2238 }
2239 }
2240 }
2241 switch width {
2242 case 21:
2243 if (v<<11)>>11 != v {
2244 c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
2245 }
2246 o1 = OP_16IR_5I(c.opirr(as), uint32(v), uint32(rj))
2247 case 16:
2248 if (v<<16)>>16 != v {
2249 c.ctxt.Diag("16 bit-width, short branch too far\n%v", p)
2250 }
2251 o1 = OP_16IRR(c.opirr(as), uint32(v), uint32(rj), uint32(rd))
2252 default:
2253 c.ctxt.Diag("unexpected branch encoding\n%v", p)
2254 }
2255
2256 case 7:
2257 r := int(p.To.Reg)
2258 if r == 0 {
2259 r = int(o.param)
2260 }
2261 v := c.regoff(&p.To)
2262 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2263
2264 case 8:
2265 r := int(p.From.Reg)
2266 if r == 0 {
2267 r = int(o.param)
2268 }
2269 v := c.regoff(&p.From)
2270 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2271
2272 case 9:
2273 o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
2274
2275 case 10:
2276 v := c.regoff(&p.From)
2277 a := AOR
2278 if v < 0 {
2279 a = AADDU
2280 }
2281 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2282 r := int(p.Reg)
2283 if r == 0 {
2284 r = int(p.To.Reg)
2285 }
2286 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2287
2288 case 11:
2289 v := int32(0)
2290 if p.To.Target() != nil {
2291 v = int32(p.To.Target().Pc-p.Pc) >> 2
2292 }
2293 o1 = OP_B_BL(c.opirr(p.As), uint32(v))
2294 if p.To.Sym != nil {
2295 c.cursym.AddRel(c.ctxt, obj.Reloc{
2296 Type: objabi.R_CALLLOONG64,
2297 Off: int32(c.pc),
2298 Siz: 4,
2299 Sym: p.To.Sym,
2300 Add: p.To.Offset,
2301 })
2302 }
2303
2304 case 12:
2305 switch p.As {
2306 case AMOVB:
2307 o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg))
2308 case AMOVH:
2309 o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg))
2310 case AMOVBU:
2311 o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg))
2312 case AMOVHU:
2313 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2314 case AMOVWU:
2315 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2316 default:
2317 c.ctxt.Diag("unexpected encoding\n%v", p)
2318 }
2319
2320 case 13:
2321 v := c.regoff(&p.From)
2322 r := int(p.Reg)
2323 if r == 0 {
2324 r = int(p.To.Reg)
2325 }
2326 o1 = OP_3IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2327
2328 case 14:
2329 v := c.regoff(&p.From)
2330 r := int(p.Reg)
2331 if r == 0 {
2332 r = int(p.To.Reg)
2333 }
2334 o1 = OP_4IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2335
2336 case 15:
2337 v := c.regoff(&p.From)
2338 r := int(p.Reg)
2339 if r == 0 {
2340 r = REGZERO
2341 }
2342
2350 if p.As == ATEQ {
2351 o1 = OP_16IRR(c.opirr(ABNE), uint32(2), uint32(r), uint32(p.To.Reg))
2352 } else {
2353 o1 = OP_16IRR(c.opirr(ABEQ), uint32(2), uint32(r), uint32(p.To.Reg))
2354 }
2355 o2 = OP_15I(c.opi(ABREAK), uint32(v))
2356
2357 case 16:
2358 v := c.regoff(&p.From)
2359 r := int(p.Reg)
2360 if r == 0 {
2361 r = int(p.To.Reg)
2362 }
2363
2364
2365 if v >= 32 && vshift(p.As) {
2366 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x3f, uint32(r), uint32(p.To.Reg))
2367 } else {
2368 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x1f, uint32(r), uint32(p.To.Reg))
2369 }
2370
2371 case 17:
2372 rd, rj := p.To.Reg, p.Reg
2373 if rj == obj.REG_NONE {
2374 rj = rd
2375 }
2376 msb, lsb := p.From.Offset, p.GetFrom3().Offset
2377
2378
2379 var b uint32
2380 if p.As == ABSTRPICKW || p.As == ABSTRINSW {
2381 b = 32
2382 } else {
2383 b = 64
2384 }
2385 if lsb < 0 || uint32(lsb) >= b || msb < 0 || uint32(msb) >= b || uint32(lsb) > uint32(msb) {
2386 c.ctxt.Diag("illegal bit number\n%v", p)
2387 }
2388
2389 o1 = OP_IRIR(c.opirir(p.As), uint32(msb), uint32(rj), uint32(lsb), uint32(rd))
2390
2391 case 18:
2392 r := int(p.Reg)
2393 if r == 0 {
2394 r = int(o.param)
2395 }
2396 o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.To.Reg), uint32(r))
2397 if p.As == obj.ACALL {
2398 c.cursym.AddRel(c.ctxt, obj.Reloc{
2399 Type: objabi.R_CALLIND,
2400 Off: int32(c.pc),
2401 })
2402 }
2403
2404 case 19:
2405
2406
2407 v := c.regoff(&p.From)
2408 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2409 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2410
2411 case 20:
2412 o1 = OP_RRR(c.oprrr(p.As), uint32(p.To.Index), uint32(p.To.Reg), uint32(p.From.Reg))
2413
2414 case 21:
2415 o1 = OP_RRR(c.oprrr(-p.As), uint32(p.From.Index), uint32(p.From.Reg), uint32(p.To.Reg))
2416
2417 case 22:
2418 v := c.regoff(&p.From)
2419 r := int(p.Reg)
2420 if r == 0 {
2421 r = int(p.To.Reg)
2422 }
2423
2424 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2425
2426 case 23:
2427 v := c.regoff(&p.From)
2428 r := int(p.Reg)
2429 if r == 0 {
2430 r = int(p.To.Reg)
2431 }
2432
2433
2434 if p.As == AVSHUF4IV || p.As == AXVSHUF4IV {
2435 operand := uint32(v)
2436 c.checkoperand(p, operand, 15)
2437 }
2438
2439 o1 = OP_8IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2440
2441 case 24:
2442 v := c.regoff(&p.From)
2443 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2444 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2445 r := int(p.Reg)
2446 if r == 0 {
2447 r = int(p.To.Reg)
2448 }
2449 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2450
2451 case 25:
2452 v := c.regoff(&p.From)
2453 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2454
2455 case 26:
2456 v := c.regoff(&p.From)
2457 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2458 r := int(p.Reg)
2459 if r == 0 {
2460 r = int(p.To.Reg)
2461 }
2462 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2463
2464 case 27:
2465 v := c.regoff(&p.From)
2466 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2467 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2468 r := int(p.From.Reg)
2469 if r == 0 {
2470 r = int(o.param)
2471 }
2472 o3 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2473
2474 case 28:
2475 v := c.regoff(&p.From)
2476 r := int(p.From.Reg)
2477 if r == 0 {
2478 r = int(o.param)
2479 }
2480 switch o.size {
2481 case 12:
2482 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2483 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2484 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2485
2486 case 4:
2487 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2488 }
2489
2490 case 29:
2491 v := c.regoff(&p.To)
2492 r := int(p.To.Reg)
2493 if r == 0 {
2494 r = int(o.param)
2495 }
2496 switch o.size {
2497 case 12:
2498 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2499 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2500 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2501
2502 case 4:
2503 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2504 }
2505
2506 case 30:
2507 a := c.specialFpMovInst(p.As, oclass(&p.From), oclass(&p.To))
2508 o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
2509
2510 case 31:
2511 v := c.regoff(&p.From)
2512 r := int(p.Reg)
2513 if r == 0 {
2514 r = int(p.To.Reg)
2515 }
2516 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2517
2518 case 32:
2519 v := c.regoff(&p.From)
2520 r := int(p.Reg)
2521 if r == 0 {
2522 r = int(p.To.Reg)
2523 }
2524 o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2525
2526 case 33:
2527 ca := uint32(p.From.Reg)
2528 fk := uint32(p.Reg)
2529 fd := uint32(p.To.Reg)
2530 fj := fd
2531 if len(p.RestArgs) > 0 {
2532 fj = uint32(p.GetFrom3().Reg)
2533 }
2534 o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F)
2535
2536 case 34:
2537 v := c.regoff(&p.From)
2538 a := AADDU
2539 if v > 0 {
2540 a = AOR
2541 }
2542 a2 := c.specialFpMovInst(p.As, C_REG, oclass(&p.To))
2543 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2544 o2 = OP_RR(a2, uint32(REGTMP), uint32(p.To.Reg))
2545
2546 case 35:
2547 v := c.regoff(&p.To)
2548 r := int(p.To.Reg)
2549 if r == 0 {
2550 r = int(o.param)
2551 }
2552 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2553 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2554 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2555
2556 case 36:
2557 v := c.regoff(&p.From)
2558 r := int(p.From.Reg)
2559 if r == 0 {
2560 r = int(o.param)
2561 }
2562 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2563 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2564 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2565
2566 case 37:
2567 r := int(p.To.Reg)
2568 if len(p.RestArgs) > 0 {
2569 r = int(p.GetFrom3().Reg)
2570 }
2571 o1 = OP_RRRR(c.oprrrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(r), uint32(p.To.Reg))
2572
2573 case 38:
2574 o1 = uint32(c.regoff(&p.From))
2575
2576 case 39:
2577 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2578 if v == 0 {
2579 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2580 }
2581
2582 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2583 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2584 index := uint32(p.To.Index)
2585 c.checkindex(p, index, m)
2586 o1 = v | (index << 10) | (Rj << 5) | Vd
2587
2588 case 40:
2589 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2590 if v == 0 {
2591 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2592 }
2593
2594 Vj := uint32(p.From.Reg & EXT_REG_MASK)
2595 Rd := uint32(p.To.Reg & EXT_REG_MASK)
2596 index := uint32(p.From.Index)
2597 c.checkindex(p, index, m)
2598 o1 = v | (index << 10) | (Vj << 5) | Rd
2599
2600 case 41:
2601 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2602 if v == 0 {
2603 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2604 }
2605
2606 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2607 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2608 o1 = v | (Rj << 5) | Vd
2609
2610 case 42:
2611 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2612 if v == 0 {
2613 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2614 }
2615
2616 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2617 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2618 o1 = v | (Xj << 5) | Xd
2619
2620 case 43:
2621 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2622 if v == 0 {
2623 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2624 }
2625
2626 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2627 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2628 index := uint32(p.To.Index)
2629 c.checkindex(p, index, m)
2630 o1 = v | (index << 10) | (Xj << 5) | Xd
2631
2632 case 44:
2633 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2634 if v == 0 {
2635 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2636 }
2637
2638 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2639 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2640 index := uint32(p.From.Index)
2641 c.checkindex(p, index, m)
2642 o1 = v | (index << 10) | (Xj << 5) | Xd
2643
2644 case 45:
2645 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2646 if v == 0 {
2647 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2648 }
2649
2650 vj := uint32(p.From.Reg & EXT_REG_MASK)
2651 vd := uint32(p.To.Reg & EXT_REG_MASK)
2652 index := uint32(p.From.Index)
2653 c.checkindex(p, index, m)
2654 o1 = v | (index << 10) | (vj << 5) | vd
2655
2656 case 46:
2657 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, true)
2658 if v == 0 {
2659 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2660 }
2661
2662 si := c.regoff(&p.From)
2663 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2664 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2665 switch v & 0xc00000 {
2666 case 0x800000:
2667 o1 = OP_12IRR(v, uint32(si), Rj, Vd)
2668 case 0x400000:
2669 if si&1 != 0 {
2670 c.ctxt.Diag("%v: offset must be a multiple of 2.\n", p)
2671 }
2672 o1 = OP_11IRR(v, uint32(si>>1), Rj, Vd)
2673 case 0x0:
2674 switch v & 0x300000 {
2675 case 0x200000:
2676 if si&3 != 0 {
2677 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
2678 }
2679 o1 = OP_10IRR(v, uint32(si>>2), Rj, Vd)
2680 case 0x100000:
2681 if si&7 != 0 {
2682 c.ctxt.Diag("%v: offset must be a multiple of 8.\n", p)
2683 }
2684 o1 = OP_9IRR(v, uint32(si>>3), Rj, Vd)
2685 }
2686 }
2687
2688 case 47:
2689 offs := c.regoff(&p.From)
2690 hint := p.GetFrom3().Offset
2691 o1 = OP_12IR_5I(c.opiir(p.As), uint32(offs), uint32(p.From.Reg), uint32(hint))
2692
2693 case 48:
2694 offs := c.regoff(&p.From)
2695 hint := p.RestArgs[1].Offset
2696 n := uint64(p.GetFrom3().Offset)
2697
2698 addrSeq := (n >> 0) & 0x1
2699 blkSize := (n >> 1) & 0x7ff
2700 blkNums := (n >> 12) & 0x1ff
2701 stride := (n >> 21) & 0xffff
2702
2703 if blkSize > 1024 {
2704 c.ctxt.Diag("%v: block_size amount out of range[16, 1024]: %v\n", p, blkSize)
2705 }
2706
2707 if blkNums > 256 {
2708 c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkSize)
2709 }
2710
2711 v := (uint64(offs) & 0xffff)
2712 v += addrSeq << 16
2713 v += ((blkSize / 16) - 1) << 20
2714 v += (blkNums - 1) << 32
2715 v += stride << 44
2716
2717 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2718 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2719 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2720 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2721 o5 = OP_5IRR(c.opirr(p.As), uint32(REGTMP), uint32(p.From.Reg), uint32(hint))
2722
2723 case 49:
2724 if p.As == ANOOP {
2725
2726 o1 = OP_12IRR(c.opirr(AAND), 0, 0, 0)
2727 } else {
2728
2729 o1 = OP_15I(c.opi(ABREAK), 0)
2730 }
2731
2732
2733 case 50:
2734 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2735 c.cursym.AddRel(c.ctxt, obj.Reloc{
2736 Type: objabi.R_LOONG64_ADDR_HI,
2737 Off: int32(c.pc),
2738 Siz: 4,
2739 Sym: p.To.Sym,
2740 Add: p.To.Offset,
2741 })
2742 o2 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2743 c.cursym.AddRel(c.ctxt, obj.Reloc{
2744 Type: objabi.R_LOONG64_ADDR_LO,
2745 Off: int32(c.pc + 4),
2746 Siz: 4,
2747 Sym: p.To.Sym,
2748 Add: p.To.Offset,
2749 })
2750
2751 case 51:
2752 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2753 c.cursym.AddRel(c.ctxt, obj.Reloc{
2754 Type: objabi.R_LOONG64_ADDR_HI,
2755 Off: int32(c.pc),
2756 Siz: 4,
2757 Sym: p.From.Sym,
2758 Add: p.From.Offset,
2759 })
2760 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2761 c.cursym.AddRel(c.ctxt, obj.Reloc{
2762 Type: objabi.R_LOONG64_ADDR_LO,
2763 Off: int32(c.pc + 4),
2764 Siz: 4,
2765 Sym: p.From.Sym,
2766 Add: p.From.Offset,
2767 })
2768
2769 case 52:
2770
2771
2772 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2773 c.cursym.AddRel(c.ctxt, obj.Reloc{
2774 Type: objabi.R_LOONG64_ADDR_HI,
2775 Off: int32(c.pc),
2776 Siz: 4,
2777 Sym: p.From.Sym,
2778 Add: p.From.Offset,
2779 })
2780 o2 = OP_12IRR(c.opirr(add), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2781 c.cursym.AddRel(c.ctxt, obj.Reloc{
2782 Type: objabi.R_LOONG64_ADDR_LO,
2783 Off: int32(c.pc + 4),
2784 Siz: 4,
2785 Sym: p.From.Sym,
2786 Add: p.From.Offset,
2787 })
2788
2789 case 53:
2790
2791
2792 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2793 c.cursym.AddRel(c.ctxt, obj.Reloc{
2794 Type: objabi.R_LOONG64_TLS_LE_HI,
2795 Off: int32(c.pc),
2796 Siz: 4,
2797 Sym: p.To.Sym,
2798 Add: p.To.Offset,
2799 })
2800 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2801 c.cursym.AddRel(c.ctxt, obj.Reloc{
2802 Type: objabi.R_LOONG64_TLS_LE_LO,
2803 Off: int32(c.pc + 4),
2804 Siz: 4,
2805 Sym: p.To.Sym,
2806 Add: p.To.Offset,
2807 })
2808 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2809 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2810
2811 case 54:
2812
2813
2814 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2815 c.cursym.AddRel(c.ctxt, obj.Reloc{
2816 Type: objabi.R_LOONG64_TLS_LE_HI,
2817 Off: int32(c.pc),
2818 Siz: 4,
2819 Sym: p.From.Sym,
2820 Add: p.From.Offset,
2821 })
2822 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2823 c.cursym.AddRel(c.ctxt, obj.Reloc{
2824 Type: objabi.R_LOONG64_TLS_LE_LO,
2825 Off: int32(c.pc + 4),
2826 Siz: 4,
2827 Sym: p.From.Sym,
2828 Add: p.From.Offset,
2829 })
2830 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2831 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2832
2833 case 56:
2834 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2835 c.cursym.AddRel(c.ctxt, obj.Reloc{
2836 Type: objabi.R_LOONG64_TLS_IE_HI,
2837 Off: int32(c.pc),
2838 Siz: 4,
2839 Sym: p.To.Sym,
2840 })
2841 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2842 c.cursym.AddRel(c.ctxt, obj.Reloc{
2843 Type: objabi.R_LOONG64_TLS_IE_LO,
2844 Off: int32(c.pc + 4),
2845 Siz: 4,
2846 Sym: p.To.Sym,
2847 })
2848 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
2849 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2850
2851 case 57:
2852 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2853 c.cursym.AddRel(c.ctxt, obj.Reloc{
2854 Type: objabi.R_LOONG64_TLS_IE_HI,
2855 Off: int32(c.pc),
2856 Siz: 4,
2857 Sym: p.From.Sym,
2858 })
2859 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2860 c.cursym.AddRel(c.ctxt, obj.Reloc{
2861 Type: objabi.R_LOONG64_TLS_IE_LO,
2862 Off: int32(c.pc + 4),
2863 Siz: 4,
2864 Sym: p.From.Sym,
2865 })
2866 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
2867 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2868
2869 case 59:
2870
2871
2872 v := c.vregoff(&p.From)
2873 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2874 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2875 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2876 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2877
2878 case 60:
2879 v := c.vregoff(&p.From)
2880 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2881 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2882 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2883 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2884 r := int(p.Reg)
2885 if r == 0 {
2886 r = int(p.To.Reg)
2887 }
2888 o5 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2889
2890 case 61:
2891 o1 = uint32(c.vregoff(&p.From))
2892 o2 = uint32(c.vregoff(&p.From) >> 32)
2893
2894 case 62:
2895 o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
2896
2897 case 64:
2898 sa := p.From.Offset - 1
2899 if sa < 0 || sa > 3 {
2900 c.ctxt.Diag("%v: shift amount out of range[1, 4].\n", p)
2901 }
2902 r := p.GetFrom3().Reg
2903 o1 = OP_2IRRR(c.opirrr(p.As), uint32(sa), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
2904
2905 case 65:
2906 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2907 c.cursym.AddRel(c.ctxt, obj.Reloc{
2908 Type: objabi.R_LOONG64_GOT_HI,
2909 Off: int32(c.pc),
2910 Siz: 4,
2911 Sym: p.From.Sym,
2912 })
2913 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2914 c.cursym.AddRel(c.ctxt, obj.Reloc{
2915 Type: objabi.R_LOONG64_GOT_LO,
2916 Off: int32(c.pc + 4),
2917 Siz: 4,
2918 Sym: p.From.Sym,
2919 })
2920
2921 case 66:
2922 rk := p.From.Reg
2923 rj := p.To.Reg
2924 rd := p.RegTo2
2925
2926
2927
2928 if rd == rj || rd == rk {
2929 c.ctxt.Diag("illegal register combination: %v\n", p)
2930 }
2931 o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
2932
2933 case 67:
2934 v := c.vregoff(&p.From)
2935 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(p.To.Reg))
2936
2937 case 68:
2938 v := c.vregoff(&p.From)
2939 contype := c.aclass(&p.From)
2940 switch contype {
2941 default:
2942 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2943 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2944 case C_DCON20S_20:
2945 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2946 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2947 case C_DCON12_12S:
2948 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(p.To.Reg))
2949 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2950 case C_DCON20S_12S, C_DCON20S_0:
2951 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
2952 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2953 case C_DCON12_12U:
2954 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2955 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2956 case C_DCON20S_12U:
2957 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2958 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2959 }
2960
2961 case 69:
2962 v := c.vregoff(&p.From)
2963 contype := c.aclass(&p.From)
2964 switch contype {
2965 default:
2966 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
2967 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2968 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2969 case C_DCON32_20:
2970 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2971 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2972 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2973 case C_DCON12_32S:
2974 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2975 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2976 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2977 case C_DCON20S_32:
2978 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2979 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2980 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2981 case C_DCON32_12U:
2982 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2983 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2984 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2985 }
2986
2987 case 70:
2988 v := c.vregoff(&p.From)
2989 r := int(p.Reg)
2990 if r == 0 {
2991 r = int(p.To.Reg)
2992 }
2993 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(REGTMP))
2994 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2995
2996 case 71:
2997 v := c.vregoff(&p.From)
2998 r := int(p.Reg)
2999 if r == 0 {
3000 r = int(p.To.Reg)
3001 }
3002 contype := c.aclass(&p.From)
3003 switch contype {
3004 default:
3005 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3006 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3007 case C_DCON20S_20:
3008 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3009 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3010 case C_DCON12_12S:
3011 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(REGTMP))
3012 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3013 case C_DCON20S_12S, C_DCON20S_0:
3014 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
3015 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3016 case C_DCON12_12U:
3017 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
3018 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3019 case C_DCON20S_12U:
3020 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
3021 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3022 }
3023 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
3024
3025 case 72:
3026 v := c.vregoff(&p.From)
3027 r := int(p.Reg)
3028 if r == 0 {
3029 r = int(p.To.Reg)
3030 }
3031 contype := c.aclass(&p.From)
3032 switch contype {
3033 default:
3034 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
3035 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3036 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3037 case C_DCON32_20:
3038 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3039 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3040 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3041 case C_DCON12_32S:
3042 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3043 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3044 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3045 case C_DCON20S_32:
3046 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3047 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3048 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3049 case C_DCON32_12U:
3050 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
3051 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3052 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3053 }
3054 o4 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
3055
3056 case 73:
3057 v := c.vregoff(&p.To)
3058 r := p.To.Reg
3059 if v&3 != 0 {
3060 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
3061 }
3062
3063 switch o.size {
3064 case 4:
3065 o1 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(r), uint32(p.From.Reg))
3066 case 12:
3067 o1 = OP_16IRR(c.opirr(AADDV16), uint32(v>>16), uint32(REG_R0), uint32(REGTMP))
3068 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
3069 o3 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(REGTMP), uint32(p.From.Reg))
3070 case 24:
3071 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3072 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3073 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3074 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3075 o5 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(r))
3076 o6 = OP_14IRR(c.opirr(p.As), uint32(0), uint32(r), uint32(p.From.Reg))
3077 }
3078
3079 case 74:
3080 v := c.vregoff(&p.From)
3081 r := p.From.Reg
3082 if v&3 != 0 {
3083 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
3084 }
3085
3086 switch o.size {
3087 case 4:
3088 o1 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(r), uint32(p.To.Reg))
3089 case 12:
3090 o1 = OP_16IRR(c.opirr(AADDV16), uint32(v>>16), uint32(REG_R0), uint32(REGTMP))
3091 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
3092 o3 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(REGTMP), uint32(p.To.Reg))
3093 case 24:
3094 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3095 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3096 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3097 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3098 o5 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(r))
3099 o6 = OP_14IRR(c.opirr(p.As), uint32(0), uint32(r), uint32(p.To.Reg))
3100 }
3101
3102 }
3103
3104 out[0] = o1
3105 out[1] = o2
3106 out[2] = o3
3107 out[3] = o4
3108 out[4] = o5
3109 out[5] = o6
3110 }
3111
3112
3113 func (c *ctxt0) checkoperand(p *obj.Prog, operand uint32, mask uint32) {
3114 if (operand & ^mask) != 0 {
3115 c.ctxt.Diag("operand out of range 0 to %d: %v", mask, p)
3116 }
3117 }
3118
3119
3120 func (c *ctxt0) checkindex(p *obj.Prog, index uint32, mask uint32) {
3121 if (index & ^mask) != 0 {
3122 c.ctxt.Diag("register element index out of range 0 to %d: %v", mask, p)
3123 }
3124 }
3125
3126 func (c *ctxt0) vregoff(a *obj.Addr) int64 {
3127 c.instoffset = 0
3128 c.aclass(a)
3129 return c.instoffset
3130 }
3131
3132 func (c *ctxt0) regoff(a *obj.Addr) int32 {
3133 return int32(c.vregoff(a))
3134 }
3135
3136 func (c *ctxt0) oprrrr(a obj.As) uint32 {
3137 switch a {
3138 case AFMADDF:
3139 return 0x81 << 20
3140 case AFMADDD:
3141 return 0x82 << 20
3142 case AFMSUBF:
3143 return 0x85 << 20
3144 case AFMSUBD:
3145 return 0x86 << 20
3146 case AFNMADDF:
3147 return 0x89 << 20
3148 case AFNMADDD:
3149 return 0x8a << 20
3150 case AFNMSUBF:
3151 return 0x8d << 20
3152 case AFNMSUBD:
3153 return 0x8e << 20
3154 case AVSHUFB:
3155 return 0x0D5 << 20
3156 case AXVSHUFB:
3157 return 0x0D6 << 20
3158 }
3159
3160 c.ctxt.Diag("bad rrrr opcode %v", a)
3161 return 0
3162 }
3163
3164 func (c *ctxt0) oprrr(a obj.As) uint32 {
3165 switch a {
3166 case AADD:
3167 return 0x20 << 15
3168 case AADDU:
3169 return 0x20 << 15
3170 case ASGT:
3171 return 0x24 << 15
3172 case ASGTU:
3173 return 0x25 << 15
3174 case AMASKEQZ:
3175 return 0x26 << 15
3176 case AMASKNEZ:
3177 return 0x27 << 15
3178 case AAND:
3179 return 0x29 << 15
3180 case AOR:
3181 return 0x2a << 15
3182 case AXOR:
3183 return 0x2b << 15
3184 case AORN:
3185 return 0x2c << 15
3186 case AANDN:
3187 return 0x2d << 15
3188 case ASUB:
3189 return 0x22 << 15
3190 case ASUBU, ANEGW:
3191 return 0x22 << 15
3192 case ANOR:
3193 return 0x28 << 15
3194 case ASLL:
3195 return 0x2e << 15
3196 case ASRL:
3197 return 0x2f << 15
3198 case ASRA:
3199 return 0x30 << 15
3200 case AROTR:
3201 return 0x36 << 15
3202 case ASLLV:
3203 return 0x31 << 15
3204 case ASRLV:
3205 return 0x32 << 15
3206 case ASRAV:
3207 return 0x33 << 15
3208 case AROTRV:
3209 return 0x37 << 15
3210 case AADDV:
3211 return 0x21 << 15
3212 case AADDVU:
3213 return 0x21 << 15
3214 case ASUBV:
3215 return 0x23 << 15
3216 case ASUBVU, ANEGV:
3217 return 0x23 << 15
3218
3219 case AMUL:
3220 return 0x38 << 15
3221 case AMULU:
3222 return 0x38 << 15
3223 case AMULH:
3224 return 0x39 << 15
3225 case AMULHU:
3226 return 0x3a << 15
3227 case AMULV:
3228 return 0x3b << 15
3229 case AMULVU:
3230 return 0x3b << 15
3231 case AMULHV:
3232 return 0x3c << 15
3233 case AMULHVU:
3234 return 0x3d << 15
3235 case AMULWVW:
3236 return 0x3e << 15
3237 case AMULWVWU:
3238 return 0x3f << 15
3239 case ADIV:
3240 return 0x40 << 15
3241 case ADIVU:
3242 return 0x42 << 15
3243 case ADIVV:
3244 return 0x44 << 15
3245 case ADIVVU:
3246 return 0x46 << 15
3247 case AREM:
3248 return 0x41 << 15
3249 case AREMU:
3250 return 0x43 << 15
3251 case AREMV:
3252 return 0x45 << 15
3253 case AREMVU:
3254 return 0x47 << 15
3255 case ACRCWBW:
3256 return 0x48 << 15
3257 case ACRCWHW:
3258 return 0x49 << 15
3259 case ACRCWWW:
3260 return 0x4a << 15
3261 case ACRCWVW:
3262 return 0x4b << 15
3263 case ACRCCWBW:
3264 return 0x4c << 15
3265 case ACRCCWHW:
3266 return 0x4d << 15
3267 case ACRCCWWW:
3268 return 0x4e << 15
3269 case ACRCCWVW:
3270 return 0x4f << 15
3271 case AJMP:
3272 return 0x13 << 26
3273 case AJAL:
3274 return (0x13 << 26) | 1
3275
3276 case ADIVF:
3277 return 0x20d << 15
3278 case ADIVD:
3279 return 0x20e << 15
3280 case AMULF:
3281 return 0x209 << 15
3282 case AMULD:
3283 return 0x20a << 15
3284 case ASUBF:
3285 return 0x205 << 15
3286 case ASUBD:
3287 return 0x206 << 15
3288 case AADDF:
3289 return 0x201 << 15
3290 case AADDD:
3291 return 0x202 << 15
3292 case ACMPEQF:
3293 return 0x0c1<<20 | 0x4<<15
3294 case ACMPEQD:
3295 return 0x0c2<<20 | 0x4<<15
3296 case ACMPGED:
3297 return 0x0c2<<20 | 0x7<<15
3298 case ACMPGEF:
3299 return 0x0c1<<20 | 0x7<<15
3300 case ACMPGTD:
3301 return 0x0c2<<20 | 0x3<<15
3302 case ACMPGTF:
3303 return 0x0c1<<20 | 0x3<<15
3304 case AFMINF:
3305 return 0x215 << 15
3306 case AFMIND:
3307 return 0x216 << 15
3308 case AFMAXF:
3309 return 0x211 << 15
3310 case AFMAXD:
3311 return 0x212 << 15
3312 case AFMAXAF:
3313 return 0x219 << 15
3314 case AFMAXAD:
3315 return 0x21a << 15
3316 case AFMINAF:
3317 return 0x21d << 15
3318 case AFMINAD:
3319 return 0x21e << 15
3320 case AFSCALEBF:
3321 return 0x221 << 15
3322 case AFSCALEBD:
3323 return 0x222 << 15
3324 case AFCOPYSGF:
3325 return 0x225 << 15
3326 case AFCOPYSGD:
3327 return 0x226 << 15
3328 case -AMOVB:
3329 return 0x07000 << 15
3330 case -AMOVH:
3331 return 0x07008 << 15
3332 case -AMOVW:
3333 return 0x07010 << 15
3334 case -AMOVV:
3335 return 0x07018 << 15
3336 case -AMOVBU:
3337 return 0x07040 << 15
3338 case -AMOVHU:
3339 return 0x07048 << 15
3340 case -AMOVWU:
3341 return 0x07050 << 15
3342 case AMOVB:
3343 return 0x07020 << 15
3344 case AMOVH:
3345 return 0x07028 << 15
3346 case AMOVW:
3347 return 0x07030 << 15
3348 case AMOVV:
3349 return 0x07038 << 15
3350 case -AMOVF:
3351 return 0x07060 << 15
3352 case -AMOVD:
3353 return 0x07068 << 15
3354 case AMOVF:
3355 return 0x07070 << 15
3356 case AMOVD:
3357 return 0x07078 << 15
3358 case -AVMOVQ:
3359 return 0x07080 << 15
3360 case -AXVMOVQ:
3361 return 0x07090 << 15
3362 case AVMOVQ:
3363 return 0x07088 << 15
3364 case AXVMOVQ:
3365 return 0x07098 << 15
3366 case AVSEQB:
3367 return 0x0e000 << 15
3368 case AXVSEQB:
3369 return 0x0e800 << 15
3370 case AVSEQH:
3371 return 0x0e001 << 15
3372 case AXVSEQH:
3373 return 0x0e801 << 15
3374 case AVSEQW:
3375 return 0x0e002 << 15
3376 case AXVSEQW:
3377 return 0x0e802 << 15
3378 case AVSEQV:
3379 return 0x0e003 << 15
3380 case AXVSEQV:
3381 return 0x0e803 << 15
3382 case AVANDV:
3383 return 0x0E24C << 15
3384 case AVORV:
3385 return 0x0E24D << 15
3386 case AVXORV:
3387 return 0x0E24E << 15
3388 case AVNORV:
3389 return 0x0E24F << 15
3390 case AVANDNV:
3391 return 0x0E250 << 15
3392 case AVORNV:
3393 return 0x0E251 << 15
3394 case AXVANDV:
3395 return 0x0EA4C << 15
3396 case AXVORV:
3397 return 0x0EA4D << 15
3398 case AXVXORV:
3399 return 0x0EA4E << 15
3400 case AXVNORV:
3401 return 0x0EA4F << 15
3402 case AXVANDNV:
3403 return 0x0EA50 << 15
3404 case AXVORNV:
3405 return 0x0EA51 << 15
3406 case AVDIVB:
3407 return 0xe1c0 << 15
3408 case AVDIVH:
3409 return 0xe1c1 << 15
3410 case AVDIVW:
3411 return 0xe1c2 << 15
3412 case AVDIVV:
3413 return 0xe1c3 << 15
3414 case AVMODB:
3415 return 0xe1c4 << 15
3416 case AVMODH:
3417 return 0xe1c5 << 15
3418 case AVMODW:
3419 return 0xe1c6 << 15
3420 case AVMODV:
3421 return 0xe1c7 << 15
3422 case AVDIVBU:
3423 return 0xe1c8 << 15
3424 case AVDIVHU:
3425 return 0xe1c9 << 15
3426 case AVDIVWU:
3427 return 0xe1ca << 15
3428 case AVDIVVU:
3429 return 0xe1cb << 15
3430 case AVMODBU:
3431 return 0xe1cc << 15
3432 case AVMODHU:
3433 return 0xe1cd << 15
3434 case AVMODWU:
3435 return 0xe1ce << 15
3436 case AVMODVU:
3437 return 0xe1cf << 15
3438 case AXVDIVB:
3439 return 0xe9c0 << 15
3440 case AXVDIVH:
3441 return 0xe9c1 << 15
3442 case AXVDIVW:
3443 return 0xe9c2 << 15
3444 case AXVDIVV:
3445 return 0xe9c3 << 15
3446 case AXVMODB:
3447 return 0xe9c4 << 15
3448 case AXVMODH:
3449 return 0xe9c5 << 15
3450 case AXVMODW:
3451 return 0xe9c6 << 15
3452 case AXVMODV:
3453 return 0xe9c7 << 15
3454 case AXVDIVBU:
3455 return 0xe9c8 << 15
3456 case AXVDIVHU:
3457 return 0xe9c9 << 15
3458 case AXVDIVWU:
3459 return 0xe9ca << 15
3460 case AXVDIVVU:
3461 return 0xe9cb << 15
3462 case AXVMODBU:
3463 return 0xe9cc << 15
3464 case AXVMODHU:
3465 return 0xe9cd << 15
3466 case AXVMODWU:
3467 return 0xe9ce << 15
3468 case AXVMODVU:
3469 return 0xe9cf << 15
3470 case AVMULWEVHB:
3471 return 0xe120 << 15
3472 case AVMULWEVWH:
3473 return 0xe121 << 15
3474 case AVMULWEVVW:
3475 return 0xe122 << 15
3476 case AVMULWEVQV:
3477 return 0xe123 << 15
3478 case AVMULWODHB:
3479 return 0xe124 << 15
3480 case AVMULWODWH:
3481 return 0xe125 << 15
3482 case AVMULWODVW:
3483 return 0xe126 << 15
3484 case AVMULWODQV:
3485 return 0xe127 << 15
3486 case AVMULWEVHBU:
3487 return 0xe130 << 15
3488 case AVMULWEVWHU:
3489 return 0xe131 << 15
3490 case AVMULWEVVWU:
3491 return 0xe132 << 15
3492 case AVMULWEVQVU:
3493 return 0xe133 << 15
3494 case AVMULWODHBU:
3495 return 0xe134 << 15
3496 case AVMULWODWHU:
3497 return 0xe135 << 15
3498 case AVMULWODVWU:
3499 return 0xe136 << 15
3500 case AVMULWODQVU:
3501 return 0xe137 << 15
3502 case AVMULWEVHBUB:
3503 return 0xe140 << 15
3504 case AVMULWEVWHUH:
3505 return 0xe141 << 15
3506 case AVMULWEVVWUW:
3507 return 0xe142 << 15
3508 case AVMULWEVQVUV:
3509 return 0xe143 << 15
3510 case AVMULWODHBUB:
3511 return 0xe144 << 15
3512 case AVMULWODWHUH:
3513 return 0xe145 << 15
3514 case AVMULWODVWUW:
3515 return 0xe146 << 15
3516 case AVMULWODQVUV:
3517 return 0xe147 << 15
3518 case AXVMULWEVHB:
3519 return 0xe920 << 15
3520 case AXVMULWEVWH:
3521 return 0xe921 << 15
3522 case AXVMULWEVVW:
3523 return 0xe922 << 15
3524 case AXVMULWEVQV:
3525 return 0xe923 << 15
3526 case AXVMULWODHB:
3527 return 0xe924 << 15
3528 case AXVMULWODWH:
3529 return 0xe925 << 15
3530 case AXVMULWODVW:
3531 return 0xe926 << 15
3532 case AXVMULWODQV:
3533 return 0xe927 << 15
3534 case AXVMULWEVHBU:
3535 return 0xe930 << 15
3536 case AXVMULWEVWHU:
3537 return 0xe931 << 15
3538 case AXVMULWEVVWU:
3539 return 0xe932 << 15
3540 case AXVMULWEVQVU:
3541 return 0xe933 << 15
3542 case AXVMULWODHBU:
3543 return 0xe934 << 15
3544 case AXVMULWODWHU:
3545 return 0xe935 << 15
3546 case AXVMULWODVWU:
3547 return 0xe936 << 15
3548 case AXVMULWODQVU:
3549 return 0xe937 << 15
3550 case AXVMULWEVHBUB:
3551 return 0xe940 << 15
3552 case AXVMULWEVWHUH:
3553 return 0xe941 << 15
3554 case AXVMULWEVVWUW:
3555 return 0xe942 << 15
3556 case AXVMULWEVQVUV:
3557 return 0xe943 << 15
3558 case AXVMULWODHBUB:
3559 return 0xe944 << 15
3560 case AXVMULWODWHUH:
3561 return 0xe945 << 15
3562 case AXVMULWODVWUW:
3563 return 0xe946 << 15
3564 case AXVMULWODQVUV:
3565 return 0xe947 << 15
3566 case AVSLLB:
3567 return 0xe1d0 << 15
3568 case AVSLLH:
3569 return 0xe1d1 << 15
3570 case AVSLLW:
3571 return 0xe1d2 << 15
3572 case AVSLLV:
3573 return 0xe1d3 << 15
3574 case AVSRLB:
3575 return 0xe1d4 << 15
3576 case AVSRLH:
3577 return 0xe1d5 << 15
3578 case AVSRLW:
3579 return 0xe1d6 << 15
3580 case AVSRLV:
3581 return 0xe1d7 << 15
3582 case AVSRAB:
3583 return 0xe1d8 << 15
3584 case AVSRAH:
3585 return 0xe1d9 << 15
3586 case AVSRAW:
3587 return 0xe1da << 15
3588 case AVSRAV:
3589 return 0xe1db << 15
3590 case AVROTRB:
3591 return 0xe1dc << 15
3592 case AVROTRH:
3593 return 0xe1dd << 15
3594 case AVROTRW:
3595 return 0xe1de << 15
3596 case AVROTRV:
3597 return 0xe1df << 15
3598 case AXVSLLB:
3599 return 0xe9d0 << 15
3600 case AXVSLLH:
3601 return 0xe9d1 << 15
3602 case AXVSLLW:
3603 return 0xe9d2 << 15
3604 case AXVSLLV:
3605 return 0xe9d3 << 15
3606 case AXVSRLB:
3607 return 0xe9d4 << 15
3608 case AXVSRLH:
3609 return 0xe9d5 << 15
3610 case AXVSRLW:
3611 return 0xe9d6 << 15
3612 case AXVSRLV:
3613 return 0xe9d7 << 15
3614 case AXVSRAB:
3615 return 0xe9d8 << 15
3616 case AXVSRAH:
3617 return 0xe9d9 << 15
3618 case AXVSRAW:
3619 return 0xe9da << 15
3620 case AXVSRAV:
3621 return 0xe9db << 15
3622 case AXVROTRB:
3623 return 0xe9dc << 15
3624 case AXVROTRH:
3625 return 0xe9dd << 15
3626 case AXVROTRW:
3627 return 0xe9de << 15
3628 case AXVROTRV:
3629 return 0xe9df << 15
3630 case AVADDB:
3631 return 0xe014 << 15
3632 case AVADDH:
3633 return 0xe015 << 15
3634 case AVADDW:
3635 return 0xe016 << 15
3636 case AVADDV:
3637 return 0xe017 << 15
3638 case AVADDQ:
3639 return 0xe25a << 15
3640 case AVSUBB:
3641 return 0xe018 << 15
3642 case AVSUBH:
3643 return 0xe019 << 15
3644 case AVSUBW:
3645 return 0xe01a << 15
3646 case AVSUBV:
3647 return 0xe01b << 15
3648 case AVSUBQ:
3649 return 0xe25b << 15
3650 case AXVADDB:
3651 return 0xe814 << 15
3652 case AXVADDH:
3653 return 0xe815 << 15
3654 case AXVADDW:
3655 return 0xe816 << 15
3656 case AXVADDV:
3657 return 0xe817 << 15
3658 case AXVADDQ:
3659 return 0xea5a << 15
3660 case AXVSUBB:
3661 return 0xe818 << 15
3662 case AXVSUBH:
3663 return 0xe819 << 15
3664 case AXVSUBW:
3665 return 0xe81a << 15
3666 case AXVSUBV:
3667 return 0xe81b << 15
3668 case AXVSUBQ:
3669 return 0xea5b << 15
3670 case AVSADDB:
3671 return 0x0E08C << 15
3672 case AVSADDH:
3673 return 0x0E08D << 15
3674 case AVSADDW:
3675 return 0x0E08E << 15
3676 case AVSADDV:
3677 return 0x0E08F << 15
3678 case AVSSUBB:
3679 return 0x0E090 << 15
3680 case AVSSUBH:
3681 return 0x0E091 << 15
3682 case AVSSUBW:
3683 return 0x0E092 << 15
3684 case AVSSUBV:
3685 return 0x0E093 << 15
3686 case AVSADDBU:
3687 return 0x0E094 << 15
3688 case AVSADDHU:
3689 return 0x0E095 << 15
3690 case AVSADDWU:
3691 return 0x0E096 << 15
3692 case AVSADDVU:
3693 return 0x0E097 << 15
3694 case AVSSUBBU:
3695 return 0x0E098 << 15
3696 case AVSSUBHU:
3697 return 0x0E099 << 15
3698 case AVSSUBWU:
3699 return 0x0E09A << 15
3700 case AVSSUBVU:
3701 return 0x0E09B << 15
3702 case AXVSADDB:
3703 return 0x0E88C << 15
3704 case AXVSADDH:
3705 return 0x0E88D << 15
3706 case AXVSADDW:
3707 return 0x0E88E << 15
3708 case AXVSADDV:
3709 return 0x0E88F << 15
3710 case AXVSSUBB:
3711 return 0x0E890 << 15
3712 case AXVSSUBH:
3713 return 0x0E891 << 15
3714 case AXVSSUBW:
3715 return 0x0E892 << 15
3716 case AXVSSUBV:
3717 return 0x0E893 << 15
3718 case AXVSADDBU:
3719 return 0x0E894 << 15
3720 case AXVSADDHU:
3721 return 0x0E896 << 15
3722 case AXVSADDWU:
3723 return 0x0E896 << 15
3724 case AXVSADDVU:
3725 return 0x0E897 << 15
3726 case AXVSSUBBU:
3727 return 0x0E898 << 15
3728 case AXVSSUBHU:
3729 return 0x0E899 << 15
3730 case AXVSSUBWU:
3731 return 0x0E89A << 15
3732 case AXVSSUBVU:
3733 return 0x0E89B << 15
3734 case AVILVLB:
3735 return 0xe234 << 15
3736 case AVILVLH:
3737 return 0xe235 << 15
3738 case AVILVLW:
3739 return 0xe236 << 15
3740 case AVILVLV:
3741 return 0xe237 << 15
3742 case AVILVHB:
3743 return 0xe238 << 15
3744 case AVILVHH:
3745 return 0xe239 << 15
3746 case AVILVHW:
3747 return 0xe23a << 15
3748 case AVILVHV:
3749 return 0xe23b << 15
3750 case AXVILVLB:
3751 return 0xea34 << 15
3752 case AXVILVLH:
3753 return 0xea35 << 15
3754 case AXVILVLW:
3755 return 0xea36 << 15
3756 case AXVILVLV:
3757 return 0xea37 << 15
3758 case AXVILVHB:
3759 return 0xea38 << 15
3760 case AXVILVHH:
3761 return 0xea39 << 15
3762 case AXVILVHW:
3763 return 0xea3a << 15
3764 case AXVILVHV:
3765 return 0xea3b << 15
3766 case AVMULB:
3767 return 0xe108 << 15
3768 case AVMULH:
3769 return 0xe109 << 15
3770 case AVMULW:
3771 return 0xe10a << 15
3772 case AVMULV:
3773 return 0xe10b << 15
3774 case AVMUHB:
3775 return 0xe10c << 15
3776 case AVMUHH:
3777 return 0xe10d << 15
3778 case AVMUHW:
3779 return 0xe10e << 15
3780 case AVMUHV:
3781 return 0xe10f << 15
3782 case AVMUHBU:
3783 return 0xe110 << 15
3784 case AVMUHHU:
3785 return 0xe111 << 15
3786 case AVMUHWU:
3787 return 0xe112 << 15
3788 case AVMUHVU:
3789 return 0xe113 << 15
3790 case AXVMULB:
3791 return 0xe908 << 15
3792 case AXVMULH:
3793 return 0xe909 << 15
3794 case AXVMULW:
3795 return 0xe90a << 15
3796 case AXVMULV:
3797 return 0xe90b << 15
3798 case AXVMUHB:
3799 return 0xe90c << 15
3800 case AXVMUHH:
3801 return 0xe90d << 15
3802 case AXVMUHW:
3803 return 0xe90e << 15
3804 case AXVMUHV:
3805 return 0xe90f << 15
3806 case AXVMUHBU:
3807 return 0xe910 << 15
3808 case AXVMUHHU:
3809 return 0xe911 << 15
3810 case AXVMUHWU:
3811 return 0xe912 << 15
3812 case AXVMUHVU:
3813 return 0xe913 << 15
3814 case AVADDF:
3815 return 0xe261 << 15
3816 case AVADDD:
3817 return 0xe262 << 15
3818 case AVSUBF:
3819 return 0xe265 << 15
3820 case AVSUBD:
3821 return 0xe266 << 15
3822 case AVMULF:
3823 return 0xe271 << 15
3824 case AVMULD:
3825 return 0xe272 << 15
3826 case AVDIVF:
3827 return 0xe275 << 15
3828 case AVDIVD:
3829 return 0xe276 << 15
3830 case AXVADDF:
3831 return 0xea61 << 15
3832 case AXVADDD:
3833 return 0xea62 << 15
3834 case AXVSUBF:
3835 return 0xea65 << 15
3836 case AXVSUBD:
3837 return 0xea66 << 15
3838 case AXVMULF:
3839 return 0xea71 << 15
3840 case AXVMULD:
3841 return 0xea72 << 15
3842 case AXVDIVF:
3843 return 0xea75 << 15
3844 case AXVDIVD:
3845 return 0xea76 << 15
3846 case AVBITCLRB:
3847 return 0xe218 << 15
3848 case AVBITCLRH:
3849 return 0xe219 << 15
3850 case AVBITCLRW:
3851 return 0xe21a << 15
3852 case AVBITCLRV:
3853 return 0xe21b << 15
3854 case AVBITSETB:
3855 return 0xe21c << 15
3856 case AVBITSETH:
3857 return 0xe21d << 15
3858 case AVBITSETW:
3859 return 0xe21e << 15
3860 case AVBITSETV:
3861 return 0xe21f << 15
3862 case AVBITREVB:
3863 return 0xe220 << 15
3864 case AVBITREVH:
3865 return 0xe221 << 15
3866 case AVBITREVW:
3867 return 0xe222 << 15
3868 case AVBITREVV:
3869 return 0xe223 << 15
3870 case AXVBITCLRB:
3871 return 0xea18 << 15
3872 case AXVBITCLRH:
3873 return 0xea19 << 15
3874 case AXVBITCLRW:
3875 return 0xea1a << 15
3876 case AXVBITCLRV:
3877 return 0xea1b << 15
3878 case AXVBITSETB:
3879 return 0xea1c << 15
3880 case AXVBITSETH:
3881 return 0xea1d << 15
3882 case AXVBITSETW:
3883 return 0xea1e << 15
3884 case AXVBITSETV:
3885 return 0xea1f << 15
3886 case AXVBITREVB:
3887 return 0xea20 << 15
3888 case AXVBITREVH:
3889 return 0xea21 << 15
3890 case AXVBITREVW:
3891 return 0xea22 << 15
3892 case AXVBITREVV:
3893 return 0xea23 << 15
3894 case AVSHUFH:
3895 return 0x0E2F5 << 15
3896 case AVSHUFW:
3897 return 0x0E2F6 << 15
3898 case AVSHUFV:
3899 return 0x0E2F7 << 15
3900 case AXVSHUFH:
3901 return 0x0EAF5 << 15
3902 case AXVSHUFW:
3903 return 0x0EAF6 << 15
3904 case AXVSHUFV:
3905 return 0x0EAF7 << 15
3906 }
3907
3908 if a < 0 {
3909 c.ctxt.Diag("bad rrr opcode -%v", -a)
3910 } else {
3911 c.ctxt.Diag("bad rrr opcode %v", a)
3912 }
3913 return 0
3914 }
3915
3916 func (c *ctxt0) oprr(a obj.As) uint32 {
3917 switch a {
3918 case ACLOW:
3919 return 0x4 << 10
3920 case ACLZW:
3921 return 0x5 << 10
3922 case ACTOW:
3923 return 0x6 << 10
3924 case ACTZW:
3925 return 0x7 << 10
3926 case ACLOV:
3927 return 0x8 << 10
3928 case ACLZV:
3929 return 0x9 << 10
3930 case ACTOV:
3931 return 0xa << 10
3932 case ACTZV:
3933 return 0xb << 10
3934 case AREVB2H:
3935 return 0xc << 10
3936 case AREVB4H:
3937 return 0xd << 10
3938 case AREVB2W:
3939 return 0xe << 10
3940 case AREVBV:
3941 return 0xf << 10
3942 case AREVH2W:
3943 return 0x10 << 10
3944 case AREVHV:
3945 return 0x11 << 10
3946 case ABITREV4B:
3947 return 0x12 << 10
3948 case ABITREV8B:
3949 return 0x13 << 10
3950 case ABITREVW:
3951 return 0x14 << 10
3952 case ABITREVV:
3953 return 0x15 << 10
3954 case AEXTWH:
3955 return 0x16 << 10
3956 case AEXTWB:
3957 return 0x17 << 10
3958 case ACPUCFG:
3959 return 0x1b << 10
3960 case ARDTIMELW:
3961 return 0x18 << 10
3962 case ARDTIMEHW:
3963 return 0x19 << 10
3964 case ARDTIMED:
3965 return 0x1a << 10
3966 case ATRUNCFV:
3967 return 0x46a9 << 10
3968 case ATRUNCDV:
3969 return 0x46aa << 10
3970 case ATRUNCFW:
3971 return 0x46a1 << 10
3972 case ATRUNCDW:
3973 return 0x46a2 << 10
3974 case AMOVFV:
3975 return 0x46c9 << 10
3976 case AMOVDV:
3977 return 0x46ca << 10
3978 case AMOVVF:
3979 return 0x4746 << 10
3980 case AMOVVD:
3981 return 0x474a << 10
3982 case AMOVFW:
3983 return 0x46c1 << 10
3984 case AMOVDW:
3985 return 0x46c2 << 10
3986 case AMOVWF:
3987 return 0x4744 << 10
3988 case AMOVDF:
3989 return 0x4646 << 10
3990 case AMOVWD:
3991 return 0x4748 << 10
3992 case AMOVFD:
3993 return 0x4649 << 10
3994 case AABSF:
3995 return 0x4501 << 10
3996 case AABSD:
3997 return 0x4502 << 10
3998 case AMOVF:
3999 return 0x4525 << 10
4000 case AMOVD:
4001 return 0x4526 << 10
4002 case ANEGF:
4003 return 0x4505 << 10
4004 case ANEGD:
4005 return 0x4506 << 10
4006 case ASQRTF:
4007 return 0x4511 << 10
4008 case ASQRTD:
4009 return 0x4512 << 10
4010 case AFLOGBF:
4011 return 0x4509 << 10
4012 case AFLOGBD:
4013 return 0x450a << 10
4014 case AFCLASSF:
4015 return 0x450d << 10
4016 case AFCLASSD:
4017 return 0x450e << 10
4018 case AFFINTFW:
4019 return 0x4744 << 10
4020 case AFFINTFV:
4021 return 0x4746 << 10
4022 case AFFINTDW:
4023 return 0x4748 << 10
4024 case AFFINTDV:
4025 return 0x474a << 10
4026 case AFTINTWF:
4027 return 0x46c1 << 10
4028 case AFTINTWD:
4029 return 0x46c2 << 10
4030 case AFTINTVF:
4031 return 0x46c9 << 10
4032 case AFTINTVD:
4033 return 0x46ca << 10
4034 case AFTINTRMWF:
4035 return 0x4681 << 10
4036 case AFTINTRMWD:
4037 return 0x4682 << 10
4038 case AFTINTRMVF:
4039 return 0x4689 << 10
4040 case AFTINTRMVD:
4041 return 0x468a << 10
4042 case AFTINTRPWF:
4043 return 0x4691 << 10
4044 case AFTINTRPWD:
4045 return 0x4692 << 10
4046 case AFTINTRPVF:
4047 return 0x4699 << 10
4048 case AFTINTRPVD:
4049 return 0x469a << 10
4050 case AFTINTRZWF:
4051 return 0x46a1 << 10
4052 case AFTINTRZWD:
4053 return 0x46a2 << 10
4054 case AFTINTRZVF:
4055 return 0x46a9 << 10
4056 case AFTINTRZVD:
4057 return 0x46aa << 10
4058 case AFTINTRNEWF:
4059 return 0x46b1 << 10
4060 case AFTINTRNEWD:
4061 return 0x46b2 << 10
4062 case AFTINTRNEVF:
4063 return 0x46b9 << 10
4064 case AFTINTRNEVD:
4065 return 0x46ba << 10
4066 case AVPCNTB:
4067 return 0x1ca708 << 10
4068 case AVPCNTH:
4069 return 0x1ca709 << 10
4070 case AVPCNTW:
4071 return 0x1ca70a << 10
4072 case AVPCNTV:
4073 return 0x1ca70b << 10
4074 case AXVPCNTB:
4075 return 0x1da708 << 10
4076 case AXVPCNTH:
4077 return 0x1da709 << 10
4078 case AXVPCNTW:
4079 return 0x1da70a << 10
4080 case AXVPCNTV:
4081 return 0x1da70b << 10
4082 case AVFSQRTF:
4083 return 0x1ca739 << 10
4084 case AVFSQRTD:
4085 return 0x1ca73a << 10
4086 case AVFRECIPF:
4087 return 0x1ca73d << 10
4088 case AVFRECIPD:
4089 return 0x1ca73e << 10
4090 case AVFRSQRTF:
4091 return 0x1ca741 << 10
4092 case AVFRSQRTD:
4093 return 0x1ca742 << 10
4094 case AXVFSQRTF:
4095 return 0x1da739 << 10
4096 case AXVFSQRTD:
4097 return 0x1da73a << 10
4098 case AXVFRECIPF:
4099 return 0x1da73d << 10
4100 case AXVFRECIPD:
4101 return 0x1da73e << 10
4102 case AXVFRSQRTF:
4103 return 0x1da741 << 10
4104 case AXVFRSQRTD:
4105 return 0x1da742 << 10
4106 case AVNEGB:
4107 return 0x1ca70c << 10
4108 case AVNEGH:
4109 return 0x1ca70d << 10
4110 case AVNEGW:
4111 return 0x1ca70e << 10
4112 case AVNEGV:
4113 return 0x1ca70f << 10
4114 case AXVNEGB:
4115 return 0x1da70c << 10
4116 case AXVNEGH:
4117 return 0x1da70d << 10
4118 case AXVNEGW:
4119 return 0x1da70e << 10
4120 case AXVNEGV:
4121 return 0x1da70f << 10
4122 case AVFRINTRNEF:
4123 return 0x1ca75d << 10
4124 case AVFRINTRNED:
4125 return 0x1ca75e << 10
4126 case AVFRINTRZF:
4127 return 0x1ca759 << 10
4128 case AVFRINTRZD:
4129 return 0x1ca75a << 10
4130 case AVFRINTRPF:
4131 return 0x1ca755 << 10
4132 case AVFRINTRPD:
4133 return 0x1ca756 << 10
4134 case AVFRINTRMF:
4135 return 0x1ca751 << 10
4136 case AVFRINTRMD:
4137 return 0x1ca752 << 10
4138 case AVFRINTF:
4139 return 0x1ca74d << 10
4140 case AVFRINTD:
4141 return 0x1ca74e << 10
4142 case AXVFRINTRNEF:
4143 return 0x1da75d << 10
4144 case AXVFRINTRNED:
4145 return 0x1da75e << 10
4146 case AXVFRINTRZF:
4147 return 0x1da759 << 10
4148 case AXVFRINTRZD:
4149 return 0x1da75a << 10
4150 case AXVFRINTRPF:
4151 return 0x1da755 << 10
4152 case AXVFRINTRPD:
4153 return 0x1da756 << 10
4154 case AXVFRINTRMF:
4155 return 0x1da751 << 10
4156 case AXVFRINTRMD:
4157 return 0x1da752 << 10
4158 case AXVFRINTF:
4159 return 0x1da74d << 10
4160 case AXVFRINTD:
4161 return 0x1da74e << 10
4162 case AVFCLASSF:
4163 return 0x1ca735 << 10
4164 case AVFCLASSD:
4165 return 0x1ca736 << 10
4166 case AXVFCLASSF:
4167 return 0x1da735 << 10
4168 case AXVFCLASSD:
4169 return 0x1da736 << 10
4170 case AVSETEQV:
4171 return 0x1ca726<<10 | 0x0<<3
4172 case AVSETNEV:
4173 return 0x1ca727<<10 | 0x0<<3
4174 case AVSETANYEQB:
4175 return 0x1ca728<<10 | 0x0<<3
4176 case AVSETANYEQH:
4177 return 0x1ca729<<10 | 0x0<<3
4178 case AVSETANYEQW:
4179 return 0x1ca72a<<10 | 0x0<<3
4180 case AVSETANYEQV:
4181 return 0x1ca72b<<10 | 0x0<<3
4182 case AVSETALLNEB:
4183 return 0x1ca72c<<10 | 0x0<<3
4184 case AVSETALLNEH:
4185 return 0x1ca72d<<10 | 0x0<<3
4186 case AVSETALLNEW:
4187 return 0x1ca72e<<10 | 0x0<<3
4188 case AVSETALLNEV:
4189 return 0x1ca72f<<10 | 0x0<<3
4190 case AXVSETEQV:
4191 return 0x1da726<<10 | 0x0<<3
4192 case AXVSETNEV:
4193 return 0x1da727<<10 | 0x0<<3
4194 case AXVSETANYEQB:
4195 return 0x1da728<<10 | 0x0<<3
4196 case AXVSETANYEQH:
4197 return 0x1da729<<10 | 0x0<<3
4198 case AXVSETANYEQW:
4199 return 0x1da72a<<10 | 0x0<<3
4200 case AXVSETANYEQV:
4201 return 0x1da72b<<10 | 0x0<<3
4202 case AXVSETALLNEB:
4203 return 0x1da72c<<10 | 0x0<<3
4204 case AXVSETALLNEH:
4205 return 0x1da72d<<10 | 0x0<<3
4206 case AXVSETALLNEW:
4207 return 0x1da72e<<10 | 0x0<<3
4208 case AXVSETALLNEV:
4209 return 0x1da72f<<10 | 0x0<<3
4210 }
4211
4212 c.ctxt.Diag("bad rr opcode %v", a)
4213 return 0
4214 }
4215
4216 func (c *ctxt0) opi(a obj.As) uint32 {
4217 switch a {
4218 case ASYSCALL:
4219 return 0x56 << 15
4220 case ABREAK:
4221 return 0x54 << 15
4222 case ADBAR:
4223 return 0x70e4 << 15
4224 }
4225
4226 c.ctxt.Diag("bad ic opcode %v", a)
4227
4228 return 0
4229 }
4230
4231 func (c *ctxt0) opir(a obj.As) uint32 {
4232 switch a {
4233 case ALU12IW:
4234 return 0x0a << 25
4235 case ALU32ID:
4236 return 0x0b << 25
4237 case APCALAU12I:
4238 return 0x0d << 25
4239 case APCADDU12I:
4240 return 0x0e << 25
4241 }
4242 return 0
4243 }
4244
4245 func (c *ctxt0) opirr(a obj.As) uint32 {
4246 switch a {
4247 case AADD, AADDU:
4248 return 0x00a << 22
4249 case ASGT:
4250 return 0x008 << 22
4251 case ASGTU:
4252 return 0x009 << 22
4253 case AAND:
4254 return 0x00d << 22
4255 case AOR:
4256 return 0x00e << 22
4257 case ALU52ID:
4258 return 0x00c << 22
4259 case AXOR:
4260 return 0x00f << 22
4261 case ASLL:
4262 return 0x00081 << 15
4263 case ASRL:
4264 return 0x00089 << 15
4265 case ASRA:
4266 return 0x00091 << 15
4267 case AROTR:
4268 return 0x00099 << 15
4269 case AADDV:
4270 return 0x00b << 22
4271 case AADDVU:
4272 return 0x00b << 22
4273 case AADDV16:
4274 return 0x4 << 26
4275
4276 case AJMP:
4277 return 0x14 << 26
4278 case AJAL:
4279 return 0x15 << 26
4280
4281 case AJIRL:
4282 return 0x13 << 26
4283 case ABLTU:
4284 return 0x1a << 26
4285 case ABLT, ABLTZ, ABGTZ:
4286 return 0x18 << 26
4287 case ABGEU:
4288 return 0x1b << 26
4289 case ABGE, ABGEZ, ABLEZ:
4290 return 0x19 << 26
4291 case -ABEQ:
4292 return 0x10 << 26
4293 case -ABNE:
4294 return 0x11 << 26
4295 case ABEQ:
4296 return 0x16 << 26
4297 case ABNE:
4298 return 0x17 << 26
4299 case ABFPT:
4300 return 0x12<<26 | 0x1<<8
4301 case ABFPF:
4302 return 0x12<<26 | 0x0<<8
4303 case APRELDX:
4304 return 0x07058 << 15
4305 case AMOVB,
4306 AMOVBU:
4307 return 0x0a4 << 22
4308 case AMOVH,
4309 AMOVHU:
4310 return 0x0a5 << 22
4311 case AMOVW,
4312 AMOVWU:
4313 return 0x0a6 << 22
4314 case AMOVV:
4315 return 0x0a7 << 22
4316 case AMOVF:
4317 return 0x0ad << 22
4318 case AMOVD:
4319 return 0x0af << 22
4320 case AMOVVP:
4321 return 0x27 << 24
4322 case AMOVWP:
4323 return 0x25 << 24
4324 case -AMOVB:
4325 return 0x0a0 << 22
4326 case -AMOVBU:
4327 return 0x0a8 << 22
4328 case -AMOVH:
4329 return 0x0a1 << 22
4330 case -AMOVHU:
4331 return 0x0a9 << 22
4332 case -AMOVW:
4333 return 0x0a2 << 22
4334 case -AMOVWU:
4335 return 0x0aa << 22
4336 case -AMOVV:
4337 return 0x0a3 << 22
4338 case -AMOVF:
4339 return 0x0ac << 22
4340 case -AMOVD:
4341 return 0x0ae << 22
4342 case -AMOVVP:
4343 return 0x26 << 24
4344 case -AMOVWP:
4345 return 0x24 << 24
4346 case -AVMOVQ:
4347 return 0x0b0 << 22
4348 case -AXVMOVQ:
4349 return 0x0b2 << 22
4350 case AVMOVQ:
4351 return 0x0b1 << 22
4352 case AXVMOVQ:
4353 return 0x0b3 << 22
4354 case ASLLV:
4355 return 0x0041 << 16
4356 case ASRLV:
4357 return 0x0045 << 16
4358 case ASRAV:
4359 return 0x0049 << 16
4360 case AROTRV:
4361 return 0x004d << 16
4362 case -ALL:
4363 return 0x020 << 24
4364 case -ALLV:
4365 return 0x022 << 24
4366 case ASC:
4367 return 0x021 << 24
4368 case ASCV:
4369 return 0x023 << 24
4370 case AVANDB:
4371 return 0x1CF4 << 18
4372 case AVORB:
4373 return 0x1CF5 << 18
4374 case AVXORB:
4375 return 0x1CF6 << 18
4376 case AVNORB:
4377 return 0x1CF7 << 18
4378 case AXVANDB:
4379 return 0x1DF4 << 18
4380 case AXVORB:
4381 return 0x1DF5 << 18
4382 case AXVXORB:
4383 return 0x1DF6 << 18
4384 case AXVNORB:
4385 return 0x1DF7 << 18
4386 case AVSEQB:
4387 return 0x0E500 << 15
4388 case AVSEQH:
4389 return 0x0E501 << 15
4390 case AVSEQW:
4391 return 0x0E502 << 15
4392 case AVSEQV:
4393 return 0x0E503 << 15
4394 case AXVSEQB:
4395 return 0x0ED00 << 15
4396 case AXVSEQH:
4397 return 0x0ED01 << 15
4398 case AXVSEQW:
4399 return 0x0ED02 << 15
4400 case AXVSEQV:
4401 return 0x0ED03 << 15
4402 case AVROTRB:
4403 return 0x1ca8<<18 | 0x1<<13
4404 case AVROTRH:
4405 return 0x1ca8<<18 | 0x1<<14
4406 case AVROTRW:
4407 return 0x1ca8<<18 | 0x1<<15
4408 case AVROTRV:
4409 return 0x1ca8<<18 | 0x1<<16
4410 case AXVROTRB:
4411 return 0x1da8<<18 | 0x1<<13
4412 case AXVROTRH:
4413 return 0x1da8<<18 | 0x1<<14
4414 case AXVROTRW:
4415 return 0x1da8<<18 | 0x1<<15
4416 case AXVROTRV:
4417 return 0x1da8<<18 | 0x1<<16
4418 case AVSLLB:
4419 return 0x1ccb<<18 | 0x1<<13
4420 case AVSLLH:
4421 return 0x1ccb<<18 | 0x1<<14
4422 case AVSLLW:
4423 return 0x1ccb<<18 | 0x1<<15
4424 case AVSLLV:
4425 return 0x1ccb<<18 | 0x1<<16
4426 case AVSRLB:
4427 return 0x1ccc<<18 | 0x1<<13
4428 case AVSRLH:
4429 return 0x1ccc<<18 | 0x1<<14
4430 case AVSRLW:
4431 return 0x1ccc<<18 | 0x1<<15
4432 case AVSRLV:
4433 return 0x1ccc<<18 | 0x1<<16
4434 case AVSRAB:
4435 return 0x1ccd<<18 | 0x1<<13
4436 case AVSRAH:
4437 return 0x1ccd<<18 | 0x1<<14
4438 case AVSRAW:
4439 return 0x1ccd<<18 | 0x1<<15
4440 case AVSRAV:
4441 return 0x1ccd<<18 | 0x1<<16
4442 case AXVSLLB:
4443 return 0x1dcb<<18 | 0x1<<13
4444 case AXVSLLH:
4445 return 0x1dcb<<18 | 0x1<<14
4446 case AXVSLLW:
4447 return 0x1dcb<<18 | 0x1<<15
4448 case AXVSLLV:
4449 return 0x1dcb<<18 | 0x1<<16
4450 case AXVSRLB:
4451 return 0x1dcc<<18 | 0x1<<13
4452 case AXVSRLH:
4453 return 0x1dcc<<18 | 0x1<<14
4454 case AXVSRLW:
4455 return 0x1dcc<<18 | 0x1<<15
4456 case AXVSRLV:
4457 return 0x1dcc<<18 | 0x1<<16
4458 case AXVSRAB:
4459 return 0x1dcd<<18 | 0x1<<13
4460 case AXVSRAH:
4461 return 0x1dcd<<18 | 0x1<<14
4462 case AXVSRAW:
4463 return 0x1dcd<<18 | 0x1<<15
4464 case AXVSRAV:
4465 return 0x1dcd<<18 | 0x1<<16
4466 case AVADDBU:
4467 return 0xe514 << 15
4468 case AVADDHU:
4469 return 0xe515 << 15
4470 case AVADDWU:
4471 return 0xe516 << 15
4472 case AVADDVU:
4473 return 0xe517 << 15
4474 case AVSUBBU:
4475 return 0xe518 << 15
4476 case AVSUBHU:
4477 return 0xe519 << 15
4478 case AVSUBWU:
4479 return 0xe51a << 15
4480 case AVSUBVU:
4481 return 0xe51b << 15
4482 case AXVADDBU:
4483 return 0xed14 << 15
4484 case AXVADDHU:
4485 return 0xed15 << 15
4486 case AXVADDWU:
4487 return 0xed16 << 15
4488 case AXVADDVU:
4489 return 0xed17 << 15
4490 case AXVSUBBU:
4491 return 0xed18 << 15
4492 case AXVSUBHU:
4493 return 0xed19 << 15
4494 case AXVSUBWU:
4495 return 0xed1a << 15
4496 case AXVSUBVU:
4497 return 0xed1b << 15
4498 case AVSHUF4IB:
4499 return 0x1ce4 << 18
4500 case AVSHUF4IH:
4501 return 0x1ce5 << 18
4502 case AVSHUF4IW:
4503 return 0x1ce6 << 18
4504 case AVSHUF4IV:
4505 return 0x1ce7 << 18
4506 case AXVSHUF4IB:
4507 return 0x1de4 << 18
4508 case AXVSHUF4IH:
4509 return 0x1de5 << 18
4510 case AXVSHUF4IW:
4511 return 0x1de6 << 18
4512 case AXVSHUF4IV:
4513 return 0x1de7 << 18
4514 case AVPERMIW:
4515 return 0x1cf9 << 18
4516 case AXVPERMIW:
4517 return 0x1df9 << 18
4518 case AXVPERMIV:
4519 return 0x1dfa << 18
4520 case AXVPERMIQ:
4521 return 0x1dfb << 18
4522 case AVEXTRINSB:
4523 return 0x1ce3 << 18
4524 case AVEXTRINSH:
4525 return 0x1ce2 << 18
4526 case AVEXTRINSW:
4527 return 0x1ce1 << 18
4528 case AVEXTRINSV:
4529 return 0x1ce0 << 18
4530 case AXVEXTRINSB:
4531 return 0x1de3 << 18
4532 case AXVEXTRINSH:
4533 return 0x1de2 << 18
4534 case AXVEXTRINSW:
4535 return 0x1de1 << 18
4536 case AXVEXTRINSV:
4537 return 0x1de0 << 18
4538 case AVBITCLRB:
4539 return 0x1CC4<<18 | 0x1<<13
4540 case AVBITCLRH:
4541 return 0x1CC4<<18 | 0x1<<14
4542 case AVBITCLRW:
4543 return 0x1CC4<<18 | 0x1<<15
4544 case AVBITCLRV:
4545 return 0x1CC4<<18 | 0x1<<16
4546 case AVBITSETB:
4547 return 0x1CC5<<18 | 0x1<<13
4548 case AVBITSETH:
4549 return 0x1CC5<<18 | 0x1<<14
4550 case AVBITSETW:
4551 return 0x1CC5<<18 | 0x1<<15
4552 case AVBITSETV:
4553 return 0x1CC5<<18 | 0x1<<16
4554 case AVBITREVB:
4555 return 0x1CC6<<18 | 0x1<<13
4556 case AVBITREVH:
4557 return 0x1CC6<<18 | 0x1<<14
4558 case AVBITREVW:
4559 return 0x1CC6<<18 | 0x1<<15
4560 case AVBITREVV:
4561 return 0x1CC6<<18 | 0x1<<16
4562 case AXVBITCLRB:
4563 return 0x1DC4<<18 | 0x1<<13
4564 case AXVBITCLRH:
4565 return 0x1DC4<<18 | 0x1<<14
4566 case AXVBITCLRW:
4567 return 0x1DC4<<18 | 0x1<<15
4568 case AXVBITCLRV:
4569 return 0x1DC4<<18 | 0x1<<16
4570 case AXVBITSETB:
4571 return 0x1DC5<<18 | 0x1<<13
4572 case AXVBITSETH:
4573 return 0x1DC5<<18 | 0x1<<14
4574 case AXVBITSETW:
4575 return 0x1DC5<<18 | 0x1<<15
4576 case AXVBITSETV:
4577 return 0x1DC5<<18 | 0x1<<16
4578 case AXVBITREVB:
4579 return 0x1DC6<<18 | 0x1<<13
4580 case AXVBITREVH:
4581 return 0x1DC6<<18 | 0x1<<14
4582 case AXVBITREVW:
4583 return 0x1DC6<<18 | 0x1<<15
4584 case AXVBITREVV:
4585 return 0x1DC6<<18 | 0x1<<16
4586 }
4587
4588 if a < 0 {
4589 c.ctxt.Diag("bad irr opcode -%v", -a)
4590 } else {
4591 c.ctxt.Diag("bad irr opcode %v", a)
4592 }
4593 return 0
4594 }
4595
4596 func (c *ctxt0) opirrr(a obj.As) uint32 {
4597 switch a {
4598 case AALSLW:
4599 return 0x2 << 17
4600 case AALSLWU:
4601 return 0x3 << 17
4602 case AALSLV:
4603 return 0x16 << 17
4604 }
4605
4606 return 0
4607 }
4608
4609 func (c *ctxt0) opirir(a obj.As) uint32 {
4610 switch a {
4611 case ABSTRINSW:
4612 return 0x3<<21 | 0x0<<15
4613 case ABSTRINSV:
4614 return 0x2 << 22
4615 case ABSTRPICKW:
4616 return 0x3<<21 | 0x1<<15
4617 case ABSTRPICKV:
4618 return 0x3 << 22
4619 }
4620
4621 return 0
4622 }
4623
4624 func (c *ctxt0) opiir(a obj.As) uint32 {
4625 switch a {
4626 case APRELD:
4627 return 0x0AB << 22
4628 }
4629
4630 return 0
4631 }
4632
4633 func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 {
4634 switch a {
4635 case AMOVV:
4636 switch fclass {
4637 case C_REG:
4638 switch tclass {
4639 case C_FREG:
4640 return 0x452a << 10
4641 case C_FCCREG:
4642 return 0x4536 << 10
4643 case C_FCSRREG:
4644 return 0x4530 << 10
4645 }
4646 case C_FREG:
4647 switch tclass {
4648 case C_REG:
4649 return 0x452e << 10
4650 case C_FCCREG:
4651 return 0x4534 << 10
4652 }
4653 case C_FCCREG:
4654 switch tclass {
4655 case C_REG:
4656 return 0x4537 << 10
4657 case C_FREG:
4658 return 0x4535 << 10
4659 }
4660 case C_FCSRREG:
4661 switch tclass {
4662 case C_REG:
4663 return 0x4532 << 10
4664 }
4665 }
4666
4667 case AMOVW:
4668 switch fclass {
4669 case C_REG:
4670 switch tclass {
4671 case C_FREG:
4672 return 0x4529 << 10
4673 }
4674 case C_FREG:
4675 switch tclass {
4676 case C_REG:
4677 return 0x452d << 10
4678 }
4679 }
4680 }
4681
4682 c.ctxt.Diag("bad class combination: %s %d,%d\n", a, fclass, tclass)
4683
4684 return 0
4685 }
4686
4687 func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) {
4688 farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
4689 tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
4690 fclass := c.rclass(fReg)
4691 tclass := c.rclass(tReg)
4692
4693 switch fclass | (tclass << 16) {
4694 case C_REG | (C_ELEM << 16):
4695
4696 switch a {
4697 case AVMOVQ:
4698 switch tarng {
4699 case ARNG_B:
4700 return (0x01CBAE << 14), 0xf
4701 case ARNG_H:
4702 return (0x03975E << 13), 0x7
4703 case ARNG_W:
4704 return (0x072EBE << 12), 0x3
4705 case ARNG_V:
4706 return (0x0E5D7E << 11), 0x1
4707 }
4708 case AXVMOVQ:
4709 switch tarng {
4710 case ARNG_W:
4711 return (0x03B75E << 13), 0x7
4712 case ARNG_V:
4713 return (0x076EBE << 12), 0x3
4714 }
4715 }
4716
4717 case C_ELEM | (C_REG << 16):
4718
4719 switch a {
4720 case AVMOVQ:
4721 switch farng {
4722 case ARNG_B:
4723 return (0x01CBBE << 14), 0xf
4724 case ARNG_H:
4725 return (0x03977E << 13), 0x7
4726 case ARNG_W:
4727 return (0x072EFE << 12), 0x3
4728 case ARNG_V:
4729 return (0x0E5DFE << 11), 0x1
4730 case ARNG_BU:
4731 return (0x01CBCE << 14), 0xf
4732 case ARNG_HU:
4733 return (0x03979E << 13), 0x7
4734 case ARNG_WU:
4735 return (0x072F3E << 12), 0x3
4736 case ARNG_VU:
4737 return (0x0E5E7E << 11), 0x1
4738 }
4739 case AXVMOVQ:
4740 switch farng {
4741 case ARNG_W:
4742 return (0x03B77E << 13), 0x7
4743 case ARNG_V:
4744 return (0x076EFE << 12), 0x3
4745 case ARNG_WU:
4746 return (0x03B79E << 13), 0x7
4747 case ARNG_VU:
4748 return (0x076F3E << 12), 0x3
4749 }
4750 }
4751
4752 case C_REG | (C_ARNG << 16):
4753 switch {
4754 case offset_flag:
4755
4756 switch a {
4757 case AVMOVQ:
4758 switch tarng {
4759 case ARNG_16B:
4760 return (0xC2 << 22), 0x0
4761 case ARNG_8H:
4762 return (0x182 << 21), 0x0
4763 case ARNG_4W:
4764 return (0x302 << 20), 0x0
4765 case ARNG_2V:
4766 return (0x602 << 19), 0x0
4767 }
4768 case AXVMOVQ:
4769 switch tarng {
4770 case ARNG_32B:
4771 return (0xCA << 22), 0x0
4772 case ARNG_16H:
4773 return (0x192 << 21), 0x0
4774 case ARNG_8W:
4775 return (0x322 << 20), 0x0
4776 case ARNG_4V:
4777 return (0x642 << 19), 0x0
4778 }
4779 }
4780 default:
4781
4782 switch a {
4783 case AVMOVQ:
4784 switch tarng {
4785 case ARNG_16B:
4786 return (0x1CA7C0 << 10), 0x0
4787 case ARNG_8H:
4788 return (0x1CA7C1 << 10), 0x0
4789 case ARNG_4W:
4790 return (0x1CA7C2 << 10), 0x0
4791 case ARNG_2V:
4792 return (0x1CA7C3 << 10), 0x0
4793 }
4794 case AXVMOVQ:
4795 switch tarng {
4796 case ARNG_32B:
4797 return (0x1DA7C0 << 10), 0x0
4798 case ARNG_16H:
4799 return (0x1DA7C1 << 10), 0x0
4800 case ARNG_8W:
4801 return (0x1DA7C2 << 10), 0x0
4802 case ARNG_4V:
4803 return (0x1DA7C3 << 10), 0x0
4804 }
4805 }
4806 }
4807
4808 case C_XREG | (C_ARNG << 16):
4809
4810 switch a {
4811 case AVMOVQ:
4812 return 0, 0
4813 case AXVMOVQ:
4814 switch tarng {
4815 case ARNG_32B:
4816 return (0x1DC1C0 << 10), 0x0
4817 case ARNG_16H:
4818 return (0x1DC1E0 << 10), 0x0
4819 case ARNG_8W:
4820 return (0x1DC1F0 << 10), 0x0
4821 case ARNG_4V:
4822 return (0x1DC1F8 << 10), 0x0
4823 case ARNG_2Q:
4824 return (0x1DC1FC << 10), 0x0
4825 }
4826 }
4827
4828 case C_XREG | (C_ELEM << 16):
4829
4830 switch a {
4831 case AVMOVQ:
4832 return 0, 0
4833 case AXVMOVQ:
4834 switch tarng {
4835 case ARNG_W:
4836 return (0x03B7FE << 13), 0x7
4837 case ARNG_V:
4838 return (0x076FFE << 12), 0x3
4839 }
4840 }
4841
4842 case C_ELEM | (C_XREG << 16):
4843
4844 switch a {
4845 case AVMOVQ:
4846 return 0, 0
4847 case AXVMOVQ:
4848 switch farng {
4849 case ARNG_W:
4850 return (0x03B81E << 13), 0x7
4851 case ARNG_V:
4852 return (0x07703E << 12), 0x3
4853 }
4854 }
4855
4856 case C_ELEM | (C_ARNG << 16):
4857
4858 switch a {
4859 case AVMOVQ:
4860 switch int32(farng) | (int32(tarng) << 16) {
4861 case int32(ARNG_B) | (int32(ARNG_16B) << 16):
4862 return (0x01CBDE << 14), 0xf
4863 case int32(ARNG_H) | (int32(ARNG_8H) << 16):
4864 return (0x0397BE << 13), 0x7
4865 case int32(ARNG_W) | (int32(ARNG_4W) << 16):
4866 return (0x072F7E << 12), 0x3
4867 case int32(ARNG_V) | (int32(ARNG_2V) << 16):
4868 return (0x0E5EFE << 11), 0x1
4869 }
4870 case AXVMOVQ:
4871 return 0, 0
4872 }
4873 }
4874
4875 return 0, 0
4876 }
4877
4878 func vshift(a obj.As) bool {
4879 switch a {
4880 case ASLLV,
4881 ASRLV,
4882 ASRAV,
4883 AROTRV:
4884 return true
4885 }
4886 return false
4887 }
4888
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