1
2
3
4
5 package loong64
6
7 import (
8 "cmd/internal/obj"
9 "cmd/internal/objabi"
10 "fmt"
11 "log"
12 "math/bits"
13 "slices"
14 )
15
16
17
18
19 type ctxt0 struct {
20 ctxt *obj.Link
21 newprog obj.ProgAlloc
22 cursym *obj.LSym
23 autosize int32
24 instoffset int64
25 pc int64
26 }
27
28
29
30 const (
31 FuncAlign = 4
32 loopAlign = 16
33 )
34
35 type Optab struct {
36 as obj.As
37 from1 uint8
38 reg uint8
39 from3 uint8
40 to1 uint8
41 to2 uint8
42 type_ int8
43 size int8
44 param int16
45 flag uint8
46 }
47
48 const (
49 NOTUSETMP = 1 << iota
50
51
52
53 branchLoopHead
54 )
55
56 var optab = []Optab{
57 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, C_NONE, 0, 0, 0, 0},
58
59 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
60 {AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
61 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 1, 4, 0, 0},
62 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 1, 4, 0, 0},
63 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
64 {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
65 {AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
66
67 {ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
68 {AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
69 {AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
70 {AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
71 {ASUB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
72 {AADD, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
73 {AADDV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
74 {AAND, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
75 {ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
76 {AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
77 {ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
78 {ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
79 {ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
80 {ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
81 {AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
82 {AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
83 {ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
84
85 {AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
86 {AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
87 {AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0},
88 {AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0},
89
90 {AVSLTB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
91 {AXVSLTB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
92 {AVSLTB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0},
93 {AXVSLTB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0},
94 {AVSLTB, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
95 {AXVSLTB, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
96
97 {AVANDV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
98 {AVANDV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
99 {AXVANDV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
100 {AXVANDV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
101 {AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
102 {AVANDB, C_U8CON, C_NONE, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
103 {AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
104 {AXVANDB, C_U8CON, C_NONE, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
105
106 {AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
107 {AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
108 {AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
109 {AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
110
111 {AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
112 {AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
113 {AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
114 {AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
115 {AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
116 {AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
117 {AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
118 {AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
119
120 {AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
121 {AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
122 {AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
123 {AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
124 {AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
125 {AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
126 {AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
127 {AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
128
129 {AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
130 {AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
131 {AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
132 {AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
133 {AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
134 {AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
135 {AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
136 {AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
137
138 {AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
139 {AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
140 {AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
141 {AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
142 {AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
143 {AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
144 {AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
145 {AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
146
147 {ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
148 {AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
149 {AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
150 {AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
151 {AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
152 {AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0},
153 {AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0},
154 {AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
155 {AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
156
157 {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
158 {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
159 {AVSHUFB, C_VREG, C_VREG, C_VREG, C_VREG, C_NONE, 37, 4, 0, 0},
160 {AXVSHUFB, C_XREG, C_XREG, C_XREG, C_XREG, C_NONE, 37, 4, 0, 0},
161
162 {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
163 {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
164
165 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
166 {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
167 {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
168 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
169 {AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
170 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
171 {AMOVWU, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
172 {AMOVV, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
173 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
174 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
175 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
176 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 7, 4, REGZERO, 0},
177 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
178 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
179
180 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
181 {AMOVWU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
182 {AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
183 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
184 {AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
185 {AMOVW, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
186 {AMOVWU, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
187 {AMOVV, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
188 {AMOVB, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
189 {AMOVBU, C_SOREG_12, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
190 {AVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
191 {AXVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
192 {AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
193 {AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
194
195 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
196 {AMOVWU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
197 {AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
198 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
199 {AMOVBU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
200 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
201 {AMOVWU, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
202 {AMOVV, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
203 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
204 {AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 35, 12, REGZERO, 0},
205 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
206 {AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
207 {AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
208 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
209 {AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
210 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
211 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
212 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
213 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
214 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
215 {AMOVWP, C_REG, C_NONE, C_NONE, C_SOREG_16, C_NONE, 73, 4, 0, 0},
216 {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 73, 12, 0, 0},
217 {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG_64, C_NONE, 73, 24, 0, 0},
218
219 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
220 {AMOVWU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
221 {AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
222 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
223 {AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
224 {AMOVW, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
225 {AMOVWU, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
226 {AMOVV, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
227 {AMOVB, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
228 {AMOVBU, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
229 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
230 {AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
231 {AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
232 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
233 {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
234 {AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
235 {AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
236 {AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
237 {AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
238 {AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
239 {AMOVWP, C_SOREG_16, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0},
240 {AMOVWP, C_LOREG_32, C_NONE, C_NONE, C_REG, C_NONE, 74, 12, 0, 0},
241 {AMOVWP, C_LOREG_64, C_NONE, C_NONE, C_REG, C_NONE, 74, 24, 0, 0},
242
243 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
244 {AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
245 {AMOVW, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
246 {AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
247
248 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
249 {AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
250 {AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
251 {AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
252
253 {AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
254 {AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
255 {AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
256 {AMOVV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
257 {AMOVV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 67, 4, 0, NOTUSETMP},
258 {AMOVV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 68, 8, 0, NOTUSETMP},
259 {AMOVV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 69, 12, 0, NOTUSETMP},
260 {AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
261
262 {AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
263 {AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
264 {AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
265 {AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
266
267 {AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
268 {AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
269 {AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
270 {AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
271
272 {AADDV16, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
273 {AADDV16, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
274
275 {AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
276 {AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
277 {AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
278 {AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
279
280 {AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
281 {AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
282 {AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
283 {AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
284 {AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
285 {AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
286
287 {AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
288 {AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
289 {AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
290 {AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
291 {AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
292 {AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
293
294 {AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
295 {AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
296 {AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
297 {AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
298 {AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
299 {AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
300 {AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
301 {AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
302 {AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
303 {AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
304 {AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
305 {AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
306 {AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
307 {AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
308 {AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
309 {AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
310
311 {ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
312 {ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
313
314 {ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
315 {ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
316
317 {ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0},
318 {ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
319 {ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
320
321 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
322 {ASYSCALL, C_U15CON, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
323
324 {ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
325 {ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
326 {ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
327 {ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
328 {ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
329
330 {AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
331 {AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
332
333 {AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0},
334 {AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0},
335
336 {AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
337 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
338 {AMOVF, C_SOREG_12, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
339 {AMOVD, C_SOREG_12, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
340
341 {AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
342 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
343 {AMOVF, C_LOREG_32, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
344 {AMOVD, C_LOREG_32, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
345 {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
346 {AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
347
348 {AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
349 {AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
350 {AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 29, 4, REGZERO, 0},
351 {AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG_12, C_NONE, 29, 4, REGZERO, 0},
352
353 {AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
354 {AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
355 {AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 29, 12, REGZERO, 0},
356 {AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG_32, C_NONE, 29, 12, REGZERO, 0},
357 {AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
358 {AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
359
360 {AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
361 {AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
362 {AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
363 {AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
364 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
365 {AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
366 {AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
367 {AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0},
368 {AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
369 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
370
371 {AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0},
372
373 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
374 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
375 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
376 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
377 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
378
379 {AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
380 {AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
381 {AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
382 {AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
383 {AMOVWU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
384
385 {AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0},
386 {AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0},
387
388 {AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0},
389
390 {ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
391 {ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
392
393 {ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0},
394 {AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0},
395 {ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
396
397
398 {AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
399 {AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
400 {AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
401 {AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
402 {AMOVD, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
403 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
404 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
405
406
407 {AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
408 {AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
409 {AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
410 {AMOVWU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
411 {AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
412 {AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
413 {AMOVD, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
414 {AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0},
415 {AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0},
416
417 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
418 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
419 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
420 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
421
422 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 43, 4, 0, 0},
423 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 44, 4, 0, 0},
424
425 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
426 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
427 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0},
428
429 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
430
431 {AVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
432 {AXVMOVQ, C_SOREG_12, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
433
434 {APRELD, C_SOREG_12, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
435 {APRELDX, C_SOREG_16, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
436
437 {AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
438
439 {obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
440 {obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
441 {obj.APCDATA, C_DCON, C_NONE, C_NONE, C_DCON, C_NONE, 0, 0, 0, 0},
442 {obj.AFUNCDATA, C_U12CON, C_NONE, C_NONE, C_ADDR, C_NONE, 0, 0, 0, 0},
443 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
444 {obj.ANOP, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
445 {obj.ANOP, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
446 {obj.ANOP, C_REG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
447 {obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
448 }
449
450 var atomicInst = map[obj.As]uint32{
451 AAMSWAPB: 0x070B8 << 15,
452 AAMSWAPH: 0x070B9 << 15,
453 AAMSWAPW: 0x070C0 << 15,
454 AAMSWAPV: 0x070C1 << 15,
455 AAMCASB: 0x070B0 << 15,
456 AAMCASH: 0x070B1 << 15,
457 AAMCASW: 0x070B2 << 15,
458 AAMCASV: 0x070B3 << 15,
459 AAMADDW: 0x070C2 << 15,
460 AAMADDV: 0x070C3 << 15,
461 AAMANDW: 0x070C4 << 15,
462 AAMANDV: 0x070C5 << 15,
463 AAMORW: 0x070C6 << 15,
464 AAMORV: 0x070C7 << 15,
465 AAMXORW: 0x070C8 << 15,
466 AAMXORV: 0x070C9 << 15,
467 AAMMAXW: 0x070CA << 15,
468 AAMMAXV: 0x070CB << 15,
469 AAMMINW: 0x070CC << 15,
470 AAMMINV: 0x070CD << 15,
471 AAMMAXWU: 0x070CE << 15,
472 AAMMAXVU: 0x070CF << 15,
473 AAMMINWU: 0x070D0 << 15,
474 AAMMINVU: 0x070D1 << 15,
475 AAMSWAPDBB: 0x070BC << 15,
476 AAMSWAPDBH: 0x070BD << 15,
477 AAMSWAPDBW: 0x070D2 << 15,
478 AAMSWAPDBV: 0x070D3 << 15,
479 AAMCASDBB: 0x070B4 << 15,
480 AAMCASDBH: 0x070B5 << 15,
481 AAMCASDBW: 0x070B6 << 15,
482 AAMCASDBV: 0x070B7 << 15,
483 AAMADDDBW: 0x070D4 << 15,
484 AAMADDDBV: 0x070D5 << 15,
485 AAMANDDBW: 0x070D6 << 15,
486 AAMANDDBV: 0x070D7 << 15,
487 AAMORDBW: 0x070D8 << 15,
488 AAMORDBV: 0x070D9 << 15,
489 AAMXORDBW: 0x070DA << 15,
490 AAMXORDBV: 0x070DB << 15,
491 AAMMAXDBW: 0x070DC << 15,
492 AAMMAXDBV: 0x070DD << 15,
493 AAMMINDBW: 0x070DE << 15,
494 AAMMINDBV: 0x070DF << 15,
495 AAMMAXDBWU: 0x070E0 << 15,
496 AAMMAXDBVU: 0x070E1 << 15,
497 AAMMINDBWU: 0x070E2 << 15,
498 AAMMINDBVU: 0x070E3 << 15,
499 }
500
501 func IsAtomicInst(as obj.As) bool {
502 _, ok := atomicInst[as]
503
504 return ok
505 }
506
507
508
509 func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int {
510 if !((alignedValue&(alignedValue-1) == 0) && 8 <= alignedValue && alignedValue <= 2048) {
511 ctxt.Diag("alignment value of an instruction must be a power of two and in the range [8, 2048], got %d\n", alignedValue)
512 }
513 return int(-pc & (alignedValue - 1))
514 }
515
516 var oprange [ALAST & obj.AMask][]Optab
517
518 var xcmp [C_NCLASS][C_NCLASS]bool
519
520 func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
521 if ctxt.Retpoline {
522 ctxt.Diag("-spectre=ret not supported on loong64")
523 ctxt.Retpoline = false
524 }
525
526 p := cursym.Func().Text
527 if p == nil || p.Link == nil {
528 return
529 }
530
531 c := ctxt0{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset + ctxt.Arch.FixedFrameSize)}
532
533 if oprange[AOR&obj.AMask] == nil {
534 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
535 }
536
537 pc := int64(0)
538 p.Pc = pc
539
540 var m int
541 var o *Optab
542 for p = p.Link; p != nil; p = p.Link {
543 p.Pc = pc
544 o = c.oplook(p)
545 m = int(o.size)
546 if m == 0 {
547 switch p.As {
548 case obj.APCALIGN:
549 alignedValue := p.From.Offset
550 m = pcAlignPadLength(ctxt, pc, alignedValue)
551
552 if int32(alignedValue) > cursym.Func().Align {
553 cursym.Func().Align = int32(alignedValue)
554 }
555 break
556 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
557 continue
558 default:
559 c.ctxt.Diag("zero-width instruction\n%v", p)
560 }
561 }
562
563 pc += int64(m)
564 }
565
566 c.cursym.Size = pc
567
568
569
570 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
571 if q := p.To.Target(); q != nil && q.Pc < p.Pc {
572 q.Mark |= branchLoopHead
573 }
574 }
575
576
577 for {
578 rescan := false
579 pc = 0
580 prev := c.cursym.Func().Text
581 for p = prev.Link; p != nil; prev, p = p, p.Link {
582 p.Pc = pc
583 o = c.oplook(p)
584
585
586
587
588
589
590
591 if p.Mark&branchLoopHead != 0 && pc&(loopAlign-1) != 0 &&
592 !(prev.As == obj.APCALIGN && prev.From.Offset >= loopAlign) {
593 q := c.newprog()
594 prev.Link = q
595 q.Link = p
596 q.Pc = pc
597 q.As = obj.APCALIGN
598 q.From.Type = obj.TYPE_CONST
599 q.From.Offset = loopAlign
600
601
602
603
604
605
606
607 pc += int64(pcAlignPadLength(ctxt, pc, loopAlign))
608 p.Pc = pc
609 rescan = true
610 }
611
612
613
614
615
616 if o.type_ == 6 && p.To.Target() != nil {
617 otxt := p.To.Target().Pc - pc
618
619
620
621
622
623 bound := int64(1 << (18 - 1))
624
625 switch p.As {
626 case ABFPT, ABFPF:
627 bound = int64(1 << (23 - 1))
628 }
629
630 if otxt < -bound || otxt >= bound {
631 q := c.newprog()
632 q.Link = p.Link
633 p.Link = q
634 q.As = AJMP
635 q.Pos = p.Pos
636 q.To.Type = obj.TYPE_BRANCH
637 q.To.SetTarget(p.To.Target())
638 p.To.SetTarget(q)
639 q = c.newprog()
640 q.Link = p.Link
641 p.Link = q
642 q.As = AJMP
643 q.Pos = p.Pos
644 q.To.Type = obj.TYPE_BRANCH
645 q.To.SetTarget(q.Link.Link)
646 rescan = true
647 }
648 }
649
650 m = int(o.size)
651 if m == 0 {
652 switch p.As {
653 case obj.APCALIGN:
654 alignedValue := p.From.Offset
655 m = pcAlignPadLength(ctxt, pc, alignedValue)
656 break
657 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
658 continue
659 default:
660 c.ctxt.Diag("zero-width instruction\n%v", p)
661 }
662 }
663
664 pc += int64(m)
665 }
666
667 c.cursym.Size = pc
668
669 if !rescan {
670 break
671 }
672 }
673
674 pc += -pc & (FuncAlign - 1)
675 c.cursym.Size = pc
676
677
678
679 c.cursym.Grow(c.cursym.Size)
680
681 bp := c.cursym.P
682 var i int32
683 var out [6]uint32
684 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
685 c.pc = p.Pc
686 o = c.oplook(p)
687 if int(o.size) > 4*len(out) {
688 log.Fatalf("out array in span0 is too small, need at least %d for %v", o.size/4, p)
689 }
690 if p.As == obj.APCALIGN {
691 alignedValue := p.From.Offset
692 v := pcAlignPadLength(c.ctxt, p.Pc, alignedValue)
693 for i = 0; i < int32(v/4); i++ {
694
695 c.ctxt.Arch.ByteOrder.PutUint32(bp, OP_12IRR(c.opirr(AAND), 0, 0, 0))
696 bp = bp[4:]
697 }
698 continue
699 }
700 c.asmout(p, o, out[:])
701 for i = 0; i < int32(o.size/4); i++ {
702 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
703 bp = bp[4:]
704 }
705 }
706
707
708
709
710
711 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, c.isRestartable)
712
713
714 for _, jt := range cursym.Func().JumpTables {
715 for i, p := range jt.Targets {
716
717
718 jt.Sym.WriteAddr(ctxt, int64(i)*8, 8, cursym, p.Pc)
719 }
720 }
721 }
722
723
724 func (c *ctxt0) isUnsafePoint(p *obj.Prog) bool {
725
726
727 return p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP
728 }
729
730
731
732 func (c *ctxt0) isRestartable(p *obj.Prog) bool {
733 if c.isUnsafePoint(p) {
734 return false
735 }
736
737
738
739
740
741
742
743 o := c.oplook(p)
744 return o.size > 4 && o.flag&NOTUSETMP == 0
745 }
746
747 func isint32(v int64) bool {
748 return int64(int32(v)) == v
749 }
750
751 func (c *ctxt0) aclass(a *obj.Addr) int {
752 switch a.Type {
753 case obj.TYPE_NONE:
754 return C_NONE
755
756 case obj.TYPE_REG:
757 return c.rclass(a.Reg)
758
759 case obj.TYPE_MEM:
760 switch a.Name {
761 case obj.NAME_EXTERN,
762 obj.NAME_STATIC:
763 if a.Sym == nil {
764 break
765 }
766 c.instoffset = a.Offset
767 if a.Sym.Type == objabi.STLSBSS {
768 if c.ctxt.Flag_shared {
769 return C_TLS_IE
770 } else {
771 return C_TLS_LE
772 }
773 }
774 return C_ADDR
775
776 case obj.NAME_AUTO:
777 if a.Reg == REGSP {
778
779
780 a.Reg = obj.REG_NONE
781 }
782 c.instoffset = int64(c.autosize) + a.Offset
783 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
784 return C_SAUTO
785 }
786 return C_LAUTO
787
788 case obj.NAME_PARAM:
789 if a.Reg == REGSP {
790
791
792 a.Reg = obj.REG_NONE
793 }
794 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
795 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
796 return C_SAUTO
797 }
798 return C_LAUTO
799
800 case obj.NAME_NONE:
801 if a.Index != 0 {
802 if a.Offset != 0 {
803 return C_GOK
804 }
805
806 return C_ROFF
807 }
808
809 c.instoffset = a.Offset
810 if c.instoffset == 0 {
811 return C_ZOREG
812 }
813 if c.instoffset >= -BIG_8 && c.instoffset < BIG_8 {
814 return C_SOREG_8
815 } else if c.instoffset >= -BIG_9 && c.instoffset < BIG_9 {
816 return C_SOREG_9
817 } else if c.instoffset >= -BIG_10 && c.instoffset < BIG_10 {
818 return C_SOREG_10
819 } else if c.instoffset >= -BIG_11 && c.instoffset < BIG_11 {
820 return C_SOREG_11
821 } else if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
822 return C_SOREG_12
823 } else if c.instoffset >= -BIG_16 && c.instoffset < BIG_16 {
824 return C_SOREG_16
825 } else if c.instoffset >= -BIG_32 && c.instoffset < BIG_32 {
826 return C_LOREG_32
827 } else {
828 return C_LOREG_64
829 }
830
831 case obj.NAME_GOTREF:
832 return C_GOTADDR
833 }
834
835 return C_GOK
836
837 case obj.TYPE_TEXTSIZE:
838 return C_TEXTSIZE
839
840 case obj.TYPE_CONST,
841 obj.TYPE_ADDR:
842 switch a.Name {
843 case obj.NAME_NONE:
844 c.instoffset = a.Offset
845 if a.Reg != 0 {
846 if -BIG_12 <= c.instoffset && c.instoffset <= BIG_12 {
847 return C_SACON
848 }
849 if isint32(c.instoffset) {
850 return C_LACON
851 }
852 return C_DACON
853 }
854
855 case obj.NAME_EXTERN,
856 obj.NAME_STATIC:
857 s := a.Sym
858 if s == nil {
859 return C_GOK
860 }
861
862 c.instoffset = a.Offset
863 if s.Type == objabi.STLSBSS {
864 c.ctxt.Diag("taking address of TLS variable is not supported")
865 }
866 return C_EXTADDR
867
868 case obj.NAME_AUTO:
869 if a.Reg == REGSP {
870
871
872 a.Reg = obj.REG_NONE
873 }
874 c.instoffset = int64(c.autosize) + a.Offset
875 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
876 return C_SACON
877 }
878 return C_LACON
879
880 case obj.NAME_PARAM:
881 if a.Reg == REGSP {
882
883
884 a.Reg = obj.REG_NONE
885 }
886 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
887 if c.instoffset >= -BIG_12 && c.instoffset < BIG_12 {
888 return C_SACON
889 }
890 return C_LACON
891
892 default:
893 return C_GOK
894 }
895
896 if c.instoffset != int64(int32(c.instoffset)) {
897 return dconClass(c.instoffset)
898 }
899
900 if c.instoffset >= 0 {
901 sbits := bits.Len64(uint64(c.instoffset))
902 switch {
903 case sbits <= 8:
904 return C_ZCON + sbits
905 case sbits <= 12:
906 if c.instoffset <= 0x7ff {
907 return C_US12CON
908 }
909 return C_U12CON
910 case sbits <= 13:
911 if c.instoffset&0xfff == 0 {
912 return C_U13CON20_0
913 }
914 return C_U13CON
915 case sbits <= 15:
916 if c.instoffset&0xfff == 0 {
917 return C_U15CON20_0
918 }
919 return C_U15CON
920 }
921 } else {
922 sbits := bits.Len64(uint64(^c.instoffset))
923 switch {
924 case sbits < 5:
925 return C_S5CON
926 case sbits < 12:
927 return C_S12CON
928 case sbits < 13:
929 if c.instoffset&0xfff == 0 {
930 return C_S13CON20_0
931 }
932 return C_S13CON
933 }
934 }
935
936 if c.instoffset&0xfff == 0 {
937 return C_32CON20_0
938 }
939 return C_32CON
940
941 case obj.TYPE_BRANCH:
942 return C_BRAN
943 }
944
945 return C_GOK
946 }
947
948
949
950
951
952
953
954 const (
955 ALL1 = iota
956 ALL0
957 ST1
958 ST0
959 )
960
961
962
963 func mask(suf int8, len int8) (uint64, uint64) {
964 if len == 12 {
965 if suf == 0 {
966 return 0xfff, 0x800
967 } else {
968 return 0xfff0000000000000, 0x8000000000000000
969 }
970 } else {
971 if suf == 12 {
972 return 0xfffff000, 0x80000000
973 } else {
974 return 0xfffff00000000, 0x8000000000000
975 }
976 }
977 }
978
979
980
981
982
983 func bitField(val int64, suf int8, len int8) int8 {
984 mask1, mask2 := mask(suf, len)
985 if uint64(val)&mask1 == mask1 {
986 return ALL1
987 } else if uint64(val)&mask1 == 0x0 {
988 return ALL0
989 } else if uint64(val)&mask2 == mask2 {
990 return ST1
991 } else {
992 return ST0
993 }
994 }
995
996
997
998
999
1000
1001
1002
1003
1004 func dconClass(offset int64) int {
1005 tzb := bits.TrailingZeros64(uint64(offset))
1006 hi12 := bitField(offset, 52, 12)
1007 hi20 := bitField(offset, 32, 20)
1008 lo20 := bitField(offset, 12, 20)
1009 lo12 := bitField(offset, 0, 12)
1010 if tzb >= 52 {
1011 return C_DCON12_0
1012 }
1013 if tzb >= 32 {
1014 if ((hi20 == ALL1 || hi20 == ST1) && hi12 == ALL1) || ((hi20 == ALL0 || hi20 == ST0) && hi12 == ALL0) {
1015 return C_DCON20S_0
1016 }
1017 return C_DCON32_0
1018 }
1019 if tzb >= 12 {
1020 if lo20 == ST1 || lo20 == ALL1 {
1021 if hi20 == ALL1 {
1022 return C_DCON12_20S
1023 }
1024 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1025 return C_DCON20S_20
1026 }
1027 return C_DCON32_20
1028 }
1029 if hi20 == ALL0 {
1030 return C_DCON12_20S
1031 }
1032 if (hi20 == ST0 && hi12 == ALL0) || ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) {
1033 return C_DCON20S_20
1034 }
1035 return C_DCON32_20
1036 }
1037 if lo12 == ST1 || lo12 == ALL1 {
1038 if lo20 == ALL1 {
1039 if hi20 == ALL1 {
1040 return C_DCON12_12S
1041 }
1042 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1043 return C_DCON20S_12S
1044 }
1045 return C_DCON32_12S
1046 }
1047 if lo20 == ST1 {
1048 if hi20 == ALL1 {
1049
1050 return C_DCON12_32S
1051 }
1052 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1053 return C_DCON20S_32
1054 }
1055 return C_DCON
1056 }
1057 if lo20 == ALL0 {
1058 if hi20 == ALL0 {
1059 return C_DCON12_12U
1060 }
1061 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1062 return C_DCON20S_12U
1063 }
1064 return C_DCON32_12U
1065 }
1066 if hi20 == ALL0 {
1067 return C_DCON12_32S
1068 }
1069 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1070 return C_DCON20S_32
1071 }
1072 return C_DCON
1073 }
1074 if lo20 == ALL0 {
1075 if hi20 == ALL0 {
1076 return C_DCON12_12U
1077 }
1078 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1079 return C_DCON20S_12U
1080 }
1081 return C_DCON32_12U
1082 }
1083 if lo20 == ST1 || lo20 == ALL1 {
1084 if hi20 == ALL1 {
1085 return C_DCON12_32S
1086 }
1087 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1088 return C_DCON20S_32
1089 }
1090 return C_DCON
1091 }
1092 if hi20 == ALL0 {
1093 return C_DCON12_32S
1094 }
1095 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1096 return C_DCON20S_32
1097 }
1098 return C_DCON
1099 }
1100
1101
1102
1103 func (c *ctxt0) rclass(r int16) int {
1104 switch {
1105 case REG_R0 <= r && r <= REG_R31:
1106 return C_REG
1107 case REG_F0 <= r && r <= REG_F31:
1108 return C_FREG
1109 case REG_FCC0 <= r && r <= REG_FCC7:
1110 return C_FCCREG
1111 case REG_FCSR0 <= r && r <= REG_FCSR3:
1112 return C_FCSRREG
1113 case REG_V0 <= r && r <= REG_V31:
1114 return C_VREG
1115 case REG_X0 <= r && r <= REG_X31:
1116 return C_XREG
1117 case r >= REG_ARNG && r < REG_ELEM:
1118 return C_ARNG
1119 case r >= REG_ELEM && r < REG_ELEM_END:
1120 return C_ELEM
1121 }
1122
1123 return C_GOK
1124 }
1125
1126 func oclass(a *obj.Addr) int {
1127 return int(a.Class) - 1
1128 }
1129
1130 func prasm(p *obj.Prog) {
1131 fmt.Printf("%v\n", p)
1132 }
1133
1134 func (c *ctxt0) oplook(p *obj.Prog) *Optab {
1135 if oprange[AOR&obj.AMask] == nil {
1136 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
1137 }
1138
1139 restArgsIndex := 0
1140 restArgsLen := len(p.RestArgs)
1141 if restArgsLen > 2 {
1142 c.ctxt.Diag("too many RestArgs: got %v, maximum is 2\n", restArgsLen)
1143 return nil
1144 }
1145
1146 restArgsv := [2]int{C_NONE + 1, C_NONE + 1}
1147 for i, ap := range p.RestArgs {
1148 restArgsv[i] = int(ap.Addr.Class)
1149 if restArgsv[i] == 0 {
1150 restArgsv[i] = c.aclass(&ap.Addr) + 1
1151 ap.Addr.Class = int8(restArgsv[i])
1152 }
1153 }
1154
1155 a1 := int(p.Optab)
1156 if a1 != 0 {
1157 return &optab[a1-1]
1158 }
1159
1160
1161 a1 = int(p.From.Class)
1162 if a1 == 0 {
1163 a1 = c.aclass(&p.From) + 1
1164 p.From.Class = int8(a1)
1165 }
1166 a1--
1167
1168
1169 a4 := int(p.To.Class)
1170 if a4 == 0 {
1171 a4 = c.aclass(&p.To) + 1
1172 p.To.Class = int8(a4)
1173 }
1174 a4--
1175
1176
1177 a2 := C_NONE
1178 if p.Reg != 0 {
1179 a2 = c.rclass(p.Reg)
1180 } else if restArgsLen > 0 {
1181 a2 = restArgsv[restArgsIndex] - 1
1182 restArgsIndex++
1183 }
1184
1185
1186 a5 := C_NONE
1187 if p.RegTo2 != 0 {
1188 a5 = C_REG
1189 }
1190
1191
1192 a3 := C_NONE
1193 if restArgsLen > 0 && restArgsIndex < restArgsLen {
1194 a3 = restArgsv[restArgsIndex] - 1
1195 restArgsIndex++
1196 }
1197
1198 ops := oprange[p.As&obj.AMask]
1199 c1 := &xcmp[a1]
1200 c2 := &xcmp[a2]
1201 c3 := &xcmp[a3]
1202 c4 := &xcmp[a4]
1203 c5 := &xcmp[a5]
1204 for i := range ops {
1205 op := &ops[i]
1206 if c1[op.from1] && c2[op.reg] && c3[op.from3] && c4[op.to1] && c5[op.to2] {
1207 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1208 return op
1209 }
1210 }
1211
1212 c.ctxt.Diag("illegal combination %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5))
1213 prasm(p)
1214
1215 return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}
1216 }
1217
1218 func cmp(a int, b int) bool {
1219 if a == b {
1220 return true
1221 }
1222 switch a {
1223 case C_DCON:
1224 return cmp(C_32CON, b) || cmp(C_DCON12_20S, b) || cmp(C_DCON32_12S, b) || b == C_DCON12_0
1225 case C_32CON:
1226 return cmp(C_32CON20_0, b) || cmp(C_U15CON, b) || cmp(C_13CON, b) || cmp(C_12CON, b)
1227 case C_32CON20_0:
1228 return b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_S13CON20_0 || b == C_ZCON
1229 case C_U15CON:
1230 return cmp(C_U12CON, b) || b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_U13CON
1231 case C_13CON:
1232 return cmp(C_U13CON, b) || cmp(C_S13CON, b)
1233 case C_U13CON:
1234 return cmp(C_12CON, b) || b == C_U13CON20_0
1235 case C_S13CON:
1236 return cmp(C_12CON, b) || b == C_S13CON20_0
1237 case C_12CON:
1238 return cmp(C_U12CON, b) || cmp(C_S12CON, b)
1239 case C_UU12CON:
1240 return cmp(C_U12CON, b)
1241 case C_U12CON:
1242 return cmp(C_U8CON, b) || b == C_US12CON
1243 case C_U8CON:
1244 return cmp(C_U7CON, b)
1245 case C_U7CON:
1246 return cmp(C_U6CON, b)
1247 case C_U6CON:
1248 return cmp(C_U5CON, b)
1249 case C_U5CON:
1250 return cmp(C_U4CON, b)
1251 case C_U4CON:
1252 return cmp(C_U3CON, b)
1253 case C_U3CON:
1254 return cmp(C_U2CON, b)
1255 case C_U2CON:
1256 return cmp(C_U1CON, b)
1257 case C_U1CON:
1258 return cmp(C_ZCON, b)
1259 case C_US12CON:
1260 return cmp(C_S12CON, b)
1261 case C_S12CON:
1262 return cmp(C_S5CON, b) || cmp(C_U8CON, b) || b == C_US12CON
1263 case C_S5CON:
1264 return cmp(C_ZCON, b) || cmp(C_U4CON, b)
1265
1266 case C_DCON12_20S:
1267 if b == C_DCON20S_20 || b == C_DCON12_12S ||
1268 b == C_DCON20S_12S || b == C_DCON12_12U ||
1269 b == C_DCON20S_12U || b == C_DCON20S_0 {
1270 return true
1271 }
1272
1273 case C_DCON32_12S:
1274 if b == C_DCON32_20 || b == C_DCON12_32S ||
1275 b == C_DCON20S_32 || b == C_DCON32_12U ||
1276 b == C_DCON32_0 {
1277 return true
1278 }
1279
1280 case C_LACON:
1281 return b == C_SACON
1282
1283 case C_LAUTO:
1284 return b == C_SAUTO
1285
1286 case C_REG:
1287 return b == C_ZCON
1288
1289 case C_LOREG_64:
1290 if b == C_ZOREG || b == C_SOREG_8 ||
1291 b == C_SOREG_9 || b == C_SOREG_10 ||
1292 b == C_SOREG_11 || b == C_SOREG_12 ||
1293 b == C_SOREG_16 || b == C_LOREG_32 {
1294 return true
1295 }
1296
1297 case C_LOREG_32:
1298 return cmp(C_SOREG_16, b)
1299
1300 case C_SOREG_16:
1301 return cmp(C_SOREG_12, b)
1302
1303 case C_SOREG_12:
1304 return cmp(C_SOREG_11, b)
1305
1306 case C_SOREG_11:
1307 return cmp(C_SOREG_10, b)
1308
1309 case C_SOREG_10:
1310 return cmp(C_SOREG_9, b)
1311
1312 case C_SOREG_9:
1313 return cmp(C_SOREG_8, b)
1314
1315 case C_SOREG_8:
1316 return b == C_ZOREG
1317 }
1318
1319 return false
1320 }
1321
1322 func ocmp(p1, p2 Optab) int {
1323 if p1.as != p2.as {
1324 return int(p1.as) - int(p2.as)
1325 }
1326 if p1.from1 != p2.from1 {
1327 return int(p1.from1) - int(p2.from1)
1328 }
1329 if p1.reg != p2.reg {
1330 return int(p1.reg) - int(p2.reg)
1331 }
1332 if p1.to1 != p2.to1 {
1333 return int(p1.to1) - int(p2.to1)
1334 }
1335 return 0
1336 }
1337
1338 func opset(a, b0 obj.As) {
1339 oprange[a&obj.AMask] = oprange[b0]
1340 }
1341
1342 func buildop(ctxt *obj.Link) {
1343 if ctxt.DiagFunc == nil {
1344 ctxt.DiagFunc = func(format string, args ...any) {
1345 log.Printf(format, args...)
1346 }
1347 }
1348
1349 if oprange[AOR&obj.AMask] != nil {
1350
1351
1352
1353 return
1354 }
1355
1356 for i := range C_NCLASS {
1357 for j := range C_NCLASS {
1358 if cmp(j, i) {
1359 xcmp[i][j] = true
1360 }
1361 }
1362 }
1363
1364 slices.SortFunc(optab, ocmp)
1365 for i := 0; i < len(optab); i++ {
1366 as, start := optab[i].as, i
1367 for ; i < len(optab)-1; i++ {
1368 if optab[i+1].as != as {
1369 break
1370 }
1371 }
1372 r0 := as & obj.AMask
1373 oprange[r0] = optab[start : i+1]
1374 switch as {
1375 default:
1376 ctxt.Diag("unknown op in build: %v", as)
1377 ctxt.DiagFlush()
1378 log.Fatalf("bad code")
1379
1380 case AABSF:
1381 opset(AMOVFD, r0)
1382 opset(AMOVDF, r0)
1383 opset(AMOVWF, r0)
1384 opset(AMOVFW, r0)
1385 opset(AMOVWD, r0)
1386 opset(AMOVDW, r0)
1387 opset(ANEGF, r0)
1388 opset(ANEGD, r0)
1389 opset(AABSD, r0)
1390 opset(ATRUNCDW, r0)
1391 opset(ATRUNCFW, r0)
1392 opset(ASQRTF, r0)
1393 opset(ASQRTD, r0)
1394 opset(AFCLASSF, r0)
1395 opset(AFCLASSD, r0)
1396 opset(AFLOGBF, r0)
1397 opset(AFLOGBD, r0)
1398
1399 case AMOVVF:
1400 opset(AMOVVD, r0)
1401 opset(AMOVFV, r0)
1402 opset(AMOVDV, r0)
1403 opset(ATRUNCDV, r0)
1404 opset(ATRUNCFV, r0)
1405 opset(AFFINTFW, r0)
1406 opset(AFFINTFV, r0)
1407 opset(AFFINTDW, r0)
1408 opset(AFFINTDV, r0)
1409 opset(AFTINTWF, r0)
1410 opset(AFTINTWD, r0)
1411 opset(AFTINTVF, r0)
1412 opset(AFTINTVD, r0)
1413 opset(AFTINTRPWF, r0)
1414 opset(AFTINTRPWD, r0)
1415 opset(AFTINTRPVF, r0)
1416 opset(AFTINTRPVD, r0)
1417 opset(AFTINTRMWF, r0)
1418 opset(AFTINTRMWD, r0)
1419 opset(AFTINTRMVF, r0)
1420 opset(AFTINTRMVD, r0)
1421 opset(AFTINTRZWF, r0)
1422 opset(AFTINTRZWD, r0)
1423 opset(AFTINTRZVF, r0)
1424 opset(AFTINTRZVD, r0)
1425 opset(AFTINTRNEWF, r0)
1426 opset(AFTINTRNEWD, r0)
1427 opset(AFTINTRNEVF, r0)
1428 opset(AFTINTRNEVD, r0)
1429
1430 case AADD:
1431 opset(AADDW, r0)
1432 opset(ASGT, r0)
1433 opset(ASGTU, r0)
1434
1435 case AADDV:
1436 opset(AADDVU, r0)
1437
1438 case AADDF:
1439 opset(ADIVF, r0)
1440 opset(ADIVD, r0)
1441 opset(AMULF, r0)
1442 opset(AMULD, r0)
1443 opset(ASUBF, r0)
1444 opset(ASUBD, r0)
1445 opset(AADDD, r0)
1446 opset(AFMINF, r0)
1447 opset(AFMIND, r0)
1448 opset(AFMAXF, r0)
1449 opset(AFMAXD, r0)
1450 opset(AFCOPYSGF, r0)
1451 opset(AFCOPYSGD, r0)
1452 opset(AFSCALEBF, r0)
1453 opset(AFSCALEBD, r0)
1454 opset(AFMAXAF, r0)
1455 opset(AFMAXAD, r0)
1456 opset(AFMINAF, r0)
1457 opset(AFMINAD, r0)
1458
1459 case AFMADDF:
1460 opset(AFMADDD, r0)
1461 opset(AFMSUBF, r0)
1462 opset(AFMSUBD, r0)
1463 opset(AFNMADDF, r0)
1464 opset(AFNMADDD, r0)
1465 opset(AFNMSUBF, r0)
1466 opset(AFNMSUBD, r0)
1467
1468 case AAND:
1469 opset(AOR, r0)
1470 opset(AXOR, r0)
1471 opset(AORN, r0)
1472 opset(AANDN, r0)
1473
1474 case ABEQ:
1475 opset(ABNE, r0)
1476 opset(ABLT, r0)
1477 opset(ABGE, r0)
1478 opset(ABGEU, r0)
1479 opset(ABLTU, r0)
1480
1481 case ABLEZ:
1482 opset(ABGEZ, r0)
1483 opset(ABLTZ, r0)
1484 opset(ABGTZ, r0)
1485
1486 case AMOVB:
1487 opset(AMOVH, r0)
1488
1489 case AMOVBU:
1490 opset(AMOVHU, r0)
1491
1492 case AMOVWP:
1493 opset(AMOVVP, r0)
1494 opset(ASC, r0)
1495 opset(ASCV, r0)
1496 opset(ALL, r0)
1497 opset(ALLV, r0)
1498
1499 case ASLL:
1500 opset(ASRL, r0)
1501 opset(ASRA, r0)
1502 opset(AROTR, r0)
1503
1504 case ASLLV:
1505 opset(ASRAV, r0)
1506 opset(ASRLV, r0)
1507 opset(AROTRV, r0)
1508
1509 case ABSTRPICKW:
1510 opset(ABSTRPICKV, r0)
1511 opset(ABSTRINSW, r0)
1512 opset(ABSTRINSV, r0)
1513
1514 case ASUB:
1515 opset(ASUBW, r0)
1516 opset(ANOR, r0)
1517 opset(ASUBV, r0)
1518 opset(ASUBVU, r0)
1519 opset(AMUL, r0)
1520 opset(AMULW, r0)
1521 opset(AMULH, r0)
1522 opset(AMULHU, r0)
1523 opset(AREM, r0)
1524 opset(AREMW, r0)
1525 opset(AREMU, r0)
1526 opset(AREMWU, r0)
1527 opset(ADIV, r0)
1528 opset(ADIVW, r0)
1529 opset(ADIVU, r0)
1530 opset(ADIVWU, r0)
1531 opset(AMULV, r0)
1532 opset(AMULVU, r0)
1533 opset(AMULHV, r0)
1534 opset(AMULHVU, r0)
1535 opset(AREMV, r0)
1536 opset(AREMVU, r0)
1537 opset(ADIVV, r0)
1538 opset(ADIVVU, r0)
1539 opset(AMULWVW, r0)
1540 opset(AMULWVWU, r0)
1541
1542 case ASYSCALL:
1543 opset(ADBAR, r0)
1544 opset(ABREAK, r0)
1545
1546 case ACMPEQF:
1547 opset(ACMPGTF, r0)
1548 opset(ACMPGTD, r0)
1549 opset(ACMPGEF, r0)
1550 opset(ACMPGED, r0)
1551 opset(ACMPEQD, r0)
1552
1553 case ABFPT:
1554 opset(ABFPF, r0)
1555
1556 case AALSLV:
1557 opset(AALSLW, r0)
1558 opset(AALSLWU, r0)
1559
1560 case ANEGW:
1561 opset(ANEGV, r0)
1562
1563 case AMOVW,
1564 AMOVD,
1565 AMOVF,
1566 AMOVV,
1567 ARFE,
1568 AJAL,
1569 AJMP,
1570 AMOVWU,
1571 AVMOVQ,
1572 AXVMOVQ,
1573 AVSHUFB,
1574 AXVSHUFB,
1575 AWORD,
1576 APRELD,
1577 APRELDX,
1578 AFSEL,
1579 AADDV16,
1580 obj.ANOP,
1581 obj.ATEXT,
1582 obj.AFUNCDATA,
1583 obj.APCALIGN,
1584 obj.APCDATA:
1585 break
1586
1587 case ARDTIMELW:
1588 opset(ARDTIMEHW, r0)
1589 opset(ARDTIMED, r0)
1590
1591 case ACLOW:
1592 opset(ACLZW, r0)
1593 opset(ACTOW, r0)
1594 opset(ACTZW, r0)
1595 opset(ACLOV, r0)
1596 opset(ACLZV, r0)
1597 opset(ACTOV, r0)
1598 opset(ACTZV, r0)
1599 opset(AREVB2H, r0)
1600 opset(AREVB4H, r0)
1601 opset(AREVB2W, r0)
1602 opset(AREVBV, r0)
1603 opset(AREVH2W, r0)
1604 opset(AREVHV, r0)
1605 opset(ABITREV4B, r0)
1606 opset(ABITREV8B, r0)
1607 opset(ABITREVW, r0)
1608 opset(ABITREVV, r0)
1609 opset(AEXTWB, r0)
1610 opset(AEXTWH, r0)
1611 opset(ACPUCFG, r0)
1612
1613 case ATEQ:
1614 opset(ATNE, r0)
1615
1616 case AMASKEQZ:
1617 opset(AMASKNEZ, r0)
1618 opset(ACRCWBW, r0)
1619 opset(ACRCWHW, r0)
1620 opset(ACRCWWW, r0)
1621 opset(ACRCWVW, r0)
1622 opset(ACRCCWBW, r0)
1623 opset(ACRCCWHW, r0)
1624 opset(ACRCCWWW, r0)
1625 opset(ACRCCWVW, r0)
1626
1627 case ANOOP:
1628 opset(obj.AUNDEF, r0)
1629
1630 case AAMSWAPW:
1631 for i := range atomicInst {
1632 if i == AAMSWAPW {
1633 continue
1634 }
1635 opset(i, r0)
1636 }
1637
1638 case AVSEQB:
1639 opset(AVSEQH, r0)
1640 opset(AVSEQW, r0)
1641 opset(AVSEQV, r0)
1642 opset(AVILVLB, r0)
1643 opset(AVILVLH, r0)
1644 opset(AVILVLW, r0)
1645 opset(AVILVLV, r0)
1646 opset(AVILVHB, r0)
1647 opset(AVILVHH, r0)
1648 opset(AVILVHW, r0)
1649 opset(AVILVHV, r0)
1650 opset(AVMULB, r0)
1651 opset(AVMULH, r0)
1652 opset(AVMULW, r0)
1653 opset(AVMULV, r0)
1654 opset(AVMUHB, r0)
1655 opset(AVMUHH, r0)
1656 opset(AVMUHW, r0)
1657 opset(AVMUHV, r0)
1658 opset(AVMUHBU, r0)
1659 opset(AVMUHHU, r0)
1660 opset(AVMUHWU, r0)
1661 opset(AVMUHVU, r0)
1662 opset(AVDIVB, r0)
1663 opset(AVDIVH, r0)
1664 opset(AVDIVW, r0)
1665 opset(AVDIVV, r0)
1666 opset(AVMODB, r0)
1667 opset(AVMODH, r0)
1668 opset(AVMODW, r0)
1669 opset(AVMODV, r0)
1670 opset(AVDIVBU, r0)
1671 opset(AVDIVHU, r0)
1672 opset(AVDIVWU, r0)
1673 opset(AVDIVVU, r0)
1674 opset(AVMODBU, r0)
1675 opset(AVMODHU, r0)
1676 opset(AVMODWU, r0)
1677 opset(AVMODVU, r0)
1678 opset(AVMULWEVHB, r0)
1679 opset(AVMULWEVWH, r0)
1680 opset(AVMULWEVVW, r0)
1681 opset(AVMULWEVQV, r0)
1682 opset(AVMULWODHB, r0)
1683 opset(AVMULWODWH, r0)
1684 opset(AVMULWODVW, r0)
1685 opset(AVMULWODQV, r0)
1686 opset(AVMULWEVHBU, r0)
1687 opset(AVMULWEVWHU, r0)
1688 opset(AVMULWEVVWU, r0)
1689 opset(AVMULWEVQVU, r0)
1690 opset(AVMULWODHBU, r0)
1691 opset(AVMULWODWHU, r0)
1692 opset(AVMULWODVWU, r0)
1693 opset(AVMULWODQVU, r0)
1694 opset(AVMULWEVHBUB, r0)
1695 opset(AVMULWEVWHUH, r0)
1696 opset(AVMULWEVVWUW, r0)
1697 opset(AVMULWEVQVUV, r0)
1698 opset(AVMULWODHBUB, r0)
1699 opset(AVMULWODWHUH, r0)
1700 opset(AVMULWODVWUW, r0)
1701 opset(AVMULWODQVUV, r0)
1702 opset(AVADDF, r0)
1703 opset(AVADDD, r0)
1704 opset(AVSUBF, r0)
1705 opset(AVSUBD, r0)
1706 opset(AVMULF, r0)
1707 opset(AVMULD, r0)
1708 opset(AVDIVF, r0)
1709 opset(AVDIVD, r0)
1710 opset(AVSHUFH, r0)
1711 opset(AVSHUFW, r0)
1712 opset(AVSHUFV, r0)
1713
1714 case AXVSEQB:
1715 opset(AXVSEQH, r0)
1716 opset(AXVSEQW, r0)
1717 opset(AXVSEQV, r0)
1718 opset(AXVILVLB, r0)
1719 opset(AXVILVLH, r0)
1720 opset(AXVILVLW, r0)
1721 opset(AXVILVLV, r0)
1722 opset(AXVILVHB, r0)
1723 opset(AXVILVHH, r0)
1724 opset(AXVILVHW, r0)
1725 opset(AXVILVHV, r0)
1726 opset(AXVMULB, r0)
1727 opset(AXVMULH, r0)
1728 opset(AXVMULW, r0)
1729 opset(AXVMULV, r0)
1730 opset(AXVMUHB, r0)
1731 opset(AXVMUHH, r0)
1732 opset(AXVMUHW, r0)
1733 opset(AXVMUHV, r0)
1734 opset(AXVMUHBU, r0)
1735 opset(AXVMUHHU, r0)
1736 opset(AXVMUHWU, r0)
1737 opset(AXVMUHVU, r0)
1738 opset(AXVDIVB, r0)
1739 opset(AXVDIVH, r0)
1740 opset(AXVDIVW, r0)
1741 opset(AXVDIVV, r0)
1742 opset(AXVMODB, r0)
1743 opset(AXVMODH, r0)
1744 opset(AXVMODW, r0)
1745 opset(AXVMODV, r0)
1746 opset(AXVDIVBU, r0)
1747 opset(AXVDIVHU, r0)
1748 opset(AXVDIVWU, r0)
1749 opset(AXVDIVVU, r0)
1750 opset(AXVMODBU, r0)
1751 opset(AXVMODHU, r0)
1752 opset(AXVMODWU, r0)
1753 opset(AXVMODVU, r0)
1754 opset(AXVMULWEVHB, r0)
1755 opset(AXVMULWEVWH, r0)
1756 opset(AXVMULWEVVW, r0)
1757 opset(AXVMULWEVQV, r0)
1758 opset(AXVMULWODHB, r0)
1759 opset(AXVMULWODWH, r0)
1760 opset(AXVMULWODVW, r0)
1761 opset(AXVMULWODQV, r0)
1762 opset(AXVMULWEVHBU, r0)
1763 opset(AXVMULWEVWHU, r0)
1764 opset(AXVMULWEVVWU, r0)
1765 opset(AXVMULWEVQVU, r0)
1766 opset(AXVMULWODHBU, r0)
1767 opset(AXVMULWODWHU, r0)
1768 opset(AXVMULWODVWU, r0)
1769 opset(AXVMULWODQVU, r0)
1770 opset(AXVMULWEVHBUB, r0)
1771 opset(AXVMULWEVWHUH, r0)
1772 opset(AXVMULWEVVWUW, r0)
1773 opset(AXVMULWEVQVUV, r0)
1774 opset(AXVMULWODHBUB, r0)
1775 opset(AXVMULWODWHUH, r0)
1776 opset(AXVMULWODVWUW, r0)
1777 opset(AXVMULWODQVUV, r0)
1778 opset(AXVADDF, r0)
1779 opset(AXVADDD, r0)
1780 opset(AXVSUBF, r0)
1781 opset(AXVSUBD, r0)
1782 opset(AXVMULF, r0)
1783 opset(AXVMULD, r0)
1784 opset(AXVDIVF, r0)
1785 opset(AXVDIVD, r0)
1786 opset(AXVSHUFH, r0)
1787 opset(AXVSHUFW, r0)
1788 opset(AXVSHUFV, r0)
1789
1790 case AVSLTB:
1791 opset(AVSLTH, r0)
1792 opset(AVSLTW, r0)
1793 opset(AVSLTV, r0)
1794 opset(AVSLTBU, r0)
1795 opset(AVSLTHU, r0)
1796 opset(AVSLTWU, r0)
1797 opset(AVSLTVU, r0)
1798 opset(AVADDWEVHB, r0)
1799 opset(AVADDWEVWH, r0)
1800 opset(AVADDWEVVW, r0)
1801 opset(AVADDWEVQV, r0)
1802 opset(AVSUBWEVHB, r0)
1803 opset(AVSUBWEVWH, r0)
1804 opset(AVSUBWEVVW, r0)
1805 opset(AVSUBWEVQV, r0)
1806 opset(AVADDWODHB, r0)
1807 opset(AVADDWODWH, r0)
1808 opset(AVADDWODVW, r0)
1809 opset(AVADDWODQV, r0)
1810 opset(AVSUBWODHB, r0)
1811 opset(AVSUBWODWH, r0)
1812 opset(AVSUBWODVW, r0)
1813 opset(AVSUBWODQV, r0)
1814 opset(AVADDWEVHBU, r0)
1815 opset(AVADDWEVWHU, r0)
1816 opset(AVADDWEVVWU, r0)
1817 opset(AVADDWEVQVU, r0)
1818 opset(AVSUBWEVHBU, r0)
1819 opset(AVSUBWEVWHU, r0)
1820 opset(AVSUBWEVVWU, r0)
1821 opset(AVSUBWEVQVU, r0)
1822 opset(AVADDWODHBU, r0)
1823 opset(AVADDWODWHU, r0)
1824 opset(AVADDWODVWU, r0)
1825 opset(AVADDWODQVU, r0)
1826 opset(AVSUBWODHBU, r0)
1827 opset(AVSUBWODWHU, r0)
1828 opset(AVSUBWODVWU, r0)
1829 opset(AVSUBWODQVU, r0)
1830 opset(AVMADDB, r0)
1831 opset(AVMADDH, r0)
1832 opset(AVMADDW, r0)
1833 opset(AVMADDV, r0)
1834 opset(AVMSUBB, r0)
1835 opset(AVMSUBH, r0)
1836 opset(AVMSUBW, r0)
1837 opset(AVMSUBV, r0)
1838 opset(AVMADDWEVHB, r0)
1839 opset(AVMADDWEVWH, r0)
1840 opset(AVMADDWEVVW, r0)
1841 opset(AVMADDWEVQV, r0)
1842 opset(AVMADDWODHB, r0)
1843 opset(AVMADDWODWH, r0)
1844 opset(AVMADDWODVW, r0)
1845 opset(AVMADDWODQV, r0)
1846 opset(AVMADDWEVHBU, r0)
1847 opset(AVMADDWEVWHU, r0)
1848 opset(AVMADDWEVVWU, r0)
1849 opset(AVMADDWEVQVU, r0)
1850 opset(AVMADDWODHBU, r0)
1851 opset(AVMADDWODWHU, r0)
1852 opset(AVMADDWODVWU, r0)
1853 opset(AVMADDWODQVU, r0)
1854 opset(AVMADDWEVHBUB, r0)
1855 opset(AVMADDWEVWHUH, r0)
1856 opset(AVMADDWEVVWUW, r0)
1857 opset(AVMADDWEVQVUV, r0)
1858 opset(AVMADDWODHBUB, r0)
1859 opset(AVMADDWODWHUH, r0)
1860 opset(AVMADDWODVWUW, r0)
1861 opset(AVMADDWODQVUV, r0)
1862
1863 case AXVSLTB:
1864 opset(AXVSLTH, r0)
1865 opset(AXVSLTW, r0)
1866 opset(AXVSLTV, r0)
1867 opset(AXVSLTBU, r0)
1868 opset(AXVSLTHU, r0)
1869 opset(AXVSLTWU, r0)
1870 opset(AXVSLTVU, r0)
1871 opset(AXVADDWEVHB, r0)
1872 opset(AXVADDWEVWH, r0)
1873 opset(AXVADDWEVVW, r0)
1874 opset(AXVADDWEVQV, r0)
1875 opset(AXVSUBWEVHB, r0)
1876 opset(AXVSUBWEVWH, r0)
1877 opset(AXVSUBWEVVW, r0)
1878 opset(AXVSUBWEVQV, r0)
1879 opset(AXVADDWODHB, r0)
1880 opset(AXVADDWODWH, r0)
1881 opset(AXVADDWODVW, r0)
1882 opset(AXVADDWODQV, r0)
1883 opset(AXVSUBWODHB, r0)
1884 opset(AXVSUBWODWH, r0)
1885 opset(AXVSUBWODVW, r0)
1886 opset(AXVSUBWODQV, r0)
1887 opset(AXVADDWEVHBU, r0)
1888 opset(AXVADDWEVWHU, r0)
1889 opset(AXVADDWEVVWU, r0)
1890 opset(AXVADDWEVQVU, r0)
1891 opset(AXVSUBWEVHBU, r0)
1892 opset(AXVSUBWEVWHU, r0)
1893 opset(AXVSUBWEVVWU, r0)
1894 opset(AXVSUBWEVQVU, r0)
1895 opset(AXVADDWODHBU, r0)
1896 opset(AXVADDWODWHU, r0)
1897 opset(AXVADDWODVWU, r0)
1898 opset(AXVADDWODQVU, r0)
1899 opset(AXVSUBWODHBU, r0)
1900 opset(AXVSUBWODWHU, r0)
1901 opset(AXVSUBWODVWU, r0)
1902 opset(AXVSUBWODQVU, r0)
1903 opset(AXVMADDB, r0)
1904 opset(AXVMADDH, r0)
1905 opset(AXVMADDW, r0)
1906 opset(AXVMADDV, r0)
1907 opset(AXVMSUBB, r0)
1908 opset(AXVMSUBH, r0)
1909 opset(AXVMSUBW, r0)
1910 opset(AXVMSUBV, r0)
1911 opset(AXVMADDWEVHB, r0)
1912 opset(AXVMADDWEVWH, r0)
1913 opset(AXVMADDWEVVW, r0)
1914 opset(AXVMADDWEVQV, r0)
1915 opset(AXVMADDWODHB, r0)
1916 opset(AXVMADDWODWH, r0)
1917 opset(AXVMADDWODVW, r0)
1918 opset(AXVMADDWODQV, r0)
1919 opset(AXVMADDWEVHBU, r0)
1920 opset(AXVMADDWEVWHU, r0)
1921 opset(AXVMADDWEVVWU, r0)
1922 opset(AXVMADDWEVQVU, r0)
1923 opset(AXVMADDWODHBU, r0)
1924 opset(AXVMADDWODWHU, r0)
1925 opset(AXVMADDWODVWU, r0)
1926 opset(AXVMADDWODQVU, r0)
1927 opset(AXVMADDWEVHBUB, r0)
1928 opset(AXVMADDWEVWHUH, r0)
1929 opset(AXVMADDWEVVWUW, r0)
1930 opset(AXVMADDWEVQVUV, r0)
1931 opset(AXVMADDWODHBUB, r0)
1932 opset(AXVMADDWODWHUH, r0)
1933 opset(AXVMADDWODVWUW, r0)
1934 opset(AXVMADDWODQVUV, r0)
1935
1936 case AVANDB:
1937 opset(AVORB, r0)
1938 opset(AVXORB, r0)
1939 opset(AVNORB, r0)
1940 opset(AVSHUF4IB, r0)
1941 opset(AVSHUF4IH, r0)
1942 opset(AVSHUF4IW, r0)
1943 opset(AVSHUF4IV, r0)
1944 opset(AVPERMIW, r0)
1945 opset(AVEXTRINSB, r0)
1946 opset(AVEXTRINSH, r0)
1947 opset(AVEXTRINSW, r0)
1948 opset(AVEXTRINSV, r0)
1949
1950 case AXVANDB:
1951 opset(AXVORB, r0)
1952 opset(AXVXORB, r0)
1953 opset(AXVNORB, r0)
1954 opset(AXVSHUF4IB, r0)
1955 opset(AXVSHUF4IH, r0)
1956 opset(AXVSHUF4IW, r0)
1957 opset(AXVSHUF4IV, r0)
1958 opset(AXVPERMIW, r0)
1959 opset(AXVPERMIV, r0)
1960 opset(AXVPERMIQ, r0)
1961 opset(AXVEXTRINSB, r0)
1962 opset(AXVEXTRINSH, r0)
1963 opset(AXVEXTRINSW, r0)
1964 opset(AXVEXTRINSV, r0)
1965
1966 case AVANDV:
1967 opset(AVORV, r0)
1968 opset(AVXORV, r0)
1969 opset(AVNORV, r0)
1970 opset(AVANDNV, r0)
1971 opset(AVORNV, r0)
1972
1973 case AXVANDV:
1974 opset(AXVORV, r0)
1975 opset(AXVXORV, r0)
1976 opset(AXVNORV, r0)
1977 opset(AXVANDNV, r0)
1978 opset(AXVORNV, r0)
1979
1980 case AVPCNTB:
1981 opset(AVPCNTH, r0)
1982 opset(AVPCNTW, r0)
1983 opset(AVPCNTV, r0)
1984 opset(AVFSQRTF, r0)
1985 opset(AVFSQRTD, r0)
1986 opset(AVFRECIPF, r0)
1987 opset(AVFRECIPD, r0)
1988 opset(AVFRSQRTF, r0)
1989 opset(AVFRSQRTD, r0)
1990 opset(AVNEGB, r0)
1991 opset(AVNEGH, r0)
1992 opset(AVNEGW, r0)
1993 opset(AVNEGV, r0)
1994 opset(AVFRINTRNEF, r0)
1995 opset(AVFRINTRNED, r0)
1996 opset(AVFRINTRZF, r0)
1997 opset(AVFRINTRZD, r0)
1998 opset(AVFRINTRPF, r0)
1999 opset(AVFRINTRPD, r0)
2000 opset(AVFRINTRMF, r0)
2001 opset(AVFRINTRMD, r0)
2002 opset(AVFRINTF, r0)
2003 opset(AVFRINTD, r0)
2004 opset(AVFCLASSF, r0)
2005 opset(AVFCLASSD, r0)
2006
2007 case AXVPCNTB:
2008 opset(AXVPCNTH, r0)
2009 opset(AXVPCNTW, r0)
2010 opset(AXVPCNTV, r0)
2011 opset(AXVFSQRTF, r0)
2012 opset(AXVFSQRTD, r0)
2013 opset(AXVFRECIPF, r0)
2014 opset(AXVFRECIPD, r0)
2015 opset(AXVFRSQRTF, r0)
2016 opset(AXVFRSQRTD, r0)
2017 opset(AXVNEGB, r0)
2018 opset(AXVNEGH, r0)
2019 opset(AXVNEGW, r0)
2020 opset(AXVNEGV, r0)
2021 opset(AXVFRINTRNEF, r0)
2022 opset(AXVFRINTRNED, r0)
2023 opset(AXVFRINTRZF, r0)
2024 opset(AXVFRINTRZD, r0)
2025 opset(AXVFRINTRPF, r0)
2026 opset(AXVFRINTRPD, r0)
2027 opset(AXVFRINTRMF, r0)
2028 opset(AXVFRINTRMD, r0)
2029 opset(AXVFRINTF, r0)
2030 opset(AXVFRINTD, r0)
2031 opset(AXVFCLASSF, r0)
2032 opset(AXVFCLASSD, r0)
2033
2034 case AVADDB:
2035 opset(AVADDH, r0)
2036 opset(AVADDW, r0)
2037 opset(AVADDV, r0)
2038 opset(AVADDQ, r0)
2039 opset(AVSUBB, r0)
2040 opset(AVSUBH, r0)
2041 opset(AVSUBW, r0)
2042 opset(AVSUBV, r0)
2043 opset(AVSUBQ, r0)
2044 opset(AVSADDB, r0)
2045 opset(AVSADDH, r0)
2046 opset(AVSADDW, r0)
2047 opset(AVSADDV, r0)
2048 opset(AVSSUBB, r0)
2049 opset(AVSSUBH, r0)
2050 opset(AVSSUBW, r0)
2051 opset(AVSSUBV, r0)
2052 opset(AVSADDBU, r0)
2053 opset(AVSADDHU, r0)
2054 opset(AVSADDWU, r0)
2055 opset(AVSADDVU, r0)
2056 opset(AVSSUBBU, r0)
2057 opset(AVSSUBHU, r0)
2058 opset(AVSSUBWU, r0)
2059 opset(AVSSUBVU, r0)
2060
2061 case AXVADDB:
2062 opset(AXVADDH, r0)
2063 opset(AXVADDW, r0)
2064 opset(AXVADDV, r0)
2065 opset(AXVADDQ, r0)
2066 opset(AXVSUBB, r0)
2067 opset(AXVSUBH, r0)
2068 opset(AXVSUBW, r0)
2069 opset(AXVSUBV, r0)
2070 opset(AXVSUBQ, r0)
2071 opset(AXVSADDB, r0)
2072 opset(AXVSADDH, r0)
2073 opset(AXVSADDW, r0)
2074 opset(AXVSADDV, r0)
2075 opset(AXVSSUBB, r0)
2076 opset(AXVSSUBH, r0)
2077 opset(AXVSSUBW, r0)
2078 opset(AXVSSUBV, r0)
2079 opset(AXVSADDBU, r0)
2080 opset(AXVSADDHU, r0)
2081 opset(AXVSADDWU, r0)
2082 opset(AXVSADDVU, r0)
2083 opset(AXVSSUBBU, r0)
2084 opset(AXVSSUBHU, r0)
2085 opset(AXVSSUBWU, r0)
2086 opset(AXVSSUBVU, r0)
2087
2088 case AVSLLB:
2089 opset(AVSRLB, r0)
2090 opset(AVSRAB, r0)
2091 opset(AVROTRB, r0)
2092 opset(AVBITCLRB, r0)
2093 opset(AVBITSETB, r0)
2094 opset(AVBITREVB, r0)
2095
2096 case AXVSLLB:
2097 opset(AXVSRLB, r0)
2098 opset(AXVSRAB, r0)
2099 opset(AXVROTRB, r0)
2100 opset(AXVBITCLRB, r0)
2101 opset(AXVBITSETB, r0)
2102 opset(AXVBITREVB, r0)
2103
2104 case AVSLLH:
2105 opset(AVSRLH, r0)
2106 opset(AVSRAH, r0)
2107 opset(AVROTRH, r0)
2108 opset(AVBITCLRH, r0)
2109 opset(AVBITSETH, r0)
2110 opset(AVBITREVH, r0)
2111
2112 case AXVSLLH:
2113 opset(AXVSRLH, r0)
2114 opset(AXVSRAH, r0)
2115 opset(AXVROTRH, r0)
2116 opset(AXVBITCLRH, r0)
2117 opset(AXVBITSETH, r0)
2118 opset(AXVBITREVH, r0)
2119
2120 case AVSLLW:
2121 opset(AVSRLW, r0)
2122 opset(AVSRAW, r0)
2123 opset(AVROTRW, r0)
2124 opset(AVADDBU, r0)
2125 opset(AVADDHU, r0)
2126 opset(AVADDWU, r0)
2127 opset(AVADDVU, r0)
2128 opset(AVSUBBU, r0)
2129 opset(AVSUBHU, r0)
2130 opset(AVSUBWU, r0)
2131 opset(AVSUBVU, r0)
2132 opset(AVBITCLRW, r0)
2133 opset(AVBITSETW, r0)
2134 opset(AVBITREVW, r0)
2135
2136 case AXVSLLW:
2137 opset(AXVSRLW, r0)
2138 opset(AXVSRAW, r0)
2139 opset(AXVROTRW, r0)
2140 opset(AXVADDBU, r0)
2141 opset(AXVADDHU, r0)
2142 opset(AXVADDWU, r0)
2143 opset(AXVADDVU, r0)
2144 opset(AXVSUBBU, r0)
2145 opset(AXVSUBHU, r0)
2146 opset(AXVSUBWU, r0)
2147 opset(AXVSUBVU, r0)
2148 opset(AXVBITCLRW, r0)
2149 opset(AXVBITSETW, r0)
2150 opset(AXVBITREVW, r0)
2151
2152 case AVSLLV:
2153 opset(AVSRLV, r0)
2154 opset(AVSRAV, r0)
2155 opset(AVROTRV, r0)
2156 opset(AVBITCLRV, r0)
2157 opset(AVBITSETV, r0)
2158 opset(AVBITREVV, r0)
2159
2160 case AXVSLLV:
2161 opset(AXVSRLV, r0)
2162 opset(AXVSRAV, r0)
2163 opset(AXVROTRV, r0)
2164 opset(AXVBITCLRV, r0)
2165 opset(AXVBITSETV, r0)
2166 opset(AXVBITREVV, r0)
2167
2168 case AVSETEQV:
2169 opset(AVSETNEV, r0)
2170 opset(AVSETANYEQB, r0)
2171 opset(AVSETANYEQH, r0)
2172 opset(AVSETANYEQW, r0)
2173 opset(AVSETANYEQV, r0)
2174 opset(AVSETALLNEB, r0)
2175 opset(AVSETALLNEH, r0)
2176 opset(AVSETALLNEW, r0)
2177 opset(AVSETALLNEV, r0)
2178
2179 case AXVSETEQV:
2180 opset(AXVSETNEV, r0)
2181 opset(AXVSETANYEQB, r0)
2182 opset(AXVSETANYEQH, r0)
2183 opset(AXVSETANYEQW, r0)
2184 opset(AXVSETANYEQV, r0)
2185 opset(AXVSETALLNEB, r0)
2186 opset(AXVSETALLNEH, r0)
2187 opset(AXVSETALLNEW, r0)
2188 opset(AXVSETALLNEV, r0)
2189
2190 }
2191 }
2192 }
2193
2194 func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
2195 return op | (r1&0x1F)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4 & 0x1F)
2196 }
2197
2198
2199
2200
2201 func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32 {
2202 return op | (r1&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2203 }
2204
2205
2206
2207 func OP_RR(op uint32, r2 uint32, r3 uint32) uint32 {
2208 return op | (r2&0x1F)<<5 | (r3&0x1F)<<0
2209 }
2210
2211 func OP_2IRRR(op uint32, i uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
2212 return op | (i&0x3)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4&0x1F)<<0
2213 }
2214
2215 func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32 {
2216 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | ((i >> 16) & 0x1F)
2217 }
2218
2219 func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2220 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2221 }
2222
2223 func OP_14IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2224 return op | (i&0x3FFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2225 }
2226
2227 func OP_12IR_5I(op uint32, i1 uint32, r2 uint32, i2 uint32) uint32 {
2228 return op | (i1&0xFFF)<<10 | (r2&0x1F)<<5 | (i2&0x1F)<<0
2229 }
2230
2231 func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2232 return op | (i&0xFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2233 }
2234
2235 func OP_11IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2236 return op | (i&0x7FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2237 }
2238
2239 func OP_10IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2240 return op | (i&0x3FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2241 }
2242
2243 func OP_9IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2244 return op | (i&0x1FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2245 }
2246
2247 func OP_8IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2248 return op | (i&0xFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2249 }
2250
2251 func OP_6IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2252 return op | (i&0x3F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2253 }
2254
2255 func OP_5IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2256 return op | (i&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2257 }
2258
2259 func OP_4IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2260 return op | (i&0xF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2261 }
2262
2263 func OP_3IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2264 return op | (i&0x7)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2265 }
2266
2267 func OP_IR(op uint32, i uint32, r2 uint32) uint32 {
2268 return op | (i&0xFFFFF)<<5 | (r2&0x1F)<<0
2269 }
2270
2271 func OP_15I(op uint32, i uint32) uint32 {
2272 return op | (i&0x7FFF)<<0
2273 }
2274
2275
2276
2277
2278
2279 func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32 {
2280 return op | (i1 << 16) | (r2&0x1F)<<5 | (i3 << 10) | (r4&0x1F)<<0
2281 }
2282
2283
2284 func OP_B_BL(op uint32, i uint32) uint32 {
2285 return op | ((i & 0xFFFF) << 10) | ((i >> 16) & 0x3FF)
2286 }
2287
2288 func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
2289 o1 := uint32(0)
2290 o2 := uint32(0)
2291 o3 := uint32(0)
2292 o4 := uint32(0)
2293 o5 := uint32(0)
2294 o6 := uint32(0)
2295
2296 add := AADDVU
2297
2298 switch o.type_ {
2299 default:
2300 c.ctxt.Diag("unknown type %d", o.type_)
2301 prasm(p)
2302
2303 case 0:
2304 break
2305
2306 case 1:
2307 switch p.As {
2308 case AMOVW:
2309 o1 = OP_RRR(c.oprrr(ASLL), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
2310 case AMOVV:
2311 o1 = OP_RRR(c.oprrr(AOR), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
2312 case AVMOVQ:
2313 o1 = OP_6IRR(c.opirr(AVSLLV), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
2314 case AXVMOVQ:
2315 o1 = OP_6IRR(c.opirr(AXVSLLV), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
2316 default:
2317 c.ctxt.Diag("unexpected encoding\n%v", p)
2318 }
2319
2320 case 2:
2321 r := int(p.Reg)
2322 if p.As == ANEGW || p.As == ANEGV {
2323 r = REGZERO
2324 }
2325 if r == 0 {
2326 r = int(p.To.Reg)
2327 }
2328 o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
2329
2330 case 3:
2331 v := c.regoff(&p.From)
2332
2333 r := int(p.From.Reg)
2334 if r == 0 {
2335 r = int(o.param)
2336 }
2337 a := add
2338 if o.from1 == C_12CON && v > 0 {
2339 a = AOR
2340 }
2341
2342 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.To.Reg))
2343
2344 case 4:
2345 v := c.regoff(&p.From)
2346 r := int(p.Reg)
2347 if r == 0 {
2348 r = int(p.To.Reg)
2349 }
2350 if p.As == AADDV16 {
2351 if v&65535 != 0 {
2352 c.ctxt.Diag("%v: the constant must be a multiple of 65536.\n", p)
2353 }
2354 o1 = OP_16IRR(c.opirr(p.As), uint32(v>>16), uint32(r), uint32(p.To.Reg))
2355 } else {
2356 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2357 }
2358
2359 case 5:
2360 v := c.regoff(&p.From)
2361 o1 = OP_15I(c.opi(p.As), uint32(v))
2362
2363 case 6:
2364 v := int32(0)
2365 if p.To.Target() != nil {
2366 v = int32(p.To.Target().Pc-p.Pc) >> 2
2367 }
2368 as, rd, rj, width := p.As, p.Reg, p.From.Reg, 16
2369 switch as {
2370 case ABGTZ, ABLEZ:
2371 rd, rj = rj, rd
2372 case ABFPT, ABFPF:
2373 width = 21
2374
2375
2376 if rj == 0 {
2377 rj = REG_FCC0
2378 }
2379 case ABEQ, ABNE:
2380 if rd == 0 || rd == REGZERO || rj == REGZERO {
2381
2382 width = 21
2383 as = -as
2384 if rj == 0 || rj == REGZERO {
2385 rj = rd
2386 }
2387 }
2388 }
2389 switch width {
2390 case 21:
2391 if (v<<11)>>11 != v {
2392 c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
2393 }
2394 o1 = OP_16IR_5I(c.opirr(as), uint32(v), uint32(rj))
2395 case 16:
2396 if (v<<16)>>16 != v {
2397 c.ctxt.Diag("16 bit-width, short branch too far\n%v", p)
2398 }
2399 o1 = OP_16IRR(c.opirr(as), uint32(v), uint32(rj), uint32(rd))
2400 default:
2401 c.ctxt.Diag("unexpected branch encoding\n%v", p)
2402 }
2403
2404 case 7:
2405 r := int(p.To.Reg)
2406 if r == 0 {
2407 r = int(o.param)
2408 }
2409 v := c.regoff(&p.To)
2410 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2411
2412 case 8:
2413 r := int(p.From.Reg)
2414 if r == 0 {
2415 r = int(o.param)
2416 }
2417 v := c.regoff(&p.From)
2418 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2419
2420 case 9:
2421 o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
2422
2423 case 10:
2424 v := c.regoff(&p.From)
2425 a := AOR
2426 if v < 0 {
2427 a = AADD
2428 }
2429 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2430 r := int(p.Reg)
2431 if r == 0 {
2432 r = int(p.To.Reg)
2433 }
2434 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2435
2436 case 11:
2437 v := int32(0)
2438 if p.To.Target() != nil {
2439 v = int32(p.To.Target().Pc-p.Pc) >> 2
2440 if v < -1<<25 || v >= 1<<25 {
2441 c.ctxt.Diag("branch too far \n%v", p)
2442 }
2443 }
2444 o1 = OP_B_BL(c.opirr(p.As), uint32(v))
2445 if p.To.Sym != nil {
2446 c.cursym.AddRel(c.ctxt, obj.Reloc{
2447 Type: objabi.R_CALLLOONG64,
2448 Off: int32(c.pc),
2449 Siz: 4,
2450 Sym: p.To.Sym,
2451 Add: p.To.Offset,
2452 })
2453 }
2454
2455 case 12:
2456 switch p.As {
2457 case AMOVB:
2458 o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg))
2459 case AMOVH:
2460 o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg))
2461 case AMOVBU:
2462 o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg))
2463 case AMOVHU:
2464 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2465 case AMOVWU:
2466 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2467 default:
2468 c.ctxt.Diag("unexpected encoding\n%v", p)
2469 }
2470
2471 case 13:
2472 v := c.regoff(&p.From)
2473 r := int(p.Reg)
2474 if r == 0 {
2475 r = int(p.To.Reg)
2476 }
2477 o1 = OP_3IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2478
2479 case 14:
2480 v := c.regoff(&p.From)
2481 r := int(p.Reg)
2482 if r == 0 {
2483 r = int(p.To.Reg)
2484 }
2485 o1 = OP_4IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2486
2487 case 15:
2488 v := c.regoff(&p.From)
2489 r := int(p.Reg)
2490 if r == 0 {
2491 r = REGZERO
2492 }
2493
2501 if p.As == ATEQ {
2502 o1 = OP_16IRR(c.opirr(ABNE), uint32(2), uint32(r), uint32(p.To.Reg))
2503 } else {
2504 o1 = OP_16IRR(c.opirr(ABEQ), uint32(2), uint32(r), uint32(p.To.Reg))
2505 }
2506 o2 = OP_15I(c.opi(ABREAK), uint32(v))
2507
2508 case 16:
2509 v := c.regoff(&p.From)
2510 r := int(p.Reg)
2511 if r == 0 {
2512 r = int(p.To.Reg)
2513 }
2514
2515
2516 if v >= 32 && vshift(p.As) {
2517 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x3f, uint32(r), uint32(p.To.Reg))
2518 } else {
2519 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x1f, uint32(r), uint32(p.To.Reg))
2520 }
2521
2522 case 17:
2523 rd, rj := p.To.Reg, p.Reg
2524 if rj == obj.REG_NONE {
2525 rj = rd
2526 }
2527 msb, lsb := p.From.Offset, p.GetFrom3().Offset
2528
2529
2530 var b uint32
2531 if p.As == ABSTRPICKW || p.As == ABSTRINSW {
2532 b = 32
2533 } else {
2534 b = 64
2535 }
2536 if lsb < 0 || uint32(lsb) >= b || msb < 0 || uint32(msb) >= b || uint32(lsb) > uint32(msb) {
2537 c.ctxt.Diag("illegal bit number\n%v", p)
2538 }
2539
2540 o1 = OP_IRIR(c.opirir(p.As), uint32(msb), uint32(rj), uint32(lsb), uint32(rd))
2541
2542 case 18:
2543 r := int(p.Reg)
2544 if r == 0 {
2545 r = int(o.param)
2546 }
2547 o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.To.Reg), uint32(r))
2548 if p.As == obj.ACALL {
2549 c.cursym.AddRel(c.ctxt, obj.Reloc{
2550 Type: objabi.R_CALLIND,
2551 Off: int32(c.pc),
2552 })
2553 }
2554
2555 case 19:
2556
2557
2558 v := c.regoff(&p.From)
2559 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2560 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2561
2562 case 20:
2563 o1 = OP_RRR(c.oprrr(p.As), uint32(p.To.Index), uint32(p.To.Reg), uint32(p.From.Reg))
2564
2565 case 21:
2566 o1 = OP_RRR(c.oprrr(-p.As), uint32(p.From.Index), uint32(p.From.Reg), uint32(p.To.Reg))
2567
2568 case 22:
2569 v := c.regoff(&p.From)
2570 r := int(p.Reg)
2571 if r == 0 {
2572 r = int(p.To.Reg)
2573 }
2574
2575 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2576
2577 case 23:
2578 v := c.regoff(&p.From)
2579 r := int(p.Reg)
2580 if r == 0 {
2581 r = int(p.To.Reg)
2582 }
2583
2584
2585 if p.As == AVSHUF4IV || p.As == AXVSHUF4IV {
2586 operand := uint32(v)
2587 c.checkoperand(p, operand, 15)
2588 }
2589
2590 o1 = OP_8IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2591
2592 case 24:
2593 v := c.regoff(&p.From)
2594 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2595 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2596 r := int(p.Reg)
2597 if r == 0 {
2598 r = int(p.To.Reg)
2599 }
2600 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2601
2602 case 25:
2603 v := c.regoff(&p.From)
2604 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2605
2606 case 26:
2607 v := c.regoff(&p.From)
2608 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2609 r := int(p.Reg)
2610 if r == 0 {
2611 r = int(p.To.Reg)
2612 }
2613 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2614
2615 case 27:
2616 v := c.regoff(&p.From)
2617 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2618 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2619 r := int(p.From.Reg)
2620 if r == 0 {
2621 r = int(o.param)
2622 }
2623 o3 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2624
2625 case 28:
2626 v := c.regoff(&p.From)
2627 r := int(p.From.Reg)
2628 if r == 0 {
2629 r = int(o.param)
2630 }
2631 switch o.size {
2632 case 12:
2633 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2634 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2635 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2636
2637 case 4:
2638 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2639 }
2640
2641 case 29:
2642 v := c.regoff(&p.To)
2643 r := int(p.To.Reg)
2644 if r == 0 {
2645 r = int(o.param)
2646 }
2647 switch o.size {
2648 case 12:
2649 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2650 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2651 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2652
2653 case 4:
2654 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2655 }
2656
2657 case 30:
2658 a := c.specialFpMovInst(p.As, oclass(&p.From), oclass(&p.To))
2659 o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
2660
2661 case 31:
2662 v := c.regoff(&p.From)
2663 r := int(p.Reg)
2664 if r == 0 {
2665 r = int(p.To.Reg)
2666 }
2667 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2668
2669 case 32:
2670 v := c.regoff(&p.From)
2671 r := int(p.Reg)
2672 if r == 0 {
2673 r = int(p.To.Reg)
2674 }
2675 o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2676
2677 case 33:
2678 ca := uint32(p.From.Reg)
2679 fk := uint32(p.Reg)
2680 fd := uint32(p.To.Reg)
2681 fj := fd
2682 if len(p.RestArgs) > 0 {
2683 fj = uint32(p.GetFrom3().Reg)
2684 }
2685 o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F)
2686
2687 case 34:
2688 v := c.regoff(&p.From)
2689 a := AADD
2690 if v > 0 {
2691 a = AOR
2692 }
2693 a2 := c.specialFpMovInst(p.As, C_REG, oclass(&p.To))
2694 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2695 o2 = OP_RR(a2, uint32(REGTMP), uint32(p.To.Reg))
2696
2697 case 35:
2698 v := c.regoff(&p.To)
2699 r := int(p.To.Reg)
2700 if r == 0 {
2701 r = int(o.param)
2702 }
2703 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2704 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2705 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2706
2707 case 36:
2708 v := c.regoff(&p.From)
2709 r := int(p.From.Reg)
2710 if r == 0 {
2711 r = int(o.param)
2712 }
2713 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2714 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2715 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2716
2717 case 37:
2718 r := int(p.To.Reg)
2719 if len(p.RestArgs) > 0 {
2720 r = int(p.GetFrom3().Reg)
2721 }
2722 o1 = OP_RRRR(c.oprrrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(r), uint32(p.To.Reg))
2723
2724 case 38:
2725 o1 = uint32(c.regoff(&p.From))
2726
2727 case 39:
2728 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2729 if v == 0 {
2730 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2731 }
2732
2733 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2734 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2735 index := uint32(p.To.Index)
2736 c.checkindex(p, index, m)
2737 o1 = v | (index << 10) | (Rj << 5) | Vd
2738
2739 case 40:
2740 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2741 if v == 0 {
2742 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2743 }
2744
2745 Vj := uint32(p.From.Reg & EXT_REG_MASK)
2746 Rd := uint32(p.To.Reg & EXT_REG_MASK)
2747 index := uint32(p.From.Index)
2748 c.checkindex(p, index, m)
2749 o1 = v | (index << 10) | (Vj << 5) | Rd
2750
2751 case 41:
2752 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2753 if v == 0 {
2754 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2755 }
2756
2757 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2758 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2759 o1 = v | (Rj << 5) | Vd
2760
2761 case 42:
2762 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2763 if v == 0 {
2764 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2765 }
2766
2767 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2768 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2769 o1 = v | (Xj << 5) | Xd
2770
2771 case 43:
2772 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2773 if v == 0 {
2774 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2775 }
2776
2777 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2778 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2779 index := uint32(p.To.Index)
2780 c.checkindex(p, index, m)
2781 o1 = v | (index << 10) | (Xj << 5) | Xd
2782
2783 case 44:
2784 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2785 if v == 0 {
2786 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2787 }
2788
2789 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2790 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2791 index := uint32(p.From.Index)
2792 c.checkindex(p, index, m)
2793 o1 = v | (index << 10) | (Xj << 5) | Xd
2794
2795 case 45:
2796 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2797 if v == 0 {
2798 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2799 }
2800
2801 vj := uint32(p.From.Reg & EXT_REG_MASK)
2802 vd := uint32(p.To.Reg & EXT_REG_MASK)
2803 index := uint32(p.From.Index)
2804 c.checkindex(p, index, m)
2805 o1 = v | (index << 10) | (vj << 5) | vd
2806
2807 case 46:
2808 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, true)
2809 if v == 0 {
2810 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2811 }
2812
2813 si := c.regoff(&p.From)
2814 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2815 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2816 switch v & 0xc00000 {
2817 case 0x800000:
2818 o1 = OP_12IRR(v, uint32(si), Rj, Vd)
2819 case 0x400000:
2820 if si&1 != 0 {
2821 c.ctxt.Diag("%v: offset must be a multiple of 2.\n", p)
2822 }
2823 o1 = OP_11IRR(v, uint32(si>>1), Rj, Vd)
2824 case 0x0:
2825 switch v & 0x300000 {
2826 case 0x200000:
2827 if si&3 != 0 {
2828 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
2829 }
2830 o1 = OP_10IRR(v, uint32(si>>2), Rj, Vd)
2831 case 0x100000:
2832 if si&7 != 0 {
2833 c.ctxt.Diag("%v: offset must be a multiple of 8.\n", p)
2834 }
2835 o1 = OP_9IRR(v, uint32(si>>3), Rj, Vd)
2836 }
2837 }
2838
2839 case 47:
2840 offs := c.regoff(&p.From)
2841 hint := p.GetFrom3().Offset
2842 o1 = OP_12IR_5I(c.opiir(p.As), uint32(offs), uint32(p.From.Reg), uint32(hint))
2843
2844 case 48:
2845 offs := c.regoff(&p.From)
2846 hint := p.RestArgs[1].Offset
2847 n := uint64(p.GetFrom3().Offset)
2848
2849 addrSeq := (n >> 0) & 0x1
2850 blkSize := (n >> 1) & 0x7ff
2851 blkNums := (n >> 12) & 0x1ff
2852 stride := (n >> 21) & 0xffff
2853
2854 if blkSize > 1024 {
2855 c.ctxt.Diag("%v: block_size amount out of range[16, 1024]: %v\n", p, blkSize)
2856 }
2857
2858 if blkNums > 256 {
2859 c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkSize)
2860 }
2861
2862 v := (uint64(offs) & 0xffff)
2863 v += addrSeq << 16
2864 v += ((blkSize / 16) - 1) << 20
2865 v += (blkNums - 1) << 32
2866 v += stride << 44
2867
2868 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2869 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2870 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2871 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2872 o5 = OP_5IRR(c.opirr(p.As), uint32(REGTMP), uint32(p.From.Reg), uint32(hint))
2873
2874 case 49:
2875 if p.As == ANOOP {
2876
2877 o1 = OP_12IRR(c.opirr(AAND), 0, 0, 0)
2878 } else {
2879
2880 o1 = OP_15I(c.opi(ABREAK), 0)
2881 }
2882
2883
2884 case 50:
2885 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2886 c.cursym.AddRel(c.ctxt, obj.Reloc{
2887 Type: objabi.R_LOONG64_ADDR_HI,
2888 Off: int32(c.pc),
2889 Siz: 4,
2890 Sym: p.To.Sym,
2891 Add: p.To.Offset,
2892 })
2893 o2 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2894 c.cursym.AddRel(c.ctxt, obj.Reloc{
2895 Type: objabi.R_LOONG64_ADDR_LO,
2896 Off: int32(c.pc + 4),
2897 Siz: 4,
2898 Sym: p.To.Sym,
2899 Add: p.To.Offset,
2900 })
2901
2902 case 51:
2903 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2904 c.cursym.AddRel(c.ctxt, obj.Reloc{
2905 Type: objabi.R_LOONG64_ADDR_HI,
2906 Off: int32(c.pc),
2907 Siz: 4,
2908 Sym: p.From.Sym,
2909 Add: p.From.Offset,
2910 })
2911 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2912 c.cursym.AddRel(c.ctxt, obj.Reloc{
2913 Type: objabi.R_LOONG64_ADDR_LO,
2914 Off: int32(c.pc + 4),
2915 Siz: 4,
2916 Sym: p.From.Sym,
2917 Add: p.From.Offset,
2918 })
2919
2920 case 52:
2921
2922
2923 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2924 c.cursym.AddRel(c.ctxt, obj.Reloc{
2925 Type: objabi.R_LOONG64_ADDR_HI,
2926 Off: int32(c.pc),
2927 Siz: 4,
2928 Sym: p.From.Sym,
2929 Add: p.From.Offset,
2930 })
2931 o2 = OP_12IRR(c.opirr(add), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2932 c.cursym.AddRel(c.ctxt, obj.Reloc{
2933 Type: objabi.R_LOONG64_ADDR_LO,
2934 Off: int32(c.pc + 4),
2935 Siz: 4,
2936 Sym: p.From.Sym,
2937 Add: p.From.Offset,
2938 })
2939
2940 case 53:
2941
2942
2943 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2944 c.cursym.AddRel(c.ctxt, obj.Reloc{
2945 Type: objabi.R_LOONG64_TLS_LE_HI,
2946 Off: int32(c.pc),
2947 Siz: 4,
2948 Sym: p.To.Sym,
2949 Add: p.To.Offset,
2950 })
2951 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2952 c.cursym.AddRel(c.ctxt, obj.Reloc{
2953 Type: objabi.R_LOONG64_TLS_LE_LO,
2954 Off: int32(c.pc + 4),
2955 Siz: 4,
2956 Sym: p.To.Sym,
2957 Add: p.To.Offset,
2958 })
2959 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2960 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2961
2962 case 54:
2963
2964
2965 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2966 c.cursym.AddRel(c.ctxt, obj.Reloc{
2967 Type: objabi.R_LOONG64_TLS_LE_HI,
2968 Off: int32(c.pc),
2969 Siz: 4,
2970 Sym: p.From.Sym,
2971 Add: p.From.Offset,
2972 })
2973 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2974 c.cursym.AddRel(c.ctxt, obj.Reloc{
2975 Type: objabi.R_LOONG64_TLS_LE_LO,
2976 Off: int32(c.pc + 4),
2977 Siz: 4,
2978 Sym: p.From.Sym,
2979 Add: p.From.Offset,
2980 })
2981 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2982 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2983
2984 case 56:
2985 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2986 c.cursym.AddRel(c.ctxt, obj.Reloc{
2987 Type: objabi.R_LOONG64_TLS_IE_HI,
2988 Off: int32(c.pc),
2989 Siz: 4,
2990 Sym: p.To.Sym,
2991 })
2992 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2993 c.cursym.AddRel(c.ctxt, obj.Reloc{
2994 Type: objabi.R_LOONG64_TLS_IE_LO,
2995 Off: int32(c.pc + 4),
2996 Siz: 4,
2997 Sym: p.To.Sym,
2998 })
2999 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
3000 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
3001
3002 case 57:
3003 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
3004 c.cursym.AddRel(c.ctxt, obj.Reloc{
3005 Type: objabi.R_LOONG64_TLS_IE_HI,
3006 Off: int32(c.pc),
3007 Siz: 4,
3008 Sym: p.From.Sym,
3009 })
3010 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
3011 c.cursym.AddRel(c.ctxt, obj.Reloc{
3012 Type: objabi.R_LOONG64_TLS_IE_LO,
3013 Off: int32(c.pc + 4),
3014 Siz: 4,
3015 Sym: p.From.Sym,
3016 })
3017 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
3018 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
3019
3020 case 59:
3021
3022
3023 v := c.vregoff(&p.From)
3024 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
3025 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
3026 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
3027 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
3028
3029 case 60:
3030 v := c.vregoff(&p.From)
3031 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3032 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3033 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3034 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3035 r := int(p.Reg)
3036 if r == 0 {
3037 r = int(p.To.Reg)
3038 }
3039 o5 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
3040
3041 case 61:
3042 o1 = uint32(c.vregoff(&p.From))
3043 o2 = uint32(c.vregoff(&p.From) >> 32)
3044
3045 case 62:
3046 o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
3047
3048 case 64:
3049 sa := p.From.Offset - 1
3050 if sa < 0 || sa > 3 {
3051 c.ctxt.Diag("%v: shift amount out of range[1, 4].\n", p)
3052 }
3053 r := p.GetFrom3().Reg
3054 o1 = OP_2IRRR(c.opirrr(p.As), uint32(sa), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
3055
3056 case 65:
3057 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
3058 c.cursym.AddRel(c.ctxt, obj.Reloc{
3059 Type: objabi.R_LOONG64_GOT_HI,
3060 Off: int32(c.pc),
3061 Siz: 4,
3062 Sym: p.From.Sym,
3063 })
3064 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
3065 c.cursym.AddRel(c.ctxt, obj.Reloc{
3066 Type: objabi.R_LOONG64_GOT_LO,
3067 Off: int32(c.pc + 4),
3068 Siz: 4,
3069 Sym: p.From.Sym,
3070 })
3071
3072 case 66:
3073 rk := p.From.Reg
3074 rj := p.To.Reg
3075 rd := p.RegTo2
3076
3077
3078
3079 if rd == rj || rd == rk {
3080 c.ctxt.Diag("illegal register combination: %v\n", p)
3081 }
3082 o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
3083
3084 case 67:
3085 v := c.vregoff(&p.From)
3086 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(p.To.Reg))
3087
3088 case 68:
3089 v := c.vregoff(&p.From)
3090 contype := c.aclass(&p.From)
3091 switch contype {
3092 default:
3093 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
3094 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
3095 case C_DCON20S_20:
3096 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
3097 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
3098 case C_DCON12_12S:
3099 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(p.To.Reg))
3100 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
3101 case C_DCON20S_12S, C_DCON20S_0:
3102 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
3103 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
3104 case C_DCON12_12U:
3105 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
3106 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
3107 case C_DCON20S_12U:
3108 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
3109 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
3110 }
3111
3112 case 69:
3113 v := c.vregoff(&p.From)
3114 contype := c.aclass(&p.From)
3115 switch contype {
3116 default:
3117 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
3118 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
3119 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
3120 case C_DCON32_20:
3121 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
3122 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
3123 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
3124 case C_DCON12_32S:
3125 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
3126 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
3127 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
3128 case C_DCON20S_32:
3129 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
3130 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
3131 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
3132 case C_DCON32_12U:
3133 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
3134 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
3135 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
3136 }
3137
3138 case 70:
3139 v := c.vregoff(&p.From)
3140 r := int(p.Reg)
3141 if r == 0 {
3142 r = int(p.To.Reg)
3143 }
3144 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(REGTMP))
3145 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
3146
3147 case 71:
3148 v := c.vregoff(&p.From)
3149 r := int(p.Reg)
3150 if r == 0 {
3151 r = int(p.To.Reg)
3152 }
3153 contype := c.aclass(&p.From)
3154 switch contype {
3155 default:
3156 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3157 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3158 case C_DCON20S_20:
3159 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3160 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3161 case C_DCON12_12S:
3162 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(REGTMP))
3163 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3164 case C_DCON20S_12S, C_DCON20S_0:
3165 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
3166 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3167 case C_DCON12_12U:
3168 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
3169 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3170 case C_DCON20S_12U:
3171 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
3172 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3173 }
3174 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
3175
3176 case 72:
3177 v := c.vregoff(&p.From)
3178 r := int(p.Reg)
3179 if r == 0 {
3180 r = int(p.To.Reg)
3181 }
3182 contype := c.aclass(&p.From)
3183 switch contype {
3184 default:
3185 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
3186 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3187 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3188 case C_DCON32_20:
3189 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3190 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3191 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3192 case C_DCON12_32S:
3193 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3194 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3195 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3196 case C_DCON20S_32:
3197 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3198 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3199 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3200 case C_DCON32_12U:
3201 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
3202 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3203 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3204 }
3205 o4 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
3206
3207 case 73:
3208 v := c.vregoff(&p.To)
3209 r := p.To.Reg
3210 if v&3 != 0 {
3211 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
3212 }
3213
3214 switch o.size {
3215 case 4:
3216 o1 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(r), uint32(p.From.Reg))
3217 case 12:
3218 o1 = OP_16IRR(c.opirr(AADDV16), uint32(v>>16), uint32(REG_R0), uint32(REGTMP))
3219 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
3220 o3 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(REGTMP), uint32(p.From.Reg))
3221 case 24:
3222 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3223 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3224 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3225 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3226 o5 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(r))
3227 o6 = OP_14IRR(c.opirr(p.As), uint32(0), uint32(r), uint32(p.From.Reg))
3228 }
3229
3230 case 74:
3231 v := c.vregoff(&p.From)
3232 r := p.From.Reg
3233 if v&3 != 0 {
3234 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
3235 }
3236
3237 switch o.size {
3238 case 4:
3239 o1 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(r), uint32(p.To.Reg))
3240 case 12:
3241 o1 = OP_16IRR(c.opirr(AADDV16), uint32(v>>16), uint32(REG_R0), uint32(REGTMP))
3242 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
3243 o3 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(REGTMP), uint32(p.To.Reg))
3244 case 24:
3245 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
3246 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
3247 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
3248 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
3249 o5 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(r))
3250 o6 = OP_14IRR(c.opirr(p.As), uint32(0), uint32(r), uint32(p.To.Reg))
3251 }
3252
3253 }
3254
3255 out[0] = o1
3256 out[1] = o2
3257 out[2] = o3
3258 out[3] = o4
3259 out[4] = o5
3260 out[5] = o6
3261 }
3262
3263
3264 func (c *ctxt0) checkoperand(p *obj.Prog, operand uint32, mask uint32) {
3265 if (operand & ^mask) != 0 {
3266 c.ctxt.Diag("operand out of range 0 to %d: %v", mask, p)
3267 }
3268 }
3269
3270
3271 func (c *ctxt0) checkindex(p *obj.Prog, index uint32, mask uint32) {
3272 if (index & ^mask) != 0 {
3273 c.ctxt.Diag("register element index out of range 0 to %d: %v", mask, p)
3274 }
3275 }
3276
3277 func (c *ctxt0) vregoff(a *obj.Addr) int64 {
3278 c.instoffset = 0
3279 c.aclass(a)
3280 return c.instoffset
3281 }
3282
3283 func (c *ctxt0) regoff(a *obj.Addr) int32 {
3284 return int32(c.vregoff(a))
3285 }
3286
3287 func (c *ctxt0) oprrrr(a obj.As) uint32 {
3288 switch a {
3289 case AFMADDF:
3290 return 0x81 << 20
3291 case AFMADDD:
3292 return 0x82 << 20
3293 case AFMSUBF:
3294 return 0x85 << 20
3295 case AFMSUBD:
3296 return 0x86 << 20
3297 case AFNMADDF:
3298 return 0x89 << 20
3299 case AFNMADDD:
3300 return 0x8a << 20
3301 case AFNMSUBF:
3302 return 0x8d << 20
3303 case AFNMSUBD:
3304 return 0x8e << 20
3305 case AVSHUFB:
3306 return 0x0D5 << 20
3307 case AXVSHUFB:
3308 return 0x0D6 << 20
3309 }
3310
3311 c.ctxt.Diag("bad rrrr opcode %v", a)
3312 return 0
3313 }
3314
3315 func (c *ctxt0) oprrr(a obj.As) uint32 {
3316 switch a {
3317 case AADD, AADDW:
3318 return 0x20 << 15
3319 case ASGT:
3320 return 0x24 << 15
3321 case ASGTU:
3322 return 0x25 << 15
3323 case AMASKEQZ:
3324 return 0x26 << 15
3325 case AMASKNEZ:
3326 return 0x27 << 15
3327 case AAND:
3328 return 0x29 << 15
3329 case AOR:
3330 return 0x2a << 15
3331 case AXOR:
3332 return 0x2b << 15
3333 case AORN:
3334 return 0x2c << 15
3335 case AANDN:
3336 return 0x2d << 15
3337 case ASUB, ASUBW, ANEGW:
3338 return 0x22 << 15
3339 case ANOR:
3340 return 0x28 << 15
3341 case ASLL:
3342 return 0x2e << 15
3343 case ASRL:
3344 return 0x2f << 15
3345 case ASRA:
3346 return 0x30 << 15
3347 case AROTR:
3348 return 0x36 << 15
3349 case ASLLV:
3350 return 0x31 << 15
3351 case ASRLV:
3352 return 0x32 << 15
3353 case ASRAV:
3354 return 0x33 << 15
3355 case AROTRV:
3356 return 0x37 << 15
3357 case AADDV:
3358 return 0x21 << 15
3359 case AADDVU:
3360 return 0x21 << 15
3361 case ASUBV:
3362 return 0x23 << 15
3363 case ASUBVU, ANEGV:
3364 return 0x23 << 15
3365
3366 case AMUL, AMULW:
3367 return 0x38 << 15
3368 case AMULH:
3369 return 0x39 << 15
3370 case AMULHU:
3371 return 0x3a << 15
3372 case AMULV:
3373 return 0x3b << 15
3374 case AMULVU:
3375 return 0x3b << 15
3376 case AMULHV:
3377 return 0x3c << 15
3378 case AMULHVU:
3379 return 0x3d << 15
3380 case AMULWVW:
3381 return 0x3e << 15
3382 case AMULWVWU:
3383 return 0x3f << 15
3384 case ADIV, ADIVW:
3385 return 0x40 << 15
3386 case ADIVU, ADIVWU:
3387 return 0x42 << 15
3388 case ADIVV:
3389 return 0x44 << 15
3390 case ADIVVU:
3391 return 0x46 << 15
3392 case AREM, AREMW:
3393 return 0x41 << 15
3394 case AREMU, AREMWU:
3395 return 0x43 << 15
3396 case AREMV:
3397 return 0x45 << 15
3398 case AREMVU:
3399 return 0x47 << 15
3400 case ACRCWBW:
3401 return 0x48 << 15
3402 case ACRCWHW:
3403 return 0x49 << 15
3404 case ACRCWWW:
3405 return 0x4a << 15
3406 case ACRCWVW:
3407 return 0x4b << 15
3408 case ACRCCWBW:
3409 return 0x4c << 15
3410 case ACRCCWHW:
3411 return 0x4d << 15
3412 case ACRCCWWW:
3413 return 0x4e << 15
3414 case ACRCCWVW:
3415 return 0x4f << 15
3416 case AJMP:
3417 return 0x13 << 26
3418 case AJAL:
3419 return (0x13 << 26) | 1
3420
3421 case ADIVF:
3422 return 0x20d << 15
3423 case ADIVD:
3424 return 0x20e << 15
3425 case AMULF:
3426 return 0x209 << 15
3427 case AMULD:
3428 return 0x20a << 15
3429 case ASUBF:
3430 return 0x205 << 15
3431 case ASUBD:
3432 return 0x206 << 15
3433 case AADDF:
3434 return 0x201 << 15
3435 case AADDD:
3436 return 0x202 << 15
3437 case ACMPEQF:
3438 return 0x0c1<<20 | 0x4<<15
3439 case ACMPEQD:
3440 return 0x0c2<<20 | 0x4<<15
3441 case ACMPGED:
3442 return 0x0c2<<20 | 0x7<<15
3443 case ACMPGEF:
3444 return 0x0c1<<20 | 0x7<<15
3445 case ACMPGTD:
3446 return 0x0c2<<20 | 0x3<<15
3447 case ACMPGTF:
3448 return 0x0c1<<20 | 0x3<<15
3449 case AFMINF:
3450 return 0x215 << 15
3451 case AFMIND:
3452 return 0x216 << 15
3453 case AFMAXF:
3454 return 0x211 << 15
3455 case AFMAXD:
3456 return 0x212 << 15
3457 case AFMAXAF:
3458 return 0x219 << 15
3459 case AFMAXAD:
3460 return 0x21a << 15
3461 case AFMINAF:
3462 return 0x21d << 15
3463 case AFMINAD:
3464 return 0x21e << 15
3465 case AFSCALEBF:
3466 return 0x221 << 15
3467 case AFSCALEBD:
3468 return 0x222 << 15
3469 case AFCOPYSGF:
3470 return 0x225 << 15
3471 case AFCOPYSGD:
3472 return 0x226 << 15
3473 case -AMOVB:
3474 return 0x07000 << 15
3475 case -AMOVH:
3476 return 0x07008 << 15
3477 case -AMOVW:
3478 return 0x07010 << 15
3479 case -AMOVV:
3480 return 0x07018 << 15
3481 case -AMOVBU:
3482 return 0x07040 << 15
3483 case -AMOVHU:
3484 return 0x07048 << 15
3485 case -AMOVWU:
3486 return 0x07050 << 15
3487 case AMOVB:
3488 return 0x07020 << 15
3489 case AMOVH:
3490 return 0x07028 << 15
3491 case AMOVW:
3492 return 0x07030 << 15
3493 case AMOVV:
3494 return 0x07038 << 15
3495 case -AMOVF:
3496 return 0x07060 << 15
3497 case -AMOVD:
3498 return 0x07068 << 15
3499 case AMOVF:
3500 return 0x07070 << 15
3501 case AMOVD:
3502 return 0x07078 << 15
3503 case -AVMOVQ:
3504 return 0x07080 << 15
3505 case -AXVMOVQ:
3506 return 0x07090 << 15
3507 case AVMOVQ:
3508 return 0x07088 << 15
3509 case AXVMOVQ:
3510 return 0x07098 << 15
3511 case AVSEQB:
3512 return 0x0e000 << 15
3513 case AXVSEQB:
3514 return 0x0e800 << 15
3515 case AVSEQH:
3516 return 0x0e001 << 15
3517 case AXVSEQH:
3518 return 0x0e801 << 15
3519 case AVSEQW:
3520 return 0x0e002 << 15
3521 case AXVSEQW:
3522 return 0x0e802 << 15
3523 case AVSEQV:
3524 return 0x0e003 << 15
3525 case AXVSEQV:
3526 return 0x0e803 << 15
3527 case AVSLTB:
3528 return 0x0E00C << 15
3529 case AVSLTH:
3530 return 0x0E00D << 15
3531 case AVSLTW:
3532 return 0x0E00E << 15
3533 case AVSLTV:
3534 return 0x0E00F << 15
3535 case AVSLTBU:
3536 return 0x0E010 << 15
3537 case AVSLTHU:
3538 return 0x0E011 << 15
3539 case AVSLTWU:
3540 return 0x0E012 << 15
3541 case AVSLTVU:
3542 return 0x0E013 << 15
3543 case AXVSLTB:
3544 return 0x0E80C << 15
3545 case AXVSLTH:
3546 return 0x0E80D << 15
3547 case AXVSLTW:
3548 return 0x0E80E << 15
3549 case AXVSLTV:
3550 return 0x0E80F << 15
3551 case AXVSLTBU:
3552 return 0x0E810 << 15
3553 case AXVSLTHU:
3554 return 0x0E811 << 15
3555 case AXVSLTWU:
3556 return 0x0E812 << 15
3557 case AXVSLTVU:
3558 return 0x0E813 << 15
3559 case AVANDV:
3560 return 0x0E24C << 15
3561 case AVORV:
3562 return 0x0E24D << 15
3563 case AVXORV:
3564 return 0x0E24E << 15
3565 case AVNORV:
3566 return 0x0E24F << 15
3567 case AVANDNV:
3568 return 0x0E250 << 15
3569 case AVORNV:
3570 return 0x0E251 << 15
3571 case AXVANDV:
3572 return 0x0EA4C << 15
3573 case AXVORV:
3574 return 0x0EA4D << 15
3575 case AXVXORV:
3576 return 0x0EA4E << 15
3577 case AXVNORV:
3578 return 0x0EA4F << 15
3579 case AXVANDNV:
3580 return 0x0EA50 << 15
3581 case AXVORNV:
3582 return 0x0EA51 << 15
3583 case AVDIVB:
3584 return 0xe1c0 << 15
3585 case AVDIVH:
3586 return 0xe1c1 << 15
3587 case AVDIVW:
3588 return 0xe1c2 << 15
3589 case AVDIVV:
3590 return 0xe1c3 << 15
3591 case AVMODB:
3592 return 0xe1c4 << 15
3593 case AVMODH:
3594 return 0xe1c5 << 15
3595 case AVMODW:
3596 return 0xe1c6 << 15
3597 case AVMODV:
3598 return 0xe1c7 << 15
3599 case AVDIVBU:
3600 return 0xe1c8 << 15
3601 case AVDIVHU:
3602 return 0xe1c9 << 15
3603 case AVDIVWU:
3604 return 0xe1ca << 15
3605 case AVDIVVU:
3606 return 0xe1cb << 15
3607 case AVMODBU:
3608 return 0xe1cc << 15
3609 case AVMODHU:
3610 return 0xe1cd << 15
3611 case AVMODWU:
3612 return 0xe1ce << 15
3613 case AVMODVU:
3614 return 0xe1cf << 15
3615 case AXVDIVB:
3616 return 0xe9c0 << 15
3617 case AXVDIVH:
3618 return 0xe9c1 << 15
3619 case AXVDIVW:
3620 return 0xe9c2 << 15
3621 case AXVDIVV:
3622 return 0xe9c3 << 15
3623 case AXVMODB:
3624 return 0xe9c4 << 15
3625 case AXVMODH:
3626 return 0xe9c5 << 15
3627 case AXVMODW:
3628 return 0xe9c6 << 15
3629 case AXVMODV:
3630 return 0xe9c7 << 15
3631 case AXVDIVBU:
3632 return 0xe9c8 << 15
3633 case AXVDIVHU:
3634 return 0xe9c9 << 15
3635 case AXVDIVWU:
3636 return 0xe9ca << 15
3637 case AXVDIVVU:
3638 return 0xe9cb << 15
3639 case AXVMODBU:
3640 return 0xe9cc << 15
3641 case AXVMODHU:
3642 return 0xe9cd << 15
3643 case AXVMODWU:
3644 return 0xe9ce << 15
3645 case AXVMODVU:
3646 return 0xe9cf << 15
3647 case AVMULWEVHB:
3648 return 0xe120 << 15
3649 case AVMULWEVWH:
3650 return 0xe121 << 15
3651 case AVMULWEVVW:
3652 return 0xe122 << 15
3653 case AVMULWEVQV:
3654 return 0xe123 << 15
3655 case AVMULWODHB:
3656 return 0xe124 << 15
3657 case AVMULWODWH:
3658 return 0xe125 << 15
3659 case AVMULWODVW:
3660 return 0xe126 << 15
3661 case AVMULWODQV:
3662 return 0xe127 << 15
3663 case AVMULWEVHBU:
3664 return 0xe130 << 15
3665 case AVMULWEVWHU:
3666 return 0xe131 << 15
3667 case AVMULWEVVWU:
3668 return 0xe132 << 15
3669 case AVMULWEVQVU:
3670 return 0xe133 << 15
3671 case AVMULWODHBU:
3672 return 0xe134 << 15
3673 case AVMULWODWHU:
3674 return 0xe135 << 15
3675 case AVMULWODVWU:
3676 return 0xe136 << 15
3677 case AVMULWODQVU:
3678 return 0xe137 << 15
3679 case AVMULWEVHBUB:
3680 return 0xe140 << 15
3681 case AVMULWEVWHUH:
3682 return 0xe141 << 15
3683 case AVMULWEVVWUW:
3684 return 0xe142 << 15
3685 case AVMULWEVQVUV:
3686 return 0xe143 << 15
3687 case AVMULWODHBUB:
3688 return 0xe144 << 15
3689 case AVMULWODWHUH:
3690 return 0xe145 << 15
3691 case AVMULWODVWUW:
3692 return 0xe146 << 15
3693 case AVMULWODQVUV:
3694 return 0xe147 << 15
3695 case AXVMULWEVHB:
3696 return 0xe920 << 15
3697 case AXVMULWEVWH:
3698 return 0xe921 << 15
3699 case AXVMULWEVVW:
3700 return 0xe922 << 15
3701 case AXVMULWEVQV:
3702 return 0xe923 << 15
3703 case AXVMULWODHB:
3704 return 0xe924 << 15
3705 case AXVMULWODWH:
3706 return 0xe925 << 15
3707 case AXVMULWODVW:
3708 return 0xe926 << 15
3709 case AXVMULWODQV:
3710 return 0xe927 << 15
3711 case AXVMULWEVHBU:
3712 return 0xe930 << 15
3713 case AXVMULWEVWHU:
3714 return 0xe931 << 15
3715 case AXVMULWEVVWU:
3716 return 0xe932 << 15
3717 case AXVMULWEVQVU:
3718 return 0xe933 << 15
3719 case AXVMULWODHBU:
3720 return 0xe934 << 15
3721 case AXVMULWODWHU:
3722 return 0xe935 << 15
3723 case AXVMULWODVWU:
3724 return 0xe936 << 15
3725 case AXVMULWODQVU:
3726 return 0xe937 << 15
3727 case AXVMULWEVHBUB:
3728 return 0xe940 << 15
3729 case AXVMULWEVWHUH:
3730 return 0xe941 << 15
3731 case AXVMULWEVVWUW:
3732 return 0xe942 << 15
3733 case AXVMULWEVQVUV:
3734 return 0xe943 << 15
3735 case AXVMULWODHBUB:
3736 return 0xe944 << 15
3737 case AXVMULWODWHUH:
3738 return 0xe945 << 15
3739 case AXVMULWODVWUW:
3740 return 0xe946 << 15
3741 case AXVMULWODQVUV:
3742 return 0xe947 << 15
3743 case AVADDWEVHB:
3744 return 0x0E03C << 15
3745 case AVADDWEVWH:
3746 return 0x0E03D << 15
3747 case AVADDWEVVW:
3748 return 0x0E03E << 15
3749 case AVADDWEVQV:
3750 return 0x0E03F << 15
3751 case AVSUBWEVHB:
3752 return 0x0E040 << 15
3753 case AVSUBWEVWH:
3754 return 0x0E041 << 15
3755 case AVSUBWEVVW:
3756 return 0x0E042 << 15
3757 case AVSUBWEVQV:
3758 return 0x0E043 << 15
3759 case AVADDWODHB:
3760 return 0x0E044 << 15
3761 case AVADDWODWH:
3762 return 0x0E045 << 15
3763 case AVADDWODVW:
3764 return 0x0E046 << 15
3765 case AVADDWODQV:
3766 return 0x0E047 << 15
3767 case AVSUBWODHB:
3768 return 0x0E048 << 15
3769 case AVSUBWODWH:
3770 return 0x0E049 << 15
3771 case AVSUBWODVW:
3772 return 0x0E04A << 15
3773 case AVSUBWODQV:
3774 return 0x0E04B << 15
3775 case AXVADDWEVHB:
3776 return 0x0E83C << 15
3777 case AXVADDWEVWH:
3778 return 0x0E83D << 15
3779 case AXVADDWEVVW:
3780 return 0x0E83E << 15
3781 case AXVADDWEVQV:
3782 return 0x0E83F << 15
3783 case AXVSUBWEVHB:
3784 return 0x0E840 << 15
3785 case AXVSUBWEVWH:
3786 return 0x0E841 << 15
3787 case AXVSUBWEVVW:
3788 return 0x0E842 << 15
3789 case AXVSUBWEVQV:
3790 return 0x0E843 << 15
3791 case AXVADDWODHB:
3792 return 0x0E844 << 15
3793 case AXVADDWODWH:
3794 return 0x0E845 << 15
3795 case AXVADDWODVW:
3796 return 0x0E846 << 15
3797 case AXVADDWODQV:
3798 return 0x0E847 << 15
3799 case AXVSUBWODHB:
3800 return 0x0E848 << 15
3801 case AXVSUBWODWH:
3802 return 0x0E849 << 15
3803 case AXVSUBWODVW:
3804 return 0x0E84A << 15
3805 case AXVSUBWODQV:
3806 return 0x0E84B << 15
3807 case AVADDWEVHBU:
3808 return 0x0E05C << 15
3809 case AVADDWEVWHU:
3810 return 0x0E05E << 15
3811 case AVADDWEVVWU:
3812 return 0x0E05E << 15
3813 case AVADDWEVQVU:
3814 return 0x0E05F << 15
3815 case AVSUBWEVHBU:
3816 return 0x0E060 << 15
3817 case AVSUBWEVWHU:
3818 return 0x0E061 << 15
3819 case AVSUBWEVVWU:
3820 return 0x0E062 << 15
3821 case AVSUBWEVQVU:
3822 return 0x0E063 << 15
3823 case AVADDWODHBU:
3824 return 0x0E064 << 15
3825 case AVADDWODWHU:
3826 return 0x0E065 << 15
3827 case AVADDWODVWU:
3828 return 0x0E066 << 15
3829 case AVADDWODQVU:
3830 return 0x0E067 << 15
3831 case AVSUBWODHBU:
3832 return 0x0E068 << 15
3833 case AVSUBWODWHU:
3834 return 0x0E069 << 15
3835 case AVSUBWODVWU:
3836 return 0x0E06A << 15
3837 case AVSUBWODQVU:
3838 return 0x0E06B << 15
3839 case AXVADDWEVHBU:
3840 return 0x0E85C << 15
3841 case AXVADDWEVWHU:
3842 return 0x0E85D << 15
3843 case AXVADDWEVVWU:
3844 return 0x0E85E << 15
3845 case AXVADDWEVQVU:
3846 return 0x0E85F << 15
3847 case AXVSUBWEVHBU:
3848 return 0x0E860 << 15
3849 case AXVSUBWEVWHU:
3850 return 0x0E861 << 15
3851 case AXVSUBWEVVWU:
3852 return 0x0E862 << 15
3853 case AXVSUBWEVQVU:
3854 return 0x0E863 << 15
3855 case AXVADDWODHBU:
3856 return 0x0E864 << 15
3857 case AXVADDWODWHU:
3858 return 0x0E865 << 15
3859 case AXVADDWODVWU:
3860 return 0x0E866 << 15
3861 case AXVADDWODQVU:
3862 return 0x0E867 << 15
3863 case AXVSUBWODHBU:
3864 return 0x0E868 << 15
3865 case AXVSUBWODWHU:
3866 return 0x0E869 << 15
3867 case AXVSUBWODVWU:
3868 return 0x0E86A << 15
3869 case AXVSUBWODQVU:
3870 return 0x0E86B << 15
3871 case AVMADDB:
3872 return 0x0E150 << 15
3873 case AVMADDH:
3874 return 0x0E151 << 15
3875 case AVMADDW:
3876 return 0x0E152 << 15
3877 case AVMADDV:
3878 return 0x0E153 << 15
3879 case AVMSUBB:
3880 return 0x0E154 << 15
3881 case AVMSUBH:
3882 return 0x0E155 << 15
3883 case AVMSUBW:
3884 return 0x0E156 << 15
3885 case AVMSUBV:
3886 return 0x0E157 << 15
3887 case AXVMADDB:
3888 return 0x0E950 << 15
3889 case AXVMADDH:
3890 return 0x0E951 << 15
3891 case AXVMADDW:
3892 return 0x0E952 << 15
3893 case AXVMADDV:
3894 return 0x0E953 << 15
3895 case AXVMSUBB:
3896 return 0x0E954 << 15
3897 case AXVMSUBH:
3898 return 0x0E955 << 15
3899 case AXVMSUBW:
3900 return 0x0E956 << 15
3901 case AXVMSUBV:
3902 return 0x0E957 << 15
3903 case AVMADDWEVHB:
3904 return 0x0E158 << 15
3905 case AVMADDWEVWH:
3906 return 0x0E159 << 15
3907 case AVMADDWEVVW:
3908 return 0x0E15A << 15
3909 case AVMADDWEVQV:
3910 return 0x0E15B << 15
3911 case AVMADDWODHB:
3912 return 0x0E15C << 15
3913 case AVMADDWODWH:
3914 return 0x0E15D << 15
3915 case AVMADDWODVW:
3916 return 0x0E15E << 15
3917 case AVMADDWODQV:
3918 return 0x0E15F << 15
3919 case AVMADDWEVHBU:
3920 return 0x0E168 << 15
3921 case AVMADDWEVWHU:
3922 return 0x0E169 << 15
3923 case AVMADDWEVVWU:
3924 return 0x0E16A << 15
3925 case AVMADDWEVQVU:
3926 return 0x0E16B << 15
3927 case AVMADDWODHBU:
3928 return 0x0E16C << 15
3929 case AVMADDWODWHU:
3930 return 0x0E16D << 15
3931 case AVMADDWODVWU:
3932 return 0x0E16E << 15
3933 case AVMADDWODQVU:
3934 return 0x0E16F << 15
3935 case AVMADDWEVHBUB:
3936 return 0x0E178 << 15
3937 case AVMADDWEVWHUH:
3938 return 0x0E179 << 15
3939 case AVMADDWEVVWUW:
3940 return 0x0E17A << 15
3941 case AVMADDWEVQVUV:
3942 return 0x0E17B << 15
3943 case AVMADDWODHBUB:
3944 return 0x0E17C << 15
3945 case AVMADDWODWHUH:
3946 return 0x0E17D << 15
3947 case AVMADDWODVWUW:
3948 return 0x0E17E << 15
3949 case AVMADDWODQVUV:
3950 return 0x0E17F << 15
3951 case AXVMADDWEVHB:
3952 return 0x0E958 << 15
3953 case AXVMADDWEVWH:
3954 return 0x0E959 << 15
3955 case AXVMADDWEVVW:
3956 return 0x0E95A << 15
3957 case AXVMADDWEVQV:
3958 return 0x0E95B << 15
3959 case AXVMADDWODHB:
3960 return 0x0E95C << 15
3961 case AXVMADDWODWH:
3962 return 0x0E95D << 15
3963 case AXVMADDWODVW:
3964 return 0x0E95E << 15
3965 case AXVMADDWODQV:
3966 return 0x0E95F << 15
3967 case AXVMADDWEVHBU:
3968 return 0x0E968 << 15
3969 case AXVMADDWEVWHU:
3970 return 0x0E969 << 15
3971 case AXVMADDWEVVWU:
3972 return 0x0E96A << 15
3973 case AXVMADDWEVQVU:
3974 return 0x0E96B << 15
3975 case AXVMADDWODHBU:
3976 return 0x0E96C << 15
3977 case AXVMADDWODWHU:
3978 return 0x0E96D << 15
3979 case AXVMADDWODVWU:
3980 return 0x0E96E << 15
3981 case AXVMADDWODQVU:
3982 return 0x0E96F << 15
3983 case AXVMADDWEVHBUB:
3984 return 0x0E978 << 15
3985 case AXVMADDWEVWHUH:
3986 return 0x0E979 << 15
3987 case AXVMADDWEVVWUW:
3988 return 0x0E97A << 15
3989 case AXVMADDWEVQVUV:
3990 return 0x0E97B << 15
3991 case AXVMADDWODHBUB:
3992 return 0x0E97C << 15
3993 case AXVMADDWODWHUH:
3994 return 0x0E97D << 15
3995 case AXVMADDWODVWUW:
3996 return 0x0E97E << 15
3997 case AXVMADDWODQVUV:
3998 return 0x0E97F << 15
3999 case AVSLLB:
4000 return 0xe1d0 << 15
4001 case AVSLLH:
4002 return 0xe1d1 << 15
4003 case AVSLLW:
4004 return 0xe1d2 << 15
4005 case AVSLLV:
4006 return 0xe1d3 << 15
4007 case AVSRLB:
4008 return 0xe1d4 << 15
4009 case AVSRLH:
4010 return 0xe1d5 << 15
4011 case AVSRLW:
4012 return 0xe1d6 << 15
4013 case AVSRLV:
4014 return 0xe1d7 << 15
4015 case AVSRAB:
4016 return 0xe1d8 << 15
4017 case AVSRAH:
4018 return 0xe1d9 << 15
4019 case AVSRAW:
4020 return 0xe1da << 15
4021 case AVSRAV:
4022 return 0xe1db << 15
4023 case AVROTRB:
4024 return 0xe1dc << 15
4025 case AVROTRH:
4026 return 0xe1dd << 15
4027 case AVROTRW:
4028 return 0xe1de << 15
4029 case AVROTRV:
4030 return 0xe1df << 15
4031 case AXVSLLB:
4032 return 0xe9d0 << 15
4033 case AXVSLLH:
4034 return 0xe9d1 << 15
4035 case AXVSLLW:
4036 return 0xe9d2 << 15
4037 case AXVSLLV:
4038 return 0xe9d3 << 15
4039 case AXVSRLB:
4040 return 0xe9d4 << 15
4041 case AXVSRLH:
4042 return 0xe9d5 << 15
4043 case AXVSRLW:
4044 return 0xe9d6 << 15
4045 case AXVSRLV:
4046 return 0xe9d7 << 15
4047 case AXVSRAB:
4048 return 0xe9d8 << 15
4049 case AXVSRAH:
4050 return 0xe9d9 << 15
4051 case AXVSRAW:
4052 return 0xe9da << 15
4053 case AXVSRAV:
4054 return 0xe9db << 15
4055 case AXVROTRB:
4056 return 0xe9dc << 15
4057 case AXVROTRH:
4058 return 0xe9dd << 15
4059 case AXVROTRW:
4060 return 0xe9de << 15
4061 case AXVROTRV:
4062 return 0xe9df << 15
4063 case AVADDB:
4064 return 0xe014 << 15
4065 case AVADDH:
4066 return 0xe015 << 15
4067 case AVADDW:
4068 return 0xe016 << 15
4069 case AVADDV:
4070 return 0xe017 << 15
4071 case AVADDQ:
4072 return 0xe25a << 15
4073 case AVSUBB:
4074 return 0xe018 << 15
4075 case AVSUBH:
4076 return 0xe019 << 15
4077 case AVSUBW:
4078 return 0xe01a << 15
4079 case AVSUBV:
4080 return 0xe01b << 15
4081 case AVSUBQ:
4082 return 0xe25b << 15
4083 case AXVADDB:
4084 return 0xe814 << 15
4085 case AXVADDH:
4086 return 0xe815 << 15
4087 case AXVADDW:
4088 return 0xe816 << 15
4089 case AXVADDV:
4090 return 0xe817 << 15
4091 case AXVADDQ:
4092 return 0xea5a << 15
4093 case AXVSUBB:
4094 return 0xe818 << 15
4095 case AXVSUBH:
4096 return 0xe819 << 15
4097 case AXVSUBW:
4098 return 0xe81a << 15
4099 case AXVSUBV:
4100 return 0xe81b << 15
4101 case AXVSUBQ:
4102 return 0xea5b << 15
4103 case AVSADDB:
4104 return 0x0E08C << 15
4105 case AVSADDH:
4106 return 0x0E08D << 15
4107 case AVSADDW:
4108 return 0x0E08E << 15
4109 case AVSADDV:
4110 return 0x0E08F << 15
4111 case AVSSUBB:
4112 return 0x0E090 << 15
4113 case AVSSUBH:
4114 return 0x0E091 << 15
4115 case AVSSUBW:
4116 return 0x0E092 << 15
4117 case AVSSUBV:
4118 return 0x0E093 << 15
4119 case AVSADDBU:
4120 return 0x0E094 << 15
4121 case AVSADDHU:
4122 return 0x0E095 << 15
4123 case AVSADDWU:
4124 return 0x0E096 << 15
4125 case AVSADDVU:
4126 return 0x0E097 << 15
4127 case AVSSUBBU:
4128 return 0x0E098 << 15
4129 case AVSSUBHU:
4130 return 0x0E099 << 15
4131 case AVSSUBWU:
4132 return 0x0E09A << 15
4133 case AVSSUBVU:
4134 return 0x0E09B << 15
4135 case AXVSADDB:
4136 return 0x0E88C << 15
4137 case AXVSADDH:
4138 return 0x0E88D << 15
4139 case AXVSADDW:
4140 return 0x0E88E << 15
4141 case AXVSADDV:
4142 return 0x0E88F << 15
4143 case AXVSSUBB:
4144 return 0x0E890 << 15
4145 case AXVSSUBH:
4146 return 0x0E891 << 15
4147 case AXVSSUBW:
4148 return 0x0E892 << 15
4149 case AXVSSUBV:
4150 return 0x0E893 << 15
4151 case AXVSADDBU:
4152 return 0x0E894 << 15
4153 case AXVSADDHU:
4154 return 0x0E896 << 15
4155 case AXVSADDWU:
4156 return 0x0E896 << 15
4157 case AXVSADDVU:
4158 return 0x0E897 << 15
4159 case AXVSSUBBU:
4160 return 0x0E898 << 15
4161 case AXVSSUBHU:
4162 return 0x0E899 << 15
4163 case AXVSSUBWU:
4164 return 0x0E89A << 15
4165 case AXVSSUBVU:
4166 return 0x0E89B << 15
4167 case AVILVLB:
4168 return 0xe234 << 15
4169 case AVILVLH:
4170 return 0xe235 << 15
4171 case AVILVLW:
4172 return 0xe236 << 15
4173 case AVILVLV:
4174 return 0xe237 << 15
4175 case AVILVHB:
4176 return 0xe238 << 15
4177 case AVILVHH:
4178 return 0xe239 << 15
4179 case AVILVHW:
4180 return 0xe23a << 15
4181 case AVILVHV:
4182 return 0xe23b << 15
4183 case AXVILVLB:
4184 return 0xea34 << 15
4185 case AXVILVLH:
4186 return 0xea35 << 15
4187 case AXVILVLW:
4188 return 0xea36 << 15
4189 case AXVILVLV:
4190 return 0xea37 << 15
4191 case AXVILVHB:
4192 return 0xea38 << 15
4193 case AXVILVHH:
4194 return 0xea39 << 15
4195 case AXVILVHW:
4196 return 0xea3a << 15
4197 case AXVILVHV:
4198 return 0xea3b << 15
4199 case AVMULB:
4200 return 0xe108 << 15
4201 case AVMULH:
4202 return 0xe109 << 15
4203 case AVMULW:
4204 return 0xe10a << 15
4205 case AVMULV:
4206 return 0xe10b << 15
4207 case AVMUHB:
4208 return 0xe10c << 15
4209 case AVMUHH:
4210 return 0xe10d << 15
4211 case AVMUHW:
4212 return 0xe10e << 15
4213 case AVMUHV:
4214 return 0xe10f << 15
4215 case AVMUHBU:
4216 return 0xe110 << 15
4217 case AVMUHHU:
4218 return 0xe111 << 15
4219 case AVMUHWU:
4220 return 0xe112 << 15
4221 case AVMUHVU:
4222 return 0xe113 << 15
4223 case AXVMULB:
4224 return 0xe908 << 15
4225 case AXVMULH:
4226 return 0xe909 << 15
4227 case AXVMULW:
4228 return 0xe90a << 15
4229 case AXVMULV:
4230 return 0xe90b << 15
4231 case AXVMUHB:
4232 return 0xe90c << 15
4233 case AXVMUHH:
4234 return 0xe90d << 15
4235 case AXVMUHW:
4236 return 0xe90e << 15
4237 case AXVMUHV:
4238 return 0xe90f << 15
4239 case AXVMUHBU:
4240 return 0xe910 << 15
4241 case AXVMUHHU:
4242 return 0xe911 << 15
4243 case AXVMUHWU:
4244 return 0xe912 << 15
4245 case AXVMUHVU:
4246 return 0xe913 << 15
4247 case AVADDF:
4248 return 0xe261 << 15
4249 case AVADDD:
4250 return 0xe262 << 15
4251 case AVSUBF:
4252 return 0xe265 << 15
4253 case AVSUBD:
4254 return 0xe266 << 15
4255 case AVMULF:
4256 return 0xe271 << 15
4257 case AVMULD:
4258 return 0xe272 << 15
4259 case AVDIVF:
4260 return 0xe275 << 15
4261 case AVDIVD:
4262 return 0xe276 << 15
4263 case AXVADDF:
4264 return 0xea61 << 15
4265 case AXVADDD:
4266 return 0xea62 << 15
4267 case AXVSUBF:
4268 return 0xea65 << 15
4269 case AXVSUBD:
4270 return 0xea66 << 15
4271 case AXVMULF:
4272 return 0xea71 << 15
4273 case AXVMULD:
4274 return 0xea72 << 15
4275 case AXVDIVF:
4276 return 0xea75 << 15
4277 case AXVDIVD:
4278 return 0xea76 << 15
4279 case AVBITCLRB:
4280 return 0xe218 << 15
4281 case AVBITCLRH:
4282 return 0xe219 << 15
4283 case AVBITCLRW:
4284 return 0xe21a << 15
4285 case AVBITCLRV:
4286 return 0xe21b << 15
4287 case AVBITSETB:
4288 return 0xe21c << 15
4289 case AVBITSETH:
4290 return 0xe21d << 15
4291 case AVBITSETW:
4292 return 0xe21e << 15
4293 case AVBITSETV:
4294 return 0xe21f << 15
4295 case AVBITREVB:
4296 return 0xe220 << 15
4297 case AVBITREVH:
4298 return 0xe221 << 15
4299 case AVBITREVW:
4300 return 0xe222 << 15
4301 case AVBITREVV:
4302 return 0xe223 << 15
4303 case AXVBITCLRB:
4304 return 0xea18 << 15
4305 case AXVBITCLRH:
4306 return 0xea19 << 15
4307 case AXVBITCLRW:
4308 return 0xea1a << 15
4309 case AXVBITCLRV:
4310 return 0xea1b << 15
4311 case AXVBITSETB:
4312 return 0xea1c << 15
4313 case AXVBITSETH:
4314 return 0xea1d << 15
4315 case AXVBITSETW:
4316 return 0xea1e << 15
4317 case AXVBITSETV:
4318 return 0xea1f << 15
4319 case AXVBITREVB:
4320 return 0xea20 << 15
4321 case AXVBITREVH:
4322 return 0xea21 << 15
4323 case AXVBITREVW:
4324 return 0xea22 << 15
4325 case AXVBITREVV:
4326 return 0xea23 << 15
4327 case AVSHUFH:
4328 return 0x0E2F5 << 15
4329 case AVSHUFW:
4330 return 0x0E2F6 << 15
4331 case AVSHUFV:
4332 return 0x0E2F7 << 15
4333 case AXVSHUFH:
4334 return 0x0EAF5 << 15
4335 case AXVSHUFW:
4336 return 0x0EAF6 << 15
4337 case AXVSHUFV:
4338 return 0x0EAF7 << 15
4339 }
4340
4341 if a < 0 {
4342 c.ctxt.Diag("bad rrr opcode -%v", -a)
4343 } else {
4344 c.ctxt.Diag("bad rrr opcode %v", a)
4345 }
4346 return 0
4347 }
4348
4349 func (c *ctxt0) oprr(a obj.As) uint32 {
4350 switch a {
4351 case ACLOW:
4352 return 0x4 << 10
4353 case ACLZW:
4354 return 0x5 << 10
4355 case ACTOW:
4356 return 0x6 << 10
4357 case ACTZW:
4358 return 0x7 << 10
4359 case ACLOV:
4360 return 0x8 << 10
4361 case ACLZV:
4362 return 0x9 << 10
4363 case ACTOV:
4364 return 0xa << 10
4365 case ACTZV:
4366 return 0xb << 10
4367 case AREVB2H:
4368 return 0xc << 10
4369 case AREVB4H:
4370 return 0xd << 10
4371 case AREVB2W:
4372 return 0xe << 10
4373 case AREVBV:
4374 return 0xf << 10
4375 case AREVH2W:
4376 return 0x10 << 10
4377 case AREVHV:
4378 return 0x11 << 10
4379 case ABITREV4B:
4380 return 0x12 << 10
4381 case ABITREV8B:
4382 return 0x13 << 10
4383 case ABITREVW:
4384 return 0x14 << 10
4385 case ABITREVV:
4386 return 0x15 << 10
4387 case AEXTWH:
4388 return 0x16 << 10
4389 case AEXTWB:
4390 return 0x17 << 10
4391 case ACPUCFG:
4392 return 0x1b << 10
4393 case ARDTIMELW:
4394 return 0x18 << 10
4395 case ARDTIMEHW:
4396 return 0x19 << 10
4397 case ARDTIMED:
4398 return 0x1a << 10
4399 case ATRUNCFV:
4400 return 0x46a9 << 10
4401 case ATRUNCDV:
4402 return 0x46aa << 10
4403 case ATRUNCFW:
4404 return 0x46a1 << 10
4405 case ATRUNCDW:
4406 return 0x46a2 << 10
4407 case AMOVFV:
4408 return 0x46c9 << 10
4409 case AMOVDV:
4410 return 0x46ca << 10
4411 case AMOVVF:
4412 return 0x4746 << 10
4413 case AMOVVD:
4414 return 0x474a << 10
4415 case AMOVFW:
4416 return 0x46c1 << 10
4417 case AMOVDW:
4418 return 0x46c2 << 10
4419 case AMOVWF:
4420 return 0x4744 << 10
4421 case AMOVDF:
4422 return 0x4646 << 10
4423 case AMOVWD:
4424 return 0x4748 << 10
4425 case AMOVFD:
4426 return 0x4649 << 10
4427 case AABSF:
4428 return 0x4501 << 10
4429 case AABSD:
4430 return 0x4502 << 10
4431 case AMOVF:
4432 return 0x4525 << 10
4433 case AMOVD:
4434 return 0x4526 << 10
4435 case ANEGF:
4436 return 0x4505 << 10
4437 case ANEGD:
4438 return 0x4506 << 10
4439 case ASQRTF:
4440 return 0x4511 << 10
4441 case ASQRTD:
4442 return 0x4512 << 10
4443 case AFLOGBF:
4444 return 0x4509 << 10
4445 case AFLOGBD:
4446 return 0x450a << 10
4447 case AFCLASSF:
4448 return 0x450d << 10
4449 case AFCLASSD:
4450 return 0x450e << 10
4451 case AFFINTFW:
4452 return 0x4744 << 10
4453 case AFFINTFV:
4454 return 0x4746 << 10
4455 case AFFINTDW:
4456 return 0x4748 << 10
4457 case AFFINTDV:
4458 return 0x474a << 10
4459 case AFTINTWF:
4460 return 0x46c1 << 10
4461 case AFTINTWD:
4462 return 0x46c2 << 10
4463 case AFTINTVF:
4464 return 0x46c9 << 10
4465 case AFTINTVD:
4466 return 0x46ca << 10
4467 case AFTINTRMWF:
4468 return 0x4681 << 10
4469 case AFTINTRMWD:
4470 return 0x4682 << 10
4471 case AFTINTRMVF:
4472 return 0x4689 << 10
4473 case AFTINTRMVD:
4474 return 0x468a << 10
4475 case AFTINTRPWF:
4476 return 0x4691 << 10
4477 case AFTINTRPWD:
4478 return 0x4692 << 10
4479 case AFTINTRPVF:
4480 return 0x4699 << 10
4481 case AFTINTRPVD:
4482 return 0x469a << 10
4483 case AFTINTRZWF:
4484 return 0x46a1 << 10
4485 case AFTINTRZWD:
4486 return 0x46a2 << 10
4487 case AFTINTRZVF:
4488 return 0x46a9 << 10
4489 case AFTINTRZVD:
4490 return 0x46aa << 10
4491 case AFTINTRNEWF:
4492 return 0x46b1 << 10
4493 case AFTINTRNEWD:
4494 return 0x46b2 << 10
4495 case AFTINTRNEVF:
4496 return 0x46b9 << 10
4497 case AFTINTRNEVD:
4498 return 0x46ba << 10
4499 case AVPCNTB:
4500 return 0x1ca708 << 10
4501 case AVPCNTH:
4502 return 0x1ca709 << 10
4503 case AVPCNTW:
4504 return 0x1ca70a << 10
4505 case AVPCNTV:
4506 return 0x1ca70b << 10
4507 case AXVPCNTB:
4508 return 0x1da708 << 10
4509 case AXVPCNTH:
4510 return 0x1da709 << 10
4511 case AXVPCNTW:
4512 return 0x1da70a << 10
4513 case AXVPCNTV:
4514 return 0x1da70b << 10
4515 case AVFSQRTF:
4516 return 0x1ca739 << 10
4517 case AVFSQRTD:
4518 return 0x1ca73a << 10
4519 case AVFRECIPF:
4520 return 0x1ca73d << 10
4521 case AVFRECIPD:
4522 return 0x1ca73e << 10
4523 case AVFRSQRTF:
4524 return 0x1ca741 << 10
4525 case AVFRSQRTD:
4526 return 0x1ca742 << 10
4527 case AXVFSQRTF:
4528 return 0x1da739 << 10
4529 case AXVFSQRTD:
4530 return 0x1da73a << 10
4531 case AXVFRECIPF:
4532 return 0x1da73d << 10
4533 case AXVFRECIPD:
4534 return 0x1da73e << 10
4535 case AXVFRSQRTF:
4536 return 0x1da741 << 10
4537 case AXVFRSQRTD:
4538 return 0x1da742 << 10
4539 case AVNEGB:
4540 return 0x1ca70c << 10
4541 case AVNEGH:
4542 return 0x1ca70d << 10
4543 case AVNEGW:
4544 return 0x1ca70e << 10
4545 case AVNEGV:
4546 return 0x1ca70f << 10
4547 case AXVNEGB:
4548 return 0x1da70c << 10
4549 case AXVNEGH:
4550 return 0x1da70d << 10
4551 case AXVNEGW:
4552 return 0x1da70e << 10
4553 case AXVNEGV:
4554 return 0x1da70f << 10
4555 case AVFRINTRNEF:
4556 return 0x1ca75d << 10
4557 case AVFRINTRNED:
4558 return 0x1ca75e << 10
4559 case AVFRINTRZF:
4560 return 0x1ca759 << 10
4561 case AVFRINTRZD:
4562 return 0x1ca75a << 10
4563 case AVFRINTRPF:
4564 return 0x1ca755 << 10
4565 case AVFRINTRPD:
4566 return 0x1ca756 << 10
4567 case AVFRINTRMF:
4568 return 0x1ca751 << 10
4569 case AVFRINTRMD:
4570 return 0x1ca752 << 10
4571 case AVFRINTF:
4572 return 0x1ca74d << 10
4573 case AVFRINTD:
4574 return 0x1ca74e << 10
4575 case AXVFRINTRNEF:
4576 return 0x1da75d << 10
4577 case AXVFRINTRNED:
4578 return 0x1da75e << 10
4579 case AXVFRINTRZF:
4580 return 0x1da759 << 10
4581 case AXVFRINTRZD:
4582 return 0x1da75a << 10
4583 case AXVFRINTRPF:
4584 return 0x1da755 << 10
4585 case AXVFRINTRPD:
4586 return 0x1da756 << 10
4587 case AXVFRINTRMF:
4588 return 0x1da751 << 10
4589 case AXVFRINTRMD:
4590 return 0x1da752 << 10
4591 case AXVFRINTF:
4592 return 0x1da74d << 10
4593 case AXVFRINTD:
4594 return 0x1da74e << 10
4595 case AVFCLASSF:
4596 return 0x1ca735 << 10
4597 case AVFCLASSD:
4598 return 0x1ca736 << 10
4599 case AXVFCLASSF:
4600 return 0x1da735 << 10
4601 case AXVFCLASSD:
4602 return 0x1da736 << 10
4603 case AVSETEQV:
4604 return 0x1ca726<<10 | 0x0<<3
4605 case AVSETNEV:
4606 return 0x1ca727<<10 | 0x0<<3
4607 case AVSETANYEQB:
4608 return 0x1ca728<<10 | 0x0<<3
4609 case AVSETANYEQH:
4610 return 0x1ca729<<10 | 0x0<<3
4611 case AVSETANYEQW:
4612 return 0x1ca72a<<10 | 0x0<<3
4613 case AVSETANYEQV:
4614 return 0x1ca72b<<10 | 0x0<<3
4615 case AVSETALLNEB:
4616 return 0x1ca72c<<10 | 0x0<<3
4617 case AVSETALLNEH:
4618 return 0x1ca72d<<10 | 0x0<<3
4619 case AVSETALLNEW:
4620 return 0x1ca72e<<10 | 0x0<<3
4621 case AVSETALLNEV:
4622 return 0x1ca72f<<10 | 0x0<<3
4623 case AXVSETEQV:
4624 return 0x1da726<<10 | 0x0<<3
4625 case AXVSETNEV:
4626 return 0x1da727<<10 | 0x0<<3
4627 case AXVSETANYEQB:
4628 return 0x1da728<<10 | 0x0<<3
4629 case AXVSETANYEQH:
4630 return 0x1da729<<10 | 0x0<<3
4631 case AXVSETANYEQW:
4632 return 0x1da72a<<10 | 0x0<<3
4633 case AXVSETANYEQV:
4634 return 0x1da72b<<10 | 0x0<<3
4635 case AXVSETALLNEB:
4636 return 0x1da72c<<10 | 0x0<<3
4637 case AXVSETALLNEH:
4638 return 0x1da72d<<10 | 0x0<<3
4639 case AXVSETALLNEW:
4640 return 0x1da72e<<10 | 0x0<<3
4641 case AXVSETALLNEV:
4642 return 0x1da72f<<10 | 0x0<<3
4643 }
4644
4645 c.ctxt.Diag("bad rr opcode %v", a)
4646 return 0
4647 }
4648
4649 func (c *ctxt0) opi(a obj.As) uint32 {
4650 switch a {
4651 case ASYSCALL:
4652 return 0x56 << 15
4653 case ABREAK:
4654 return 0x54 << 15
4655 case ADBAR:
4656 return 0x70e4 << 15
4657 }
4658
4659 c.ctxt.Diag("bad ic opcode %v", a)
4660
4661 return 0
4662 }
4663
4664 func (c *ctxt0) opir(a obj.As) uint32 {
4665 switch a {
4666 case ALU12IW:
4667 return 0x0a << 25
4668 case ALU32ID:
4669 return 0x0b << 25
4670 case APCALAU12I:
4671 return 0x0d << 25
4672 case APCADDU12I:
4673 return 0x0e << 25
4674 }
4675 return 0
4676 }
4677
4678 func (c *ctxt0) opirr(a obj.As) uint32 {
4679 switch a {
4680 case AADD, AADDW:
4681 return 0x00a << 22
4682 case ASGT:
4683 return 0x008 << 22
4684 case ASGTU:
4685 return 0x009 << 22
4686 case AAND:
4687 return 0x00d << 22
4688 case AOR:
4689 return 0x00e << 22
4690 case ALU52ID:
4691 return 0x00c << 22
4692 case AXOR:
4693 return 0x00f << 22
4694 case ASLL:
4695 return 0x00081 << 15
4696 case ASRL:
4697 return 0x00089 << 15
4698 case ASRA:
4699 return 0x00091 << 15
4700 case AROTR:
4701 return 0x00099 << 15
4702 case AADDV:
4703 return 0x00b << 22
4704 case AADDVU:
4705 return 0x00b << 22
4706 case AADDV16:
4707 return 0x4 << 26
4708
4709 case AJMP:
4710 return 0x14 << 26
4711 case AJAL:
4712 return 0x15 << 26
4713
4714 case AJIRL:
4715 return 0x13 << 26
4716 case ABLTU:
4717 return 0x1a << 26
4718 case ABLT, ABLTZ, ABGTZ:
4719 return 0x18 << 26
4720 case ABGEU:
4721 return 0x1b << 26
4722 case ABGE, ABGEZ, ABLEZ:
4723 return 0x19 << 26
4724 case -ABEQ:
4725 return 0x10 << 26
4726 case -ABNE:
4727 return 0x11 << 26
4728 case ABEQ:
4729 return 0x16 << 26
4730 case ABNE:
4731 return 0x17 << 26
4732 case ABFPT:
4733 return 0x12<<26 | 0x1<<8
4734 case ABFPF:
4735 return 0x12<<26 | 0x0<<8
4736 case APRELDX:
4737 return 0x07058 << 15
4738 case AMOVB,
4739 AMOVBU:
4740 return 0x0a4 << 22
4741 case AMOVH,
4742 AMOVHU:
4743 return 0x0a5 << 22
4744 case AMOVW,
4745 AMOVWU:
4746 return 0x0a6 << 22
4747 case AMOVV:
4748 return 0x0a7 << 22
4749 case AMOVF:
4750 return 0x0ad << 22
4751 case AMOVD:
4752 return 0x0af << 22
4753 case AMOVVP:
4754 return 0x27 << 24
4755 case AMOVWP:
4756 return 0x25 << 24
4757 case -AMOVB:
4758 return 0x0a0 << 22
4759 case -AMOVBU:
4760 return 0x0a8 << 22
4761 case -AMOVH:
4762 return 0x0a1 << 22
4763 case -AMOVHU:
4764 return 0x0a9 << 22
4765 case -AMOVW:
4766 return 0x0a2 << 22
4767 case -AMOVWU:
4768 return 0x0aa << 22
4769 case -AMOVV:
4770 return 0x0a3 << 22
4771 case -AMOVF:
4772 return 0x0ac << 22
4773 case -AMOVD:
4774 return 0x0ae << 22
4775 case -AMOVVP:
4776 return 0x26 << 24
4777 case -AMOVWP:
4778 return 0x24 << 24
4779 case -AVMOVQ:
4780 return 0x0b0 << 22
4781 case -AXVMOVQ:
4782 return 0x0b2 << 22
4783 case AVMOVQ:
4784 return 0x0b1 << 22
4785 case AXVMOVQ:
4786 return 0x0b3 << 22
4787 case ASLLV:
4788 return 0x0041 << 16
4789 case ASRLV:
4790 return 0x0045 << 16
4791 case ASRAV:
4792 return 0x0049 << 16
4793 case AROTRV:
4794 return 0x004d << 16
4795 case -ALL:
4796 return 0x020 << 24
4797 case -ALLV:
4798 return 0x022 << 24
4799 case ASC:
4800 return 0x021 << 24
4801 case ASCV:
4802 return 0x023 << 24
4803 case AVANDB:
4804 return 0x1CF4 << 18
4805 case AVORB:
4806 return 0x1CF5 << 18
4807 case AVXORB:
4808 return 0x1CF6 << 18
4809 case AVNORB:
4810 return 0x1CF7 << 18
4811 case AXVANDB:
4812 return 0x1DF4 << 18
4813 case AXVORB:
4814 return 0x1DF5 << 18
4815 case AXVXORB:
4816 return 0x1DF6 << 18
4817 case AXVNORB:
4818 return 0x1DF7 << 18
4819 case AVSEQB:
4820 return 0x0E500 << 15
4821 case AVSEQH:
4822 return 0x0E501 << 15
4823 case AVSEQW:
4824 return 0x0E502 << 15
4825 case AVSEQV:
4826 return 0x0E503 << 15
4827 case AXVSEQB:
4828 return 0x0ED00 << 15
4829 case AXVSEQH:
4830 return 0x0ED01 << 15
4831 case AXVSEQW:
4832 return 0x0ED02 << 15
4833 case AXVSEQV:
4834 return 0x0ED03 << 15
4835 case AVSLTB:
4836 return 0x0E50C << 15
4837 case AVSLTH:
4838 return 0x0E50D << 15
4839 case AVSLTW:
4840 return 0x0E50E << 15
4841 case AVSLTV:
4842 return 0x0E50F << 15
4843 case AVSLTBU:
4844 return 0x0E510 << 15
4845 case AVSLTHU:
4846 return 0x0E511 << 15
4847 case AVSLTWU:
4848 return 0x0E512 << 15
4849 case AVSLTVU:
4850 return 0x0E513 << 15
4851 case AXVSLTB:
4852 return 0x0ED0C << 15
4853 case AXVSLTH:
4854 return 0x0ED0D << 15
4855 case AXVSLTW:
4856 return 0x0ED0E << 15
4857 case AXVSLTV:
4858 return 0x0ED0F << 15
4859 case AXVSLTBU:
4860 return 0x0ED10 << 15
4861 case AXVSLTHU:
4862 return 0x0ED11 << 15
4863 case AXVSLTWU:
4864 return 0x0ED12 << 15
4865 case AXVSLTVU:
4866 return 0x0ED13 << 15
4867 case AVROTRB:
4868 return 0x1ca8<<18 | 0x1<<13
4869 case AVROTRH:
4870 return 0x1ca8<<18 | 0x1<<14
4871 case AVROTRW:
4872 return 0x1ca8<<18 | 0x1<<15
4873 case AVROTRV:
4874 return 0x1ca8<<18 | 0x1<<16
4875 case AXVROTRB:
4876 return 0x1da8<<18 | 0x1<<13
4877 case AXVROTRH:
4878 return 0x1da8<<18 | 0x1<<14
4879 case AXVROTRW:
4880 return 0x1da8<<18 | 0x1<<15
4881 case AXVROTRV:
4882 return 0x1da8<<18 | 0x1<<16
4883 case AVSLLB:
4884 return 0x1ccb<<18 | 0x1<<13
4885 case AVSLLH:
4886 return 0x1ccb<<18 | 0x1<<14
4887 case AVSLLW:
4888 return 0x1ccb<<18 | 0x1<<15
4889 case AVSLLV:
4890 return 0x1ccb<<18 | 0x1<<16
4891 case AVSRLB:
4892 return 0x1ccc<<18 | 0x1<<13
4893 case AVSRLH:
4894 return 0x1ccc<<18 | 0x1<<14
4895 case AVSRLW:
4896 return 0x1ccc<<18 | 0x1<<15
4897 case AVSRLV:
4898 return 0x1ccc<<18 | 0x1<<16
4899 case AVSRAB:
4900 return 0x1ccd<<18 | 0x1<<13
4901 case AVSRAH:
4902 return 0x1ccd<<18 | 0x1<<14
4903 case AVSRAW:
4904 return 0x1ccd<<18 | 0x1<<15
4905 case AVSRAV:
4906 return 0x1ccd<<18 | 0x1<<16
4907 case AXVSLLB:
4908 return 0x1dcb<<18 | 0x1<<13
4909 case AXVSLLH:
4910 return 0x1dcb<<18 | 0x1<<14
4911 case AXVSLLW:
4912 return 0x1dcb<<18 | 0x1<<15
4913 case AXVSLLV:
4914 return 0x1dcb<<18 | 0x1<<16
4915 case AXVSRLB:
4916 return 0x1dcc<<18 | 0x1<<13
4917 case AXVSRLH:
4918 return 0x1dcc<<18 | 0x1<<14
4919 case AXVSRLW:
4920 return 0x1dcc<<18 | 0x1<<15
4921 case AXVSRLV:
4922 return 0x1dcc<<18 | 0x1<<16
4923 case AXVSRAB:
4924 return 0x1dcd<<18 | 0x1<<13
4925 case AXVSRAH:
4926 return 0x1dcd<<18 | 0x1<<14
4927 case AXVSRAW:
4928 return 0x1dcd<<18 | 0x1<<15
4929 case AXVSRAV:
4930 return 0x1dcd<<18 | 0x1<<16
4931 case AVADDBU:
4932 return 0xe514 << 15
4933 case AVADDHU:
4934 return 0xe515 << 15
4935 case AVADDWU:
4936 return 0xe516 << 15
4937 case AVADDVU:
4938 return 0xe517 << 15
4939 case AVSUBBU:
4940 return 0xe518 << 15
4941 case AVSUBHU:
4942 return 0xe519 << 15
4943 case AVSUBWU:
4944 return 0xe51a << 15
4945 case AVSUBVU:
4946 return 0xe51b << 15
4947 case AXVADDBU:
4948 return 0xed14 << 15
4949 case AXVADDHU:
4950 return 0xed15 << 15
4951 case AXVADDWU:
4952 return 0xed16 << 15
4953 case AXVADDVU:
4954 return 0xed17 << 15
4955 case AXVSUBBU:
4956 return 0xed18 << 15
4957 case AXVSUBHU:
4958 return 0xed19 << 15
4959 case AXVSUBWU:
4960 return 0xed1a << 15
4961 case AXVSUBVU:
4962 return 0xed1b << 15
4963 case AVSHUF4IB:
4964 return 0x1ce4 << 18
4965 case AVSHUF4IH:
4966 return 0x1ce5 << 18
4967 case AVSHUF4IW:
4968 return 0x1ce6 << 18
4969 case AVSHUF4IV:
4970 return 0x1ce7 << 18
4971 case AXVSHUF4IB:
4972 return 0x1de4 << 18
4973 case AXVSHUF4IH:
4974 return 0x1de5 << 18
4975 case AXVSHUF4IW:
4976 return 0x1de6 << 18
4977 case AXVSHUF4IV:
4978 return 0x1de7 << 18
4979 case AVPERMIW:
4980 return 0x1cf9 << 18
4981 case AXVPERMIW:
4982 return 0x1df9 << 18
4983 case AXVPERMIV:
4984 return 0x1dfa << 18
4985 case AXVPERMIQ:
4986 return 0x1dfb << 18
4987 case AVEXTRINSB:
4988 return 0x1ce3 << 18
4989 case AVEXTRINSH:
4990 return 0x1ce2 << 18
4991 case AVEXTRINSW:
4992 return 0x1ce1 << 18
4993 case AVEXTRINSV:
4994 return 0x1ce0 << 18
4995 case AXVEXTRINSB:
4996 return 0x1de3 << 18
4997 case AXVEXTRINSH:
4998 return 0x1de2 << 18
4999 case AXVEXTRINSW:
5000 return 0x1de1 << 18
5001 case AXVEXTRINSV:
5002 return 0x1de0 << 18
5003 case AVBITCLRB:
5004 return 0x1CC4<<18 | 0x1<<13
5005 case AVBITCLRH:
5006 return 0x1CC4<<18 | 0x1<<14
5007 case AVBITCLRW:
5008 return 0x1CC4<<18 | 0x1<<15
5009 case AVBITCLRV:
5010 return 0x1CC4<<18 | 0x1<<16
5011 case AVBITSETB:
5012 return 0x1CC5<<18 | 0x1<<13
5013 case AVBITSETH:
5014 return 0x1CC5<<18 | 0x1<<14
5015 case AVBITSETW:
5016 return 0x1CC5<<18 | 0x1<<15
5017 case AVBITSETV:
5018 return 0x1CC5<<18 | 0x1<<16
5019 case AVBITREVB:
5020 return 0x1CC6<<18 | 0x1<<13
5021 case AVBITREVH:
5022 return 0x1CC6<<18 | 0x1<<14
5023 case AVBITREVW:
5024 return 0x1CC6<<18 | 0x1<<15
5025 case AVBITREVV:
5026 return 0x1CC6<<18 | 0x1<<16
5027 case AXVBITCLRB:
5028 return 0x1DC4<<18 | 0x1<<13
5029 case AXVBITCLRH:
5030 return 0x1DC4<<18 | 0x1<<14
5031 case AXVBITCLRW:
5032 return 0x1DC4<<18 | 0x1<<15
5033 case AXVBITCLRV:
5034 return 0x1DC4<<18 | 0x1<<16
5035 case AXVBITSETB:
5036 return 0x1DC5<<18 | 0x1<<13
5037 case AXVBITSETH:
5038 return 0x1DC5<<18 | 0x1<<14
5039 case AXVBITSETW:
5040 return 0x1DC5<<18 | 0x1<<15
5041 case AXVBITSETV:
5042 return 0x1DC5<<18 | 0x1<<16
5043 case AXVBITREVB:
5044 return 0x1DC6<<18 | 0x1<<13
5045 case AXVBITREVH:
5046 return 0x1DC6<<18 | 0x1<<14
5047 case AXVBITREVW:
5048 return 0x1DC6<<18 | 0x1<<15
5049 case AXVBITREVV:
5050 return 0x1DC6<<18 | 0x1<<16
5051 }
5052
5053 if a < 0 {
5054 c.ctxt.Diag("bad irr opcode -%v", -a)
5055 } else {
5056 c.ctxt.Diag("bad irr opcode %v", a)
5057 }
5058 return 0
5059 }
5060
5061 func (c *ctxt0) opirrr(a obj.As) uint32 {
5062 switch a {
5063 case AALSLW:
5064 return 0x2 << 17
5065 case AALSLWU:
5066 return 0x3 << 17
5067 case AALSLV:
5068 return 0x16 << 17
5069 }
5070
5071 return 0
5072 }
5073
5074 func (c *ctxt0) opirir(a obj.As) uint32 {
5075 switch a {
5076 case ABSTRINSW:
5077 return 0x3<<21 | 0x0<<15
5078 case ABSTRINSV:
5079 return 0x2 << 22
5080 case ABSTRPICKW:
5081 return 0x3<<21 | 0x1<<15
5082 case ABSTRPICKV:
5083 return 0x3 << 22
5084 }
5085
5086 return 0
5087 }
5088
5089 func (c *ctxt0) opiir(a obj.As) uint32 {
5090 switch a {
5091 case APRELD:
5092 return 0x0AB << 22
5093 }
5094
5095 return 0
5096 }
5097
5098 func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 {
5099 switch a {
5100 case AMOVV:
5101 switch fclass {
5102 case C_REG:
5103 switch tclass {
5104 case C_FREG:
5105 return 0x452a << 10
5106 case C_FCCREG:
5107 return 0x4536 << 10
5108 case C_FCSRREG:
5109 return 0x4530 << 10
5110 }
5111 case C_FREG:
5112 switch tclass {
5113 case C_REG:
5114 return 0x452e << 10
5115 case C_FCCREG:
5116 return 0x4534 << 10
5117 }
5118 case C_FCCREG:
5119 switch tclass {
5120 case C_REG:
5121 return 0x4537 << 10
5122 case C_FREG:
5123 return 0x4535 << 10
5124 }
5125 case C_FCSRREG:
5126 switch tclass {
5127 case C_REG:
5128 return 0x4532 << 10
5129 }
5130 }
5131
5132 case AMOVW:
5133 switch fclass {
5134 case C_REG:
5135 switch tclass {
5136 case C_FREG:
5137 return 0x4529 << 10
5138 }
5139 case C_FREG:
5140 switch tclass {
5141 case C_REG:
5142 return 0x452d << 10
5143 }
5144 }
5145 }
5146
5147 c.ctxt.Diag("bad class combination: %s %d,%d\n", a, fclass, tclass)
5148
5149 return 0
5150 }
5151
5152 func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) {
5153 farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
5154 tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
5155 fclass := c.rclass(fReg)
5156 tclass := c.rclass(tReg)
5157
5158 switch fclass | (tclass << 16) {
5159 case C_REG | (C_ELEM << 16):
5160
5161 switch a {
5162 case AVMOVQ:
5163 switch tarng {
5164 case ARNG_B:
5165 return (0x01CBAE << 14), 0xf
5166 case ARNG_H:
5167 return (0x03975E << 13), 0x7
5168 case ARNG_W:
5169 return (0x072EBE << 12), 0x3
5170 case ARNG_V:
5171 return (0x0E5D7E << 11), 0x1
5172 }
5173 case AXVMOVQ:
5174 switch tarng {
5175 case ARNG_W:
5176 return (0x03B75E << 13), 0x7
5177 case ARNG_V:
5178 return (0x076EBE << 12), 0x3
5179 }
5180 }
5181
5182 case C_ELEM | (C_REG << 16):
5183
5184 switch a {
5185 case AVMOVQ:
5186 switch farng {
5187 case ARNG_B:
5188 return (0x01CBBE << 14), 0xf
5189 case ARNG_H:
5190 return (0x03977E << 13), 0x7
5191 case ARNG_W:
5192 return (0x072EFE << 12), 0x3
5193 case ARNG_V:
5194 return (0x0E5DFE << 11), 0x1
5195 case ARNG_BU:
5196 return (0x01CBCE << 14), 0xf
5197 case ARNG_HU:
5198 return (0x03979E << 13), 0x7
5199 case ARNG_WU:
5200 return (0x072F3E << 12), 0x3
5201 case ARNG_VU:
5202 return (0x0E5E7E << 11), 0x1
5203 }
5204 case AXVMOVQ:
5205 switch farng {
5206 case ARNG_W:
5207 return (0x03B77E << 13), 0x7
5208 case ARNG_V:
5209 return (0x076EFE << 12), 0x3
5210 case ARNG_WU:
5211 return (0x03B79E << 13), 0x7
5212 case ARNG_VU:
5213 return (0x076F3E << 12), 0x3
5214 }
5215 }
5216
5217 case C_REG | (C_ARNG << 16):
5218 switch {
5219 case offset_flag:
5220
5221 switch a {
5222 case AVMOVQ:
5223 switch tarng {
5224 case ARNG_16B:
5225 return (0xC2 << 22), 0x0
5226 case ARNG_8H:
5227 return (0x182 << 21), 0x0
5228 case ARNG_4W:
5229 return (0x302 << 20), 0x0
5230 case ARNG_2V:
5231 return (0x602 << 19), 0x0
5232 }
5233 case AXVMOVQ:
5234 switch tarng {
5235 case ARNG_32B:
5236 return (0xCA << 22), 0x0
5237 case ARNG_16H:
5238 return (0x192 << 21), 0x0
5239 case ARNG_8W:
5240 return (0x322 << 20), 0x0
5241 case ARNG_4V:
5242 return (0x642 << 19), 0x0
5243 }
5244 }
5245 default:
5246
5247 switch a {
5248 case AVMOVQ:
5249 switch tarng {
5250 case ARNG_16B:
5251 return (0x1CA7C0 << 10), 0x0
5252 case ARNG_8H:
5253 return (0x1CA7C1 << 10), 0x0
5254 case ARNG_4W:
5255 return (0x1CA7C2 << 10), 0x0
5256 case ARNG_2V:
5257 return (0x1CA7C3 << 10), 0x0
5258 }
5259 case AXVMOVQ:
5260 switch tarng {
5261 case ARNG_32B:
5262 return (0x1DA7C0 << 10), 0x0
5263 case ARNG_16H:
5264 return (0x1DA7C1 << 10), 0x0
5265 case ARNG_8W:
5266 return (0x1DA7C2 << 10), 0x0
5267 case ARNG_4V:
5268 return (0x1DA7C3 << 10), 0x0
5269 }
5270 }
5271 }
5272
5273 case C_XREG | (C_ARNG << 16):
5274
5275 switch a {
5276 case AVMOVQ:
5277 return 0, 0
5278 case AXVMOVQ:
5279 switch tarng {
5280 case ARNG_32B:
5281 return (0x1DC1C0 << 10), 0x0
5282 case ARNG_16H:
5283 return (0x1DC1E0 << 10), 0x0
5284 case ARNG_8W:
5285 return (0x1DC1F0 << 10), 0x0
5286 case ARNG_4V:
5287 return (0x1DC1F8 << 10), 0x0
5288 case ARNG_2Q:
5289 return (0x1DC1FC << 10), 0x0
5290 }
5291 }
5292
5293 case C_XREG | (C_ELEM << 16):
5294
5295 switch a {
5296 case AVMOVQ:
5297 return 0, 0
5298 case AXVMOVQ:
5299 switch tarng {
5300 case ARNG_W:
5301 return (0x03B7FE << 13), 0x7
5302 case ARNG_V:
5303 return (0x076FFE << 12), 0x3
5304 }
5305 }
5306
5307 case C_ELEM | (C_XREG << 16):
5308
5309 switch a {
5310 case AVMOVQ:
5311 return 0, 0
5312 case AXVMOVQ:
5313 switch farng {
5314 case ARNG_W:
5315 return (0x03B81E << 13), 0x7
5316 case ARNG_V:
5317 return (0x07703E << 12), 0x3
5318 }
5319 }
5320
5321 case C_ELEM | (C_ARNG << 16):
5322
5323 switch a {
5324 case AVMOVQ:
5325 switch int32(farng) | (int32(tarng) << 16) {
5326 case int32(ARNG_B) | (int32(ARNG_16B) << 16):
5327 return (0x01CBDE << 14), 0xf
5328 case int32(ARNG_H) | (int32(ARNG_8H) << 16):
5329 return (0x0397BE << 13), 0x7
5330 case int32(ARNG_W) | (int32(ARNG_4W) << 16):
5331 return (0x072F7E << 12), 0x3
5332 case int32(ARNG_V) | (int32(ARNG_2V) << 16):
5333 return (0x0E5EFE << 11), 0x1
5334 }
5335 case AXVMOVQ:
5336 return 0, 0
5337 }
5338 }
5339
5340 return 0, 0
5341 }
5342
5343 func vshift(a obj.As) bool {
5344 switch a {
5345 case ASLLV,
5346 ASRLV,
5347 ASRAV,
5348 AROTRV:
5349 return true
5350 }
5351 return false
5352 }
5353
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